CA1200931A

CA1200931A - Synchronous demultiplexer for a t.d.m. signal

Info

Publication number: CA1200931A
Application number: CA000434321A
Authority: CA
Inventors: Heinrich Fladerer; Johann Magerl
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1982-08-12
Filing date: 1983-08-10
Publication date: 1986-02-18
Also published as: NO158707C; JPS5950636A; EP0103163A2; EP0103163A3; DE3230064A1; US4542503A; EP0103163B1; NO158707B; AU1788783A; DE3371152D1; ES8404764A1; AU542289B2; JPH0215142B2; NO832840L; ES524866A0; BR8304312A; ATE26783T1

Abstract

ABSTRACT:

A SYNCHRONOUS DEMULTIPLEXER FOR A t.d.m. SIGNAL:

A t.d.m. signal with a high bit rate and block-form frame code word is distributed between a plurality of channels (3 to 6) in a demulitplexer (2) by means of a chain circuit composed of conductor elements (32 to 35). The connected transmission path comprises stores (7, 8, 10) and a channel distributor (9). The channel distributor (9) is controlled by the second store (7) via a decoder (15), stores (16, 17) and a coder (18). A logic-linking arrangement (21) and a frame counter (23) permit resynchronisation only when the frame code word has failed to appear four times consecutively. The synchronous demultiplexer facilitates high-speed operation at bit rates of 140 Mbit/s and 565 Mbit/s and likewise facilitates construction in ECL integrated circuit technology.

(Figure 1)

Description

A SYNCHRO~OUS l:~EMULTIPLE~ER FOR A t.d.m. SIG~lAL:

The invention relates to a synchronous demultiplexer for bit-wise demultiplexing of a t . d . m . sional having a block-form frame code wordO
Arrangements of this kind are known from the magazine "Telecom-Report" 2 (1979) special issue digital transmission, pages 59 to 64 for a bit rate of up to 139 Mbit/s.
Hitherto series-parallel con~, ersion has been carried out by means of shift registers in such manner that the items of data are input consecutively into the register and read-out in paral-10 lel at times which represent a whole multiple of the input clockpulse rate. A demultiplexer which can be used in a practical manner is described in German Specification No 28 56 565. Since the data recognition time (set-up and hold-time) of the storage elements used must be sufficiently short in relation to the bit length of the serial t.d.m. signal which is to be distributed, high-speed flip-flops exhib-iting a correspondingly high power loss are required for a bit sequence oF for example 565 Mbit/s.
As may be gathered from the magazine publication specified above, synchronisation is carried out at the input cf the demultiplexer.
20 ~lowever, speed-related difficulties occur when the bit sequence of the t . d . m . signal reaches a rate of 565 Mbit/s .
I t is an aim of the invention to provide a synchronous demultiplexer which is suitabie for handling a high bit sequence and which fulfils the CCITT recommendation as given in the Yellow Book Vol. III, pages 219 to 220 (Fascicle III.3, Rec. G922, section 3.4). In addition, as large as possible a part of the arrange-ment is to be able to be constructed as integrated circuitry (Gate-array ) using ECL technology .

09~3~

In accordance with the above mentioned CCITT recommenda-tion, the channel allocation may not be altered until the frame code word has failed to be recognised four times in succession.
According to this invention there is provided a bit-wise 5 synchronous demultiplexer for a t.d.m. signal with a block-form frame code word and a predetermined bit rate, sàid demultiplexer having at its input end a chain circuit comprising n - 1 series-connected conductor portions which each have a signal transit time which is to correspond to the bit length of the t . d . m . signal of 10 predetermined bit rate, a transmission path connected to said chain circuit, including a first store with n D-flip-flops whose inputs are connected respectively to the input of the chain circuit and to the outputs of the conductor portions, a second store, a third store, a fourth store, and a channel distributor which is connected 15 to the second and third stores, such that, in the control path between the second store and the channel distributor there is arranged a decoder, a fifth store, a sixth store, and a coder and following the fifth and sixth stores there is arranged a logic-linking arrange-ment which is followed by a frame counter arranged to control the 20 sixth store and the logic-linking arrangement.
Figure 1 is a block circuit diagram of a synchronous demul-tiplexer embodying this invention;
Figures 2 to ô are block circuit diagrams of respective parts of the demultiplexer shown in Figure 1; and

2~ Figure 9 is a pulse timing plan illustrating the mode of operation of the demultiplexer shown in Figure 1.
Referring to Figure 1 a synchronous demultiplexer embody-ing the invention has an input 1, a demultiplexer 2 with a first store 39, further stores 7, 3, 10, 16 and 17, a channel distributor 9, ?;~

outputs 11 to 14, a decoder lS, a coder 18, a logic-linking arrangement 21, a Erame counter 23, and a clock pulse supply unit 27 with an input 30.
The construction and mode of operation of the demulti-5 plexer shown in Figure 1 will be described with reference to thedetailed arrangements shown in Figures 2 to 6 and the pulse timing plan shown in Figure 9.
Referring to Figure 2 a chain circuit 31 comprises conductGr elements 32 to 34, a terminal resistor 35 whose value 10 corresponds to that of the characteristic impedance of the chain circuit 31. The conducter elements provided may have a character-istic impedance of 50 ohms, 60 ohms or 75 ohms. A first store 39 includes D-flip-flops 40 to 43 which have outputs 3 to 6, and a common clock pulse input 28. In addition the input 1 is 15 preceded by a decision stage 45 having an input 4k.
Referring to Figure 3 the decision stage 45 includes two threshold value detectors 451 and 452, one OR gate 453, and for high bit rates a D-flip-flop 454. The threshold value detector 451 emits a logic "1" whenever a threshold voltage U1 is exceeded, 20 as does the threshold value detector 452 whenever a threshold voltage U2 is exceeded.
Referring to Figure 4, the adjoining transmission path extends between the inputs 3 to 6 and the outputs 11 to 14, and includes the stores 7, 8, 10 and the channel distributor 9-2S D-flip-~ops are designated by references which consist of two figures linked by a comma. The first figure refers to the channel, whereas the second figure refers to the position of the D-flip-flop in the direction of transmission. Multiplexers 46 to 49 have control inputs 19 and 20.

Referring to Figure 5, there are shown the decoder 15, the stores 16 and 17, and the logic-linking arrangement 21 and the coder 18.
The decoder 15 comprises four AND gates 50 to 5 whose inputs are respectively connected to Q- and Q-outputs of D-flip-flops as indicated in Figure 5 by the references associated with the inputs. A stroke above the D-flip-flop reference indicates OUtpllt from the inverted output Q.
The stores 16 and 17 each comprise four D-flip-flops (54to57; 58 to 61). The cloc'~t pulse inputs of the D-flip-flops ( 54to57 ) in the store 16 are connected to the clock pulse terminal 28, whereas the clock pulse inputs of the D-flip-flops (58 to 61) in the store 17 are connected to the output of an AND gate 62.
One input of this AND gate ~i~ is connected to the clock pulse input 28, whereas the Gther input is connected to a control signal input 24.
The logic-linking arrangement 21 includes OR gates ,i 7l 63 to 66 and~;, AND gates ~7 to70, and an output 22.
In Figure 6 there are shown the frame counter 23, with a drive arrangement72, a shift register 7~ a setting pulse arrange-ment 74, and a monitoring arrangement75 .
The drive arrangement 72 includes an RS flip-flop 76, an OR gate 77, an inverter78,, a D-flip-flop79, an AND gate80,, and an AND gate 81 ~ith inverting inputs. The setting pulse arrangement 74 comprises a D-flip-flop 82 and an AND gate ~3.
The shift register 73 has four D-flip-flops 8L~ to 87. The monitoring arrangement 75 is composed of a NOR gate 88, an AND gate 899 and an RS flip-flop 90 .

~J,~ 13~L

If an AMI-coded (alternate-marl<-inversion) t.d.m.
signal is applied to the input 44 in Figurc 2, this signal is con-verted in the decision stage 45 in-to a binary t . d . m . signal . This passes via the input 1 (Figures 1 and 2) into the demulitple~er 2. As can be seen from Figure 2, here the t.d.m. signal is shown as passing into the chain circuit 31 comprising individual conductor elements 32 to 34 which each have a signal transit time which corresponds to one bit length of the t.d.m. signal at the input 1. For example with a bit sequence of 565 ~bit/s, the conductGr 10 elernents (when comprising respective cable lengths) each have a length of approximately 40 cm. However strip lines on a carrier having a high shortening factor (e.~g. 3 to 5) can be substan~ially shorter in length.
The clock pulse train T, divided by 4, o~ the t . d . m .
15 signal present at the input 1 i^, applied to the input 28. With this clock pulse train T4, -the four D-flip-flops 40 to 43 accept the signals at the outer terminals 1 and 38, and at the tappings 36 and 37 oE the chain circuit 31 and forward these signals to the outputs 3 to 6.
Referring again to the continued transmission path shown in Figure 4 inthe first channel the store 7 contains four D-flip-flops 1,1 to 1,4, in the second channel four D-flip-flops 2,1 to 2,4, in the third channel four D-flip-flops 3,1 to 3, 4 , and in the fourth channel three D-flip-flops 4,1 to 4,3 . In order to simplify 25 the store 7, a number of space saving D-flip-flops withou-L inverting outputs Q have been used. To enable the use of a simple decoder 15, following the D-flip-flops 1,3; 2,2; 3,2 and 4,2 the items of data are advanced in inverted form. As a result it is only these D-flip-flops and the D-flip-flop 2, 3 for the decoding which need to have an inverting output Q in addition to the non-inverting output Q. In the 15 D-flip-flops of the store 7, a twelve-digit frame code word 11lllO100000 can occur irl four adjacent overlapping positions. In the first position it is contained in the D-flip-flops

3,4; 2,4; 1,4; 4,3; 3,3; 2,3; 1,3; 4,2; 3,2; 2,2; 1,2 and 4,1 in the sequence of the frame code word; in the seconcl position it is located between the D-flip--flops 2,4 and 3,1; in the thi~d position between the D-flip-flops 1,4 and 2,1; and in the fourth position between the D-flip-flops 4,3 and 1,1.
The outputs of the D-flip-flops in the store 7 are loaded by l)-flip-flops which follow in the transmission path, and by the connected AND gates 5~ to 53 of the decoder 15 s hown in Figure 5. At a transmission speed of 140 Mbit/s or 565 Mbit/s, an excessive load leads to impermissible operating conditions which result in a functional breakdown. Therefore prior to the channel distribution the four derived t. d . m . signals are advanced by one step by means of the second store 8.
The channel distributor 9 is now merely connected to the D-flip-flops 1, 4; 2,4; 3, 4; 1, 5; 2,5; 3,5 and 4, 4 which comprise a lighter load than all the D-flip-flops of the store 7.
In the channel distributor 9, in accordance with the code word applied to the control inputs 19 and 209 the four multi-plexers 46 to ~9 detect the synchronous one of the four positions which they switch through via the store 10 to the outputs 11 to ~5 14. On account of the high bit rate, intermediate storage is neces-sary. The D-flip-flops 1,6; 2,6; 3,6 and 4,5 are arranged to emit the data signals in invertecl form to take account of the construc-tion of the store 7.

In the decoder 15 shown in Figure 5, one of the AND
gates 50 to 53 detects the frame code word and emits a signal to a ~ollowing D~flip-flop in the store 16. This signal is forwarded via a following D-flip-flop in the store 17 to the coder 18 and to the logic-linking arrangement 21 whenever a control signal S from the frame counter 23 is present at the input 24. The control signal S is present (logic value "1") when the arrangement is not operating synchronously so that the information "no frame code word recognised" i5 stored in the D-flip-flop S~ in the shift register ~3. The coder 18 converts the signals with which it is presented into a code K1, K2 for the control of the channel distributor 9 via the inputs 19,20.
In the non-synchronous state the logic-linking arrangement 21 switches through all the inputs of the store 17 to its output 15 22. With the first frame code word which is recognised, the appropriate output signal of the store 16 is stored in the following D-flip-flop of the store 17 and forwarded to the output 22 via which it reaches the frame counter 23. The control signal S now ` adopts the logic state "0" as a result of which the clock pulse 2~ supply of the store 17 is disconnected and pulses can now reach the output 22 only via the switched-through channel. The synchronous state is reached when three frame code words have been recognised. The situation does not change until the control signal S assumes the logic state "1" and ensures that all the 25 OR gates 63 to 66 provide a "1" output signal.
The output signals of the logic-linking arrangement 21 which signify "frame code word recognised" are fed via the terminal 22 (see Figure 6) into the shift register 7~ of the frame counter 23. This shift register 73 is step-advanced by means of the output pulses of the àrive arrangement 72.
The RS flip-flop 76 is set by means of set-ting pulse ~I from the setting pulse arrangement '74. I t is reset when the multiplexer is out of synchronism and the D-flip-flop ~34 ha.s 5 stored the information "no frame code word recognised", in which case the logic-link takes place via the AND gate 81. The ena~ling signals for the clock pulse train of the shift register 73- thus either the output signal of the RS flip-flop 76 or the frame clock pulse train RT from the clock pulse supply 27 - are logi.c-linked 10 via the ~R gate 77 and forwarded to the D-flip-flop ~9 w',lich is step-advanced via the inverter 7~3. Via the AND gate ~), the out-put signal of this D-flip-flop 7~3 supples the clock pulse train T4 for the shift register 73.
Accordingly the clock pulse train T4 is continuously 15 connected to the shift register 73 when the demultiplexer is non-synchronous and the information "no frame code word recognised"
is stored in the D-flip-flop 84. One clock pulse 4 occurs in respect of each frame when the arrangement is synchronous i . e . when the D-flip-flop 84 has stored the information "frame code word 20 recognised".
In the monitoring arrangement 75 the RS flip-flop 90 stores the information as to whether the arrangement is synchronous or non-synchronous . I t is synchronous when three frame code words have been correctly recognised in succession in which case 25 the AND gate 89 emits a signal. If four frame code words fail to be recognised in succession so that the NOR gate 88 emits a signal and resets the RS flip-flop 90, the demultiplexer is opera-ting out of synchronism.
With the first frame code word which is recognised, in the D-flip-flop 84 the output signal changes from the logic state "0" to the logic state "1". One bit later the Q-output of the .~a, D-flip-flop ~ in the setting pulse arrangement 74 changes from the logic state "1" to the logic state "0". As a result of the 5 logic-linking of the two signals in the ANI) gate 83, the setting pulse SI is available for the clock pulse supply unit 27 with a width of or.e bit.
In Figure 7 there is shown the coder 18 which converts a decimal code into a dual code in accordance with the following 10 table :-58~ ~9/Q 60/Q 61 /QK1 K2 H L L L L L
L H L L H L
L L H L L H
L L L H H H
L L L L Z Z
The logic states H ^- high-level and L '-` low-level at the Q outputs of the D-flip-flops 5~ to 61 are shown on the left-hand side of the table, and those at the outputs 19 and 20 are 20 represented on the right-hand side. Z signifies a highly ohmic state .
The coder 18 has two NOR gates 91 and 92 which each have tri-state--outputs, and one OR gate9~.
Referring to Figure 8, the clock pulse supply unit 27 25 includes a frame length counter94 ~ a frequency divider 95, and an AND gate 36.

~ . 3~

l`he frame length counter 9~ counts the number of bits per channel which occur in one frame. If a frame code word is discovered during the non-synchronous state, the setting pulse S:~
sets -the frame length counter 94 at its starting value. If a new ~/e ~ C~e d 5 frame code word is cxpcct~, the AND gate 95 emits a frame clock pulse RT which has a width of one bit.
Referring to Figure 9, the pulse timing plan illustrates fundamental function flows :-, a) is the logic state at the input of the D-flip-flop 55, 10 b) is the logic state at the output of the D-flip-flop 55, c) is the logic state at the input ofthe D-flip-flop 56, d) is the logic state at -the output of the D-flip-flop 56 and e) is the logic state at the output 22 of the OR gate 71 and thus of the logic-linking arrangement 21;
f ) is the logic state at the output of the D-flip-flop 84 in the shift register 73, g ) is the logic state at the output of the RS flip-flop 90 in the monitoring arrangement 75 and 20 h ) is the logic state at the output of the D-flip-flop 79 in the drive arrangement 72.
ln Figure 9 the following events are illustrated:-A) the first recognised frame code word B ) the second recognised frame code word 25 C ) the third recognised frame code word D ) the first non-recognised frame code word E) the second non-recognised ~rame code word F ) the third non-recognised frame code word 3~l G) the fourth non-recognised frame code word H) the first frame code word which is again recognised and I ) the second frame code word which is now not recognised.
Hunting takes place during the period up to t 1. During the period between tl and t2 synchronisation is achieved, i . e . a frame code word is discovered three times in succession. Until the time t2 the demultiplexer operates non-synchronously. During the period between t2 and t4 the demultiplexer operates synchronously.

lO During the period between t3 and t4 synchronisation is lost, i.e.
no frame code word is discovered four times in succession. From the time t4 onwards the demultiplexer again operates non- -synchronously. During the period from t4 to t5 hunting again takes place; during the period from t5 to t6 synchronisation is achieved, 15 and from the time t6 onwards hunting again takes place.
In F~igure 9, a single asterisk, ~, signifies that the rirst bit of the frame code word occurs in the third channel of the store 7 and a double asterisk, **, signifies that the first bit of the frame code word occurs in the second channel of the store 7.

20 Also the frame length has been considerably shortened for the sake of brevity and for clarity the gate transit times have not been taken into account.
The clock pulse train T4 can be obtained from the clock pulse train T of the input-end time multiplex signal by means of 25 an amplifier, a phase shlft device, and a 4:1 frequency divider.

Claims

CLAIMS:

1. A bit-wise synchronous demultiplexer for a t.d.m.
signal with a block-form frame code word and a predetermined bit rate, said demultiplexer having at its input end a chain circuit comprising n - 1 series-connected conductor portions which each have a signal transit time which is to correspond to the bit length of the t.d.m. signal of predetermined bit rate, a transmission path connected to said chain circuit, including a first store with n D-flip-flops whose inputs are connected respectively to the input of the chain circuit and to the outputs of the conductor portions, a second store, a third store, a fourth store, and a channel distributor which is connected to the second and third stores, such that, in a control path between the second store and the channel distributor there is arranged a decoder, a fifth store, a sixth store, and a coder and following the fifth and sixth stores there is arranged a logic-linking arrangement which is followed by a frame counter arranged to control the sixth store and the logic-linking arrange-ment.

2. A demultiplexer as claimed in Claim 1, wherein conductor portions are provided with a characteristic impedance of 50 ohms, 60 ohms or 75 ohms.

3. A demultiplexer as claimed in Claim 1, wherein the con-ductor portions comprise consecutive lengths of cable.

4. A demultiplexer as claimed in Claim 1 wherein the con-ductor portions comprise strip lines.

5. A demultiplexer as claimed in Claim 4, wherein the strip lines are arranged on a carrier having a shortening factor of 3 to 5.

6. A demultiplexer as claimed in Claim 1 for four outgoing channels and synchronization to a 12-digit block-form frame code word, wherein in the second store, in the first channel four D-flip-flops are connected in a chain arrangement, in the second channel four D-flip-flops, in the third channel four D-flip-flops, and in the fourth channel three D-flip-flops where only the Q-output of the third D-flip-flop in the first channel is connected for use, and similarly in the second, third and fourth channels in the case of the second D-flip-flop, whereas only the Q-output is connected for use in the case of the re-maining D-flip-flops.

7. A demultiplexer as claimed in Claim 6, wherein the third and fourth stores each include in the respective channels exclusively D-flip-flops which have only one Q-output connected for use and the clock pulse inputs of all these D-flip-flops are connected in common.

8. A demultiplexer as claimed in Claim 7, wherein in the channel distributor four multiplexers are provided each of which has two control inputs each for receiving a respective control code word, a first data input of the first multiplexer being connected to the Q-output of the D-flip-flop in the third channel of the third store, a second data input being connected to the Q-output of the D-flip-flop in the second channel of the third store, a third data input being connected to the Q-output of the D-flip-flop in the first channel of the third store, and a fourth data input being connected to the Q-output of the D-flip-flop in the fourth channel of the third store, a first data input of the second multiplexer being connected to the Q-output of the D-flip-flop in the second channel of the third store, a second data input being connected to the Q-output of the D-flip-flop in the first channel of the third store, a third data input being connected to the Q-output of the D-flip-flop in the fourth channel of the third store, a fourth data input being connected to the Q-output of the last D-flip-flop in the second channel of the second store, a first data input of the third multiplexer being connected to the Q-output of the D-flip-flop in the first channel of the third store, a second data input being connected to the Q-output of the D-flip-flop in the fourth channel of the third store, a third data input being connected to the Q-output of the last D-flip-flop in the third channel of the second store, a fourth data input being connected to the Q-output of the last D-flip-flop in the second channel of the second store, and a first data input of the fourth multiplexer being connected to the Q-output of the D-flip-flop in the fourth channel of the third store, a second data input being connected to the output of the last D-flip-flop in the third channel of the second store, a third data input being connected to the Q-output of the last D-flip-flop in the second channel of the second store, and a fourth data input being connected to the Q-output of the last D-flip-flop in the first channel of the second store.

9. A demultiplexer as claimed in Claim 6, wherein four AND gates provided with inverting inputs are arranged in respec-tive channels in the decoder, the inputs of the first AND gate being connected to the outputs in the second store of the second, third and fourth D-flip-flops in the first channel, and of the first, second and third D-flip-flops in the second, third and fourth channels, the inputs of the second AND gate being connect-ed to the outputs in the second store of the second, third and fourth D-flip-flops of the first and second channels, and of the first, second and third D-flip-flops in the third and fourth channels, the inputs of the third AND gate being connected to the outputs in the second store of the second, third and fourth D-flip-flops in the first, second and third channels and of the first, second and third D-flip-flops in the fourth channel, the inputs of the fourth AND gate being connected to the outputs in the second store of the first, second and third D-flip-flops in the first, second, third and fourth channels.

10. A demultiplexer as claimed in Claim 6 wherein in the fifth store each of four outputs of the decoder is followed by a respective D-flip-flop which is provided with a Q-output, the clock pulse inputs of all the D-flip-flops of the fifth store being connected in common.

11. A demultiplexer as claimed in Claim 6, wherein in the sixth store each output of the fifth store is followed by a res-pective D-flip-flop provided with a Q-output and a control AND
gate being provided whose first input is arranged for receiving clock pulses and whose second input is arranged for receiving a control signal and whose output is connected to the clock pulse inputs of all the D-flip-flops of the sixth store.

12. A demultiplexer as claimed in Claim 6, wherein in the logic-linking arrangement, there are provided OR gates the first input of each of which is connected to the Q-output of the appropriate D-flip-flop in the sixth store and the other input of each of which is connected to the second (control signal) input of the control AND gate, further AND gates being provided such that one input of each is connected to the output of a respective one of the OR gates and the other input of each of which further AND
gates is connected to the D-input of the respective preceding D-flip-flop in the sixth store, and there also being provided a further OR gate whose inputs are each connected to a respective output of the further AND gates.

13. A demultiplexer as claimed in claim 6, wherein in the frame counter there is arranged a shift register whose input is connect-ed to the output of the logic-linking arrangement and which has a number of D-flip-flops each provided with a Q-output and cor-responding in number to the number of channels in the transmission path, and there is further provided a drive arrangement for the shift register, a setting pulse arrangement for a clock pulse supply unit, and a monitoring arrangement.

14. A demultiplexer as claimed in Claim 1 and arranged for the processing of a t.d.m. signal which has a bit rate of 565 Mbit/s.