CA1201216A - Formation of submicron features in semiconductor devices - Google Patents
Formation of submicron features in semiconductor devicesInfo
- Publication number
- CA1201216A CA1201216A CA000416587A CA416587A CA1201216A CA 1201216 A CA1201216 A CA 1201216A CA 000416587 A CA000416587 A CA 000416587A CA 416587 A CA416587 A CA 416587A CA 1201216 A CA1201216 A CA 1201216A
- Authority
- CA
- Canada
- Prior art keywords
- layer
- sidewall
- oxide layer
- essentially
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 230000015572 biosynthetic process Effects 0.000 title abstract description 4
- 239000010410 layer Substances 0.000 claims abstract description 189
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 33
- 239000001301 oxygen Substances 0.000 claims abstract description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 19
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 12
- -1 for example Substances 0.000 claims abstract description 11
- 230000005669 field effect Effects 0.000 claims abstract description 9
- 239000011241 protective layer Substances 0.000 claims abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 37
- 238000005530 etching Methods 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 239000000377 silicon dioxide Substances 0.000 claims description 19
- 235000012239 silicon dioxide Nutrition 0.000 claims description 19
- 238000001020 plasma etching Methods 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 11
- 230000001681 protective effect Effects 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 5
- 230000000873 masking effect Effects 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 230000000295 complement effect Effects 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 abstract description 16
- 239000004411 aluminium Substances 0.000 abstract description 15
- 238000000992 sputter etching Methods 0.000 abstract description 14
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 14
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 11
- 238000001465 metallisation Methods 0.000 description 10
- 229910021339 platinum silicide Inorganic materials 0.000 description 10
- 239000000203 mixture Substances 0.000 description 7
- 229910052697 platinum Inorganic materials 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 3
- 230000004913 activation Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 3
- 229910052801 chlorine Inorganic materials 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000012044 organic layer Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 238000007792 addition Methods 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- PLXMOAALOJOTIY-FPTXNFDTSA-N Aesculin Natural products OC[C@@H]1[C@@H](O)[C@H](O)[C@@H](O)[C@H](O)[C@H]1Oc2cc3C=CC(=O)Oc3cc2O PLXMOAALOJOTIY-FPTXNFDTSA-N 0.000 description 1
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- OWNRRUFOJXFKCU-UHFFFAOYSA-N Bromadiolone Chemical compound C=1C=C(C=2C=CC(Br)=CC=2)C=CC=1C(O)CC(C=1C(OC2=CC=CC=C2C=1O)=O)C1=CC=CC=C1 OWNRRUFOJXFKCU-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229920002160 Celluloid Polymers 0.000 description 1
- 241000490229 Eucephalus Species 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 238000000637 aluminium metallisation Methods 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 239000001117 sulphuric acid Substances 0.000 description 1
- 235000011149 sulphuric acid Nutrition 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
Abstract
ABSTRACT
FORMATION OF SUBMICRON FEATURES IN SEMICONDUCTOR DEVICES
This invention involves the defining of a submicron feature 93 in a structure, typically an insulated gate field effect transistor structure.
This feature is defined by a sidewall oxide layer 71 formed by reactive oxygen ion etching of the structure being built at a time when an exposed layer 64 in the vicinity of the sidewall contains atoms of a material, for example, silicon or aluminium, which combine with the oxygen ions to form the sidewall oxide layer. The sidewall oxide layer may be used as a mask to form a feature 93 or it may itself constitute such a feature, for example a protective layer on the sidewalls of a polysilicon gate of a F.E.T.
FORMATION OF SUBMICRON FEATURES IN SEMICONDUCTOR DEVICES
This invention involves the defining of a submicron feature 93 in a structure, typically an insulated gate field effect transistor structure.
This feature is defined by a sidewall oxide layer 71 formed by reactive oxygen ion etching of the structure being built at a time when an exposed layer 64 in the vicinity of the sidewall contains atoms of a material, for example, silicon or aluminium, which combine with the oxygen ions to form the sidewall oxide layer. The sidewall oxide layer may be used as a mask to form a feature 93 or it may itself constitute such a feature, for example a protective layer on the sidewalls of a polysilicon gate of a F.E.T.
Description
3L 2~
(E, Kinsbron ~-9) FORMATION OF SU~MICRON FEATURES IN SEMICONDUCTOR
DEVICES.
This invention relates to methods for fabrica-til1g semiconductor devices, and more particularly to methods for forming submicron features of semiconductor integrated ci.rcuit transistor devices.
Sl1ort channel (below abou-t 2 microns) insulated gate :Eie.L(I ef'l'ec-t transistors, also known as metal oxide semiconductor field e:ri'ect transis-tors (~OSl~'~Ts), are desirable or high frequency opera1,ioll, typicAl.Ly above 50 MU In Canadian Patent Applications 373395 and 374257 methods are described for making insulated gate l'ield el'fect transistors with extremely small (500 or less) separations between the extremities of the gate regions and those o.f the source (and drain) regions. The transistors were therefore characterized by clesirably small source-to-channel resistances, The me-thods taught in the aforementioned patent applications include lie formation of thin silicon dioxide layers on the sidewalls of polycrystalline si.Licon gate electrodes by thermal grow-th. The resulting sidewa.ll oxide layer is useful as a spacer .layer for aligning the source relative to the gate region channel, Although ra-ther tbin (as thin as about 200 R) layers of the required sidewall oxide can be :formed by thermal growth of silicon dioxide on the polycrystalline 28 silicon ("polysilicon") ga-te, an undesirable limitation ox' ~2~2~
suGh thermal grow-th s-tems from the Eacts -that oxicle growth on the polysilicon is not easily controlled or uniform, owing to the polycrystalline structure of the underlying polysilicon; (2) at -the same time that the sidewall oxide is being grown, the source-to-drain length of the polysilicon gate elec-trode correspondingly is diminished; so that control over the crucial length of the gate electrode, and hence of the underlying transistor channel, is de-teriorated; (3) the oxide simul-taneously grown over the source and drain regions -force down the top surfaces of -the source and drain to leve],s below the top surface of the channel region by undesirably large amounts (approximately equal to one-hal-f -the thickness ox the grown oxide); and (~) a separate etching step is required for the removal of -the grown oxide L'rom locations overlying the source and drain.
Accordingly, it would be desirable to have a method for defining fea-tures in sem:iconduc-tor dev,ice structures by forming sidewall o~icle layers whicll m:itiga,-tes one or more o:t` these shor-tcomings oE the prior art.
In -the invention as set out in -the claims the sidewall oxide layer is formed by back-sputtering, so -the shortcomings of the prior art, in so far as they are due to forming the sidewall oxide layer my thermal oxidation, are overcome. Furthermore, it is possible to form sidewall oxide layers on materials, such as organic resists, which are not suscep-tible to thermal oxidation.
Some embodimen-ts o-f the inven-tion will now be described by way of example with reference -to the accompanying drawings in which:-FIGS. 1-5 depict in sec-tion various stages o:E a process of maki,ng an insulated gate field effect transistor structure in accordance with the invention;
FIG. 6 depic-ts in section a different insulated gate field effect transistor fabricated in accordance wi-th the invention;
FIGS. 7-12 depict in section various stages of 38 another process of making an insulated ga-te field effect -transistor struc-ture in accordance with the invention;
and FIG. 13 depi.cts a top section view of the transistor structure shown in FIG. 12.
For the sake of clarity, none o-f the drawings is to scale.
Referring -to JIG. 1, a silicon semiconductor body 10, typically O-e n-type conductivity, has a major planar horizontal surface -10.5, -typically a (100) crystallographic plane; and the body has a uniform ne-t significant honor impurity concentration in the neighbourhood of the surface equal to about 1016 impurities per cm3. A relatively thin gate oxide layer 11 of thermally grown silicon dioxide and a relatively -thick f'ield oxide layer 13 are located on complementary portions oi' the sur-face 10.5 in a conventi.onal pattern for forming a mul-tipli.city of similar transis-tor device s-tructures on the major surl'ace 10.5. A poLycrystalline silicon ("po1ysilicon") layer 12 is loca-ted on the exposed top surfaces of the gate oxide layer 11 and the told oxide layer ].3. On top of a limited portion of the polysilicon layer 12 is located a resist layer l typically Hunt's resist ~IPR-20~, and an auxiliary silicon dioxide layer 15.
Both layers l and 15 can have been previously patterned in accordance with, for example, the tri-level process described by J.M. Moran and D. Maydan in an article entitled "High Resolution, Steep Pro-file, Resist Patterns" published in Bell System TechnicaL Journal, 30 Vol. 58, pp. 1027-1036 (1979). As a result of this tri-level process, which utilizes reac-tive oxygen ion etching to pattern the resist layer l sidewall build-up layers 16 of silicon dioxide form on the vertical sidewalls o-f the patterned resis-t layer l during the las-t phase of -this reactive oxygen ion etching (when p~r-tions of the polysilicon layer 12 become exposed and, after being physically back-spu-t-tered, react with the oxygen ions).
38 The wid-th of the l.ayers l and 15 as -thus patterned is a _ typically about 1 or 2 micron.
The oxicle build-up layer 16 together with -the patterned oxide layer 15 are preferably then bo-th comple-tely removed by a room-temperature treatmen-t wi-th a solution of buffered hydrofluoric acid (NH4F and HF in typically a 30:1 molar ratio). Next, us:ing the pat-terned resist layer 14 as a protective mask, the struc-ture of FIG. 1 is placed in a suitable chamber and subjected to anisotropic etching with chlorine gas, at a pressure of -typically about 10 micron Hg, with an RF power density ox typically about 0.1 watt/cm , and an RF frequency of about 13.56 MHz. By "anisotropic" e-tching is meant that substantially vertical sidewalls are formed in -the etched material at locations underlying edges ox any protective mask used during the etching, that is, at intersections Oe regions O:e etched and non-e-tched ma-terial. Thereby the polysilicon Iayer 12 is pa-tterned (FIG. 2) to serve as a polysil.icon gate electrode layer O:e predetermined width, typically about 1 to 2 rnicron, with substant:ial.ly vertical sidewalls 12.5 due -to -the anisotlopy Oe -the chlorine etching.
The top suriace of the resulting structure shown in FIG. 2 is then subjected (advantageously in the same chamber used for the previous chlorine ion etchingstep) to a vertical bombardment of oxygen ions 17 suitable for anisotropically reactively ion etching the ga-te oxide layer 11. Thereby a sidewall silicon dioxide layer 21 (FIG. 3) is formed on -the vertical sidewalls 12.5 of -the ga-te electrode layer 12 (as well as on resulting sidewalls of the gate oxide layer 11). Preferably, in order to ensure complete removal of -the exposed por-tions of the silicon dioxide layer 11 a-t regions overlying suture source and drain zones, ther~active ion etching is carried out for a su-fficient time that about 15 A of silicon -prom the body 10 is removed at the exposed portions of the surface 10.5 underlying the areas between the field oxide and the gate electrode. During -this reactive ion etching 38 of the gate oxide, a top portion of the resist layer 14 is simultaneously also removed.
By using the same chamber lor the oxygen ion etching a previously used for -the chlorine ion etching, residues of chlorine are automa-tically removed -from the chamber during the oxygen ion e-tching.
The oxygen reac-tive ion e-tching ox the exposed portion of the silicon dioxide layer 11 is performed, for example, in a chamber containing pure oxygen (partially ionized) or a gas mixture (partially ionized) of oxygen and abou-t 0.5 percent to 1.0 percent by volume carbon tetrafluoride (C~4). For anisotropy of the etching, a relatively low oxygen pressure is used, ordinarily in the useful range of about 2 to micron Hg, with a relatively higher R~ power densi-ty, ordinarily in the useful range o-f about 0.25 to 0.75 watt/cm2 with an RF frequency of typically about 13,56 MHz.
Durillg -this reac-tive oxygen ion etching of the oxide layer 11, :it is believed -that the oxygen ions react wi-th -the sili.con which is back-sputtered prom -the exposed portion o-f -this silicon dioxide layer 11 (and subsequently from the exposed portion of the silicon body 10) to form a plasma from which -the sidewall silicon dioxide layer 21 (FIG. 3) is deposited on the sidewall 12.5 of the ga-te elec-trode layer 12. On the other hand, it may be that a transport O:e silicon and oxygen from the sil.icon dioxide layer 11 to eorm the sidewall oxide layer 21 can be performed by a bombardment with ions o-ther -than oxygen.
In cases of only partially etching the portion of the oxide layer 11 overlying the body 10 between the 30 polysilicon gate layer 12 and the field oxide layer 13J the sidewall oxide layer 21 can be ox thickness (measured at the bottom) as low as about 50 I, and in any event is ordinarily in the range of bout 50 -to 500 I. On the other hand, in cases of over-etching this oxide layer 11 and e-tching into underl.ying silicon of the body 10, the -thickness of the sidewall oxide layer 21 is typically in the range oi about 500 to 2,000 38 The thickness of the sidewall oxide layer 21 increases as the reactive ion etching time increases and the etching process progresses below the original surface 10.5 o-f the silicon body 10. The sidewall oxide thickness can thus be controlled by controlling the thickness o-F the gate oxide layer 11 (plus the thickness O:e silicon removed by -the reactive oxygen ion etching) and the time duration of exposure to the reac-tive ion etching. The sidewall oxide layer 21 serves as a spacer to control the distance (of closest approach) ox the source and drain to be formed) from the ga-te region of the field effect transistor being built.
After this reac-tive oxyger. ion etching s-tep has been performed, any remaining exposed portion of the oxide layer 11 is completely removed, as by plasma etching with Freon 23 (a Inixture ox about 96 percen-t by volume CHF,3 with N~13). Advantageously, in order to avoid undesirabLe isotropic etching which would be caused by any mixing ox residual C~F3 witll CL2 in a future repeti-tion oL' the process being described, this plasma e-tching with Freon is performed in a dif-feren-t chamber from that just previously used for the reactive oxygen ion etching. Any remaining thickness ox the organic resist layer 14 is thereafter removed by a standard method, such as treatment with a mixture (about 5:1 by volume) of sulphuric acid and hydrogen peroxide at a tempera-ture typically of about ~5C.
Referring next to FIG. I, platinum silicide is -forrned on the exposed surface of the silicon body 10 and on the gate electrode 12, to form source and drain Schottky barrier platinum silicide electrode contacts 33 and 35 plus a gate electrode platinum silicide metallization layer 3~.
The portion of the body 10 direc-tly underlying the gate electrode 12 constitutes the channel region o-f the first transistor struc-ture. In order to form the platinum silicide, platinum is deposited, as by evaporation, to a thickness of about 150 all over the structure being built, typically at a temperature of about 25 C to room 3~ temperature) and is then sintered, -typically by hea-ting in ~2~
argon and 1 or`2% by volume oxygen for about 30 minutes at about 625C, -to Norm platinum silicide wherever silicon underlies the deposited platinum. Al-terna-tively, sputtering of the platinum onto the heated structure (typically about 600C -to 650C) can be used to eorm -the platinum silicicle directly. The remaining platinum (overlying o,Yide) is then removed, typically by e-tching wi-th aqua regia.
Therea-~ter, a patterned insulating layer 41 is formed on the structure 30 being built (FIG. 5). This insulating layer 41 is typically si.licon dioxide (formed typically ~`rom a mixture ox silane and oxygen) or TEOS
(tetra-ethyl-ortho-silicate, deposited at a tempera-ture less than about 500C) having a thickness Oe typically about 10,000 I, and is formed and pat-terned by conventional chemical vapour deposi-ti.on followed by selec-tive maski.ng and etching thro-lgh windows. Finally, a pa-tterrled metallization .Layer ~2, ~3, and I, SLICII as a.luminium, is applied--typically by evaporation followed by selective masking and etching--~or making metallization contac-ts -to -the platinum silicide electrodes 33, 34 and 35. Thereby, an insulated gate field effect transistor s-tructure 30 (FIG. 5) is iormed. Advantageously, to preserve the Schottky barriers, at no time subsequen-t to the platinum sin~ering step is the structure being built heated above a temperatllre O:e about 500C. An in-termediate layer o-f material--such as doped polysilicon--can also be included between the aluminium metallization and the platinum silicide.
Thus, the sidewall layer 21 serves as a protective mask and spacer to control the closest approach ox -the transistor source (and drain) region with respect to the transistor channel.
Prior -to the deposition of -the platinum to form the platinum silicide electrodes, as an option, significant acceptor impurities can be introduced into the silicon body 10 at its then exposed sureace, thereby to form source 38 and drain z,ones in the body; so that, instead Oe having the g 6 pla-tinum silicide Norm Schot-tky barrier elec-trodes, the platinum silicide forms ohmic -type electrode contacts to the source and drain zones. Moreover, when using metal si.licides--such as cobal-t silicide--that can withs-tand the high temperatures (abou-t 900 degrees C) required for ac-tiva-tion of impurities, impurities can be alternatively implanted through such meta.l silicide elec-trodes 33 and 35 or can be introduced by deposition simultaneously wi-th the metal deposition and then di-ffused by suitable annealing.
Instead of forming platinum silicide electrodes 33, 34 and 35 (FIG. 5), self-aligned impurity zones 57 and 58 for source and drain can be formed (FIG. 6), as by impurity ion implantation. Duling the ion implantation, the polycrystalline silicon gate electrode 12, together with the sidewall oxide layer 21, is used as a sel-f-al.igned mask, which provides an of:ese-t for the implan-ted regions in the sil:icon body 10 flom the gate el.ectrode 12. In such a case, moreover-, a p-type conducti.vi-ty si.l:icon bocly 50 (FIG. I) can be uc;ed in conjunc-tion with n (strongly n--type) conductivity in zones 57 and 58, or making an N-channel -transistor. Also, in such a case the reac-tive oxygen ion etching of the silicon dioxide layer 11 can be terminated some time prior to etch-through to the surface 50.5 of the silicon body 50, and ion implan-tation can then be performed through the remaining exposed thickness ox this oxide layer 11 loca-ted between -the polysilicon layer 12 and -the field oxide layer 13, whereby shallower PN junctions Oe the n--type zones 57 and 58 are iormed with the p--type region of the body 10. A pat-terned TEOS layer 51, source metallization 52, gate metalliza-tion 53, and clrain metallization 54 complete a -transistor device structure 40.
The impurities for zones 57 and 58 for the transistor struc-ture 40 can be introcluced before or after removal of the original gate oxide layer.s-till remaining in regions overlying the portion of the surface 10.5 located between the polysilicon layer 12 and the field oxide layer 13. The 38 metalli.zations 52, 53 and 54 are typically formed by first g depositing doped polycrystalli.ne silicon and then depositing aluminiu~l.
In the device 40 shown in FIG 6, the thickness ox the sidewall oxide layer 21 is advantageously at least 200 I, preferably about 500 I, in order that aster activation ox the impurities by annealing (and consequent di~-~usion o-~ the source and drain zones 57 and 5X), the respective overlying edges oi the gate elec-trode 12 can be located in substantial registry with the respective edges of these source and drain zones, in orde.r to minimize overlap parasitic capacitance. Typically, activation ox the impurities is performed by annealing at about ~00C
or about 30 minu-tes. Again, in accordance with the inven-tion, -this spacing can be rather precisely controlled even though the dimensions are ox submicron size.
It should be understood that although the gate meta.Llizations ~3 and 53 are (symbolically) shown with a contact hole located directly over the ga-te oxide layer lt, ordinarily the contac-t hole is located over -thick Iield oxide, that is, removed ~`rom the ga-te region in a direc-tion perpendicular to the plane ox the drawing.
In a typical example the gate oxide layer 11 is about 250 -thick, the polycrystalline silicon layer 12 is about 3500 thick, the organic layer 14 is typically Hunt's photoresist about 1.8 micron thick, and the silicon dioxide layer 15 is about 1200 thick.
Ordinarily, high-temperature baking of the organic resist layer 14 (200 to 300 C or about 30 to 180 minutes) is advisable to harden the resist so that it is resistant to further processing, such as plasma etching or deiining the polysilicon gate electrode layer 12.
In another example, a structure 70 (FIG. 7) includes a p-type silicon semiconduc-tor body 60 which has a major planar horizontal surface 60.5, -typically oriented parallel to -the plalle (100), upon which has been grown a gate oxide layer 61 and a yield oxide layer 62.
Upon this gate oxide layer 61 is located a polycrystalline 38 silicon layer 63. On top ox this polycrys-talline silicon layer 63 is located an aluminium layer 64, -typically deposited by evaporation to a thickness of abou-t one micron And on top of the aluminium layer 64 is located an organic resis-t layer 65. Further, on top of the resist layer 65 is a pat-terned silicon dioxide layer 66 and a patterned photoresist layer 67 to comple-te -the s-tructure 70 shown in FI&. 7. The structure 70 is thus similar to that shown in FIG. 1 at an earlier stage of the latter's processing, except for the addition of the aluminium layer 64. The patterned silicon dioxide layer 66 can have been pa-tterned, for example, by either plasma etching or reactive ion e-tching with CHF3 gas or Freon 23.
The top surface of -the structure 70 is -then subjec-ted to a reactive ion anisotropic etching with oxygen ions 68 (FIG. 7). This etching with oxygen can be done in -the same chamber previously used to etch the oxide layer 66. For thls purpose, for example pure oxygen (par-tly ioni~ecl) or a gas mixture (partly ionized) O-e oxygel~ and about ~.5 to loo by volume carbon te-tra:rluoride (CF4) is used at a relatively low pressure in a useful range of about 2 to 4 micron l-Ig, typically about 3.5 micron Hg, in conjunction with an RF power in a useful range of about 0.25 to 0.75 watt/cm2, -typically about 0.5 watt/cm2, at a -typical frequency of about 13.56 MHz.
As a result of the con-tinuation of the reactive ion etching after etching through -thy resis-t, aluminium oxide build-up layers 71 form on resulting vertical sidewalls 65.5 (FIG. 8) o-f the aperture thereby formed in the resist layer 65. The thickness of the build-up layers 71 (measured a-t the bo-ttom thereoi) is proportional to the -thickness of aluminium removed by this etching from the aluminium layer 64 as determined by the time duration of the reactive ion etching. Typically about 200 of aluminium is removed at the bottom of -the resulting aper-ture in the resist layer 65 by c,ver-etching with the oxygen ions 68. Nex-t the structure being fabricated (FIG. 8) is subjected to a reactive ion etching, as with 38 Freon 23 (mixture of 96 percent by volumne CHF3 and NH3), in order to remove -the pat-terned silicon dioxide layer 66.
Next, etching with oxygen ions 81 (FIG 9) is resumed and continued until the organic layer 81 is completely removed. Thereby the aluminium layer 64 is exposed in the areas between neighbouring alnminium oxide build-up layers 71, and -typically is ove:r-etched by about 500 (in addi-tion to the previous 200 over-etch by the earlier low pressure reactive ion etching by the oxygen ions 68). This etching of the organic layer and -the previously exposed aluminium with oxygen will. also increase the thickness of the build-up layers 71, typically by a factor of about 3 or I.
`~ext, using these build-up layers 71 as a protective mask against etching, anisotropic ion etching of 15 the exposed portion Oe the aluminium layer 6~, followed by aniso-tropic etching oE the polycrystalline layer 63, brings the structure being eabricated in-to the condi-tion illus-trated in FIG. 10, wherein the aluminium layer 6~ has become a pa-t-terned aluminium layer 9~ an the polycrystalllne silicon layer 63 has become a patterned polycrystalline silicon layer 93, both these patterned polycrystalline silicon layers having a width w determined by the thickness O:e the build-up layers 71.
For example, the anisotropic ion etching of the aluminium layer 64 to form the patterned layer 94 can be performed by using a mix-ture of about 75% by volume boron trichloride (BC13) and 25% chlorine (Cl2) at a pressure o:E
typically about 20 micron Hg, with an RF power density of typically about 0.1 watt/cm2 at a frequency O-e about 13.56 MHz; and the aniso-tropic etching of the polycrystalline silicon layer 63 to form the patterned layer 93 can be performed by using a similar mixture of BCl3 and Cl2 at a pressure O:e typically about 10 micron Hg, an RF power density of typically abou-t 0.06 watt/cm at the frequency o-E about 13.56 MHz. The common width w of the patterned layers 93 and 9~ is typically in -the range of about 1500 to 4000 I.
38 The patterned aluminium layer 9~ is then etched isotropically to remove it completely and thus to remove also -the overlying build-up layers 71. Typically solution etching can be used for thi.s purpose, for example, with an aqueous solution of 16 parts by volume of 85 percent strength phosphoric acid, one part of 70 percent strength nitric acid, one part acetic acid, at about ~5 C :for about two minutes. Thereby the aluminium layer 94 together with the aluminium oxide build-ups 71 are detached and removed from the structure being built (JIG. 11). Advan-tageously, another reac-tive ion etching step wi-th oxygen is carried out to form sidewall build-up layers 111 (JIG. 12) of silicon dioxide on the vertical sidewalls of the remaining portions of -the polysilicon layer 93. Ion implan-tation and activation thereof by annealing to form zones 101, 102, 103 is then carried out to define source, drain, and auxiliary source regions--all having cross sec-tions as indica-ted in FIG. 12 and -top view contours as indicated in FIG. 13. The sidewall layers 111 -thus serve as spacer layers for con-trolling the location of -the closes-t 20 approach o e the source and clrain regions to -the gate region underlying the gate electrode 93. In addition, a gate metallization pad 104 can be added for external gate electrode access to a transistor structure 110 (FIGS. 12 and 13).
As further indicated in FIG. 12, -th.e transistor 110 is metallized by first depositing an insulating layer, such as TEOS (tetra-ethyl-ortho-silicate), pat-terning it -to form a pat-terned insulating layer 112, and applying a metalliza-tion layer which is patterned to :~orm a source electrode 113, a drain electrode 114, and another (auxiliary) source elec-trode 115.
The source electrode 113 contacts the source zone 101 through an aperture 116 in the patterned insu.lating layer 112, and the drain electrode 114 contacts the drain zone 35 102 through a separate aperture 117. The metallization for these electrodes 113, 114 and 115 is typically n-doped polys,ilicon overlaid with al~inium.
38 Al-though -the invention has been described i.n detail in terms of speci-fic embodiments, various modifications can be made withou-t departing from -the scope of the invention. For example, instead of aluminiurn the layer 6~ can be a material such as tan-talum or silicon dioxide--in conjunction with suitable anisotropic etching thereof wi-th CC13F or C~LF3, respectively---to Norm the pat-terned layer ~4. The organic resist layer can also be polyimide designated PIQ, made by ~Iitachi-Ltd~, Tokyo, Japan, or a polyimide designated Pyralin made by E. I.
DuPont DeNemours and Co., Wilmington, Delaware, or a class of novalac-type resists designed HIP made by Philip A. Hunt Chemical Corp., Palisades Parli, New Jersey, or such standard products as KPR, KM~R, AZ 1350, and Polychrome resists. Moreover, the buffered hydrofluoric acid treatrnent (to remove the oxide build-up layer 16 -together wi-th the patterned oxide layer 15 prior to pa-t-terning the polysilicon layer- 12) can be omitted so -that -the oxide builcl-up layer 16 (as well as the patternecl oxide layer 15) irl FIG. 1 rerrlains in place durirlg subsequent etching or patterning of the polysilicon layer 12 and is thereafter removed by solution etching--a particularly use:ful alternative in cases where such subsequent etching of the polysilicon layer is not to be anisotropic. Furthermore in the device of FIGS. 12 and 13 the auxiliary source region 103 and electrode 115 may be omitted.
3~
(E, Kinsbron ~-9) FORMATION OF SU~MICRON FEATURES IN SEMICONDUCTOR
DEVICES.
This invention relates to methods for fabrica-til1g semiconductor devices, and more particularly to methods for forming submicron features of semiconductor integrated ci.rcuit transistor devices.
Sl1ort channel (below abou-t 2 microns) insulated gate :Eie.L(I ef'l'ec-t transistors, also known as metal oxide semiconductor field e:ri'ect transis-tors (~OSl~'~Ts), are desirable or high frequency opera1,ioll, typicAl.Ly above 50 MU In Canadian Patent Applications 373395 and 374257 methods are described for making insulated gate l'ield el'fect transistors with extremely small (500 or less) separations between the extremities of the gate regions and those o.f the source (and drain) regions. The transistors were therefore characterized by clesirably small source-to-channel resistances, The me-thods taught in the aforementioned patent applications include lie formation of thin silicon dioxide layers on the sidewalls of polycrystalline si.Licon gate electrodes by thermal grow-th. The resulting sidewa.ll oxide layer is useful as a spacer .layer for aligning the source relative to the gate region channel, Although ra-ther tbin (as thin as about 200 R) layers of the required sidewall oxide can be :formed by thermal growth of silicon dioxide on the polycrystalline 28 silicon ("polysilicon") ga-te, an undesirable limitation ox' ~2~2~
suGh thermal grow-th s-tems from the Eacts -that oxicle growth on the polysilicon is not easily controlled or uniform, owing to the polycrystalline structure of the underlying polysilicon; (2) at -the same time that the sidewall oxide is being grown, the source-to-drain length of the polysilicon gate elec-trode correspondingly is diminished; so that control over the crucial length of the gate electrode, and hence of the underlying transistor channel, is de-teriorated; (3) the oxide simul-taneously grown over the source and drain regions -force down the top surfaces of -the source and drain to leve],s below the top surface of the channel region by undesirably large amounts (approximately equal to one-hal-f -the thickness ox the grown oxide); and (~) a separate etching step is required for the removal of -the grown oxide L'rom locations overlying the source and drain.
Accordingly, it would be desirable to have a method for defining fea-tures in sem:iconduc-tor dev,ice structures by forming sidewall o~icle layers whicll m:itiga,-tes one or more o:t` these shor-tcomings oE the prior art.
In -the invention as set out in -the claims the sidewall oxide layer is formed by back-sputtering, so -the shortcomings of the prior art, in so far as they are due to forming the sidewall oxide layer my thermal oxidation, are overcome. Furthermore, it is possible to form sidewall oxide layers on materials, such as organic resists, which are not suscep-tible to thermal oxidation.
Some embodimen-ts o-f the inven-tion will now be described by way of example with reference -to the accompanying drawings in which:-FIGS. 1-5 depict in sec-tion various stages o:E a process of maki,ng an insulated gate field effect transistor structure in accordance with the invention;
FIG. 6 depic-ts in section a different insulated gate field effect transistor fabricated in accordance wi-th the invention;
FIGS. 7-12 depict in section various stages of 38 another process of making an insulated ga-te field effect -transistor struc-ture in accordance with the invention;
and FIG. 13 depi.cts a top section view of the transistor structure shown in FIG. 12.
For the sake of clarity, none o-f the drawings is to scale.
Referring -to JIG. 1, a silicon semiconductor body 10, typically O-e n-type conductivity, has a major planar horizontal surface -10.5, -typically a (100) crystallographic plane; and the body has a uniform ne-t significant honor impurity concentration in the neighbourhood of the surface equal to about 1016 impurities per cm3. A relatively thin gate oxide layer 11 of thermally grown silicon dioxide and a relatively -thick f'ield oxide layer 13 are located on complementary portions oi' the sur-face 10.5 in a conventi.onal pattern for forming a mul-tipli.city of similar transis-tor device s-tructures on the major surl'ace 10.5. A poLycrystalline silicon ("po1ysilicon") layer 12 is loca-ted on the exposed top surfaces of the gate oxide layer 11 and the told oxide layer ].3. On top of a limited portion of the polysilicon layer 12 is located a resist layer l typically Hunt's resist ~IPR-20~, and an auxiliary silicon dioxide layer 15.
Both layers l and 15 can have been previously patterned in accordance with, for example, the tri-level process described by J.M. Moran and D. Maydan in an article entitled "High Resolution, Steep Pro-file, Resist Patterns" published in Bell System TechnicaL Journal, 30 Vol. 58, pp. 1027-1036 (1979). As a result of this tri-level process, which utilizes reac-tive oxygen ion etching to pattern the resist layer l sidewall build-up layers 16 of silicon dioxide form on the vertical sidewalls o-f the patterned resis-t layer l during the las-t phase of -this reactive oxygen ion etching (when p~r-tions of the polysilicon layer 12 become exposed and, after being physically back-spu-t-tered, react with the oxygen ions).
38 The wid-th of the l.ayers l and 15 as -thus patterned is a _ typically about 1 or 2 micron.
The oxicle build-up layer 16 together with -the patterned oxide layer 15 are preferably then bo-th comple-tely removed by a room-temperature treatmen-t wi-th a solution of buffered hydrofluoric acid (NH4F and HF in typically a 30:1 molar ratio). Next, us:ing the pat-terned resist layer 14 as a protective mask, the struc-ture of FIG. 1 is placed in a suitable chamber and subjected to anisotropic etching with chlorine gas, at a pressure of -typically about 10 micron Hg, with an RF power density ox typically about 0.1 watt/cm , and an RF frequency of about 13.56 MHz. By "anisotropic" e-tching is meant that substantially vertical sidewalls are formed in -the etched material at locations underlying edges ox any protective mask used during the etching, that is, at intersections Oe regions O:e etched and non-e-tched ma-terial. Thereby the polysilicon Iayer 12 is pa-tterned (FIG. 2) to serve as a polysil.icon gate electrode layer O:e predetermined width, typically about 1 to 2 rnicron, with substant:ial.ly vertical sidewalls 12.5 due -to -the anisotlopy Oe -the chlorine etching.
The top suriace of the resulting structure shown in FIG. 2 is then subjected (advantageously in the same chamber used for the previous chlorine ion etchingstep) to a vertical bombardment of oxygen ions 17 suitable for anisotropically reactively ion etching the ga-te oxide layer 11. Thereby a sidewall silicon dioxide layer 21 (FIG. 3) is formed on -the vertical sidewalls 12.5 of -the ga-te electrode layer 12 (as well as on resulting sidewalls of the gate oxide layer 11). Preferably, in order to ensure complete removal of -the exposed por-tions of the silicon dioxide layer 11 a-t regions overlying suture source and drain zones, ther~active ion etching is carried out for a su-fficient time that about 15 A of silicon -prom the body 10 is removed at the exposed portions of the surface 10.5 underlying the areas between the field oxide and the gate electrode. During -this reactive ion etching 38 of the gate oxide, a top portion of the resist layer 14 is simultaneously also removed.
By using the same chamber lor the oxygen ion etching a previously used for -the chlorine ion etching, residues of chlorine are automa-tically removed -from the chamber during the oxygen ion e-tching.
The oxygen reac-tive ion e-tching ox the exposed portion of the silicon dioxide layer 11 is performed, for example, in a chamber containing pure oxygen (partially ionized) or a gas mixture (partially ionized) of oxygen and abou-t 0.5 percent to 1.0 percent by volume carbon tetrafluoride (C~4). For anisotropy of the etching, a relatively low oxygen pressure is used, ordinarily in the useful range of about 2 to micron Hg, with a relatively higher R~ power densi-ty, ordinarily in the useful range o-f about 0.25 to 0.75 watt/cm2 with an RF frequency of typically about 13,56 MHz.
Durillg -this reac-tive oxygen ion etching of the oxide layer 11, :it is believed -that the oxygen ions react wi-th -the sili.con which is back-sputtered prom -the exposed portion o-f -this silicon dioxide layer 11 (and subsequently from the exposed portion of the silicon body 10) to form a plasma from which -the sidewall silicon dioxide layer 21 (FIG. 3) is deposited on the sidewall 12.5 of the ga-te elec-trode layer 12. On the other hand, it may be that a transport O:e silicon and oxygen from the sil.icon dioxide layer 11 to eorm the sidewall oxide layer 21 can be performed by a bombardment with ions o-ther -than oxygen.
In cases of only partially etching the portion of the oxide layer 11 overlying the body 10 between the 30 polysilicon gate layer 12 and the field oxide layer 13J the sidewall oxide layer 21 can be ox thickness (measured at the bottom) as low as about 50 I, and in any event is ordinarily in the range of bout 50 -to 500 I. On the other hand, in cases of over-etching this oxide layer 11 and e-tching into underl.ying silicon of the body 10, the -thickness of the sidewall oxide layer 21 is typically in the range oi about 500 to 2,000 38 The thickness of the sidewall oxide layer 21 increases as the reactive ion etching time increases and the etching process progresses below the original surface 10.5 o-f the silicon body 10. The sidewall oxide thickness can thus be controlled by controlling the thickness o-F the gate oxide layer 11 (plus the thickness O:e silicon removed by -the reactive oxygen ion etching) and the time duration of exposure to the reac-tive ion etching. The sidewall oxide layer 21 serves as a spacer to control the distance (of closest approach) ox the source and drain to be formed) from the ga-te region of the field effect transistor being built.
After this reac-tive oxyger. ion etching s-tep has been performed, any remaining exposed portion of the oxide layer 11 is completely removed, as by plasma etching with Freon 23 (a Inixture ox about 96 percen-t by volume CHF,3 with N~13). Advantageously, in order to avoid undesirabLe isotropic etching which would be caused by any mixing ox residual C~F3 witll CL2 in a future repeti-tion oL' the process being described, this plasma e-tching with Freon is performed in a dif-feren-t chamber from that just previously used for the reactive oxygen ion etching. Any remaining thickness ox the organic resist layer 14 is thereafter removed by a standard method, such as treatment with a mixture (about 5:1 by volume) of sulphuric acid and hydrogen peroxide at a tempera-ture typically of about ~5C.
Referring next to FIG. I, platinum silicide is -forrned on the exposed surface of the silicon body 10 and on the gate electrode 12, to form source and drain Schottky barrier platinum silicide electrode contacts 33 and 35 plus a gate electrode platinum silicide metallization layer 3~.
The portion of the body 10 direc-tly underlying the gate electrode 12 constitutes the channel region o-f the first transistor struc-ture. In order to form the platinum silicide, platinum is deposited, as by evaporation, to a thickness of about 150 all over the structure being built, typically at a temperature of about 25 C to room 3~ temperature) and is then sintered, -typically by hea-ting in ~2~
argon and 1 or`2% by volume oxygen for about 30 minutes at about 625C, -to Norm platinum silicide wherever silicon underlies the deposited platinum. Al-terna-tively, sputtering of the platinum onto the heated structure (typically about 600C -to 650C) can be used to eorm -the platinum silicicle directly. The remaining platinum (overlying o,Yide) is then removed, typically by e-tching wi-th aqua regia.
Therea-~ter, a patterned insulating layer 41 is formed on the structure 30 being built (FIG. 5). This insulating layer 41 is typically si.licon dioxide (formed typically ~`rom a mixture ox silane and oxygen) or TEOS
(tetra-ethyl-ortho-silicate, deposited at a tempera-ture less than about 500C) having a thickness Oe typically about 10,000 I, and is formed and pat-terned by conventional chemical vapour deposi-ti.on followed by selec-tive maski.ng and etching thro-lgh windows. Finally, a pa-tterrled metallization .Layer ~2, ~3, and I, SLICII as a.luminium, is applied--typically by evaporation followed by selective masking and etching--~or making metallization contac-ts -to -the platinum silicide electrodes 33, 34 and 35. Thereby, an insulated gate field effect transistor s-tructure 30 (FIG. 5) is iormed. Advantageously, to preserve the Schottky barriers, at no time subsequen-t to the platinum sin~ering step is the structure being built heated above a temperatllre O:e about 500C. An in-termediate layer o-f material--such as doped polysilicon--can also be included between the aluminium metallization and the platinum silicide.
Thus, the sidewall layer 21 serves as a protective mask and spacer to control the closest approach ox -the transistor source (and drain) region with respect to the transistor channel.
Prior -to the deposition of -the platinum to form the platinum silicide electrodes, as an option, significant acceptor impurities can be introduced into the silicon body 10 at its then exposed sureace, thereby to form source 38 and drain z,ones in the body; so that, instead Oe having the g 6 pla-tinum silicide Norm Schot-tky barrier elec-trodes, the platinum silicide forms ohmic -type electrode contacts to the source and drain zones. Moreover, when using metal si.licides--such as cobal-t silicide--that can withs-tand the high temperatures (abou-t 900 degrees C) required for ac-tiva-tion of impurities, impurities can be alternatively implanted through such meta.l silicide elec-trodes 33 and 35 or can be introduced by deposition simultaneously wi-th the metal deposition and then di-ffused by suitable annealing.
Instead of forming platinum silicide electrodes 33, 34 and 35 (FIG. 5), self-aligned impurity zones 57 and 58 for source and drain can be formed (FIG. 6), as by impurity ion implantation. Duling the ion implantation, the polycrystalline silicon gate electrode 12, together with the sidewall oxide layer 21, is used as a sel-f-al.igned mask, which provides an of:ese-t for the implan-ted regions in the sil:icon body 10 flom the gate el.ectrode 12. In such a case, moreover-, a p-type conducti.vi-ty si.l:icon bocly 50 (FIG. I) can be uc;ed in conjunc-tion with n (strongly n--type) conductivity in zones 57 and 58, or making an N-channel -transistor. Also, in such a case the reac-tive oxygen ion etching of the silicon dioxide layer 11 can be terminated some time prior to etch-through to the surface 50.5 of the silicon body 50, and ion implan-tation can then be performed through the remaining exposed thickness ox this oxide layer 11 loca-ted between -the polysilicon layer 12 and -the field oxide layer 13, whereby shallower PN junctions Oe the n--type zones 57 and 58 are iormed with the p--type region of the body 10. A pat-terned TEOS layer 51, source metallization 52, gate metalliza-tion 53, and clrain metallization 54 complete a -transistor device structure 40.
The impurities for zones 57 and 58 for the transistor struc-ture 40 can be introcluced before or after removal of the original gate oxide layer.s-till remaining in regions overlying the portion of the surface 10.5 located between the polysilicon layer 12 and the field oxide layer 13. The 38 metalli.zations 52, 53 and 54 are typically formed by first g depositing doped polycrystalli.ne silicon and then depositing aluminiu~l.
In the device 40 shown in FIG 6, the thickness ox the sidewall oxide layer 21 is advantageously at least 200 I, preferably about 500 I, in order that aster activation ox the impurities by annealing (and consequent di~-~usion o-~ the source and drain zones 57 and 5X), the respective overlying edges oi the gate elec-trode 12 can be located in substantial registry with the respective edges of these source and drain zones, in orde.r to minimize overlap parasitic capacitance. Typically, activation ox the impurities is performed by annealing at about ~00C
or about 30 minu-tes. Again, in accordance with the inven-tion, -this spacing can be rather precisely controlled even though the dimensions are ox submicron size.
It should be understood that although the gate meta.Llizations ~3 and 53 are (symbolically) shown with a contact hole located directly over the ga-te oxide layer lt, ordinarily the contac-t hole is located over -thick Iield oxide, that is, removed ~`rom the ga-te region in a direc-tion perpendicular to the plane ox the drawing.
In a typical example the gate oxide layer 11 is about 250 -thick, the polycrystalline silicon layer 12 is about 3500 thick, the organic layer 14 is typically Hunt's photoresist about 1.8 micron thick, and the silicon dioxide layer 15 is about 1200 thick.
Ordinarily, high-temperature baking of the organic resist layer 14 (200 to 300 C or about 30 to 180 minutes) is advisable to harden the resist so that it is resistant to further processing, such as plasma etching or deiining the polysilicon gate electrode layer 12.
In another example, a structure 70 (FIG. 7) includes a p-type silicon semiconduc-tor body 60 which has a major planar horizontal surface 60.5, -typically oriented parallel to -the plalle (100), upon which has been grown a gate oxide layer 61 and a yield oxide layer 62.
Upon this gate oxide layer 61 is located a polycrystalline 38 silicon layer 63. On top ox this polycrys-talline silicon layer 63 is located an aluminium layer 64, -typically deposited by evaporation to a thickness of abou-t one micron And on top of the aluminium layer 64 is located an organic resis-t layer 65. Further, on top of the resist layer 65 is a pat-terned silicon dioxide layer 66 and a patterned photoresist layer 67 to comple-te -the s-tructure 70 shown in FI&. 7. The structure 70 is thus similar to that shown in FIG. 1 at an earlier stage of the latter's processing, except for the addition of the aluminium layer 64. The patterned silicon dioxide layer 66 can have been pa-tterned, for example, by either plasma etching or reactive ion e-tching with CHF3 gas or Freon 23.
The top surface of -the structure 70 is -then subjec-ted to a reactive ion anisotropic etching with oxygen ions 68 (FIG. 7). This etching with oxygen can be done in -the same chamber previously used to etch the oxide layer 66. For thls purpose, for example pure oxygen (par-tly ioni~ecl) or a gas mixture (partly ionized) O-e oxygel~ and about ~.5 to loo by volume carbon te-tra:rluoride (CF4) is used at a relatively low pressure in a useful range of about 2 to 4 micron l-Ig, typically about 3.5 micron Hg, in conjunction with an RF power in a useful range of about 0.25 to 0.75 watt/cm2, -typically about 0.5 watt/cm2, at a -typical frequency of about 13.56 MHz.
As a result of the con-tinuation of the reactive ion etching after etching through -thy resis-t, aluminium oxide build-up layers 71 form on resulting vertical sidewalls 65.5 (FIG. 8) o-f the aperture thereby formed in the resist layer 65. The thickness of the build-up layers 71 (measured a-t the bo-ttom thereoi) is proportional to the -thickness of aluminium removed by this etching from the aluminium layer 64 as determined by the time duration of the reactive ion etching. Typically about 200 of aluminium is removed at the bottom of -the resulting aper-ture in the resist layer 65 by c,ver-etching with the oxygen ions 68. Nex-t the structure being fabricated (FIG. 8) is subjected to a reactive ion etching, as with 38 Freon 23 (mixture of 96 percent by volumne CHF3 and NH3), in order to remove -the pat-terned silicon dioxide layer 66.
Next, etching with oxygen ions 81 (FIG 9) is resumed and continued until the organic layer 81 is completely removed. Thereby the aluminium layer 64 is exposed in the areas between neighbouring alnminium oxide build-up layers 71, and -typically is ove:r-etched by about 500 (in addi-tion to the previous 200 over-etch by the earlier low pressure reactive ion etching by the oxygen ions 68). This etching of the organic layer and -the previously exposed aluminium with oxygen will. also increase the thickness of the build-up layers 71, typically by a factor of about 3 or I.
`~ext, using these build-up layers 71 as a protective mask against etching, anisotropic ion etching of 15 the exposed portion Oe the aluminium layer 6~, followed by aniso-tropic etching oE the polycrystalline layer 63, brings the structure being eabricated in-to the condi-tion illus-trated in FIG. 10, wherein the aluminium layer 6~ has become a pa-t-terned aluminium layer 9~ an the polycrystalllne silicon layer 63 has become a patterned polycrystalline silicon layer 93, both these patterned polycrystalline silicon layers having a width w determined by the thickness O:e the build-up layers 71.
For example, the anisotropic ion etching of the aluminium layer 64 to form the patterned layer 94 can be performed by using a mix-ture of about 75% by volume boron trichloride (BC13) and 25% chlorine (Cl2) at a pressure o:E
typically about 20 micron Hg, with an RF power density of typically about 0.1 watt/cm2 at a frequency O-e about 13.56 MHz; and the aniso-tropic etching of the polycrystalline silicon layer 63 to form the patterned layer 93 can be performed by using a similar mixture of BCl3 and Cl2 at a pressure O:e typically about 10 micron Hg, an RF power density of typically abou-t 0.06 watt/cm at the frequency o-E about 13.56 MHz. The common width w of the patterned layers 93 and 9~ is typically in -the range of about 1500 to 4000 I.
38 The patterned aluminium layer 9~ is then etched isotropically to remove it completely and thus to remove also -the overlying build-up layers 71. Typically solution etching can be used for thi.s purpose, for example, with an aqueous solution of 16 parts by volume of 85 percent strength phosphoric acid, one part of 70 percent strength nitric acid, one part acetic acid, at about ~5 C :for about two minutes. Thereby the aluminium layer 94 together with the aluminium oxide build-ups 71 are detached and removed from the structure being built (JIG. 11). Advan-tageously, another reac-tive ion etching step wi-th oxygen is carried out to form sidewall build-up layers 111 (JIG. 12) of silicon dioxide on the vertical sidewalls of the remaining portions of -the polysilicon layer 93. Ion implan-tation and activation thereof by annealing to form zones 101, 102, 103 is then carried out to define source, drain, and auxiliary source regions--all having cross sec-tions as indica-ted in FIG. 12 and -top view contours as indicated in FIG. 13. The sidewall layers 111 -thus serve as spacer layers for con-trolling the location of -the closes-t 20 approach o e the source and clrain regions to -the gate region underlying the gate electrode 93. In addition, a gate metallization pad 104 can be added for external gate electrode access to a transistor structure 110 (FIGS. 12 and 13).
As further indicated in FIG. 12, -th.e transistor 110 is metallized by first depositing an insulating layer, such as TEOS (tetra-ethyl-ortho-silicate), pat-terning it -to form a pat-terned insulating layer 112, and applying a metalliza-tion layer which is patterned to :~orm a source electrode 113, a drain electrode 114, and another (auxiliary) source elec-trode 115.
The source electrode 113 contacts the source zone 101 through an aperture 116 in the patterned insu.lating layer 112, and the drain electrode 114 contacts the drain zone 35 102 through a separate aperture 117. The metallization for these electrodes 113, 114 and 115 is typically n-doped polys,ilicon overlaid with al~inium.
38 Al-though -the invention has been described i.n detail in terms of speci-fic embodiments, various modifications can be made withou-t departing from -the scope of the invention. For example, instead of aluminiurn the layer 6~ can be a material such as tan-talum or silicon dioxide--in conjunction with suitable anisotropic etching thereof wi-th CC13F or C~LF3, respectively---to Norm the pat-terned layer ~4. The organic resist layer can also be polyimide designated PIQ, made by ~Iitachi-Ltd~, Tokyo, Japan, or a polyimide designated Pyralin made by E. I.
DuPont DeNemours and Co., Wilmington, Delaware, or a class of novalac-type resists designed HIP made by Philip A. Hunt Chemical Corp., Palisades Parli, New Jersey, or such standard products as KPR, KM~R, AZ 1350, and Polychrome resists. Moreover, the buffered hydrofluoric acid treatrnent (to remove the oxide build-up layer 16 -together wi-th the patterned oxide layer 15 prior to pa-t-terning the polysilicon layer- 12) can be omitted so -that -the oxide builcl-up layer 16 (as well as the patternecl oxide layer 15) irl FIG. 1 rerrlains in place durirlg subsequent etching or patterning of the polysilicon layer 12 and is thereafter removed by solution etching--a particularly use:ful alternative in cases where such subsequent etching of the polysilicon layer is not to be anisotropic. Furthermore in the device of FIGS. 12 and 13 the auxiliary source region 103 and electrode 115 may be omitted.
3~
Claims (27)
1. A method of forming a feature in a semiconductor device including forming a sidewall oxide layer on a substantially vertical sidewall of a first layer located over a second layer, the sidewall oxide layer defining the feature, wherein the sidewall oxide layer is formed by reactive ion etching the second layer so as to form the sidewall oxide layer by back-sputtering.
2. A method as claimed in claim 1 wherein the reactive ion etching is carried out using oxygen ions.
3. A method as claimed in claim 1 wherein the second layer is of silicon dioxide.
4. A method as claimed in claim 3 wherein the first layer is of polycrystalline silicon.
5. A method as claimed in claim 4 wherein the sidewall oxide constitutes a protective insulating layer for the sidewalls of the polycrystalline silicon gate of a field effect transistor.
6. A method as claimed in claim 2 wherein the second layer is of metal.
7. A method as claimed in claim 6 wherein the metal is aluminum.
8. A method as claimed in claim 6 wherein the first layer is of an organic resist.
9. A method as claimed in claim 8 wherein the second layer is formed over a third layer and, subsequently to forming the sidewall oxide layer, the first layer is removed, leaving the sidewall oxide layer, which is used as a mask to form the feature from the third layer.
10. A method as claimed in claim 9 wherein the feature is the gate of a field effect transistor.
11. A method for fabricating a semiconductor structure comprising the steps of forming, overlying a horizontal surface in a structure, a layer having a vertical sidewall at the bottom of which is located an exposed surface of first material, said first material containing atoms of a first kind, and forming on the vertical sidewall a masking layer of predetermined submicron horizontal thickness dimension, and using the masking layer to define a feature of the structure, CHARACTERIZED IN THAT
the masking layer is formed by bombarding said horizontal surface portion with oxygen for a predetermined time to react with said first material, whereby the masking layer, comprising a chemical compound of oxygen and said atoms, is deposited on the vertical sidewall to the predetermined submicron thickness.
the masking layer is formed by bombarding said horizontal surface portion with oxygen for a predetermined time to react with said first material, whereby the masking layer, comprising a chemical compound of oxygen and said atoms, is deposited on the vertical sidewall to the predetermined submicron thickness.
12. The method of claim 11 FURTHER CHARACTERIZED
IN THAT the first material is essentially a metal.
IN THAT the first material is essentially a metal.
13. The method of claim 12 in which said metal is essentially aluminum.
14. The method of claim 11 FURTHER CHARACTERIZED
IN THAT said first material is essentially silicon dioxide.
IN THAT said first material is essentially silicon dioxide.
15. A method for forming a submicron feature by forming a sidewall oxide layer on a vertical sidewall of a first layer of first material located on a limited portion of a second layer of second material, different from the first, said second layer located over a horizontal major surface of a semiconductor body, CHARACTERIZED BY the step of reactive ion etching said second layer to form by back-sputtering of said second material a sidewall oxide layer on the vertical sidewall of the first layer in order to define said feature.
16. The method of claim 15 in which the reactive ion etching is performed by bombardment with oxygen, said first layer is essentially a polycrystalline silicon layer, said body is essentially silicon, and said second layer is essentially silicon dioxide.
17. The method of claim 15 in which the reactive ion etching is performed by bombardment with oxygen, the body is essentially silicon, the first layer is essentially organic resist, and said second layer is essentially a layer of metal.
18. The method of claim 17, in which said second layer is separated from said major surface of the body by a layer comprising a polycrystalline silicon layer.
19. The method of claim 18 in which said polycrystal-line silicon layer is separated from said major surface of the body by a silicon dioxide layer.
20. The method of claim 19 in which the layer of metal is essentially aluminum.
21. The method of claim 17 in which the layer of metal is essentially aluminum.
22. The method of claim 19 FURTHER CHARACTERIZED BY
the step of removing said first layer whereby at least a portion of said sidewall oxide layer remains overlying said major surface of the body.
the step of removing said first layer whereby at least a portion of said sidewall oxide layer remains overlying said major surface of the body.
23. The method of claim 22 FURTHER CHARACTERIZED BY
the step of selectively anisotropically etching said metal layer and said polycrystalline layer using the sidewall oxide later as a protective mask, followed by the step of etching to remove completely said metal layer whereby said sidewall oxide layer is also removed and portions of said polycrystal-line silicon layer remain only at those regions thereof essentially underlying said sidewall oxide layer prior to removal thereof.
the step of selectively anisotropically etching said metal layer and said polycrystalline layer using the sidewall oxide later as a protective mask, followed by the step of etching to remove completely said metal layer whereby said sidewall oxide layer is also removed and portions of said polycrystal-line silicon layer remain only at those regions thereof essentially underlying said sidewall oxide layer prior to removal thereof.
24. A method for fabricating an insulated gate field effect transistor in which a gate oxide layer is grown on a major horizontal surface of a silicon body and a polycrystalline silicon gate electrode having a vertical sidewall is formed on a limited portion of the surface of the gate oxide layer CHARACTERIZED BY THE STEP OF forming an insulating layer on said sidewall by subjecting an exposed portion of the gate oxide layer, complementary to said limited portion, to reactive ion etching with oxygen to expose the major surface of the body underlying said complementary portion.
25. The method of claim 24 CHARACTERIZED FURTHER BY
the step of using said insulating layer on said sidewall as a protective mask.
the step of using said insulating layer on said sidewall as a protective mask.
26. The method of claim 25 in which said protective mask prevents a chemical reaction of the polycrystalline silicon of the gate electrode at said sidewall thereof with a metal which is deposited on said protective layer and on a neighborhood thereof to form a silicide of said metal at said exposed portion of the major surface of the body.
27. The method of claim 24, 25, or 26 FURTHER
CHARACTERIZED BY the step of implanting impurity ions into the exposed portion of the surface of the body to form implanted regions therein, whereby said insulating layer on said sidewall acts as a protective mask against said implanting in order to provide an offset for the implanted regions.
CHARACTERIZED BY the step of implanting impurity ions into the exposed portion of the surface of the body to form implanted regions therein, whereby said insulating layer on said sidewall acts as a protective mask against said implanting in order to provide an offset for the implanted regions.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/328,368 US4432132A (en) | 1981-12-07 | 1981-12-07 | Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features |
| US328,368 | 1981-12-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1201216A true CA1201216A (en) | 1986-02-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000416587A Expired CA1201216A (en) | 1981-12-07 | 1982-11-29 | Formation of submicron features in semiconductor devices |
Country Status (8)
| Country | Link |
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| US (1) | US4432132A (en) |
| JP (1) | JPS58106833A (en) |
| CA (1) | CA1201216A (en) |
| DE (1) | DE3245276A1 (en) |
| FR (1) | FR2517881B1 (en) |
| GB (1) | GB2110876B (en) |
| IT (1) | IT1153379B (en) |
| NL (1) | NL8204721A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4287660A (en) * | 1974-05-21 | 1981-09-08 | U.S. Philips Corporation | Methods of manufacturing semiconductor devices |
| US3920483A (en) * | 1974-11-25 | 1975-11-18 | Ibm | Method of ion implantation through a photoresist mask |
| US4037307A (en) * | 1975-03-21 | 1977-07-26 | Bell Telephone Laboratories, Incorporated | Methods for making transistor structures |
| DE2526382C3 (en) * | 1975-06-13 | 1979-10-25 | Philips Patentverwaltung Gmbh, 2000 Hamburg | Cathode sputtering process for the production of etched structures |
| DE2964810D1 (en) * | 1978-07-29 | 1983-03-24 | Fujitsu Ltd | A method of coating side walls of semiconductor devices |
| JPS5539647A (en) * | 1978-09-12 | 1980-03-19 | Nec Corp | Ion etching |
| US4234362A (en) * | 1978-11-03 | 1980-11-18 | International Business Machines Corporation | Method for forming an insulator between layers of conductive material |
| US4211582A (en) * | 1979-06-28 | 1980-07-08 | International Business Machines Corporation | Process for making large area isolation trenches utilizing a two-step selective etching technique |
| US4343082A (en) * | 1980-04-17 | 1982-08-10 | Bell Telephone Laboratories, Incorporated | Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device |
| US4356623A (en) * | 1980-09-15 | 1982-11-02 | Texas Instruments Incorporated | Fabrication of submicron semiconductor devices |
| US4343677A (en) * | 1981-03-23 | 1982-08-10 | Bell Telephone Laboratories, Incorporated | Method for patterning films using reactive ion etching thereof |
-
1981
- 1981-12-07 US US06/328,368 patent/US4432132A/en not_active Expired - Fee Related
-
1982
- 1982-11-29 CA CA000416587A patent/CA1201216A/en not_active Expired
- 1982-12-02 FR FR8220195A patent/FR2517881B1/en not_active Expired
- 1982-12-03 GB GB08234496A patent/GB2110876B/en not_active Expired
- 1982-12-06 IT IT24641/82A patent/IT1153379B/en active
- 1982-12-06 NL NL8204721A patent/NL8204721A/en not_active Application Discontinuation
- 1982-12-07 DE DE19823245276 patent/DE3245276A1/en not_active Withdrawn
- 1982-12-07 JP JP57213448A patent/JPS58106833A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| FR2517881B1 (en) | 1986-03-21 |
| IT1153379B (en) | 1987-01-14 |
| NL8204721A (en) | 1983-07-01 |
| IT8224641A1 (en) | 1984-06-06 |
| IT8224641A0 (en) | 1982-12-06 |
| GB2110876B (en) | 1985-10-02 |
| JPS58106833A (en) | 1983-06-25 |
| DE3245276A1 (en) | 1983-06-09 |
| US4432132A (en) | 1984-02-21 |
| GB2110876A (en) | 1983-06-22 |
| FR2517881A1 (en) | 1983-06-10 |
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