CA1202121A - Photolithographic process for fabricating thin film transistors - Google Patents
Photolithographic process for fabricating thin film transistorsInfo
- Publication number
- CA1202121A CA1202121A CA000432208A CA432208A CA1202121A CA 1202121 A CA1202121 A CA 1202121A CA 000432208 A CA000432208 A CA 000432208A CA 432208 A CA432208 A CA 432208A CA 1202121 A CA1202121 A CA 1202121A
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- Prior art keywords
- layer
- portions
- insulator
- insulator layer
- forming
- Prior art date
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- Expired
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000012212 insulator Substances 0.000 claims abstract description 68
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 230000000873 masking effect Effects 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 19
- 239000010408 film Substances 0.000 claims description 18
- 239000002131 composite material Substances 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 16
- 238000012545 processing Methods 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 8
- 239000004973 liquid crystal related substance Substances 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 238000009740 moulding (composite fabrication) Methods 0.000 claims 15
- 239000000126 substance Substances 0.000 claims 1
- 238000003491 array Methods 0.000 abstract description 9
- 238000011109 contamination Methods 0.000 abstract description 6
- 238000010276 construction Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 95
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 24
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 14
- 239000000463 material Substances 0.000 description 12
- 235000012239 silicon dioxide Nutrition 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 12
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 10
- 239000000654 additive Substances 0.000 description 9
- 230000000996 additive effect Effects 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 7
- 229910052759 nickel Inorganic materials 0.000 description 7
- 230000008021 deposition Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- GPYPVKIFOKLUGD-UHFFFAOYSA-N gold indium Chemical compound [In].[Au] GPYPVKIFOKLUGD-UHFFFAOYSA-N 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 206010013710 Drug interaction Diseases 0.000 description 1
- 241000402754 Erythranthe moschata Species 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 241000894007 species Species 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000007704 wet chemistry method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/913—Diverse treatments performed in unitary chamber
Abstract
ABSTRACT
A photolithographic method for fabricating thin film transistors and thin film transistor arrays in which the contamination vulnerable semi-conductor-insulator interfaces are formed in a single vacuum pump-down operation. To minimize step coverage problems, quasi-planar construction is employed to provide a planar substructure for receipt of the deposited thin semiconductor layer.
A photolithographic method for fabricating thin film transistors and thin film transistor arrays in which the contamination vulnerable semi-conductor-insulator interfaces are formed in a single vacuum pump-down operation. To minimize step coverage problems, quasi-planar construction is employed to provide a planar substructure for receipt of the deposited thin semiconductor layer.
Description
PHOTOLIT~IOCIRAPHIC PE~OCESS FOR IiA13I~ICATING
THIN FILM T~ANSIS'rORS
E~CKG3~OUND OF TME INVENTION
This invention broadly relates to thin film transistors, thin film transistor arrays~ and to a method of preparing the same. More particularly, the invention concerns a complete photolithographic process for fabricating thin film transistors and thin film transistor arrays in which the critical, andcontamination vulnerable, semiconductor-insulator interfaces are formed in a 10 single vacuum pump-down.
Thin film transistors, and particularly an array of thin film transistors continue to be attractive drivers for active display panels, sueh asthose incorporating liquid crystal or electroluminescent media. Because of the resolution achievable, photolithographic processes are particularly advan-15 tageous in the preparation of the high density thin film transistor arrays needed for such display panels.
It is well known to those practicing this art that the electrical performance and stability of thin film transistors are critically dependent uponthe quality o~ the interfaces between the various layers of material forming
THIN FILM T~ANSIS'rORS
E~CKG3~OUND OF TME INVENTION
This invention broadly relates to thin film transistors, thin film transistor arrays~ and to a method of preparing the same. More particularly, the invention concerns a complete photolithographic process for fabricating thin film transistors and thin film transistor arrays in which the critical, andcontamination vulnerable, semiconductor-insulator interfaces are formed in a 10 single vacuum pump-down.
Thin film transistors, and particularly an array of thin film transistors continue to be attractive drivers for active display panels, sueh asthose incorporating liquid crystal or electroluminescent media. Because of the resolution achievable, photolithographic processes are particularly advan-15 tageous in the preparation of the high density thin film transistor arrays needed for such display panels.
It is well known to those practicing this art that the electrical performance and stability of thin film transistors are critically dependent uponthe quality o~ the interfaces between the various layers of material forming
2~ the devices. Of special importanee are the interfaces between the semi-conductor and adjacent layers. It is also weU known that the quality of these intereaces is greatest when the interfaces are prepared in a single vacuum pump-down operation.
The early efforts to employ a single pump-down technique focused 25 upon the use of a multiple number of shadow masks within a vacuum system in order to deposit the proper shapes of the various component layers of the thin film transistors These early multiple shadow mask processes are not altogether satisfactory, however, because of such problems as mask to mask registration and low resolution.
The problems occasioned by the use of multiple shadow masks are avoided in the process disclosed in U.S. Patent No. 4,331,758 to Luo. In the disclosed process, during a single pump-down, a uniform layer of a semi-conducting material is deposited onto a substrate. Thereafter, without breaking vacuum, a plurality of discrete areas of an insulating material is 35 deposited onto the semiconductor layer through a single shadow mask. Then a uniform layer of a conducting material is deposited over the areas of insulating material and exposed portions of the semiconductive layer~
Yet another seqllence for fabricating thin film transistors with a sirlg1e shadow mask, single pump-down technique is shown in U.S. Patent No. 4,335,161 to Luo. In that process, the open-ing (or openings for formation of thin film transistor arrays) in ~he mask is commensurate in size and shape to -the semiconductor pads to be deposited. This mask is utilized, during a single vacuum pump-down, to deposlt the semi-conductive pad, the source and drain electrodes, and an insu-lating layer over the source and drain electrodes and the exposed portion of the semiconductive pad. The mask is moved in a simple bidirectional (180 reciprocating) manner between the successive deposi-tions of the semiconductor material which forms the transistor pad and the conductive material which forms the two electrical contacts to -the semi-conductor pad.
As suggested hereinabove, photolithographic pattern de-lineation techniques excel over shadow mask techniques in providing the resolutions required to produce thin film transistor arrays suitable for drivers in high quality pictorial devices. Characteristically, such photolitho-graphic techniques employ wet chemistry processes to selec-tively define patterned layers of conductive and insulative materials. Artisans skilled in this area recognize that exposure of the sensitive transistor interfaces to such wet processing results in impurity contamination which degrades the quality of the transistor characteristics.
Commonly assigned U. S. Patent 4,404,731, Michael Poleshuk et al, issued September 20, 1983 discloses a process for overcoming the disadvantages which can arise from exposure of the critical surfaces of the constituent layers of the thin film device to we-t processing. This is achieved through the use of a single vacuum pump-down step in which -the damage sensitive semiconductor is effectively sealed, or encapsulated, against subsequent wet processing. In the intiial steps of this fabrication sequence a gate electrode is formed and covered with a layer of insulator. An addi-tive photoresist mask is then formed for definition of the semiconductor pad. Thereafter, during a single vacuum --2a~
pump-down, layers o-f insula-tor, semiconductor, and conductor (source-drain contac-t) layers are sequentially deposited to form the critical semiconductor-insulator interface and semi-source and drain contacts. During subsequent lift-off removal of the photoresist mask, the conductive contact layer functions as a protective cap over the semiconductor pad, preventing harmful inter-action between the semiconductor and the stripping solution. After mask removal, the thin film transistor is completed by removal of the portion of the contact layer overlying the cons~ucting channel of the semiconductor and definition of the source and drain networkO
It has heretofore been recognized that technological problems are encountered in fabricating multi layered thin film transistors and transistor 5 arrays. In particular, step coverage problems are prevalent when attempting to form electrical contact between circuit elements located at different levels. In one configuration of thin film transistors, Ior example, semi-conductor films extend from the substrate level to source and drain pads on the next adjacent level. The gate oxide and electrode must necessarily follow 10 the contour of the semiconductor films. The additional layers needed to complete the array, i.eO gate structures and crossovers, likewise follow the irregularity of this contour, producing a completed device consisting of a multilayered mesas with varied geometries and individual heights. Coverage of these mesas steps with continuous films of uniform thickness poses difficulties 15 because of the sharply defined vertical edges OI patterns delineated by processing steps such as photolitho~raphic fabrication. A means for over-coming the step coverage prsblems is disclosed in commonly ~qci~rl~, u.s.
Patent 4,~389,481, Mlchael Poleshuk et al, issued June 21, 1983. In the process disclosed therein9 thin film transistors or an array of thin film are 20 formed on a substrate by sequential deposition of a series of layers fabricated such that each element of the transistor structure is disposed in a planar relationship with respect to the next adjacent layer. In accordance with the process9 the deposition of each of the elemental members of the thin film transistoP structures is immediately followed by filling in the valleys between 25 the elemental structures with an insulating material to form a planar surface.
This planar surfa~e, in turn, forms the surface upon which the succeeding planar layer is formed.
SUMMARY OF THE INVENTION
The present invention provides a process which takes advantage of 30 the single vacuum pum~down technique for minimi~ing contamination of the critical thin film transistor interfaces. This single pum~down technique is incorporated into an all photolithographic process, thus realizing the high degree of control and resolution afforded thereby. During the on~pump-down step9 the critical and contamination vulnerable semiconductor-insulator inter-35 faces are formed by sequential deposition of a transistor gate insulator layer,a semiconductor pad, and a top insulator layer. The top insulator serves as a passiYating layer on the free surface of the single gated thin film transistor, or as a top gate insulator in a double gated thin film transistor.
In addition to the one-pump-down formation of critical semi-conductor-insulator interfaces and encapsulation of contamination vulnerable 5 thin film transistor surfaces prior to wet processing, the present technque provides one-pump-down provision of a passivating layer for the free surface of single gated devices and one-pump-down formation of both gate insulator for double gated devices. As well, to minimize step coverage problems, a quasi-planar construction is employed. Thus, to eliminate the need for 10 continuous coverage of the vertical source-drain electrode walls, a planar substructure for the thin semiconductor layer is provided. To further minimi7e contamination, dry plasma etehing is employed to expose the source-drain contact areas on the semiconductor pad.
In accordance with one particularly advantageous embodiment, the 15 fabrication sequence utilizes nickle, ~ minllm oxide, cadmium selenide, silicon dioxide, and indium-gold for the gate electrode, gate insulator, semiconductor, top insulator, and source and drain contacts, respectively.
This sequence is initiated by the formation of a nickle gate electrode on a portion of a surfaee of a substrate by, for example, subtractive photolitho-20 graphic delineation. Without removing the photoresist masks employed todelineate the nickle gate electrode, a planar structure is formed by depositing aluminum oxide over the substrate to a thickness substantially equal to the thickness of the gate electrode. A gate insulator layer is then formed on top of the planar surface. Thereafter, nickle source and drain electrodes (together 25 with electrical bus lines for thin film transistor arrays) are formed on the gate insulator layer by, for example, subtractive processing. Again allowing the subtractive photoresist mask to remain in place, a second planar surface is formed by depositing aluminum oxide fill to a thickness substantially equal to the thickness of the source and drain electrodes (and bus bars). ~or definition 30 of the semiconductor pad, an additive photoresist mask is then formed on top of the second planar surface. The alllminllm oxide passivating layer, cadmium selenide, and silicon dioxide cap layers are then sequentially deposited throughthe apertures in the additive mask during a single vacuum pump-down to form the critical semiconductor-insulator interfaces. During subsequent lift-off 35 removal of the photoresist musk, the silicon dioxide cap protects the semi-conductor pad, preventing harmful interaction between the semiconductor and .~s~
.5_ the strlpping solution, i.e. the solvent per se or ionic species contained therein. After l.ift-off removal of the unwanted ma-terial and d.issolution of the additive resist mask, portions of the silicon dioxide cap are selectively removed to define the tansistor channel length and expose selected portions of -the semiconductor layer for receipt of the indium-gold conductive contacts between the semiconductor and the source and drain elec-trodes. Preferably, these contacts are formed by additive processing.
In defining the transistor channel length, dry etch-ing techniques, e.g. plasma etching, are preferred in lieu of the here-tofore employed wet processing techniques.
Thus, in removing the unprotected portions of the silicon dioxide layer, plasma etching is employed to expose the underlying cadmium selenide for source-drain contact areas. Thereafter, the resist mask is removed with an oxygen plasma.
Various aspects of the invention are as follows:
A method of photolithographically forming a thin film transistor of the type suitable for use as a driver of an element in a liquid crystal display, comprising the steps of: a) forming a gate electrode of a predetermined thick-ness of conductive material on a portion of a surface of a passivating coating on a substrate by subtractive process-ing; b) forming a first insulator layer on the remainin-ing portions of the surface of said substrate coating not occupied by the gate electrode, said insulator layer having a thickness substantially equal to the thickness of said gate electrode to thereby form a first planar surface;
c) forming a uniformally thick gate insulator layer on said first planar surface; d) forming source and drain elec-trodes of predetermined equal thickness of conductive material on selected portions of said gate insulator layer by substactive processing; e) forming a second insulator layer on the remaining portions of the gate insulator ,~
-5a-layer not occupied by said source and drain electrodes, said second insulator layer having a thickness substantial-ly equal. to the thickness of said source and drain elec-trodes to -thereby form a second planar surface; f) Eorm-ing, on said second planar surface, a masking layer havinga predetermlned opening therein exposing a portion of said second planar surface so that portions of said source and drain electrodes and a portion of said second insulator layer between said source and drain electrodes which lie in the second planar surface are exposed; g) sequentially depositing, under continuous vacuum, a third insulator layer, a semiconductor layer, and a fourth insulator layer, respectively, on said masking layer and on the exposed portion of said second planar surface, so -that the portions of the source and drain electrodes and the portion of the second insulator layer therebetween which are exposed through the opening in said masking layer are covered by said sequentially deposited layers without the need fo a spaced, movable shadow mask; h) removing said masking layer and the portions of the third insulator layer, the semiconductor layer, and the fourth insulator layer deposited thereon; i) selectively removing portions of said fourth insula-tor layer to define a transistor channel length and to expose selected portions of said semiconductor layer; and j) selectively forming conductive contacts between the source and drain electrodes and said selected portions of the semiconductor layer.
A method of forming a thin film transistor, comprising the steps of: a) forming a first composite layer on a surface of a substrate, said first composite layer having a substantially planar surface and including a first conduc-tive film pattern defining at least one gate electrode surrounded by a first insulative film pattern; b) deposit-ing a first insulator layer on the planar surface of said first composite layer; c) forming a second composite layer on said fi~st insulator layer, said second composite layer haviny a substantially planar surface and including a second conductive film pattern surrounded by a second 5 insulative film pattern, sald second conductive film pattern defining at least source and drain electrodes; d) forming on said planar surface of said second composite layer a masking layer having at least one predetermined opening therein exposing portions of said source and drain 10 electrodes and said second insulative film pattern between said source and drain electrodes, e) sequentially depositing, under continuous vacuum, a second insulator layer, a semiconductor layer, and a third insulator layer on said masking layer and on the exposed portions of said 15 second composite layer, so that said sequentially deposited layers are formed on the second composite layer without the need of a positionable shadow mask; f) removing said masking layer and the portions of the second insulator layer, the semiconductor layer, and the third insulator 20 layer deposited thereon, g) selectively removing portions of said third insulator to define a transistor channel length and -to expose selected portions of said semi-conductor layers; and; h) selectively forming conductive con-tacts between the source and drain electrodes and said 25 selected portions of said semiconductor layer.
~RIEF DESCRIPTION OF THE DRAWINGS
Figures 1-10 are diagrammatic cross-sectional views of a thin film transistor being fabricated in accordance with a preferred embodiment of the invention as well as 30 a flow chart describing steps within the process.
Figure 11 is a diagrammatic plan view of a transistor fabricated in accordance with the invention and embodied as a driver for an element of a liquid crystal display.
?~
-5c-DESCRIPTION OF THE PREFERRED EMBODIMENT
Figures 1 and 2 illustrate the formation of a gate electrode 12 upon a substrate 10. A broad range of materials may be employed for subs-trate 10, subject to the general llmitation that -the material chosen be insula-tive relative to the material selected for the gate electrode 12. The exact choice of a material for substrate 10 will, of course, depend upon the particular application in which the thin film transis-tor is utilized.
When employed as a driver of an element in the liquid crystal display, as illustrated in Figure 11, for example, substrate 10 would comprise one of the planar glass plates which are typlcally employed to contain the liquid crystal media. In other applications, utility may dictate that substrate 10 be composed of other insulative material, such as ceramics, semiconductors, plastic materials, and the like. Quite satisfactory results have been obtained with the use of a barium aluminium borosilicate compo-sition sold commercially by Corning Glass Works of Corning, N. Y. under the trademark Corning 7059 Glass.
In Figures 1 through 10 such a Corning 7059 substrate is illustrated with an insulating (aluminum :
oxide) coating 11 to passivate the same.
A subtractive processing technique is utilized to form the gate electrode. In a conventional manner, this method begins with the deposition of a nickel film layer 13 on the aluminum oxide coated substrate. A covering 5 layer of resist material is then applied to the upper surface of the nickel film layer 13. Thereafter, in accordance with well known photolithographic techniques, the resist layer is processed into a subtractive mask by the steps of exposure, development, and removal of selectively patterned areas thereof.
The nickel gate electrode 12 is then formed by etching away portions of the 10 nickel film layer 13 which are not protected by the overlying photoresist mask 14.
In the ne2ct step, as illustrated in Figure 3, the resist mask 1~ is left in place and employed in the formation of a planar structure. As illustrated, this is accomplished by depositing a layer of aluminum oxide over 15 the substrate to fill in spaces adjacent the gate electrode 12. If an array of thin film transistors was being formed, this step would encompass filling all spaces between adjacent gate electrodes of the respective transistors. In a preferred process, a 500 Angstrom layer of nickel is employed in the formation of the gate electrode 12. Thus, the ~ minllm oxide fill layer 15 would be 2~ deposited to a thickness of 500 Angstrom. Suitable solvents are then utilized to dissolve away the resist mask 1~ and lift-off unwanted areas of the aluminum oxide fill layer 15. This produces the first planar surface of this process, as shown most clearly by the arrow drawn from flow chart box A of Figure 4. A blanket gate insulator (aluminum oxide) layer 16 is then deposited 25 to a thickness of 4,500 Angstrom onto the first planar surface as illustrated in Figure ~. To begin delineation of the source and drain electrodes (and the bus lines in a thin film transistor array) a uniform layer of nickel 17 is deposited to a thickness of 500 Angstrom onto the gate insulator layer 16.
Again employing subtractive processing, the source and drain 30 electrodes (and electrical bus lines for an array) are formed. As with the subtractive process described in conjunction with forming the first planar layer (Figures 2 and 3), the subtractive resist maslc remains over the conductive materials (here the nickel source and drain electrodes, 18 and 19, respectively). With this mask in place, an additional aluminum oxide layer 20 35 is deposited to fill the spaces between the source and drain electrodes (and bus lines for arrays). Subsequent removal of the resist mask and unwanted _ I _ aluminum oxide overlying the aame forms the second planar surface, generaUy indicated 21 in Figure 5.
Thereafter, an additive resist mask 22 is prepared on top of the second planar surface 21 as shown in Figure ~. The windows in the resist mask correspond to the desired dimensions of the semieonductor pad for the thin film transistor. The additive mask 22 is then used for depositing, in successivesequence, layers of insulator 23 ~200 Angstrom of aluminum oxide), semicon-ductor 24 (500 Angstrom o CdSe), and an insulative cap 25 (1,000 Angstrom of silicon dioxide). It is of critical importance to the invention that these layers be deposited under the continuous vacuum of a single pump-down operation.
This is accomplished by placing the structure of Figure 6 into any suitable vacuum chamber and reducing the pressure thereof to about 5 x 10 7 torr.
Thereafter, utilizing conventional deposition techniques of the integrated circuit fabrication art, the layers of ~ minllm oxide, cadmium selenide, and silicon dioxide are deposited in succession without breaking vacuum. Utilizing a suitable solvent, the additive resist mask and unwanted material overlying the same is lifted off producing the structure shown in Figure 7. As shown, what remains are portions of the deposited layer of aluminum oxide 23, cadmium selenide 24, and silicon dioxide 25.
To define the transistor channel length, a resist mask 26 is formed on the silicon dioxide 25 as illustrated in Figure 8. The unprotected areas of silicon dioxide are then etched with carbon tetrafluoride and oxygen plasma to expose areas of the underlying cadmium selenide for receipt of the source and drain contacts. Then utilizing an oxygen plasma, the resist mask 2~ is removed to arrive at the structure of Figure 9. In this Figure, the layer of silicon dioxide 25 is shown etched so as to expose the semiconductor source and drain contact areas, 27 and 28, respectively. Additive delineation (lift-off) is then utili~ed to complete the transistor by forming the suitable conductive contact between source and drain electrodes, 18 and 19, respec-tively, and the semiconductive pad 24. In the completed structure of Figure 10, this conductive contact is provided by successively formed layers of indium 29 and gold 30.
Figure 11 illustrates a plan view of the completed thin film transistor of Figure 10 employed as a driver for a unit cell of a liquid crystaldisplay. It will be appreciated, of course, that thin film transistors such as the ones prepared according to this process are suitable for use in active displays using other electrooptic media. In Figure 11~ the drain of the transistor is formed as part of an enlarged continuous drain pad 40. The source of the transistor is in electrical communication with a niclcel source line 41 which, as well known to those familiar with this art, is shared by other transistors in the 5 display matrix array. A shared, or common, gate bus line 42 is indicated by phantom line. This gate bus 42 corresponds to the burried gate electrode 12 of Figures 1-10. This view illustrates the arrangement of the transistor relative to these display elemenl:s showing, for clarity, the indium gold contacts 30 andexposed silicon dioxide cap. It will be appreciated that, for most applications,10 additional insulating, encapsulating, and/or protective layers of materials would be deposited over the structure shown in Figures 10 and 11.
2~
The early efforts to employ a single pump-down technique focused 25 upon the use of a multiple number of shadow masks within a vacuum system in order to deposit the proper shapes of the various component layers of the thin film transistors These early multiple shadow mask processes are not altogether satisfactory, however, because of such problems as mask to mask registration and low resolution.
The problems occasioned by the use of multiple shadow masks are avoided in the process disclosed in U.S. Patent No. 4,331,758 to Luo. In the disclosed process, during a single pump-down, a uniform layer of a semi-conducting material is deposited onto a substrate. Thereafter, without breaking vacuum, a plurality of discrete areas of an insulating material is 35 deposited onto the semiconductor layer through a single shadow mask. Then a uniform layer of a conducting material is deposited over the areas of insulating material and exposed portions of the semiconductive layer~
Yet another seqllence for fabricating thin film transistors with a sirlg1e shadow mask, single pump-down technique is shown in U.S. Patent No. 4,335,161 to Luo. In that process, the open-ing (or openings for formation of thin film transistor arrays) in ~he mask is commensurate in size and shape to -the semiconductor pads to be deposited. This mask is utilized, during a single vacuum pump-down, to deposlt the semi-conductive pad, the source and drain electrodes, and an insu-lating layer over the source and drain electrodes and the exposed portion of the semiconductive pad. The mask is moved in a simple bidirectional (180 reciprocating) manner between the successive deposi-tions of the semiconductor material which forms the transistor pad and the conductive material which forms the two electrical contacts to -the semi-conductor pad.
As suggested hereinabove, photolithographic pattern de-lineation techniques excel over shadow mask techniques in providing the resolutions required to produce thin film transistor arrays suitable for drivers in high quality pictorial devices. Characteristically, such photolitho-graphic techniques employ wet chemistry processes to selec-tively define patterned layers of conductive and insulative materials. Artisans skilled in this area recognize that exposure of the sensitive transistor interfaces to such wet processing results in impurity contamination which degrades the quality of the transistor characteristics.
Commonly assigned U. S. Patent 4,404,731, Michael Poleshuk et al, issued September 20, 1983 discloses a process for overcoming the disadvantages which can arise from exposure of the critical surfaces of the constituent layers of the thin film device to we-t processing. This is achieved through the use of a single vacuum pump-down step in which -the damage sensitive semiconductor is effectively sealed, or encapsulated, against subsequent wet processing. In the intiial steps of this fabrication sequence a gate electrode is formed and covered with a layer of insulator. An addi-tive photoresist mask is then formed for definition of the semiconductor pad. Thereafter, during a single vacuum --2a~
pump-down, layers o-f insula-tor, semiconductor, and conductor (source-drain contac-t) layers are sequentially deposited to form the critical semiconductor-insulator interface and semi-source and drain contacts. During subsequent lift-off removal of the photoresist mask, the conductive contact layer functions as a protective cap over the semiconductor pad, preventing harmful inter-action between the semiconductor and the stripping solution. After mask removal, the thin film transistor is completed by removal of the portion of the contact layer overlying the cons~ucting channel of the semiconductor and definition of the source and drain networkO
It has heretofore been recognized that technological problems are encountered in fabricating multi layered thin film transistors and transistor 5 arrays. In particular, step coverage problems are prevalent when attempting to form electrical contact between circuit elements located at different levels. In one configuration of thin film transistors, Ior example, semi-conductor films extend from the substrate level to source and drain pads on the next adjacent level. The gate oxide and electrode must necessarily follow 10 the contour of the semiconductor films. The additional layers needed to complete the array, i.eO gate structures and crossovers, likewise follow the irregularity of this contour, producing a completed device consisting of a multilayered mesas with varied geometries and individual heights. Coverage of these mesas steps with continuous films of uniform thickness poses difficulties 15 because of the sharply defined vertical edges OI patterns delineated by processing steps such as photolitho~raphic fabrication. A means for over-coming the step coverage prsblems is disclosed in commonly ~qci~rl~, u.s.
Patent 4,~389,481, Mlchael Poleshuk et al, issued June 21, 1983. In the process disclosed therein9 thin film transistors or an array of thin film are 20 formed on a substrate by sequential deposition of a series of layers fabricated such that each element of the transistor structure is disposed in a planar relationship with respect to the next adjacent layer. In accordance with the process9 the deposition of each of the elemental members of the thin film transistoP structures is immediately followed by filling in the valleys between 25 the elemental structures with an insulating material to form a planar surface.
This planar surfa~e, in turn, forms the surface upon which the succeeding planar layer is formed.
SUMMARY OF THE INVENTION
The present invention provides a process which takes advantage of 30 the single vacuum pum~down technique for minimi~ing contamination of the critical thin film transistor interfaces. This single pum~down technique is incorporated into an all photolithographic process, thus realizing the high degree of control and resolution afforded thereby. During the on~pump-down step9 the critical and contamination vulnerable semiconductor-insulator inter-35 faces are formed by sequential deposition of a transistor gate insulator layer,a semiconductor pad, and a top insulator layer. The top insulator serves as a passiYating layer on the free surface of the single gated thin film transistor, or as a top gate insulator in a double gated thin film transistor.
In addition to the one-pump-down formation of critical semi-conductor-insulator interfaces and encapsulation of contamination vulnerable 5 thin film transistor surfaces prior to wet processing, the present technque provides one-pump-down provision of a passivating layer for the free surface of single gated devices and one-pump-down formation of both gate insulator for double gated devices. As well, to minimize step coverage problems, a quasi-planar construction is employed. Thus, to eliminate the need for 10 continuous coverage of the vertical source-drain electrode walls, a planar substructure for the thin semiconductor layer is provided. To further minimi7e contamination, dry plasma etehing is employed to expose the source-drain contact areas on the semiconductor pad.
In accordance with one particularly advantageous embodiment, the 15 fabrication sequence utilizes nickle, ~ minllm oxide, cadmium selenide, silicon dioxide, and indium-gold for the gate electrode, gate insulator, semiconductor, top insulator, and source and drain contacts, respectively.
This sequence is initiated by the formation of a nickle gate electrode on a portion of a surfaee of a substrate by, for example, subtractive photolitho-20 graphic delineation. Without removing the photoresist masks employed todelineate the nickle gate electrode, a planar structure is formed by depositing aluminum oxide over the substrate to a thickness substantially equal to the thickness of the gate electrode. A gate insulator layer is then formed on top of the planar surface. Thereafter, nickle source and drain electrodes (together 25 with electrical bus lines for thin film transistor arrays) are formed on the gate insulator layer by, for example, subtractive processing. Again allowing the subtractive photoresist mask to remain in place, a second planar surface is formed by depositing aluminum oxide fill to a thickness substantially equal to the thickness of the source and drain electrodes (and bus bars). ~or definition 30 of the semiconductor pad, an additive photoresist mask is then formed on top of the second planar surface. The alllminllm oxide passivating layer, cadmium selenide, and silicon dioxide cap layers are then sequentially deposited throughthe apertures in the additive mask during a single vacuum pump-down to form the critical semiconductor-insulator interfaces. During subsequent lift-off 35 removal of the photoresist musk, the silicon dioxide cap protects the semi-conductor pad, preventing harmful interaction between the semiconductor and .~s~
.5_ the strlpping solution, i.e. the solvent per se or ionic species contained therein. After l.ift-off removal of the unwanted ma-terial and d.issolution of the additive resist mask, portions of the silicon dioxide cap are selectively removed to define the tansistor channel length and expose selected portions of -the semiconductor layer for receipt of the indium-gold conductive contacts between the semiconductor and the source and drain elec-trodes. Preferably, these contacts are formed by additive processing.
In defining the transistor channel length, dry etch-ing techniques, e.g. plasma etching, are preferred in lieu of the here-tofore employed wet processing techniques.
Thus, in removing the unprotected portions of the silicon dioxide layer, plasma etching is employed to expose the underlying cadmium selenide for source-drain contact areas. Thereafter, the resist mask is removed with an oxygen plasma.
Various aspects of the invention are as follows:
A method of photolithographically forming a thin film transistor of the type suitable for use as a driver of an element in a liquid crystal display, comprising the steps of: a) forming a gate electrode of a predetermined thick-ness of conductive material on a portion of a surface of a passivating coating on a substrate by subtractive process-ing; b) forming a first insulator layer on the remainin-ing portions of the surface of said substrate coating not occupied by the gate electrode, said insulator layer having a thickness substantially equal to the thickness of said gate electrode to thereby form a first planar surface;
c) forming a uniformally thick gate insulator layer on said first planar surface; d) forming source and drain elec-trodes of predetermined equal thickness of conductive material on selected portions of said gate insulator layer by substactive processing; e) forming a second insulator layer on the remaining portions of the gate insulator ,~
-5a-layer not occupied by said source and drain electrodes, said second insulator layer having a thickness substantial-ly equal. to the thickness of said source and drain elec-trodes to -thereby form a second planar surface; f) Eorm-ing, on said second planar surface, a masking layer havinga predetermlned opening therein exposing a portion of said second planar surface so that portions of said source and drain electrodes and a portion of said second insulator layer between said source and drain electrodes which lie in the second planar surface are exposed; g) sequentially depositing, under continuous vacuum, a third insulator layer, a semiconductor layer, and a fourth insulator layer, respectively, on said masking layer and on the exposed portion of said second planar surface, so -that the portions of the source and drain electrodes and the portion of the second insulator layer therebetween which are exposed through the opening in said masking layer are covered by said sequentially deposited layers without the need fo a spaced, movable shadow mask; h) removing said masking layer and the portions of the third insulator layer, the semiconductor layer, and the fourth insulator layer deposited thereon; i) selectively removing portions of said fourth insula-tor layer to define a transistor channel length and to expose selected portions of said semiconductor layer; and j) selectively forming conductive contacts between the source and drain electrodes and said selected portions of the semiconductor layer.
A method of forming a thin film transistor, comprising the steps of: a) forming a first composite layer on a surface of a substrate, said first composite layer having a substantially planar surface and including a first conduc-tive film pattern defining at least one gate electrode surrounded by a first insulative film pattern; b) deposit-ing a first insulator layer on the planar surface of said first composite layer; c) forming a second composite layer on said fi~st insulator layer, said second composite layer haviny a substantially planar surface and including a second conductive film pattern surrounded by a second 5 insulative film pattern, sald second conductive film pattern defining at least source and drain electrodes; d) forming on said planar surface of said second composite layer a masking layer having at least one predetermined opening therein exposing portions of said source and drain 10 electrodes and said second insulative film pattern between said source and drain electrodes, e) sequentially depositing, under continuous vacuum, a second insulator layer, a semiconductor layer, and a third insulator layer on said masking layer and on the exposed portions of said 15 second composite layer, so that said sequentially deposited layers are formed on the second composite layer without the need of a positionable shadow mask; f) removing said masking layer and the portions of the second insulator layer, the semiconductor layer, and the third insulator 20 layer deposited thereon, g) selectively removing portions of said third insulator to define a transistor channel length and -to expose selected portions of said semi-conductor layers; and; h) selectively forming conductive con-tacts between the source and drain electrodes and said 25 selected portions of said semiconductor layer.
~RIEF DESCRIPTION OF THE DRAWINGS
Figures 1-10 are diagrammatic cross-sectional views of a thin film transistor being fabricated in accordance with a preferred embodiment of the invention as well as 30 a flow chart describing steps within the process.
Figure 11 is a diagrammatic plan view of a transistor fabricated in accordance with the invention and embodied as a driver for an element of a liquid crystal display.
?~
-5c-DESCRIPTION OF THE PREFERRED EMBODIMENT
Figures 1 and 2 illustrate the formation of a gate electrode 12 upon a substrate 10. A broad range of materials may be employed for subs-trate 10, subject to the general llmitation that -the material chosen be insula-tive relative to the material selected for the gate electrode 12. The exact choice of a material for substrate 10 will, of course, depend upon the particular application in which the thin film transis-tor is utilized.
When employed as a driver of an element in the liquid crystal display, as illustrated in Figure 11, for example, substrate 10 would comprise one of the planar glass plates which are typlcally employed to contain the liquid crystal media. In other applications, utility may dictate that substrate 10 be composed of other insulative material, such as ceramics, semiconductors, plastic materials, and the like. Quite satisfactory results have been obtained with the use of a barium aluminium borosilicate compo-sition sold commercially by Corning Glass Works of Corning, N. Y. under the trademark Corning 7059 Glass.
In Figures 1 through 10 such a Corning 7059 substrate is illustrated with an insulating (aluminum :
oxide) coating 11 to passivate the same.
A subtractive processing technique is utilized to form the gate electrode. In a conventional manner, this method begins with the deposition of a nickel film layer 13 on the aluminum oxide coated substrate. A covering 5 layer of resist material is then applied to the upper surface of the nickel film layer 13. Thereafter, in accordance with well known photolithographic techniques, the resist layer is processed into a subtractive mask by the steps of exposure, development, and removal of selectively patterned areas thereof.
The nickel gate electrode 12 is then formed by etching away portions of the 10 nickel film layer 13 which are not protected by the overlying photoresist mask 14.
In the ne2ct step, as illustrated in Figure 3, the resist mask 1~ is left in place and employed in the formation of a planar structure. As illustrated, this is accomplished by depositing a layer of aluminum oxide over 15 the substrate to fill in spaces adjacent the gate electrode 12. If an array of thin film transistors was being formed, this step would encompass filling all spaces between adjacent gate electrodes of the respective transistors. In a preferred process, a 500 Angstrom layer of nickel is employed in the formation of the gate electrode 12. Thus, the ~ minllm oxide fill layer 15 would be 2~ deposited to a thickness of 500 Angstrom. Suitable solvents are then utilized to dissolve away the resist mask 1~ and lift-off unwanted areas of the aluminum oxide fill layer 15. This produces the first planar surface of this process, as shown most clearly by the arrow drawn from flow chart box A of Figure 4. A blanket gate insulator (aluminum oxide) layer 16 is then deposited 25 to a thickness of 4,500 Angstrom onto the first planar surface as illustrated in Figure ~. To begin delineation of the source and drain electrodes (and the bus lines in a thin film transistor array) a uniform layer of nickel 17 is deposited to a thickness of 500 Angstrom onto the gate insulator layer 16.
Again employing subtractive processing, the source and drain 30 electrodes (and electrical bus lines for an array) are formed. As with the subtractive process described in conjunction with forming the first planar layer (Figures 2 and 3), the subtractive resist maslc remains over the conductive materials (here the nickel source and drain electrodes, 18 and 19, respectively). With this mask in place, an additional aluminum oxide layer 20 35 is deposited to fill the spaces between the source and drain electrodes (and bus lines for arrays). Subsequent removal of the resist mask and unwanted _ I _ aluminum oxide overlying the aame forms the second planar surface, generaUy indicated 21 in Figure 5.
Thereafter, an additive resist mask 22 is prepared on top of the second planar surface 21 as shown in Figure ~. The windows in the resist mask correspond to the desired dimensions of the semieonductor pad for the thin film transistor. The additive mask 22 is then used for depositing, in successivesequence, layers of insulator 23 ~200 Angstrom of aluminum oxide), semicon-ductor 24 (500 Angstrom o CdSe), and an insulative cap 25 (1,000 Angstrom of silicon dioxide). It is of critical importance to the invention that these layers be deposited under the continuous vacuum of a single pump-down operation.
This is accomplished by placing the structure of Figure 6 into any suitable vacuum chamber and reducing the pressure thereof to about 5 x 10 7 torr.
Thereafter, utilizing conventional deposition techniques of the integrated circuit fabrication art, the layers of ~ minllm oxide, cadmium selenide, and silicon dioxide are deposited in succession without breaking vacuum. Utilizing a suitable solvent, the additive resist mask and unwanted material overlying the same is lifted off producing the structure shown in Figure 7. As shown, what remains are portions of the deposited layer of aluminum oxide 23, cadmium selenide 24, and silicon dioxide 25.
To define the transistor channel length, a resist mask 26 is formed on the silicon dioxide 25 as illustrated in Figure 8. The unprotected areas of silicon dioxide are then etched with carbon tetrafluoride and oxygen plasma to expose areas of the underlying cadmium selenide for receipt of the source and drain contacts. Then utilizing an oxygen plasma, the resist mask 2~ is removed to arrive at the structure of Figure 9. In this Figure, the layer of silicon dioxide 25 is shown etched so as to expose the semiconductor source and drain contact areas, 27 and 28, respectively. Additive delineation (lift-off) is then utili~ed to complete the transistor by forming the suitable conductive contact between source and drain electrodes, 18 and 19, respec-tively, and the semiconductive pad 24. In the completed structure of Figure 10, this conductive contact is provided by successively formed layers of indium 29 and gold 30.
Figure 11 illustrates a plan view of the completed thin film transistor of Figure 10 employed as a driver for a unit cell of a liquid crystaldisplay. It will be appreciated, of course, that thin film transistors such as the ones prepared according to this process are suitable for use in active displays using other electrooptic media. In Figure 11~ the drain of the transistor is formed as part of an enlarged continuous drain pad 40. The source of the transistor is in electrical communication with a niclcel source line 41 which, as well known to those familiar with this art, is shared by other transistors in the 5 display matrix array. A shared, or common, gate bus line 42 is indicated by phantom line. This gate bus 42 corresponds to the burried gate electrode 12 of Figures 1-10. This view illustrates the arrangement of the transistor relative to these display elemenl:s showing, for clarity, the indium gold contacts 30 andexposed silicon dioxide cap. It will be appreciated that, for most applications,10 additional insulating, encapsulating, and/or protective layers of materials would be deposited over the structure shown in Figures 10 and 11.
2~
Claims (4)
1. A method of photolithographically forming a thin film transistor of the type suitable for use as a driver of an element in a liquid crystal display, comprising the steps of: a) forming a gate electrode of a predetermined thick-ness of conductive material on a portion of a surface of a passivating coating on a substrate by subtractive process-ing; b) forming a first insulator layer on the remainin-ing portions of the surface of said substrate coating not occupied by the gate electrode, said insulator layer having a thickness substantially equal to the thickness of said gate electrode to thereby form a first planar surface;
c) forming a uniformally thick gate insulator layer on said first planar surface; d) forming source and drain elec-trodes of predetermined equal thickness of conductive material on selected portions of said gate insulator layer by substactive processing; e) forming a second insulator layer on the remaining portions of the gate insulator layer not occupied by said source and drain electrodes, said second insulator layer having a thickness substantial-ly equal to the thickness of said source and drain elec-trodes to thereby form a second planar surface; f) form-ing, on said second planar surface, a masking layer having a predetermined opening therein exposing a portion of said second planar surface so that portions of said source and drain electrodes and a portion of said second insulator layer between said source and drain electrodes which lie in the second planar surface are exposed; g) sequentially depositing, under continuous vacuum, a third insulator layer, a semiconductor layer, and a fourth insulator layer, respectively, on said masking layer and on the exposed portion of said second planar surface, so that the portions of the source and drain electrodes and the portion of the second insulator layer therebetween which are exposed through the opening in said masking layer are covered by said sequentially deposited layers without the need fo a spaced, movable shadow mask; h) removing said masking layer and the portions of the third insulator layer, the semiconductor layer, and the fourth insulator layer deposited thereon; i) selectively removing portions of said fourth insulator layer to define a transistor channel length and to expose selected portions of said semiconductor layer; and j) selectively forming conductive contacts between the source and drain electrodes and said selected portions of the semiconductor layer.
c) forming a uniformally thick gate insulator layer on said first planar surface; d) forming source and drain elec-trodes of predetermined equal thickness of conductive material on selected portions of said gate insulator layer by substactive processing; e) forming a second insulator layer on the remaining portions of the gate insulator layer not occupied by said source and drain electrodes, said second insulator layer having a thickness substantial-ly equal to the thickness of said source and drain elec-trodes to thereby form a second planar surface; f) form-ing, on said second planar surface, a masking layer having a predetermined opening therein exposing a portion of said second planar surface so that portions of said source and drain electrodes and a portion of said second insulator layer between said source and drain electrodes which lie in the second planar surface are exposed; g) sequentially depositing, under continuous vacuum, a third insulator layer, a semiconductor layer, and a fourth insulator layer, respectively, on said masking layer and on the exposed portion of said second planar surface, so that the portions of the source and drain electrodes and the portion of the second insulator layer therebetween which are exposed through the opening in said masking layer are covered by said sequentially deposited layers without the need fo a spaced, movable shadow mask; h) removing said masking layer and the portions of the third insulator layer, the semiconductor layer, and the fourth insulator layer deposited thereon; i) selectively removing portions of said fourth insulator layer to define a transistor channel length and to expose selected portions of said semiconductor layer; and j) selectively forming conductive contacts between the source and drain electrodes and said selected portions of the semiconductor layer.
2. The method of claim 1, wherein said step (i) comprises:
(i1) forming on said fourth insulator layer a photoresist masking layer having a predetermined pattern of openings therein exposing portions of said fourth insulator; (i2) plasma etching the exposed portions of said fourth insula-tor layer to expose selected portions of said semiconductor layer; and (i3) removing said masking layer by plasma etching.
(i1) forming on said fourth insulator layer a photoresist masking layer having a predetermined pattern of openings therein exposing portions of said fourth insulator; (i2) plasma etching the exposed portions of said fourth insula-tor layer to expose selected portions of said semiconductor layer; and (i3) removing said masking layer by plasma etching.
3. A method of forming a thin film transistor, comprising the steps of: a) forming a first composite layer on a surface of a substrate, said first composite layer having a substantially planar surface and including a first conduc-tive film pattern defining at least one gate electrode surrounded by a first insulative film pattern; b) deposit-ing a first insulator layer on the planar surface of said first composite layer; c) forming a second composite layer on said first insulator layer, said second composite layer having a substantially planar surface and including a second conductive film pattern surrounded by a second insulative film pattern, said second conductive film pattern defining at least source and drain electrodes; d) forming on said planar surface of said second composite layer a masking layer having at least one predetermined opening therein exposing portions of said source and drain electrodes and said second insulative film pattern between said source and drain electrodes; e) sequentially depositing, under continuous vacuum, a second insulator layer, a semiconductor layer, and a third insulator layer on said masking layer and on the exposed portions of said second composite layer, so that said sequentially deposited layers are formed on the second composite layer without the need of a positionable shadow mask; f) removing said masking layer and the portions of the second insulator layer, the semiconductor layer, and the third insulator layer deposited thereon; g) selectively removing portions of said third insulator to define a transistor channel length and to expose selected portions of said semi-conductor layers; and; h) selectively forming conductive contacts between the source and drain electrodes and said selected portions of said semiconductor layer.
4. The method of claim 3, wherein said step (g) comprises:
(g1) forming on said third insulator layer, which only remains covering the semiconductor layer, a photoresist masking layer having a predetermined pattern therein which when subjected to a chemical etch will remove all of the masking layer except the predetermined pattern, so that portions of said third insulator are exposed; (g2) plasma etching the exposed portions of said third insulator layer to remove it and expose selected portions of said semi-conductor layer; and (g3) removing said predetermined pattern of the photoresist masking layer by plasma etch-ing.
_ ((
(g1) forming on said third insulator layer, which only remains covering the semiconductor layer, a photoresist masking layer having a predetermined pattern therein which when subjected to a chemical etch will remove all of the masking layer except the predetermined pattern, so that portions of said third insulator are exposed; (g2) plasma etching the exposed portions of said third insulator layer to remove it and expose selected portions of said semi-conductor layer; and (g3) removing said predetermined pattern of the photoresist masking layer by plasma etch-ing.
_ ((
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US410,194 | 1982-08-23 | ||
| US06/410,194 US4461071A (en) | 1982-08-23 | 1982-08-23 | Photolithographic process for fabricating thin film transistors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1202121A true CA1202121A (en) | 1986-03-18 |
Family
ID=23623659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000432208A Expired CA1202121A (en) | 1982-08-23 | 1983-07-11 | Photolithographic process for fabricating thin film transistors |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4461071A (en) |
| EP (1) | EP0102802B1 (en) |
| JP (1) | JPS5950566A (en) |
| CA (1) | CA1202121A (en) |
| DE (1) | DE3370243D1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108140736A (en) * | 2015-10-06 | 2018-06-08 | 牛津大学科技创新有限公司 | Equipment framework |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2561443B1 (en) * | 1984-03-19 | 1986-08-22 | Commissariat Energie Atomique | METHOD FOR INTERCONNECTING THE ACTIVE ZONES AND / OR THE GRIDS OF A CMOS INTEGRATED CIRCUIT |
| JPS60206174A (en) * | 1984-03-30 | 1985-10-17 | Seiko Instr & Electronics Ltd | Thin-film transistor |
| FR2566186B1 (en) * | 1984-06-14 | 1986-08-29 | Thomson Csf | METHOD FOR MANUFACTURING AT LEAST ONE THIN FILM FIELD EFFECT TRANSISTOR AND TRANSISTOR OBTAINED THEREBY |
| FR2590409B1 (en) * | 1985-11-15 | 1987-12-11 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR WITH A SELF-ALIGNED GRID WITH RESPECT TO THE DRAIN AND THE SOURCE THEREOF AND TRANSISTOR OBTAINED BY THE PROCESS |
| US6018181A (en) * | 1990-10-12 | 2000-01-25 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor and manufacturing method thereof |
| JP2791613B2 (en) * | 1990-10-12 | 1998-08-27 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| US7253440B1 (en) | 1991-10-16 | 2007-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having at least first and second thin film transistors |
| US7071910B1 (en) | 1991-10-16 | 2006-07-04 | Semiconductor Energy Laboratory Co., Ltd. | Electrooptical device and method of driving and manufacturing the same |
| US6759680B1 (en) | 1991-10-16 | 2004-07-06 | Semiconductor Energy Laboratory Co., Ltd. | Display device having thin film transistors |
| JP2784615B2 (en) * | 1991-10-16 | 1998-08-06 | 株式会社半導体エネルギー研究所 | Electro-optical display device and driving method thereof |
| US6964890B1 (en) | 1992-03-17 | 2005-11-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| CN1052568C (en) * | 1992-07-06 | 2000-05-17 | 株式会社半导体能源研究所 | Semiconductor device and method for forming the same |
| JP3227353B2 (en) * | 1995-07-13 | 2001-11-12 | 東芝セラミックス株式会社 | Silicon carbide film-coated member and method of manufacturing the same |
| GB0001254D0 (en) * | 2000-01-21 | 2000-03-08 | Central Research Lab Ltd | An active matrix electro-optic display |
| US6524899B1 (en) * | 2000-09-21 | 2003-02-25 | Trw Inc. | Process for forming a large area, high gate current HEMT diode |
| US6943066B2 (en) * | 2002-06-05 | 2005-09-13 | Advantech Global, Ltd | Active matrix backplane for controlling controlled elements and method of manufacture thereof |
| JP4569207B2 (en) * | 2004-07-28 | 2010-10-27 | ソニー株式会社 | Method for manufacturing field effect transistor |
| KR101975263B1 (en) * | 2012-02-07 | 2019-05-08 | 삼성디스플레이 주식회사 | Thin film transistor display panel and method of manufacturing the same |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL282170A (en) * | 1961-08-17 | |||
| US3817750A (en) * | 1970-05-05 | 1974-06-18 | Licentia Gmbh | Method of producing a semiconductor device |
| US3740280A (en) * | 1971-05-14 | 1973-06-19 | Rca Corp | Method of making semiconductor device |
| US3914127A (en) * | 1973-11-23 | 1975-10-21 | Texas Instruments Inc | Method of making charge-coupled devices |
| US3982943A (en) * | 1974-03-05 | 1976-09-28 | Ibm Corporation | Lift-off method of fabricating thin films and a structure utilizable as a lift-off mask |
| US4040073A (en) * | 1975-08-29 | 1977-08-02 | Westinghouse Electric Corporation | Thin film transistor and display panel using the transistor |
| JPS5922380B2 (en) * | 1975-12-03 | 1984-05-26 | 株式会社東芝 | Handout Taisoshino Seizouhouhou |
| JPS5819129B2 (en) * | 1975-12-10 | 1983-04-16 | 株式会社東芝 | Handout Taisouchino Seizouhouhou |
| US4045594A (en) * | 1975-12-31 | 1977-08-30 | Ibm Corporation | Planar insulation of conductive patterns by chemical vapor deposition and sputtering |
| US4035276A (en) * | 1976-04-29 | 1977-07-12 | Ibm Corporation | Making coplanar layers of thin films |
| GB1576055A (en) * | 1976-04-29 | 1980-10-01 | Ibm | Formation of patterns of one material surrounded by another material on a substrate |
| US4182781A (en) * | 1977-09-21 | 1980-01-08 | Texas Instruments Incorporated | Low cost method for forming elevated metal bumps on integrated circuit bodies employing an aluminum/palladium metallization base for electroless plating |
| US4186410A (en) * | 1978-06-27 | 1980-01-29 | Bell Telephone Laboratories, Incorporated | Nonalloyed ohmic contacts to n-type Group III(a)-V(a) semiconductors |
| US4224361A (en) * | 1978-09-05 | 1980-09-23 | International Business Machines Corporation | High temperature lift-off technique |
| US4389481A (en) * | 1980-06-02 | 1983-06-21 | Xerox Corporation | Method of making planar thin film transistors, transistor arrays |
| US4335161A (en) * | 1980-11-03 | 1982-06-15 | Xerox Corporation | Thin film transistors, thin film transistor arrays, and a process for preparing the same |
| US4331758A (en) * | 1980-11-03 | 1982-05-25 | Xerox Corporation | Process for the preparation of large area TFT arrays |
| US4404731A (en) * | 1981-10-01 | 1983-09-20 | Xerox Corporation | Method of forming a thin film transistor |
-
1982
- 1982-08-23 US US06/410,194 patent/US4461071A/en not_active Expired - Fee Related
-
1983
- 1983-07-11 CA CA000432208A patent/CA1202121A/en not_active Expired
- 1983-08-15 JP JP58149103A patent/JPS5950566A/en active Granted
- 1983-08-23 EP EP83304858A patent/EP0102802B1/en not_active Expired
- 1983-08-23 DE DE8383304858T patent/DE3370243D1/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108140736A (en) * | 2015-10-06 | 2018-06-08 | 牛津大学科技创新有限公司 | Equipment framework |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0102802B1 (en) | 1987-03-11 |
| JPS5950566A (en) | 1984-03-23 |
| DE3370243D1 (en) | 1987-04-16 |
| JPH0460343B2 (en) | 1992-09-25 |
| US4461071A (en) | 1984-07-24 |
| EP0102802A1 (en) | 1984-03-14 |
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