CA1203855A - Buffer circuit - Google Patents
Buffer circuitInfo
- Publication number
- CA1203855A CA1203855A CA000446138A CA446138A CA1203855A CA 1203855 A CA1203855 A CA 1203855A CA 000446138 A CA000446138 A CA 000446138A CA 446138 A CA446138 A CA 446138A CA 1203855 A CA1203855 A CA 1203855A
- Authority
- CA
- Canada
- Prior art keywords
- npn
- pnp
- circuit
- transistors
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/50—Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/307—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in push-pull amplifiers
Abstract
ABSTRACT OF THE DISCLOSURE
A buffer circuit having a main buffer circuit section formed of a pair of complementary input side transistors the bases of which are connected together and a dummy circuit section having the same circuit construction as the main buffer circuit section.
A feedback signal formed on the basis of the output from the dummy circuit section is supplied to the dummy circuit section and the main buffer circuit section so as to make the output of the dummy circuit section equal to a predetermined value,
A buffer circuit having a main buffer circuit section formed of a pair of complementary input side transistors the bases of which are connected together and a dummy circuit section having the same circuit construction as the main buffer circuit section.
A feedback signal formed on the basis of the output from the dummy circuit section is supplied to the dummy circuit section and the main buffer circuit section so as to make the output of the dummy circuit section equal to a predetermined value,
Description
~2~
BAC}~GROUND 0~ q~E INV~5~..10N
Field of the Inven ion The present ~nvention relates aenerally to S buffer c~reuit~ and ~ore part~cularly rel~te~ to a buffer clrcu~t hav~ng a hiqh ~nput ~pedance.
Description of the P~ior Art Gener~lly, ~n ~ ~ample ~nd hsla clrcu~t ~hich inter~itten~ly ~ample~ ~ ~olt~ge ~lgnal to be proc~ed and helds ~he ~ar..pled ~olt~ge ~n a capa~tor, when the hola voltage which ~-as sampled and held in the capac~tor i~ del~vered to a next ~tage c~rcuit, ~t i~ de~lred th~t the $nput lmpedance of the next Bt~ge Circu~t i8 made as h~gh as poQ~ble. By the w~y, ~f ~he ~nput impedanc~ of the next staqe circuit is low, upon hold~nq th~ ~oltage, ~he voltage ~s leaked from the cap~c~tor to the next stage c~rcuit. ~hus, the sample and hold volta~e is lowered an~ th~ lowered ~oltsge becomez an ~rror.
BR$Er DBSCRIPT~O?~ OF T~E D~AW~NGS
Fig. 1 ls a connection diagram showinq a conrer'~i~n31 bu~fer ~ircuit: and Fig7 2 15 a connection diagram showing an embodiment o~ a buffer circuit according to the pre~ent ~nventlon.
To solve the above discussed problem, a circuit of current operation system which emplovs complementary bipolar transistors has been proposed as shown in Fig. 1.
As seen in Fig. 1, this conventional circuit includes a ;main transistor Tl such as an ~IPN transistor which is connected in an emitter-follower type. The emitter thereof i 8 connected to a constant current source 1 and the collectvr thereof i.s connected to a first transistor ~
~0;~55i T2 such as an NPN transistor which forms a .feedback circuit
BAC}~GROUND 0~ q~E INV~5~..10N
Field of the Inven ion The present ~nvention relates aenerally to S buffer c~reuit~ and ~ore part~cularly rel~te~ to a buffer clrcu~t hav~ng a hiqh ~nput ~pedance.
Description of the P~ior Art Gener~lly, ~n ~ ~ample ~nd hsla clrcu~t ~hich inter~itten~ly ~ample~ ~ ~olt~ge ~lgnal to be proc~ed and helds ~he ~ar..pled ~olt~ge ~n a capa~tor, when the hola voltage which ~-as sampled and held in the capac~tor i~ del~vered to a next ~tage c~rcuit, ~t i~ de~lred th~t the $nput lmpedance of the next Bt~ge Circu~t i8 made as h~gh as poQ~ble. By the w~y, ~f ~he ~nput impedanc~ of the next staqe circuit is low, upon hold~nq th~ ~oltage, ~he voltage ~s leaked from the cap~c~tor to the next stage c~rcuit. ~hus, the sample and hold volta~e is lowered an~ th~ lowered ~oltsge becomez an ~rror.
BR$Er DBSCRIPT~O?~ OF T~E D~AW~NGS
Fig. 1 ls a connection diagram showinq a conrer'~i~n31 bu~fer ~ircuit: and Fig7 2 15 a connection diagram showing an embodiment o~ a buffer circuit according to the pre~ent ~nventlon.
To solve the above discussed problem, a circuit of current operation system which emplovs complementary bipolar transistors has been proposed as shown in Fig. 1.
As seen in Fig. 1, this conventional circuit includes a ;main transistor Tl such as an ~IPN transistor which is connected in an emitter-follower type. The emitter thereof i 8 connected to a constant current source 1 and the collectvr thereof i.s connected to a first transistor ~
~0;~55i T2 such as an NPN transistor which forms a .feedback circuit
2. To the base of the main transistor Tl is connected an input terminal 4 to which a sampled voltage from a sampling and holding capacitor 3 is supplied. Also, an output terminal 5 is connected to the emitter of the main transis-tor T1.
m e feedb~ck circuit 2 lnclude~ ~CQ~ and th~rd tran~istors T3 ~nd ~ connecLca ~n ~erles betwe~n puwer ~o~e lines 6 and 7, each of ~he 6s~rd and third transiqtors T3 and T4 belng ~or~ed o~ a PNP ~rans~tor.
The ~a~es of the fir~t and ~econd tran~stors T2 Rnd T3 are connected to each other, whi le t he base~ of the third transi~tor ~4 and the main tr~n~i~tor Tl ~re con`nect~d to oach other.
With the circuit constructed as 3hown ~n Fig. 1, it ~ a~sumed that the current ~mpl~flc~tlon $~ctors hfe f the PNP and ~PN trans~tors are taken an ~p nnd ~N~ In the feedback circuit 2, ~hen a current I ~ der~ved from the 2mitter of th~ fir6t tran~l~tor T2~ ~t~ ba~e ~ ent 20 becomes ~ which i~ derivad from ~he ~e of ~he second tr~n~tox ~3. ~ccord~ngly, the collector curre~t of the second trDnsi~tor T3 bt~ _s I ~ wh~ch then flow~ in ~N
the e~$tter of the third tran8i8tor T4. Therefore, ~he base current of the th~r~ tr~nsi~tor ~4 becomes 5 I ~ ~ x _~__ ~ I ~hich then flo~s ~n the base o~ the N P N
m~ n transi~tor ~1 as a feedb~e~ current.
~hen ~hi8 faedbxck c~rrent flo~s ~n the base of ~he ~in ~ran3~t~r Tl, the emitter ~ crt ~f th~ tr~n~s~or ~1 be~ ~ ~ x ~N ~ I. m u , the ¢urrent which ~low~
30 fro~n ~he emitter of the fir~t trans1stor T2 to the ~oIl~etor o th~ ~Da~n ~ran~iY~or ~l he~- o~ eau~l B0 ~at the c~rcNlt 1B pl~!l. el~ lnto the ~t~ t~te. ~ 0table ~t~te ~8 deter~ ne~ by the con3ta~alt5 of th~! ~ain tran~i~tor Tl ~nd the tr~n~3tor~ T2 ~o T4 in t:he feedba~k ~rcu~t 2 ~o ~hat ~ 3 -q ,1 `
when the tran~tor Tl ~nd the ~ran~Rtors T2 to T4 are formed on an inte~rated c~rcuit [IC), the curre~t I
~et~ ined.
~n~er ~h~s stable 3tate, when ~he 6amp1e~
S ~oltage Vs f the capacltor 3 ~8 ~uppl~ed to the ba~e of ~he ~ain tran~istor Tl, the e~itter ~urr~nt I ~h~reof chan~e~ in respon~e t~ereto. ~h~s ~hange 1B pcsitively fed bA~k thr~ugh the loop ~f the feedbac~ circu~t 2 ~ro~
the ba~e ~urrent ~ of the f~r~t tr~ns~tor T2 the collector current of the second tran~tor T3 ~ the ba~e current of the third tr~nsistor T4 ~ thè emitter cùrrent of the main tran~tstor T1 ~o th~t the circuit ~ placed into a ~ew stab~e state. Thus, the voltage ~t the emitter of ~he transi3t~r Tl, accord~ngly, the outpu~ ~oltage VO
becomes a voltaqe which iB lower by the base~emltter ~oltage VBE of the ~ranq~tor T~ ~han the ~nput ~o~t~ge V$ ~ that the output voltage VO fluc~uates in re~pon~e to tbe input voltaae Vs and that thus the c~rcuitry constructea ~ as shown ~n F~g. 1 iB operated as the b~fer c~rcuit. In addition, when the above circuit ~ o~erated a~ ~he buffer circuit, it 1~ not neces~ary to derive the b~s2 ~L,~t from the input terminal 4 ~namely, the ~ampl~y ~nd holding ~tor 3 at the prece~ing ~tage~ ~o ~8 to operate ~he ~aîn tr~nsi~tor Tl. Such ~ase current ~, howe~er~ ~uppli-2S ed thereto from the Pe~dback ~ireui~ 2 equallyO
~here~ore, acc~rd~ng to the clreuit ~on~tru~tion ~how~ ~n Pig. 1, wlthout deriv~ns ~he ~urrent fYom ~he input tenmin~l 40 ~he output ~oltage VO ~hi~h changes aecordance wi~h ~he input volt~g~ n ~e ob~ n~
other wordsO the buff~r e~r~u~t having ~uff~c~tly ~gh -- 4 ~
\
~5 , .
input ~ nce can be renl~zed.
~ow~er, ~n ~he c$rcuit con6truc~ed a8 ~hown ~n Fig. 1, since the correctin~ current ~hich 18 ~upplied to the b~se of the ~ain tran~6tor Tl i8 pos~tively fed back ~ro~ ~he ~ee~h~c~ ~rcu~t 2 ~n the ~a~ of the ~oll~tor ~u~ent of ~he mai~ transistor Tl (n~m~ly, the emit~er current ~f the first transistor.T2~, ~hen the level Gf ~he $nput v~lt~ge ~S is changed at hi~h ~peed, there ~ then a ri~k that an undesirable ~n~tabl~ oper~t~on ~uch a~ a so-callea r~nsing or the like ~ay occur on ~he ba~ of the del~y ~n t~e opera~ion of the feedbàck clrcuit 2.
Moreover, when the lnput volta~e Vs i~ changea con~iderably large in ampli~ude snd at high speed, ghere i~ ~ disadvsntage that the changed wavefo~m of the outp~t voltage ~0 ~e~ different between the leading edge and the trail~ng edge. In thls connectionr ~hen the input ~ltage VB i8 raised at high speed and large in amplitude, the emitter current of the main tran~istox ~ flo~ed - much ~n a ~oment ~o that the output ~olta~e VO ri~es up ~ithout delay. On the other~hand, when the input ~oltage VS is lower~d at high ~peed ana lax~e in ~plitude unt~l the 3~ray capacity at the emitter of the main tran~itor Tl is di~char~ed by the current ~ource ~, th~ main tr~nsistor Tl i~ m~de off ~n an ~nstant ~o that the outpu~ ~ol~a~e VO
fa11B down wl~h s~gnifi~ant delay.
In ~hi~ c~se, lt ~zy b~ ~onsidered ~hat an F~T
~ ld effect tr~nsistDr) ls us~d in ~he buffer ~rcuit or ~he ~nput ~olt~e of large a~plitu~e. Ro.?~ , ~hen ~h~ ~T i~ fQrmea together with ~he IC includ~ng bipolar ~r~aR~Dr~, a di~ad~a~tag~ 1~ brought ~bout ln ~l~w of az~i~
~n~nufact~ring the ~C.
OBJECTS AND- ~UF~RY: OF T~E INVENTION
S Accordin~ly, it ls an ob~ect`of the pre~ent ~n~ntion to pro~ide an impro~ed buffer circu~t.
It ~s another ob~ect of the pre3ent invention to provide a buf~er c~rcu~t hav~ng a quite high ~nput ~mpedance.
It i~ a further o~ect of the pr~s~n~ inv~tion to prov~de ~ buffer c~rcui~ includino ~ b~polnr ~ran~i~tor w~ich c~n operate ~o as to practically cope with a ~se ~n ~hich ~n ~nput voltage is changed at h$gh speed and with a large ~mplitude.
It is a 3till further o~ect of the present ln~ention ~o prov~de a ~uffer circuit which can ~urely prevent the flow of an input current even when there 1 3cattering in circult elements.
Accord~ng to one aspect of the pre~ent i~v~ntion, there i8 provl ded ~ high input impedance c~rcuit comprising:
(a) f~r~t and ~econd buffer c~rcults, eac~ of ~aid flr~t and second buffer circuit~ havin~ fir~t and ~econd pa~rs of NPN and PNP transi~tors, bas~s of said first pair o~
NPN nnd PNP tran3istors be~n~ connected to each other, ~mltter~ of said sec~nd pa~r o~ NPN ana PNP tran~l~tors ~*lng connec~d to ~ach other, em~tter~ of ~a~d firs~
p~ir o~ P~P and NPN tran3~stor3 belnn ~nnec~ed re~pe~- ;
t~vely to the ba~e~ of ~aid ~cond NPN and PNP tr~n~iator~, ~ firs~ ~nd ~cond ~on~t~nt ~ nt elrculta wh~h ~r~
re~pe~ti~ly oDnnec~ea ~o ~a~d e~itter~ of ~aia ~r~
-~2~3BS5 pair of PNP and NPN tr~nsi~tors;
~b) ~r~t and ~econd con~t~nt current ~ource clrcui~ for driving ~A~ d ~irst and ~econd oon~tant current clrcuit~
sf ~aid ~irst and 3econd buf~er clrcuits respectively~-and (~) a control circu~t for controll~nc an a unt o~ ~ current vf ~t least one of said first and ~econd con~tant current 30U~ ce circ-~it~.
The other ob~ects, features and aav~ntages of the pre~ent lnrention w~ll become apparent from the follow-ing descr~ption taken in con~unct~on with ~he accc, ~nying drawings through which the iike reference~ de~ignate the ~ame element~ and parts.
DESCRIP~IO~ OF ~H~ PREFEXRED EM~3ODIMEN~
Now, an e~bodiment of a buffer circui~ according to the present invention will hereinafter be described in detail with reference to ~ig. 2 wh$ch ~ ~ connec~ion d~agram thereof. In Flg. 2, reference numeral 8 designa~s a ma~n buffer circuit section, 9 a dummy circui~ section and 10 a ~eedbac~ circuit section, respectively.
~ ~he ~nain buffer circuit section S includes a ,i _ 7 _ ~`Z6~38~ ~
pair of input ~ide ~ran~i~tors ~lA and TlB ormed o~ PNP
and NPN transistor~ which ar~ conn~ctcd complementaxy to each other. The bases ther~of are connected directly to each other and then connected to an input terminal 1~.
The collectors thereo~ are respectively connected to negative and posltive power source lines 12 and 13, wh~l~
the emitter~ thereof are re3pectively connected through constant current ~ource transistors T2A and T2B formed of PNP and ~P~ tran~stors to the positive anfl neqative power source lin~ 13 and 12. An~, the outputs are ~upplie~ to base~ of output side tran~i~tors T~A ana T3B ~rom the emitter~ of the input side transi~tors TlA and TlB.
Thu~, the lnput side transi~tor~ TlA ~n~ TlB ~re connec~ed in a manner of emitter-~ollower circuit coniauration.
lS The output side ~ran~i~tor~ T3~ and T3s are formed of ~PN and PNP transistors, ~oth bein~ connected complementary to each other. The emitters ~hereof are connected commonly to an output terminal 1~, while the collector~ ~hereof are r~spectively connected to the po~itive and ne~ative power ~ouxce ltnes 13 an~
The dummy circuit section 9 iæ con~tructe~ th~
~ame as the ~ain bu~fex cixc~it section 8 and includes input side tran~istoxs T4A and T4B, output side tran~i~tors TSA and TSB and constant current source tran~lstors T6A
and T6~.
The feedback circuit ~ection 10 includes a pair of NPN transistor~ T7 ana T8 which constitute a diferential ~mplifying circuit 15. To the base of one transistor T7 is supplied the output which is derived from the emitter~
o~ th~ output ~de transistors T5A and T5B in the dum~y ~20~5 circuit ~ection ~. TQ the common connection pQint of th~
emlttexs of th~ txansistors T7 and TS i connected an NPN
transistor T9 serving as a constant current source the base of which is connected to the base o~ a con~tant current source drivin~ transistor T10 and the emitter of a trans~stor Tll. ~ .
To ~he base o the other transistor T8 is supplted a xe~erence volta~e VR whic~ is obtained at the co ~ ection point of volt~ge-dIviain~ xes~stQrs Rl and R2 connected in series between the positive and negative power source lines 13 and 12. Accord.in~ly, the transi~tor~ T7 and T8 compare the output volt~e VN rom the dummy aircuit section 9 wi~h the re~erence volta~e ~'~ which i~ determ~ned by ~he resistance values of the rasl~tors Rl and R2 to thereby supply a current of a value corre~pondin~ to a difference between volta~es VN an~ VR to constant ~u~`lent source driving transistor~ T12 and T13 fr~m the tran~istox T8.
One d~ivin~ transistor~ T10 and Tll are connect~d ~hrough re~istors R3 and R4 to the positive and ne~ative power source lines 13 and 12, whereby a constant current which is determined by the reslstance values o the re~i.stoxs ~3 and R4 is flowed to the transistors T7 and T8 from the t~ansistor T9. The base of the driving transistor T10 is connec~ed to th~ bases of the constant current source transistor T2B in the main ~uffe~ circuit section 8 and the constant current source transistor T6B in ~he dummy circuit section 9 so that a value o a current supplied to one ~nput side transistors T13 and T4B is made coincident with a current value supplied to the constant current s~ce _ g _ \
'~
tran~tor ~9 ~ ths feed~ack c~rcuit sec~on 10.
On the other hand, the ~mitter an~ base o the other constant current source ~riving transistors T12 and T13 are connecte~ to the bases o~ the constant current ~ource trans~stor T2A in the main b~fer c~rcu~t sectlon 8 and the constant ~u~.ent souxce transistor T6A in the dummy circuit section 9 so that a value of a current ~lowed into the input side transistors T2A and T6A is controllea by a di~ference output derived-from the difexential amplifyin~ circuit 15 in the feedback circuit section 10 so as to reduce t~is difference output to 2ero~
With the circuit construction as described above, the ~C. bias conditions o~ respective ~ortions in the Main buffer circuit section 3 are determined by the re~istanc~
values o the re~istors Rl, R2 an~ R3, R4 in th~ feedback circuit section 10. More specifically, since the dummy circuit section 9 is constructed the s~me as the main b~ffer~circuit section 8~ the currents o the sa~e value are flowad through the correspondin~ portions. The valus of the current 10wea through the constant curr~nt source txans~stor T6B .~n the dummy circuit section 9 ~a~cordingly, the constant curxent source transistor T2B in the main buffer circuit sect~on 8) is de~ermined by the re~istance values of the xe~i~tors R3 and R4 connected to the driving transistors T10 and Tll. Meanwhile, the value of the current flowed through the constant current source tran~istor TSA in the du~my circuit section 9 taccordingly~ the consta~t current sourca transistor T2.~ in the main buer circuit ~ectlon 8) is deter~ined by the resi~tance ~alue of ~he resistors Rl and R2 which are connected to the ba~e ~ ~ O --~Q38~5 of one tran~ or ~8 in the diff~.rential amplifyin~
circuit lS. The reason is that the constant ~r~nt ~ource transistor T6A in the aummy circuit section ~ i5 controlled hy the out~ut frQm the driving transistors T12 and T13 so S as to make the output volta~e VN from the emltters of the output side transistors TSA an~ T5B in the dummy circuit section g equal to the reference voltaqe VR.
When the feedback sy~tem which is established by feedin~ the output voltaae ~ of the dummy circuit section 9 back to the constant current source txan~istor T6~ throuqh the ~ifferential amplifyin~ c~rcuit lS is made in the sta~le state as descri~ed ahove, a current In derived from the emit~er of th~ input side transistor T4A
to the base thereof is all supplled throu~h the base of lS the input side transistox T4B to the emitter thereof.
This operation condition can be established for the main buffer circuit section 8 of the same construct~on as the dummy ci~cuit section 9. That is, such a stable state that the output of the emitters o the output si~e tran~stors ~3A and T3B is fed back to the constant current source transistor T2A ~hrough the differential amplifyin~ circuit 15 is equivalently es~ablished in the main buffex circuit section ~.
CoQse~uently, also in the main buffer circuit section 8, the current delivered from the emitt2r of the transistor TlA to the base thereof hecomes Ia and ths current del~vered rom the base of the transistor TlB to the emitter thereof also becomes Ia. In other words, '_ ~his~ means that it is not neces~ary to take in any current from an external cir~uit connected to the input ter~n~l 11 ~D3~
~for exampl~, a capacitor 17 for sampl~ng and holdin~) so as to dxive the ma~n buffer circuit section 8.
Under the above biasin~ condition, the input v~ltage Vs applied to the input t~r~i n~l 11 is transmitted through the base-emitter path of the input si~e P~P
transistor TlA and the base-emitter path of the output s~de NPN transistor T3A to the output t~n~inAl 14. The input voltage Vs is also transmitted throu~h the base emitter path of the input side NPN transistor TlB and the hase-emi~ter path of the output side PNP tran~istor T3B to the output ~e tn~l 14. ~ccordingly, in one transmi~sion path, ~he potentlal is raised temporax~ly hi~h by the base-emitter volta~e of the input æide trans~stor ~lA (of the PNP
transistor) and this potential is lowered by the base-em~tter voltage of the output side transistor T3A (of the NRN
transistorl, while in the other transmission path, th~
potential is lowered temporarily by the ba~e-emi~ter volta~e of the inpu~ side transistor TlB (of the NPN
transistor) and this po~ential 1B raised hi~h hy the ba~e-emitter ~olta~e of the output s.ide tran~i~tor T3~ (of the PNP tran~istor).
If the above circuit i~ formed on the same IC
chip, the base-emitter volta~es o the transistors TlA and T3B, each tran~istor bein~ a PNP transistor, hecome s~stantially e~ual to each other and the ~a~e-emitter ~oltages o the transistor6 ~lB and T3A, each transistor being an NPN transistor, become sub~tanti~lly egual to each other. Therefore, 1~ both o the transmission path~, the relation o~ ~he potential at the output termlnal 14 relative to the potential at the input term; nal 11 becom2s - 12 ~
` 12~3~;S`
. ,.. -`
equal to each other witll the resul~ that as the input voltage Vs i~ changed, the output voltage V0 is changed in correspondenc~ thereto. ~nd, ~ven when the voltage in the transl;~ission path for the output signal is changed, the D.C. bias condition in ~he dummy circuit section 9 is never chang~d s~ that the curr~nt value which i3 fed back ~o the constant cu~Fent source transistor T2A in the m~in bufer circuit section 8 is never changed. A3 a xesult, the input side transi~tors TlA and TlB in ~he main buffer circuit ~ection 8 maintain the above state under which the transistors TlA and TlB do not take ~n the current from the external circuit by way of the input te~ ~ n In addition to ~uch operation, even ~f the current amplification ~actor he of the tr~nsi~tor i5 ~catte~ed at each sub~trate when the circùlt constructlon shown in Fig. 2 is foxmed on a number of the IC substrates, in respon~e to ~uch difference, the current which is fed back to the constant curren~ source transi~tor T6A
(accordin~ly, the constant current source tran~istor T2A
in the main bufer clrcuit section 8) ~hr~uqh the difer~ntial amplifyin~ c~rcuit 15 ~y the output from the dum~ly circuit ~ectlon 9 is change~l in correspondence with the a~ove ~cattering to thereby establish the stable ~state under which the output voltage V~ from the dummy circuit ~ection ~5 9 is coincident with the r~ference voltage VR, thus ~he scattering o~ the current amplification Eactor~ h~e being corrected.
As de.scribed above, according to the c~rcuit o~
the present lnven~ion consLructed as ~hown in Fi~. 2, without taking in the current to the input termin~l 11 - 13 ~
~2~).~
.. ~. " ., ~.
from th~ e~ternal circult, the input volt~e Vs can be transmitted to the output terminal 14, thu3 raaliz~ng the buffer circuit havin~ the considerably lar~e input impe-dance. Also, in the present invention, essentially the complementary circuits are constructed ~o that even when the input volta~e Vs is chan~ed over the range from the positive to the ne~ative, the ahove circuits can be operated in the same ~nn~r. Therefore, it is pnssible to transmit the signal of high speed and lar~e ampl~tude.
As set forth a~ove, accordina to the pr~ent invention, the dummy circuit havinq the ~ame clrcuit con-struction as the main buffer circuit incl~ding ~he oomplementary input side transistor~ i5 provided and the output thererom i~ compared with t~e reerence ~oltage by the differential ampliyin~ circuit to proviae the correctin~ feedback signal for the con~t~nt cuxrent ~ource~
of the dummy circuit and the main bu~fer circuit~ Ther~ore, even if the c~rrent amplification factors o~ the transi~tor~
are scattered, ~uch ~cattered cu~Lent amplification ac~or~
can be corrected so that the buffar circuit which alway~
ha~ a hl~h input impedance and which c~n transmit the input ~ignal of high speed ~nd lar~e amplitude can be real.ized ~y usinq the bipolar transistors.
The above de~cription is qiven on a single p~eferr-ed embodiment of the invention, but it. will be appaxent that many modifications and variations could be eff~cted by one sXilled in the art without departing from the spirit~
or scope of the novel concepts of the ~nvention, so that the scope of the ~nvention should be det~rrined by the appended clsims only.
m e feedb~ck circuit 2 lnclude~ ~CQ~ and th~rd tran~istors T3 ~nd ~ connecLca ~n ~erles betwe~n puwer ~o~e lines 6 and 7, each of ~he 6s~rd and third transiqtors T3 and T4 belng ~or~ed o~ a PNP ~rans~tor.
The ~a~es of the fir~t and ~econd tran~stors T2 Rnd T3 are connected to each other, whi le t he base~ of the third transi~tor ~4 and the main tr~n~i~tor Tl ~re con`nect~d to oach other.
With the circuit constructed as 3hown ~n Fig. 1, it ~ a~sumed that the current ~mpl~flc~tlon $~ctors hfe f the PNP and ~PN trans~tors are taken an ~p nnd ~N~ In the feedback circuit 2, ~hen a current I ~ der~ved from the 2mitter of th~ fir6t tran~l~tor T2~ ~t~ ba~e ~ ent 20 becomes ~ which i~ derivad from ~he ~e of ~he second tr~n~tox ~3. ~ccord~ngly, the collector curre~t of the second trDnsi~tor T3 bt~ _s I ~ wh~ch then flow~ in ~N
the e~$tter of the third tran8i8tor T4. Therefore, ~he base current of the th~r~ tr~nsi~tor ~4 becomes 5 I ~ ~ x _~__ ~ I ~hich then flo~s ~n the base o~ the N P N
m~ n transi~tor ~1 as a feedb~e~ current.
~hen ~hi8 faedbxck c~rrent flo~s ~n the base of ~he ~in ~ran3~t~r Tl, the emitter ~ crt ~f th~ tr~n~s~or ~1 be~ ~ ~ x ~N ~ I. m u , the ¢urrent which ~low~
30 fro~n ~he emitter of the fir~t trans1stor T2 to the ~oIl~etor o th~ ~Da~n ~ran~iY~or ~l he~- o~ eau~l B0 ~at the c~rcNlt 1B pl~!l. el~ lnto the ~t~ t~te. ~ 0table ~t~te ~8 deter~ ne~ by the con3ta~alt5 of th~! ~ain tran~i~tor Tl ~nd the tr~n~3tor~ T2 ~o T4 in t:he feedba~k ~rcu~t 2 ~o ~hat ~ 3 -q ,1 `
when the tran~tor Tl ~nd the ~ran~Rtors T2 to T4 are formed on an inte~rated c~rcuit [IC), the curre~t I
~et~ ined.
~n~er ~h~s stable 3tate, when ~he 6amp1e~
S ~oltage Vs f the capacltor 3 ~8 ~uppl~ed to the ba~e of ~he ~ain tran~istor Tl, the e~itter ~urr~nt I ~h~reof chan~e~ in respon~e t~ereto. ~h~s ~hange 1B pcsitively fed bA~k thr~ugh the loop ~f the feedbac~ circu~t 2 ~ro~
the ba~e ~urrent ~ of the f~r~t tr~ns~tor T2 the collector current of the second tran~tor T3 ~ the ba~e current of the third tr~nsistor T4 ~ thè emitter cùrrent of the main tran~tstor T1 ~o th~t the circuit ~ placed into a ~ew stab~e state. Thus, the voltage ~t the emitter of ~he transi3t~r Tl, accord~ngly, the outpu~ ~oltage VO
becomes a voltaqe which iB lower by the base~emltter ~oltage VBE of the ~ranq~tor T~ ~han the ~nput ~o~t~ge V$ ~ that the output voltage VO fluc~uates in re~pon~e to tbe input voltaae Vs and that thus the c~rcuitry constructea ~ as shown ~n F~g. 1 iB operated as the b~fer c~rcuit. In addition, when the above circuit ~ o~erated a~ ~he buffer circuit, it 1~ not neces~ary to derive the b~s2 ~L,~t from the input terminal 4 ~namely, the ~ampl~y ~nd holding ~tor 3 at the prece~ing ~tage~ ~o ~8 to operate ~he ~aîn tr~nsi~tor Tl. Such ~ase current ~, howe~er~ ~uppli-2S ed thereto from the Pe~dback ~ireui~ 2 equallyO
~here~ore, acc~rd~ng to the clreuit ~on~tru~tion ~how~ ~n Pig. 1, wlthout deriv~ns ~he ~urrent fYom ~he input tenmin~l 40 ~he output ~oltage VO ~hi~h changes aecordance wi~h ~he input volt~g~ n ~e ob~ n~
other wordsO the buff~r e~r~u~t having ~uff~c~tly ~gh -- 4 ~
\
~5 , .
input ~ nce can be renl~zed.
~ow~er, ~n ~he c$rcuit con6truc~ed a8 ~hown ~n Fig. 1, since the correctin~ current ~hich 18 ~upplied to the b~se of the ~ain tran~6tor Tl i8 pos~tively fed back ~ro~ ~he ~ee~h~c~ ~rcu~t 2 ~n the ~a~ of the ~oll~tor ~u~ent of ~he mai~ transistor Tl (n~m~ly, the emit~er current ~f the first transistor.T2~, ~hen the level Gf ~he $nput v~lt~ge ~S is changed at hi~h ~peed, there ~ then a ri~k that an undesirable ~n~tabl~ oper~t~on ~uch a~ a so-callea r~nsing or the like ~ay occur on ~he ba~ of the del~y ~n t~e opera~ion of the feedbàck clrcuit 2.
Moreover, when the lnput volta~e Vs i~ changea con~iderably large in ampli~ude snd at high speed, ghere i~ ~ disadvsntage that the changed wavefo~m of the outp~t voltage ~0 ~e~ different between the leading edge and the trail~ng edge. In thls connectionr ~hen the input ~ltage VB i8 raised at high speed and large in amplitude, the emitter current of the main tran~istox ~ flo~ed - much ~n a ~oment ~o that the output ~olta~e VO ri~es up ~ithout delay. On the other~hand, when the input ~oltage VS is lower~d at high ~peed ana lax~e in ~plitude unt~l the 3~ray capacity at the emitter of the main tran~itor Tl is di~char~ed by the current ~ource ~, th~ main tr~nsistor Tl i~ m~de off ~n an ~nstant ~o that the outpu~ ~ol~a~e VO
fa11B down wl~h s~gnifi~ant delay.
In ~hi~ c~se, lt ~zy b~ ~onsidered ~hat an F~T
~ ld effect tr~nsistDr) ls us~d in ~he buffer ~rcuit or ~he ~nput ~olt~e of large a~plitu~e. Ro.?~ , ~hen ~h~ ~T i~ fQrmea together with ~he IC includ~ng bipolar ~r~aR~Dr~, a di~ad~a~tag~ 1~ brought ~bout ln ~l~w of az~i~
~n~nufact~ring the ~C.
OBJECTS AND- ~UF~RY: OF T~E INVENTION
S Accordin~ly, it ls an ob~ect`of the pre~ent ~n~ntion to pro~ide an impro~ed buffer circu~t.
It ~s another ob~ect of the pre3ent invention to provide a buf~er c~rcu~t hav~ng a quite high ~nput ~mpedance.
It i~ a further o~ect of the pr~s~n~ inv~tion to prov~de ~ buffer c~rcui~ includino ~ b~polnr ~ran~i~tor w~ich c~n operate ~o as to practically cope with a ~se ~n ~hich ~n ~nput voltage is changed at h$gh speed and with a large ~mplitude.
It is a 3till further o~ect of the present ln~ention ~o prov~de a ~uffer circuit which can ~urely prevent the flow of an input current even when there 1 3cattering in circult elements.
Accord~ng to one aspect of the pre~ent i~v~ntion, there i8 provl ded ~ high input impedance c~rcuit comprising:
(a) f~r~t and ~econd buffer c~rcults, eac~ of ~aid flr~t and second buffer circuit~ havin~ fir~t and ~econd pa~rs of NPN and PNP transi~tors, bas~s of said first pair o~
NPN nnd PNP tran3istors be~n~ connected to each other, ~mltter~ of said sec~nd pa~r o~ NPN ana PNP tran~l~tors ~*lng connec~d to ~ach other, em~tter~ of ~a~d firs~
p~ir o~ P~P and NPN tran3~stor3 belnn ~nnec~ed re~pe~- ;
t~vely to the ba~e~ of ~aid ~cond NPN and PNP tr~n~iator~, ~ firs~ ~nd ~cond ~on~t~nt ~ nt elrculta wh~h ~r~
re~pe~ti~ly oDnnec~ea ~o ~a~d e~itter~ of ~aia ~r~
-~2~3BS5 pair of PNP and NPN tr~nsi~tors;
~b) ~r~t and ~econd con~t~nt current ~ource clrcui~ for driving ~A~ d ~irst and ~econd oon~tant current clrcuit~
sf ~aid ~irst and 3econd buf~er clrcuits respectively~-and (~) a control circu~t for controll~nc an a unt o~ ~ current vf ~t least one of said first and ~econd con~tant current 30U~ ce circ-~it~.
The other ob~ects, features and aav~ntages of the pre~ent lnrention w~ll become apparent from the follow-ing descr~ption taken in con~unct~on with ~he accc, ~nying drawings through which the iike reference~ de~ignate the ~ame element~ and parts.
DESCRIP~IO~ OF ~H~ PREFEXRED EM~3ODIMEN~
Now, an e~bodiment of a buffer circui~ according to the present invention will hereinafter be described in detail with reference to ~ig. 2 wh$ch ~ ~ connec~ion d~agram thereof. In Flg. 2, reference numeral 8 designa~s a ma~n buffer circuit section, 9 a dummy circui~ section and 10 a ~eedbac~ circuit section, respectively.
~ ~he ~nain buffer circuit section S includes a ,i _ 7 _ ~`Z6~38~ ~
pair of input ~ide ~ran~i~tors ~lA and TlB ormed o~ PNP
and NPN transistor~ which ar~ conn~ctcd complementaxy to each other. The bases ther~of are connected directly to each other and then connected to an input terminal 1~.
The collectors thereo~ are respectively connected to negative and posltive power source lines 12 and 13, wh~l~
the emitter~ thereof are re3pectively connected through constant current ~ource transistors T2A and T2B formed of PNP and ~P~ tran~stors to the positive anfl neqative power source lin~ 13 and 12. An~, the outputs are ~upplie~ to base~ of output side tran~i~tors T~A ana T3B ~rom the emitter~ of the input side transi~tors TlA and TlB.
Thu~, the lnput side transi~tor~ TlA ~n~ TlB ~re connec~ed in a manner of emitter-~ollower circuit coniauration.
lS The output side ~ran~i~tor~ T3~ and T3s are formed of ~PN and PNP transistors, ~oth bein~ connected complementary to each other. The emitters ~hereof are connected commonly to an output terminal 1~, while the collector~ ~hereof are r~spectively connected to the po~itive and ne~ative power ~ouxce ltnes 13 an~
The dummy circuit section 9 iæ con~tructe~ th~
~ame as the ~ain bu~fex cixc~it section 8 and includes input side tran~istoxs T4A and T4B, output side tran~i~tors TSA and TSB and constant current source tran~lstors T6A
and T6~.
The feedback circuit ~ection 10 includes a pair of NPN transistor~ T7 ana T8 which constitute a diferential ~mplifying circuit 15. To the base of one transistor T7 is supplied the output which is derived from the emitter~
o~ th~ output ~de transistors T5A and T5B in the dum~y ~20~5 circuit ~ection ~. TQ the common connection pQint of th~
emlttexs of th~ txansistors T7 and TS i connected an NPN
transistor T9 serving as a constant current source the base of which is connected to the base o~ a con~tant current source drivin~ transistor T10 and the emitter of a trans~stor Tll. ~ .
To ~he base o the other transistor T8 is supplted a xe~erence volta~e VR whic~ is obtained at the co ~ ection point of volt~ge-dIviain~ xes~stQrs Rl and R2 connected in series between the positive and negative power source lines 13 and 12. Accord.in~ly, the transi~tor~ T7 and T8 compare the output volt~e VN rom the dummy aircuit section 9 wi~h the re~erence volta~e ~'~ which i~ determ~ned by ~he resistance values of the rasl~tors Rl and R2 to thereby supply a current of a value corre~pondin~ to a difference between volta~es VN an~ VR to constant ~u~`lent source driving transistor~ T12 and T13 fr~m the tran~istox T8.
One d~ivin~ transistor~ T10 and Tll are connect~d ~hrough re~istors R3 and R4 to the positive and ne~ative power source lines 13 and 12, whereby a constant current which is determined by the reslstance values o the re~i.stoxs ~3 and R4 is flowed to the transistors T7 and T8 from the t~ansistor T9. The base of the driving transistor T10 is connec~ed to th~ bases of the constant current source transistor T2B in the main ~uffe~ circuit section 8 and the constant current source transistor T6B in ~he dummy circuit section 9 so that a value o a current supplied to one ~nput side transistors T13 and T4B is made coincident with a current value supplied to the constant current s~ce _ g _ \
'~
tran~tor ~9 ~ ths feed~ack c~rcuit sec~on 10.
On the other hand, the ~mitter an~ base o the other constant current source ~riving transistors T12 and T13 are connecte~ to the bases o~ the constant current ~ource trans~stor T2A in the main b~fer c~rcu~t sectlon 8 and the constant ~u~.ent souxce transistor T6A in the dummy circuit section 9 so that a value of a current ~lowed into the input side transistors T2A and T6A is controllea by a di~ference output derived-from the difexential amplifyin~ circuit 15 in the feedback circuit section 10 so as to reduce t~is difference output to 2ero~
With the circuit construction as described above, the ~C. bias conditions o~ respective ~ortions in the Main buffer circuit section 3 are determined by the re~istanc~
values o the re~istors Rl, R2 an~ R3, R4 in th~ feedback circuit section 10. More specifically, since the dummy circuit section 9 is constructed the s~me as the main b~ffer~circuit section 8~ the currents o the sa~e value are flowad through the correspondin~ portions. The valus of the current 10wea through the constant curr~nt source txans~stor T6B .~n the dummy circuit section 9 ~a~cordingly, the constant curxent source transistor T2B in the main buffer circuit sect~on 8) is de~ermined by the re~istance values of the xe~i~tors R3 and R4 connected to the driving transistors T10 and Tll. Meanwhile, the value of the current flowed through the constant current source tran~istor TSA in the du~my circuit section 9 taccordingly~ the consta~t current sourca transistor T2.~ in the main buer circuit ~ectlon 8) is deter~ined by the resi~tance ~alue of ~he resistors Rl and R2 which are connected to the ba~e ~ ~ O --~Q38~5 of one tran~ or ~8 in the diff~.rential amplifyin~
circuit lS. The reason is that the constant ~r~nt ~ource transistor T6A in the aummy circuit section ~ i5 controlled hy the out~ut frQm the driving transistors T12 and T13 so S as to make the output volta~e VN from the emltters of the output side transistors TSA an~ T5B in the dummy circuit section g equal to the reference voltaqe VR.
When the feedback sy~tem which is established by feedin~ the output voltaae ~ of the dummy circuit section 9 back to the constant current source txan~istor T6~ throuqh the ~ifferential amplifyin~ c~rcuit lS is made in the sta~le state as descri~ed ahove, a current In derived from the emit~er of th~ input side transistor T4A
to the base thereof is all supplled throu~h the base of lS the input side transistox T4B to the emitter thereof.
This operation condition can be established for the main buffer circuit section 8 of the same construct~on as the dummy ci~cuit section 9. That is, such a stable state that the output of the emitters o the output si~e tran~stors ~3A and T3B is fed back to the constant current source transistor T2A ~hrough the differential amplifyin~ circuit 15 is equivalently es~ablished in the main buffex circuit section ~.
CoQse~uently, also in the main buffer circuit section 8, the current delivered from the emitt2r of the transistor TlA to the base thereof hecomes Ia and ths current del~vered rom the base of the transistor TlB to the emitter thereof also becomes Ia. In other words, '_ ~his~ means that it is not neces~ary to take in any current from an external cir~uit connected to the input ter~n~l 11 ~D3~
~for exampl~, a capacitor 17 for sampl~ng and holdin~) so as to dxive the ma~n buffer circuit section 8.
Under the above biasin~ condition, the input v~ltage Vs applied to the input t~r~i n~l 11 is transmitted through the base-emitter path of the input si~e P~P
transistor TlA and the base-emitter path of the output s~de NPN transistor T3A to the output t~n~inAl 14. The input voltage Vs is also transmitted throu~h the base emitter path of the input side NPN transistor TlB and the hase-emi~ter path of the output side PNP tran~istor T3B to the output ~e tn~l 14. ~ccordingly, in one transmi~sion path, ~he potentlal is raised temporax~ly hi~h by the base-emitter volta~e of the input æide trans~stor ~lA (of the PNP
transistor) and this potential is lowered by the base-em~tter voltage of the output side transistor T3A (of the NRN
transistorl, while in the other transmission path, th~
potential is lowered temporarily by the ba~e-emi~ter volta~e of the inpu~ side transistor TlB (of the NPN
transistor) and this po~ential 1B raised hi~h hy the ba~e-emitter ~olta~e of the output s.ide tran~i~tor T3~ (of the PNP tran~istor).
If the above circuit i~ formed on the same IC
chip, the base-emitter volta~es o the transistors TlA and T3B, each tran~istor bein~ a PNP transistor, hecome s~stantially e~ual to each other and the ~a~e-emitter ~oltages o the transistor6 ~lB and T3A, each transistor being an NPN transistor, become sub~tanti~lly egual to each other. Therefore, 1~ both o the transmission path~, the relation o~ ~he potential at the output termlnal 14 relative to the potential at the input term; nal 11 becom2s - 12 ~
` 12~3~;S`
. ,.. -`
equal to each other witll the resul~ that as the input voltage Vs i~ changed, the output voltage V0 is changed in correspondenc~ thereto. ~nd, ~ven when the voltage in the transl;~ission path for the output signal is changed, the D.C. bias condition in ~he dummy circuit section 9 is never chang~d s~ that the curr~nt value which i3 fed back ~o the constant cu~Fent source transistor T2A in the m~in bufer circuit section 8 is never changed. A3 a xesult, the input side transi~tors TlA and TlB in ~he main buffer circuit ~ection 8 maintain the above state under which the transistors TlA and TlB do not take ~n the current from the external circuit by way of the input te~ ~ n In addition to ~uch operation, even ~f the current amplification ~actor he of the tr~nsi~tor i5 ~catte~ed at each sub~trate when the circùlt constructlon shown in Fig. 2 is foxmed on a number of the IC substrates, in respon~e to ~uch difference, the current which is fed back to the constant curren~ source transi~tor T6A
(accordin~ly, the constant current source tran~istor T2A
in the main bufer clrcuit section 8) ~hr~uqh the difer~ntial amplifyin~ c~rcuit 15 ~y the output from the dum~ly circuit ~ectlon 9 is change~l in correspondence with the a~ove ~cattering to thereby establish the stable ~state under which the output voltage V~ from the dummy circuit ~ection ~5 9 is coincident with the r~ference voltage VR, thus ~he scattering o~ the current amplification Eactor~ h~e being corrected.
As de.scribed above, according to the c~rcuit o~
the present lnven~ion consLructed as ~hown in Fi~. 2, without taking in the current to the input termin~l 11 - 13 ~
~2~).~
.. ~. " ., ~.
from th~ e~ternal circult, the input volt~e Vs can be transmitted to the output terminal 14, thu3 raaliz~ng the buffer circuit havin~ the considerably lar~e input impe-dance. Also, in the present invention, essentially the complementary circuits are constructed ~o that even when the input volta~e Vs is chan~ed over the range from the positive to the ne~ative, the ahove circuits can be operated in the same ~nn~r. Therefore, it is pnssible to transmit the signal of high speed and lar~e ampl~tude.
As set forth a~ove, accordina to the pr~ent invention, the dummy circuit havinq the ~ame clrcuit con-struction as the main buffer circuit incl~ding ~he oomplementary input side transistor~ i5 provided and the output thererom i~ compared with t~e reerence ~oltage by the differential ampliyin~ circuit to proviae the correctin~ feedback signal for the con~t~nt cuxrent ~ource~
of the dummy circuit and the main bu~fer circuit~ Ther~ore, even if the c~rrent amplification factors o~ the transi~tor~
are scattered, ~uch ~cattered cu~Lent amplification ac~or~
can be corrected so that the buffar circuit which alway~
ha~ a hl~h input impedance and which c~n transmit the input ~ignal of high speed ~nd lar~e amplitude can be real.ized ~y usinq the bipolar transistors.
The above de~cription is qiven on a single p~eferr-ed embodiment of the invention, but it. will be appaxent that many modifications and variations could be eff~cted by one sXilled in the art without departing from the spirit~
or scope of the novel concepts of the ~nvention, so that the scope of the ~nvention should be det~rrined by the appended clsims only.
Claims (3)
1. A high input impedance circuit comprising:
(a) first and second buffer circuits,/each of said first and second buffer circuits having first and second pairs of NPN and PNP transistors, bases of said first pair of NPN and PNP transistors being connected to each other, emitters of said second pair of NPN and PNP transistors being connected to each other, emitters of said first pair of PNP and NPN transistors being connected respectively to the bases of said second pair of NPN and PNP transistors,and first and second constant current circuits which are respectively connected to said emitters of said first pair of PNP
and NPN transistors;
(b) first and second constant current source circuits for driving said first and second constant current circuits of said first and second buffer circuits respectively; and (c) a control circuit for controlling an amount of a current of at least one of said first and second contact current source circuit.
(a) first and second buffer circuits,/each of said first and second buffer circuits having first and second pairs of NPN and PNP transistors, bases of said first pair of NPN and PNP transistors being connected to each other, emitters of said second pair of NPN and PNP transistors being connected to each other, emitters of said first pair of PNP and NPN transistors being connected respectively to the bases of said second pair of NPN and PNP transistors,and first and second constant current circuits which are respectively connected to said emitters of said first pair of PNP
and NPN transistors;
(b) first and second constant current source circuits for driving said first and second constant current circuits of said first and second buffer circuits respectively; and (c) a control circuit for controlling an amount of a current of at least one of said first and second contact current source circuit.
2. A high input impedience circuit according to claim 1, in which said control circuit includes a differential amplifier, first and second input terminals of said differ-rential amplifier being connected to the emitters of said second pair of NPN and PNP transistors of said second buffer circuit and a terminal having a predetermined voltage potential respectively, an output terminal of said differential amplifier being connected to at least one of said first and second constant current source circuits.
3. A high input impedance circuit according to claim 2, further comprising input and output terminals which are respectively connected to the bases of said first pair of PNP and NPN transistors and the emitters of said second pair of PNP and NPN transistors of said first buffer circuit, and a capacitor which is connected across said input terminal and a common terminal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9989/83 | 1983-01-28 | ||
| JP1983009989U JPS59118315U (en) | 1983-01-28 | 1983-01-28 | buffer circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1203855A true CA1203855A (en) | 1986-04-29 |
Family
ID=11735277
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000446138A Expired CA1203855A (en) | 1983-01-28 | 1984-01-26 | Buffer circuit |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4612464A (en) |
| EP (1) | EP0115949B1 (en) |
| JP (1) | JPS59118315U (en) |
| CA (1) | CA1203855A (en) |
| DE (1) | DE3470263D1 (en) |
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| GB9926956D0 (en) * | 1999-11-13 | 2000-01-12 | Koninkl Philips Electronics Nv | Amplifier |
| US7010286B2 (en) | 2000-04-14 | 2006-03-07 | Parkervision, Inc. | Apparatus, system, and method for down-converting and up-converting electromagnetic signals |
| US7454453B2 (en) | 2000-11-14 | 2008-11-18 | Parkervision, Inc. | Methods, systems, and computer program products for parallel correlation and applications thereof |
| US7072427B2 (en) | 2001-11-09 | 2006-07-04 | Parkervision, Inc. | Method and apparatus for reducing DC offsets in a communication system |
| US7460584B2 (en) | 2002-07-18 | 2008-12-02 | Parkervision, Inc. | Networking methods and systems |
| US7379883B2 (en) | 2002-07-18 | 2008-05-27 | Parkervision, Inc. | Networking methods and systems |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2955257A (en) * | 1956-07-25 | 1960-10-04 | Rca Corp | Transistor class b signal amplifier circuit |
| GB1059112A (en) * | 1963-08-20 | 1967-02-15 | British Broadcasting Corp | Improvements in and relating to buffer amplifiers |
| US3243606A (en) * | 1963-11-21 | 1966-03-29 | Sperry Rand Corp | Bipolar current signal driver |
| US3329836A (en) * | 1965-06-02 | 1967-07-04 | Nexus Res Lab Inc | Temperature compensated logarithmic amplifier |
| FR1461683A (en) * | 1965-10-29 | 1966-02-25 | Sfim | High input impedance power amplifier assembly |
| US3437836A (en) * | 1965-11-17 | 1969-04-08 | Westinghouse Electric Corp | Voltage adjustable limiter for operational elements |
| US3432688A (en) * | 1965-12-21 | 1969-03-11 | Ferroxcube Corp | Sense amplifier for memory system |
| US3436672A (en) * | 1966-03-08 | 1969-04-01 | Us Navy | High input impedance amplifier circuit |
| US3480800A (en) * | 1967-02-06 | 1969-11-25 | Bell Telephone Labor Inc | Balanced bistable multivibrator digital detector circuit |
| US3539835A (en) * | 1967-07-31 | 1970-11-10 | Dresser Systems Inc | Electronic driver for transverse mode pockel cell |
| US3517324A (en) * | 1968-01-22 | 1970-06-23 | Eastman Kodak Co | Complementary emitter follower |
| FR1585072A (en) * | 1968-06-26 | 1970-01-09 | ||
| US3649851A (en) * | 1970-02-25 | 1972-03-14 | Gen Instrument Corp | High capacitance driving circuit |
| US3663887A (en) * | 1970-08-14 | 1972-05-16 | Rca Corp | Memory sense amplifier inherently tolerant of large input disturbances |
| US3854057A (en) * | 1972-12-11 | 1974-12-10 | Lrc Corp | High speed impedance sensitive switch driver |
| US3932768A (en) * | 1973-03-15 | 1976-01-13 | Victor Company Of Japan, Ltd. | Limiting amplifier |
| US4149098A (en) * | 1976-05-20 | 1979-04-10 | The United States Of America As Represented By The Secretary Of The Navy | A. C. Switching system |
| DE3037528C2 (en) * | 1980-10-03 | 1983-10-13 | Vitalij Vasil'evič Andrianov | Amplifier built as an integrated circuit |
| US4419593A (en) * | 1981-06-29 | 1983-12-06 | Honeywell Inc. | Ultra fast driver circuit |
-
1983
- 1983-01-28 JP JP1983009989U patent/JPS59118315U/en active Granted
-
1984
- 1984-01-25 US US06/573,636 patent/US4612464A/en not_active Expired - Lifetime
- 1984-01-26 CA CA000446138A patent/CA1203855A/en not_active Expired
- 1984-01-27 DE DE8484300529T patent/DE3470263D1/en not_active Expired
- 1984-01-27 EP EP84300529A patent/EP0115949B1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| EP0115949A1 (en) | 1984-08-15 |
| US4612464A (en) | 1986-09-16 |
| DE3470263D1 (en) | 1988-05-05 |
| JPH0110007Y2 (en) | 1989-03-22 |
| EP0115949B1 (en) | 1988-03-30 |
| JPS59118315U (en) | 1984-08-09 |
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Legal Events
| Date | Code | Title | Description |
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| MKEX | Expiry |