CA1207915A - Data processing system having dual processors - Google Patents

Abstract

ABSTRACT

A data processing system having a host processor and an attached processor is disclosed. Each processor is capable of executing user programs under a different operating system and each processor is capable of accessing system memory but the host processor controls and performs all input and output operations for both processors. System memory is shared by the processors, therefore, only one processor is active on the bus system at any given time. Apparatus is disclosed for holding the host processor and starting the attached processor upon a command from the host and apparatus is disclosed for holding the attached processor and starting the host in the event of interrupt conditions, attempted access by the attached processor to protected areas of memory, or execution of an "out" instruction by the attached processor. Memory mapping apparatus which is under host control, but provides mapping for both the host and attached processors is shown.

Description

7~L5 na~ CF~T~G ~YST~M_~QI~ L PROC~S~ S

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F;eld of ~h~ Invention The invention relates generally to data processing systems and, more particularly, to systems having a plurality oE coupled processors utilizing different 5 operating systems.

Many manufacturers of digital computer hardware and software, for example Data General Corporation of Westboro, Massachusetts, have designed and developed proprietary 10 operating system software for use in conjunction with their computer products. Any application software which is designed to run on such a company's computers m~lst be compatible with that company's operating system. Software designed to operate under a different operating system must 15 be ~odi~ied to make it compatible. Such modifications are potentially time consuming and costly. The use of proprietary operating system software therefore limits the ability of owners of computer hardware using such proprietary operating systems to take advantage of widely available, but incompatible, applications software programs~

.

The availability o low cost, powerful microprocessors has led to the proliferation of mlcroprocessor-based data processing systems. These systems constitute a large market for application software programs. Virtually all 5 applications software programs must be.designed to run under the control of a specific operating system, which serves to interface the application program to the processor and perform various system functions. One popular microprocessor, for example, is the Intel 8086* which runs 10 the CP/M 86 operating system. In the past, however~ a computer user who has invested substantial resources in computer hardware and software of a computer manufacturer : using a proprietary operating system has typically been required either to purchase a separate microprocessor-based system or convert the software to be compatible with the ; proprietary operating system in order to utilize the various software products available.
Accordingly, a single system which is capable of running both a proprietary operating system and a popular operating system, such as CP/M 86, allows a computer hardware user to use his library of proprietary operating system related programs and still take advantage of the * - trade mark ~ZI~37~L5 variety of programs which are available under another operating system.
Summary of the Invention The present invention relates to a data processing system having a plurality of processors and having novel structure or controlling which processor is active on the bus system. ~ach processor shares the same memory space and, therefore, only one processor is active on the bus at any given time. In a preferred embodiment, each processor 10 is c~pable of executing programs under a different operating system, but one processor~ termed the host, controls all input and output operations~ Apparatus to control data/address paths and to start and hold each processor in accordance with various system or processor commands and 15 conditions is provided.
It is another feature of the present invention that memory mapping for all processors is controlled by the host processor.
It is yet another feature of the present invention that ~0 the host processor can protect certain areas of SySteM
memory from access by other processors and can regain ~ 3~7~ ~ ~

control of the bus system if an attempt to access to such an area is made by another processor.
It is an advantage of the present invention that applications software designed ~o run under a plurality of s operating systems can be executed in a single integrated system.
Other features and advantages of the present invention will be understood by those of ordinary skill in the art after referring to the detailed description of the preferred l0 embodiment and drawings herein.
~rief P~ript.io~ ~ the Drawings Figure 1 shows a simplified block diagram of a dual processor data processing system.
Figure 2 shows a more detailed block diagr~m of the 15 data processing system of Figure 1.
Figure 3 shows specific logic circuitry for implementing host processor 101.
Figure 4 shows specific logic circuitry for implementing attached processor 106, transceiver 207~ latch 20 208 and latch 209.

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Figure 5 shows specific logic circuitry for implementing transceiver 205, latch 206, and hyperspace P~OM
1~8.
Figures 6 and 6A show speciic logic circuitry for ~mplementing multiplexer 210 and map 211.
Figures 7 and 7A show specific logic circuitr~ for implemen~ing three-state buffer 213, bufer line drivers 21~, transceiver 215 and I/O device decode logic 212.
Figure 8 shows specific logic circuitry for - ~o implementing ~uffer line drivers ~16.
Figures 9 - 9~ show specific loyic circuitr~ fcr implemen~lng memory addressing 217~ R~ 218 and latch 219.
Figure 10 shows logic circuitry for ~enerating ~he ~iming signals of system timing 225 ~S Figure lOA shows timing ~iag~rams or timing sl~.gnals o~
Figure 10.
Figures 11 to llI show specific logic circuitry for i~plementing control logic 226.

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~0 Fig. 1 ~ efexring to Figure 1, a simplified block diagram of a data processing system is shown. The system contains a ` :~Z~'7~

first processor, identified as host processor 101 (HP 101), and a second processor, identified as attached processor 106 (AP 106); The processors and other system elements are interconnected by a bus system which, for the purposes of 5 this description, can be considered as consisting of a system bus and a logical address bus.
Map logic 102 can receive addresses over the logical address bus from HP 101, AP 106 or mass storage logic 107.
Map logic l02 generates an address in physical memory, RAM
10 logic 103, corresponding to the logi~al address received over the logical address bus. Data from RAM logic 103 is supplied directly to video logic 104 or over the system bus to ~P 101, AP 106, mass storage logic 107 or keyboard 105 Hyperspace ROM 108 is a memory system which provides a variety of capabilities such as power-up diagnostics, bootstraps from the mass storage device, emulated instructions, certain virtual console functions, character bit-maps for error codes which occur during the power~up procedure, and a display/keyboard emulator. Hyperspace ROM
108, when activated, receives address information from ~P
101 over the logical address bus and provides data on the system bus in response to the address received. The system ~Z~ 3~

bus also transfer addresses and data between HP 101 and keyboard 105, video logic 104, map logic 102, AP 106 and mass storage logic 107.
As will be discussed in more detail below, the flow of 5 addresses and data among the functional elements in Fig. 1 is con~rolled by a set of control signals~ ~P 101 and AP
106 share system memory, and ~herefore both HP 101 and AP
106 cannot be operatiny and in control of the bus system at the same time. In the embodiment disclosed, ~P 101 lS in l control o~ all input/output operations and certain communication paths and control ~unctions are available only to it~
Ei~ , A more detailed block diagram oE the system of Fig. 1 is shown in Fig. 2. In an exemplary embodimenti HP 101 contains CP~ 201, SIO (system input/output) 202 and XMC
(extended microcontroller chip) 203 which are interconnected via the system bus. Such an integrated circuit set is manufactured by Data General Corporation and is described in 20 various documents and publications oE that company and also : in U.S. patent 4~371l925. While the preEerred embodiment of the invention disclosed herein uses the integrated circuit chip set identified above, it will be understood by those knowledgeable in the art that the invention is not limited to this embodiment and various other processors can be used as HP 101.
Fig. 2 is intended to show the various data and address paths among the functional elements of the system. Certain paths are bidirectional, in that data/addresses are received and transmitted over the same lines, while certain paths are unidirectional ~rrows indicate the general direction of 1~ data/addrèss flow over the 16-bit parallel bus system. As mentioned above, the specific data/addres~ path which is enabled at any given time during the operation of this system is controlled by various signals and control means not shown in Fig. 2, bu~ discussed in more detail below in 15 regard to Figures 3-11.
SIO 202 provides a variety of capabilities including providing the complete 16-bit parallel ECLIPSE0 I/O bus and the byte serial microNOVA0 I/O bus; monitoring the syst~m bus for I/O instructions from the CPU; taking control of the 20 system bus to handle data channel requests from either of the I~O busses; providing the function of common peripheral devices such as the real time clock, asynchronous ,,.

12~3~9~5 communications interace, power monitor and programmable interva] timer; and maintaining a number of system configuration status signals. XMC 203 contains a number of vertical microinstructions, a decode PLA for identifying s macroinstruction opcodes and a vertical sequencing mechanism. More than one XMC chip may be connected to the system bus to provide a greater number of external microinstructions. XMC 203 sends sixteen bits of microcode (CR0-CR7~ to CPU 201 using an 8-bit time~multiplexed bus iO Transfers of microcode are sequenced by control signals passing between XMC 203 and CPU 201.
MB0-MB15 supply signals which may represent addresses, data or I/O control information to latch 206 and via buffer line drivers 204 to XMC 203~ MB0-MB15 may be supplied to or 15 received from CPU 201, SIO 202 or transceiver 205. If MB0-MB15 contains address information, latch 2Q6 will provide address signals LA0-LA15 to h~perspace ROM 108, multiplexer 210, buffer line driver 214, I/G device decode logic 212 and three-state bufer 213. AP 106 transmits 20 addresses or data over lines 86AD0-86AD15 to transceiver 207 and latch 209. Latch 20g also receives extended address bits 86AD16-86ADl9. Data is received by AP 106 rom transceiver 207 and latch 208. Latch 20g, when enabled, supplies address bits LAO~LA15 to multiplexer 210, I/O
device decode logic 212, three-state buffer 213 and buffer line driver 214. Multiplexer 210 also receives extended 5 address bits X~A0-XLA3. Multiplexer 210 in response to an address from either latch 206 or latch 209 provides address bits LM0-LM9 to MAP 211, which in turn, provides physical address bits PAO~PA9 to buffer line drivers 21A, transceiver 215 and memory addressing 217. Three-state buffer 213, iO transceiver 215 and buffer line drivers 214 provide addre~ses over lines BMB0-BMB15. Data input bits DIN0-DIN15 are provided to RAM 218 rom bufer line drivers 216.
Memory addressing and control 217 receives address information over BMB0-BM~lS and generates row/column 15 addresses and various control signals to RAM 218.
Transceivers 205, 207 and 215, video logic 104, keyboard 105 and mass storage logic 107 both receive and transmit information over ~ -BMB15.
In this embodiment~ mass storage logic 107 is 20 constructed of transceiver 222, FDC (floppy disk controller) 220, DMA (direct memory access) logic 221, latch 223, bu~fer line driver 224 and control logic (not shown). FDC 220, for example an NEC uPD765 or Intel 8272 floppy diskette controller chip, controls data transfers ko and from the floppy disk and may request and exercise control over the system and logical address bus. DMA 221, for example an 5 Intel 8257 t iS under the control of FDC 220~ Address information is supplied to the logical address bus via latch 223 and ~uffer line driver 274. Transceiver 222 receives and transmits addressf data and control information via the s~stem ~us.
RAM 218 provides output data bits DOUT0-DOUT15 to video lo~ic 104 and latch 219. Video logic 104 contains video timing circuitry, shift registers for providlng display data to the sys~em monitor and a CRT controller~ for example a Motorola 6845r which receives and transmits over BMB8~BMB15.
15 Finally~ system timing 225 provides a number of timing si~nals used throughout the system and bus control logic 226 generates the specific signals necessary to control bus access and address/data flow.

Figure 3 sho~s specific circuitry for implementing host processor 101 using CPU 201, SIO 202 and XMC 203 integrated circuits of the type identified above. Looking first at CPU

'7~s 201, ~ MB~5 transfer addresses, I/O control information and data to and from CP~ 201. If ADREN (address enable) is asserted low, CP~ 201 is supplyinq either a memory address or an I/O command on MB0 MB15. ME~C~C high indicates a 5 memory address while MEMCYC low indicates an I/O command.
I~ DATEN (data enable) is asserted low, CPU 201 is supplying memory or I/O data. The direction of the transfer when DATEN is low is indicated by the state o WB (write high byte) and WL (write low byte), as held in latch 501r l0 discussed below. If WB and WL are both hight a read operation is underway~ FETCH high indicates that the operation in progress is the fetching of an instructîon from memory. MAP (mapping enable) high indicates that logical addresses from CPU 201 or data channel logical addresses ~5 from FDC 220 are to a be translated into physical addresses by map logic 102. ABLOCK (CPU 102 bus lock) high indicates CPU 201 is inhibiting access to RAM 218 by any other device until the curren~ memcry operation is completed. PIPE

relates to the status of the internal CPU 201 instruction 20 registers.

PHl (clock phase 1) and PH2 ~clock phase 2) are provided as alternating, non-overlapping clock signals. The `` 3.Z~7~

system bus is time-multiplexed and CP~ 102, SIO 103 and XMC
103 are synchronized by these two externally yenerated clock sîgnals. In a preferre~ embodiment PHl and P~2 are each , high for approximately 200 nanoseconds. If A~REN is 5 asserted low while PHl is high, the system bus is used to select one of four address spaces (program memoryy console memory, I/O operations or local communications), the logical address within that address space and the direction and length of the data transfer. MEMCYC and MB0 arP used to ~O identify the specific address space. When P~2 goes high, MB0-MBl5 contain the data to be transferred. DATEN low indicates valid write data is available on the system bus.
READY low indicates that the data transfer underway cannot be comp`eted in the time availa~le and must be extended for ~5 additional PH2 periods. It can be seen that ADREN and DATEN
serve as interlocks to prevent addresses or data from being d~iven onto the bus at the wrong time.
REQ, STAT and ACK are related to the control of XMC 103 by CPU 201. WPROT (write protected page) high indicates that 20 a section of memory which is write protected has been accessed. VPROT (validity protection fault) high indicates that an access to a section of memory which is validity protected has been requestedO RESET low initializes the internal logic of CPU 201~ BREQ (bus request) high indicates that a system element, other than CPU 201, wants control of the system bus. In the current embodiment, there 5 axe four elements which may have control over the bus: CP~
201, SIO 202, AP 106 and FDC 220. The bus will be granted at the following PHl pulse if ABI.OCK is low and READY is high.

-- NMI (non-maskable interrupt) lo~ forces CPU 201 to l0 enter an interrupt sequence. IMTRQ (interrupt) low indicates that the processor should enter an interrup~
seguence if interrupts are enabled at that time. Finally, CR0-CR7 act as a microcode transfer bus to supply microcode from XMC 2~3 to CP~ 201.
Looking now at SIO 202, the signals not already discussed in regard to CP~ 201 will be briefly defined. As sta~ed above, SIO 202 handles the interface between the system bus and the ECLIPSE0 and microNOVA0 buses (not shown~. IONP, IODl, IOD2, IOCCK, UDCHR and UCLK control 20 transfers to and from the microNOVA bus. TTO is the asynchronous serial output line. TTI is the asynchronous serial input line. PF high, from the system power supply '7'3~i (not shown), indicates that the AC line power is coLrect.
LFREQ (AC line frequency) is used as a timing reference by the SIO 202 internal clock. CTS (clear to send) high inhibits transmissions to TT0 devices. DCHR (data channel request) low indicates a device on the ECLIPSE~ bus ls requesting a data channel transfer. DCHR is held high in this embodiment, since the ECLIPSE bus is not used. DCHM
(data channel mode) indicates whether the data channel sequence is an input (DCHM high) or an output (DCHM 14w) 10 se~uence. DCH~ is held high in this embodiment. EBLOCK
(SIO bus lock) high indicates the bus is unavailableO
MB0-MB15 are also supplied via bufer line drivers 2041 and 2042 to XMC 203. All inputs and outputs of XMC 203 have been described above with the exception of TSE, which is ~5 used to assure that no two XMC's try to drive the microcode transfer bus simultaneously when additional XMC's (not ' show,n) are added to the system~
; Fig~ 4 Fig. 4 shows an apparatus for implementing AP 106, 20 transceiver 207, latch 208 and latch 209. In this embodiment, AP 106 is an Intel 8086 16-bit HMOS
microprocessor. Persons of ordinary skill in the art will '7~3~

appreciate that this is only one of a number of other commercially available processors which could be used in this invention. Referring now to the inputs and outputs of AP 106, 86AD0-86AD15 provide addresses and data to and from 5 AP 106. These lines are time-multiplexed such that address and data information do not appear on the 86AD0 86AD15 bus simultaneously. During the address time phase, 86AD0 serves to indicate whether a byte is to be transferred on the lower 8-bits of the bus (86AD0-86AD7) during a memory or I/0 10 operation. During the address time phase, 86AD16-86ADl9 are the four most significant address lines for memory operationsr but are held low for I/0 operations. ~uring the data time phase, 86AD16-86ADl9 provide status information for both memory and I/0 operations.
]5 DEN (data enable) goes low and returns high during each memory and I/0 access. DT/R (data transmit/receive) indic~tes the directîon of data flow. M/I0 distinguishes between a memory access and an I/0 access. MN is a signal to AP 106 to indicate the AP 106 operating mode. In this 20 embodiment, MN is held high. BHE (bus high enable) low enables data onto the most significant 8-bits (86AD8-86AD15) of the data ~us. The NMI line is held low, since this 1~'7~5 function is handled by CP~ 201. The TEST feature is not used and is held low. 86INTR (interrupt request) high requests that AP 106 enter an interrupt acknowledge operation. 86HOLD high indicates that AP 106 is being S requested to enter a hold state. 86HLDA (hold acknowledge) high indicates that AP 106 acknowledges the hold request.
86WR low indicates ~P 106 is performing a write operation to either memory or I/O, depending on the state of M,/IO.

-86IMTA ~interrupt ac~nowledge) low indicates 85INTR high has l0 been acknowledged by AP 106.
ALE (address latch enable) high indicates that anaddress is avzilable on the data bus and, therefore, goes high only during the AP 106 address time phase. 86RESET
high causes te~mination of AP 106 activity. Execution is 15 reinitialized when B6RESET returns low. 86RDY low indicates that a memory or I/O transaction has not been completed~
CLR provides the basic AP 106 timing. ~P 106 is clocked by 8086CLK from system timing 217.
86AD0-86~D19 and BHE are provided from AP 106 to latch 20 209, implemented in this embodiment as latches 20gl-2098.
These inputs are latched by ALE from AP 106. Outputs are enabled by 8086 from control logic 218 (Fig. llA).

~IL2~7~

Therefore, when ~P 106 is active, indicated by 8086 low, logical addresses are supplied by latches 2091-20~3~ ~LE
~rom AP 106 will latch the information on 86AD0-~6AD1~
during the AP 106 address time phase. In addition, when 5 enabledy latch 2093 holds ~APEN (map enablet high and provides LBHE to bus control logic 218 (Fig. 11~).
The 86AD0-86AD15 lines are provided to one side of transceivers 2071 and 2072 and the BMB0-BMB15 lines are pr~vided to the other side. Enabling of transceiver 2071 J and 2072 is controlled by BE~, which i8 low when addresses are not enabled on the bus, AP 106 is not acknowledging an interrupt, a validity protected memory location is not being a~cessed/ data is enabled on 86AD0-86AD15 by AP 106 and the CP~ 201 data transfer phase is active. The direction of l5 data flow through transceivers 2071 and 2072 is controlled by DT~R from AP 106. DT/R high indicates a data transfer from AP 106~ ..
Finall~ in Fig. 4, AP 106 receives 8 bits of interrupt vector data over 86AD0-86~D7 from latch 208. BMB8-BMB15 are 20 latched into 208 by ~TPDOB2 high (Fig. 11), indicating CPU
201 is updating the AP 106 interrupt vector and PH2 is active, and outputs are enabled by 86INTA low, indicating AP
106 is acknowledging receipt of an interrupt.

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Looking now at Fig. 5, specific logic circuitry for 5 implementing transceiver 205, latch 206 and hyperspace ROM
108 is shown. Latches 2061 and 2062 receive MB0~MB7 and MB8-MB15 from CP~ 201 or SIO 202. Data is enabled into 2061 and 2062 during the PHl phase by ADREN going low and is la~ched when P~l goes high. Gating o~ ADREN with P~l 0 ensures the proper address information is present at latches 2061 and 2062 when latching occurs. Latch 2061 and 2062 outputs are enabled if 8086 is high tindicating AP 106 iS
not activeJ r a system reset is not requested and DACK high indicat~s that mass storage logic 107 is not active on ~he 15 logical address bus. Latch 501 receives MEMCYC~ WH~ WL and ~AP from CPU 201. These signals are latched as SYSMEMCY, SYSWH, SYSWL and MAPEN. Latch 501 is controlled by the same latch and enable conditions as latches 2061 and 2062.
Transceivers 2051 and 2052 are connected to BMB0-BMB7 20 and BMB8-BMB15 on one side and MB0-~B7 and MB8-MB15 on the other side. For transceivers 2051 and 2052 to be enabled, several conditions must be met. ROM high, indicating ROM

~2~7~5 10B is not enabled; SYSMEMCY high, indicating a memory cycle; V-PROT high, indicating the memory address is not validity protected, sysaDREN high, indicating addresses a~e not enabled on the bus; and NMISEL high from Fig. 7A. In 5 addition, all conditions required to enable latches 2061 and 2062 must also be present. The direction of transceiver 205 is determined by READ indicating whether the operation is a read or a wri~e (Fig. 6A).
~yperspace ROM 108 is implemented as 8K x 8 bit EPROM's 10 1081 and 1082. Both EPROM 1081 and 1082 receive LA3-LA15 rom latches 2061 and 2062. As mentioned above, ROM 108 provides a variety o~ ~eatures such as power-up diagnostics, system bootstraps, limited virtual console, some error code bit maps and a display/keyboard emulator to provide a usable 15 user interface at power-up~ In addition, ROM 108 aLlows a significant reduction in the hardware logic required to support I/O operations by emulating some I/O interface hardware. As discussed below, PAL 2121 (Fig. 7A) monitors LAl and LA2 and, when they are high along with HYPER, 20 generates ROMSEL which results in enabling o~ ROM 108. ROM
108 then supplies MB0-MB15 in response to LA3-LA15 when lZ~

AD~EN is high. As discussed below in regard to Fig. 7A, ROM
108 cannot be accessed by AP 1060 ig. 6 ~nd 6A
Fig. 6 and 6A show logic circuitry for implementing s multiplexer 210 and map 211. Map 211 (Fig. 6A) employs three 1~ x 4 bit RAM's 2111-2113 to form a lK x 12 bit memory which provides mapping for both HP 101 and hP 106.
Each of the 1024 addresses available from map 211 specifies the ph~sical location of lK words, giving the system a total 10 physical address space o 1024K words. In this embodiment, BP 101 use 256 x 12 bits of the array to provide four user maps and four data channel maps~ AP 106 mapping uses 512 x 12 bits to accommodate its 512K words of logical address space. All map loading, including the AP 106 map area, is l5 loaded by HP 101. As discussed below in regard to Figure 7, the contents of map 211 can be modified under the control of HP 101.
In response to map address bits LMO-LM9, RAM's 2111-2113 provide memory address bits PAO-PA9, WP, which 20 indicates if the memory location corresponding to the address is write protected, and VP, which indicates if ~he memory location is validity protected. LMO-LM9 are supplied `` ~2~'7~

from multiplexer 210, which is constructed of 2-line multip'exers 2101 and 2102 and 4-to-1 multiplexers 2103 and 2104. Qilad flip-flop 601 is clocked by the rising edye of the output of gate 602, which will occur when either 5 ALP~APl~OS or LMSSEL, from PAL 2121, goes high after both have been low simultaneously, Flip-flop 601 receives BMB0, BMBll~ BMB13 and BMB15 as inputs and provides WPEN (write protect enable~, ~MAPl and ~MAP2 (user map selection bits) and SLEAZE (parity indication)0 ~MARl and ~MAP2 are 10 indi~idually AN~ed with A~G~NT from bus arbitration logi.c 1180 to yield M~PA and MAPB, which are provided to multiplexer 21040 Selection among the inpu~s to mulitplexers 2103 and 2104 is based on the state oE signals ~PEN and S~B. If MAPS is high, SMB~wil~ be high~ If MAPS
is low, SMB will ha~e the same state as 8086. Table 1 shows the results of the selection done by multiplexers 2101-2103 in response to the four possible combinations of input conditions~

L~0 0 0 1 LA6 LMl 1 0 XLA0 LA7 LM2 0 ABGKNT XLAl LA8 LM3 ~YPER MAPB XLA2 LA9 LM5 LAl LAl LAl LAll LMg LA5 LA5 LA5 LA15 If MAPS (map select) from hyperspace PAL 2121 is asserted low, NAPSEL (map read/write) will be hiyh when data is enabled and low otherwise.
MAPWRT (map write) will go low at the rising edge of 5 CLR70, i~ MAPSEL is high and a write operation is underway, indicated by SYSWL or SYSWH being low. Wilen MAPWRT goes low the data PA0-PA9 from transceiver 215, discussed below, along ~ith WP and VP will be stored at the address on LM0-LM9.
Since MAPS is high and MAPEN is 10wr this addres.s ~ill be 10 speci~ied by the data on LA6-LA15 and is under the control of HP 101 only~ If MAPSEL is high, but a read operation is requested, the direction of transceiver 215 is reversed and WP, VP and PA0-PA9 will be provided to BMB0--BMB15.

~Z~:~'79i~

The 512 x 12 bit area devoted to AP 106 mapping will be entered when 8086 (and therefore L~lO) is high. As mentioned above, MAPEN is held high when 8086 is high. AP 106 provides nine bits of information, hAl-LA5 and XLA0-XLA3, to RAM's 5 2111-2113. When CP~ 201 has enabled map 211 and, therefore, 8086 is low, MAPEN will be high and 5MB will be low. In ~his condition, ABGRNT, MAPA and MAP~ allow selection among the eight HP 101 maps. Addresses for the lK blocks o memor~
wi~hin the 32 x 12 bit areas of each map are specified by 10 LAl-LA5. The 256 x 12 bit area accessed when MAPEN and SMB
are both low provides maping for all CPU 201 memory accesses other than the eigh~ HP 101 maps! such as accesses to memory areas which support hyperspace operations and accesses for identity purposes.
15 Fig. 7 Fig. 7 shows logic circuitry for implementing three-state buffer 213, buffer line driver 214 and transceiver 215. Looking first at transceiver 215r implemented as octal transceivers 2151 and 2152, one side of 20 transceivers 2151 and 2152 is connected to WP, VP~ and PA0-PA9. The other sides are connected to BMB0-BMB15. The direction of data flow is controlled b~ READ such that, if ~24~'7~LS

-25- .

MAPSEL is high, and therefore MAPS is high, and READ is low, the data on B~BO, BMBl and BMB6-BMB15 will be presented to RAM's 2111-2113 for storage at the address LA6-LA15, as specified above in Table 1. I~ MAPSEL is hi~h and READ is 5 high, PA0-PA9, VP, WP from map 211 at address LA6-LA15 are presented ~n BMBO, BMBl and BMB6-BMB15.
PA0-PA9 are also supplied to buffer line drivers 2141 and 2142, along with SYSMEMCY; SYSWHP, low when indicating that a high byte write has been requested to a memory area 10 which is not write protected; SYSWLP, low when indicating that a low byte write has been requested to a memory area which is not wri~e protected and the inverse of LA0, LA6 and LA7. The address information is placed on~o BMBO-BMB7 wherever ~S~ADREN is low. Buffer line driv~r 2142 also provides five extended memory addre~s bits XMA0-XMA4 based on PA0-PA4. XMA0-XMA4 are used in addressing expanded memory (not shown) in addition to RAM 218. LA8-LA15 are supplied to three-state buffer 213 and, if B~SADREN is low, placed onto .
BMB8-B~B15. Since BUSADREN is neve~ low when ~PSEL is high, 20 there is no conf lict on BMBO-B~B15.

-26~

F i9 - 7A
Looking now at I/O device decode Logic 212, hyperspace PAL 2121 receives LAl-LA5, LA8-LA10, FETCH and HYPER as inputs. Based on ~hese inputs PAL 2121 outputs MAPS ~map 5 select), AUXSEL (auxiliary I/O select), ROMSEL (h~perspace ROM 108 select), EMI/OSEL (emulated I/O select), 86SEL, (AP
106 select), LMSSEL (load map status select), NMIS (NMI
select) and RAMSEL (RAM 218 select). FETCH, as mentioned, indicates that the memory operation in progress is an 10 instruction fetch. ~YPERy from gate 2122, is low only when LAO and SYSMEMCY are both high (lndicating an I/O operation) and E~HYP (hyperspace PAL enable) from flip flop 2123 is also high. ENHYP will be driven high at the falling edge of CLK8 during each PHl period in which SYSADRE~ is asserted Jow.
I5 When SYSADREN goes high, at approximately the end of PHl, the set pulse to flip flop 2123 is removed. ENHYP will stay hiyh until driven low b~ READY low at the rising edge of A~P~APlMOS. ENHYP will therefore stay high wherever a current memory or I/O transaction cannot be completed and 20 will yo low when the transaction is done.
Only one of the outputs of hyperspace PAh 2121 will he high at any one time. Therefore, whenever an I/O operation ~Z~'~9~

~27-is underway and PAL 2121 is enabled/ address bits LAl-LA5 and LA8-LA10 are decoded by PAL 2121 to uniquely identify the typ~ of I/O operation being re~uested. Table 2 shows the logic statements for correlating the outputs of PAL 2121 with the inputs, An asterisk indicates ~ loglcal AND operation while a plus sign indica~es a logical OR operation.

~OMSEL = HYPER * LAl * LA2 ~ANSEL = HYPER * LAl +MYPER * LAl * LA2 * LA3 ~ HYPER * LAl * LA2 * LA3 * LA4 MAPS = HYPE~ * LAl * LA2 * LA3 * LA4 * LA5 ENIOSEL- HYPER * LAl * LA2 * LA3 * LA4 * LA5 * ~ETCH
* LA8 * LA9 * LA10 +HYPER * LAl * LA2 * LA3 * ~A4 * LA5 * FETCH
* LA8 * LA9 * LA10 ~HYPER * hAl * ~ * LA3 * LA4 * LA5 * FETC~
* LA8 * ~ * LA10 +~YPER * LAl * ~ * LA3 * LA4 * ~ * EETCH
* ~ * LA9 * LA10 AT6SEL = HYPER * LAl * LA2 * LA3 * LA4 * LA5 * FETCH
* LA8 * LA9 * LA10 LMSSEL = ~YPER * LAl * LA2 * LA3 * LA4 * LA5 * FETCH
* LA8 * LA9 * LA10 NNIS = HYPER * LAl * LAX * LA3 * LA4 * LA5 * ~ * LA9 * ~
AUXSEL = HYPER * LAl * LA~ * LA3 * LA4 * LA5 * E'ETCH
* LA8 * LAg * LA10 ,, 79~

As stated above, HP 101.controls all system I/O, therefore AP 106 does not need to communicate with PAL 2121.
Since LA0 is held low whenever AP 106 is running, keeping HYPER high, AP 106 is prevented from accessing hyperspace ROM
5 108.
~i~. 8 Logic circuitry for implementing buffer line driver 216 i& aiso shown in Fig. 7. B~B0-BMB7 are supplied to driver 2161 and BMB8-BMB15 are supplied to driver 2162. The outputs 10 of drivers 2161 and 2162 are supplied to RAM 218 as data inputs DIN0-DIN15.
Ei5~ , Circuitry for implementing R~M 218 is shown in Fig. 9.
In this embodiment, RAM 218 is constructed of thirty-six 64K
1~ x 1 bit RAMIs 901-936. RAM's 901~936 are considered as being di~ided into a "kernal" memory bank 2181 made up of ~AMS
901-918 and an "optional" memory bank ~182 made up of RANS
919-936. The kernal and optional memorie3 are further divided into a high memory byte of 8 RAM's ~901-908 and

2~ 919-926) and a low memory byte of eight RAM's tgl0-917 and 928-935~. Each byte has a ninth parity RAM a.ssociated with it (909, 918, 927, 336). This arrangement yields a system '7~
29- .

memory of 128K 16-bit words,.each word having an upper byte and lower byte parity bit associated with it. It will be appreciated by those knowledgeable in the art that well-kno~n techni~ues are available to modify the syste~ to use memories of different storage capacity~ .
As shown in Fig. 9, each RAM 901-gl8 is supplied with eight bits of address data 0RA0~0~A7, KRAS (kernal row address strobe) and KCAS (kernal column address strobe). The high memory byte receives RAM-W~ (high byte write) and the 10 low memory by~e receives ~AM-WL (low byte write)r Parity RAM's 909 and 918 receive parity data bits OPODH and OPOD~
respectively at their data inputs while RAM's 901-908 and 910-917 each receive one of the data bits DIN0-DIN15 at their data inputs. F.i~allyt each RAM 901-9n8, 910-917 supplies one 15 bit of the output DO~T0-DO~T15 while RAM 909 and 918 supply output parity bits DOPE H and DOPE L. RAMS 919-936 a~e addressed in the same manner, except that they receive address bits 1RA0-1RA8, optional memory row strobe OPTRAS, optional memory column strobe OPTCAS and parity inputs lPODH
~O and lPOD~.

Ei~L 9A
Parity data OPODH, lPODH, 0PODL and lPODL are supplied to RAM ~18 from 9-bit parity generators 930 and 931. Parity generators 930 and 931 receive BM~O-BMB15 and, in this 5 embodiment, have their even parity outputs supplied to RAM
218. In this figure, and in the other figures herein, a signal identified as "UP" or "p~pll is a "pull-up" input and is always high.
Fi~
Logic circuitry for implementing memory addressing and control 217 is shown in figs. 9B, 9C, 9D and 9E~ Looking first at Fig. 9B, row address and column address multiplexin~
rirCuitry is shown. As mentioned above, video logic 10~ in the system described herein incorporates a CRT controller.
l5 This controller, the techniques for implementation which are well understood in the art, is allowed to access RAM 218 during PHl, when memory accesses by other system components are prohibited, to retrieve data or display.
Address multiplexing 217 therefore incorporates five 20 multiplexers 950-954. Multiplexers 950 and 951 involve addressing of RAM 218 by HP 101 or AP 106 while multiplexers 952-954 involve addressing of display related information being accessed by the CRT controller. CM~X, the selection input to multiplexers 950 and 951, and GMUX, the seLection input to multiplexers 952 and 953, are timing signals to allow the source of the multiplexer outputs to change from 5 the row address to the column address at the proper time.
GMUX goes low when CLK3 goes high and returns high when CLKli goes low. CM~X goes low when CLK2 goes high and returns high when CLKll goes low. GRACYC, the selection input to multiplexer 354, is generated by video logic 104. Contention 10 on the multiplexer output lines is avoided by enabling 950 and g51 when CLK10 is low and 952-954 when CLK10 is low.

Addressing for a RAM 218 incorporating 256K x 1 bit RAM's (schematically ident.ical to RAM's 901-.436 of F;.g. 9 15 except ha~ing nine address inputs QRA0-0RA8 and lRA0-lRA8) can be accomplished in a straightforward manner and without modification of the circuitry of Fig. 9B by use of the circuitry of Fig. 9C to utilize PA2 and PA3 to generate 0R~8 and 1~A8.
20 EY4L~_2n Logic for generating the row and column address strobes for the kernal and optional memory banks and the high and low '79~5 byte write signals is shown in Fig. 9D. It can be seen that there will be a row strobe and a co~.umn strobe generated during PHl, for use by the CRT controller in accessing data for display, and a row and column strobe generated during PH2 for use by HP101 or AP106 in writing to or reading from RAM
2I8. Since the CRT controller does not write data to RAM
218, the write enable signals will occur only during P~.
KRAS and OPT~AS are low when CLR2 is high and CL~8 is high or when CLKl is high and CLK9 is high~ These CLR
0 signal~, as well as the other timing signals discussed below, are depicted in Fig. 10A. KCAS is asserted low when (a) GRACYC is high (indicating the CRT controller is generating ~he column address to memory), CLK4 is high and CLKll is high or (b) when CLKll is high, CREADY is highr (indicating 15 RE~DY is high when ~LPH~PlMOS goes high at the end of P~2), .
CLK3 is high and KMSEL ( kernal memory select) is high.

OPTCAS is asserted low when CLKll is highr CREADY is high r CLK3 is high and OPTMSEL ~optional memor~ select) is high.

Generation of KMSEL and OPTMSEL (Fig. 9E) is discussed below.

20 RAM-WL will go low if either KCAS or OPTCAS is asserted low, CLX9 is highr CLK6 is high and SYSWLPr indicating that a low byte write has been requested to a memory area which is not :_, ``" ~12~'7~

write protected, is low. Similarly, RAM-WH will go low if KCAS or OPTCAS is low, CLK 9 is high, CLK6 is high and ._ SYSWHP, indicating that a high b~te write has been requested to a memory area which is not write protectedl is low.
5 Ei~a 9E an~ 2F
Logic circuitry for generating KMS EL, OPTMS EL, DLAT
(data latching signal to latch ~19) and OBEN (output enabling signal to latch 219) is shown in Fig. 9E. Looking first at flip flop 960, when CLKO goes high, V~LCYC (valid cycle~ will lO be driven high by the output of gate 961. When ~
subsequently goes low, the output of gate 961 will return high and the reset signal is removed. If either CREADY is low or SYSADREN is low, VALCYC will be driven low at the following CLK9 rising edge. VALCYC must be low to allow l5 sele~tion of either kernal or option memory. If VALCYC is low and either RAMSEL, from hyperspace PAL 2121, is low or SYSMEMCY is high and LAO is low, indicating a memory operation, the output of gate 962 will go high. Gate 963 receives PAO-PA2, which provide the capabilit~ for expanding 20 the system to accommodate selectable memory areas in addition to the kernal and optional memory banks. In the particular embodiment described herein, either kernal or optional memory 7~3~5 will always be selected, therefore PAO-PA2 are held lo~ and the output of gate 963 is held high. When the output of gate 96~ goes high, either the kernal or optional memory will be selected, dependi.ng on the state of PA3.
~eturning to flip flop 960; when VALCYC goes low, the Q
output of flip ~lop 960 will go high. If CRE~ADY and CLK2 are high, BUSAD~EN will go low. BUSADREN iS used to enable three-sta~e ~uffer 213 and buffer line drivers 21~1 and 2142 (Fig. 7). When CLK2 goes lowr E3USADREN will go high, and l since PH2 is high at this time , BUSDA~EN will go low. If the output o~ gate 964 and WRITE go low (indicating a memory write operation is not requested) while E3USD~TEN is low, O~EN
will go low enabling the outputs of latch 219. If OBEN is low and C~EAD~ is low, the output of gate 965 will be lo~7.
l~ When CAS goes low, indicating either KCAS low or OPTCAS 10wr DLAT will go high enabling the data on DOUT0-DOUT15, ~OPE E~
and DOPE L into latches 2191~and 2192 (Fig. ~F).
Fi~. 10 and 10~
Logic circuitry ~or generating the various timing 20 signals required throughout the system is shown in Fig. 10.
Timing diagrams in Fig. 10~ graphically represent selected outputs of the Fig. 10 circuitry~ A 48 megahertz clock 7 ~ ~ ~

signal from oscillator 1001 is inverted and supplied to the clocking inputs of flip flops 1002-1004. The inputs and o~tputs of flip flops 1002-1004 are interconnected so as to cause flip flops 1002-1004 to generate twelve staggered clock s signals CLK0 CLKll and their inverses CLK0-CLKll, each signal having a period of 2 M~z (24 times the period of the 48 MHZ
signal from oscillator 1001). Based on these timing signals, several other clock signals are derived. ALPHAPlMOS goes high when CLK0 goes low and returns low when CLKll goes high.
10 ALP~AP2MOS goes high when CL~0 goes low and returns low when C~Rll goes high. P~l goes ~igh when CLRl goes high and -returns low when CLK0 goes low. PH2 goes high when CLKl goes high and returns low when CLK0 goes low. CLK21 goes low when CLKg goes high and returns high when CI~Rl~ goes low.
15 Finally, CLK70 yoes high when CLK7 goes high and returns low when CLK10 goes low.
Fig. 10 also shows logic circuitry for generating 8086CLK, the clocking pulse for AP106. Flip flop 1010 receives the inverted 48 MHZ signal from oscillator 1001 and 20 has its outputs and inputs interconnected so as to yield an 8086CLK signal having a period of 8 MHZ (six times the period of the 48 MHZ siynal). The clocking signals to HP101 (P~l ~Z(~ 5 and PH2) therefore, have periods which are an integer multiple of the AP106 clocking signal.

The system disclosed herein incorporates two processors, HP 101 and AP 106, capable of executing user programs. Since the processors share the same memory space they are constrained to run serially. That is, one processor is in an idle or hold condition while the other is running. Host processor 101 i5 the s~stem "master" in the sense that ~P 101 10 handles all I/0 operations and is the processor selected upon power-up, after a system reset and upon the occurrence of an interrupt. In additiont HP 101 is activated i~ AP 106 terminates its processing by executing an "out" inskruction or if AP 106 attempts to access a validity protected memory ~S location. To perform its functions as host HP 101 has certain capabilities, such as control over the memory mapping operation (and therefore control over the location of the AP
106 logical address space in physical memory~ and control o~er which memory areas are accessible to AP 106. HP 101 can also read, set and clear AP 106 "done", "busy" and "interrupt status" bits maintained in memory, can speci~y an AP 101 interrupt vector, and can access a hardware register ~(379~S

containing indications of why AP 106 relinquished control (e.g. "out" instruction execution, validity protected memory access~.
When AP 106 is running, it will continue to run until 5 one o~ the following conditions is met: an NMI is receivedr an interrupt (other than an NMI~ is received and interrupts are enabled, AP 106 executes an out instruction or AP 106 accesses a validity protected page. If any NMI is received~
~P 106 will be held at its current point and the NMI will be 10 handled. After it is handled, if the system was not stopped or rese~ b~ the NMI, AP 106 will be restarted at i~s last location. This action is totally transparent to the user.
If an interrupt (other than an NMI) is received while interrupts are enabled, AP 106 is held at its current l5 position, and HP 101 is started. The HP 101 interrupt vector sequence will be initiated, with the EIP 101 interrupt return address being the HP 101 address immediatel~ following the address of the command that last started AP 106. The interrupt handler may then return to that address in HP 101 20 after the interrupt(s) are handled and AP 101 may be restarted.

~(1'7S~

If AP 106 executed an o~t ins~ruction, the 860UT bit will be set in the AP 106 status register, the done bit will be set high, and AP 106 will be held at that point. ~P 1~1 will be started at the address immediately after the function 5 that started AP 106~ All information needed by HP 101 to complete ~hatever I/0 process AP 106 was performing at the ~ime the out signal was generated is retained by AP 106 in a set of locations in system memory termed the "contex~ blocknO
Since HP 101 controls the mapping of AP 106 memory, ~P 101 is lO aware o the location of the context block and can access its contents. HP 101 then performs the I/0 operation and, i~
required, restarts AP 106~
If AP 106 accessed a validity protected page, the VP bit is set in the AP 106 status register, the done bit will be l5 set high, and AP 106 will be held at that point. HP 101 will be started at the address immediately after the function that started AP 106.
Fi~
Figs. 11 to llI show logic to control bus access and the 20 starting and halting of HP 101 and AP lOS. Looking first at Fig. 11, decoder 1101 is enabled by 86SEL from hyperspace PAL
2121, as discussed below. When decoder 1101 is enabled, LA14 ~2~37~LS

and LA15 are decoded to drive either ATPDOB tAP 106 interrupt vector load), ATPDOC (AP 106 start request), ATPOUTCLR or ATPRSTCL~ low. ATPDOB is provided to flip-flop 1140 (Fig.
11D) and is also inverted, ANDed with PHl to ensure that it S is only asserted during PH2, and provided as the latching input to latch 208. AT~DOC is provided to bus arbitration PAL llg0, discussed below. ATPOUTCLR is also provided to flip-flop 1140 discussed below. AT~STCLK is inverted and used as the clocking input of flip-~lop 1102. When ATPRSTCLE~
10 gses low, flip-flop 1102 is clocked and 86RESET and 86RESET
are set according to the state of LA13. 86RESET is provided as the RST input to AP 106. 86R~SET and ATPRSTCLK are also provided to gate 1110 (Fig. llA).
In Fig. llA, 86RESET and A~'PRST~LK are nanded with the ~5 inverse of 86~LDA from AP ln6 to create 8086, which when low indicates that AP 106 is the processor which is currently running. 8086 is provided as the output enabling signal to latches 2091-2093 (Fig. 5), to the output enabliny logic of latch 206 (Fig. 4), to bus arbitration PAL 1180 ~Fig. llG) 20 and to buffer line driver 1192 (Fig. llH), The inverse, 8086, is provided to multiplexer 2010 (Fig. 6).

In Fig. llB, to synchroniæe the starting of AP 106 with HP 101 timing, 86RDY (ready signal to AP 106) is held low during PHl. During PH2, the clocking of flip flop 1120 is constrained to occur only when both CLK4 and 8086 CLK are 5 lowO 86RDY will be driven high only if ~6ADREN (from Fig.
llH), PALE (pended ALE) and READY are high at the time flip-flop 1120 is clockedO PALE is generated by flip-flop 1123, which is clocked by the rising edge of ALE. When 86RDY

-is low, PALE is held low~ 86~DY will be high either when PHl 10 is high or when flip-flop 1120 is clocked and all inputs to gate 1122 are not high. When 86RDY is high, PALE is driven high at the rising edge of ~LE. Therefore, during P~2, 86R~Y
will be driven high at the first clocking pulse to lip-flop 1120 after ALE has returned low.
Looking now at Fig. llC, 86RDY is supplied as the clocking input to flip-flop 1130. When 86RDY goes high, if ~/IO is high, indicating a memory access, and VPROT is high, indicating a validity protected page is being accessed, 86VP
will be driven low.
2~ As was discussed above, one of the ways AP 106 turns over control to host processor l0l is by an "out" operation.
Since AP 106 does not directly control any I/O, an attempt by

3~L5 AP 106 to perform an output operation is interpreted as an "out" request. In Fig. llD, 860~T is driven low when M/IO
and 86WR are both low, indicating an output write condition.
860UT is driven high b~ either an 86~ESET or an ATPO~TCLR
5 (out clear) signal from flip-flop 1102. Flip~flop 1140 also generates 86INTR, the AP 106 interrupt request signal~
86INTR is driven high by ATPDOB- Erom decoder 1101 ~Fig. 11).
86 INTR is driven low either by an attached processor reset, 86RESET, Erom 1ip-flop 1102 or by the interrupt acknowledge lO signal, 86 I~TA, from AP 106 ~oing low, indicating the interrupt request has been acknowledged.
A2106, once started, will continue to-run until one o four corlditions is met: (1) a CPU 201 non-maskable interrupt is ieceived, indicated by NMI going low, (2) an interrtlpt 15 (other than a non-maskable interrupt) is received and interrupts are enabled indicated by INTRQ (interrupt request from SIO 202 and INTEN (interrupts enabled) both being low, l3~ an "out" instruction was executed by AP 106, indicated by 860UT going low, or (4) AP 106 accessed a validity protected 20 page, indicated by 86~P going low. Logic for generating AREQ, which indicates one of the above four conditions has occurred, is shown in Fig. llE. AREQ Will cause AP 106 to 7~5 halt and CP~ 201 to become active AREQ is provided to 86R~N
logic (Fig. llF) and bus arbitration PAL 1180 (Fig. llG).
Looking at Fig. llF, if AP 106 is running, any one of four signals going high will cause AP 106 to enter a hold 5 mode, indicated by 86HOLD going high. AREQ has been discussed above. 86~EQ going high, indicates neither CPU 201 nor AP 106 is requesting that AP 106 have control of the system bus. EBREQ going high, indicates SIO 202 is requesting control of the bus. D~AHRQ going high, lndicates 10 ~ 220 is requesting control of the bus, the output of gate 1160 will go low and, at the next PH2 rising edge, 86HOLD
will be driven high. AB&RNT low indicates CPU 201 has granted control of the bus system to another device. This signal operates as a condition ~hich must be met to start ~P
]5 106, rather than a cause of AP 106 halt.
In Fig. llG, bus arbitration logic 1180 is the source of ABGRNT, B6REQ, EBLOCK and BREQ. Logic 1180 is implemented as a PAL having as inputs AREQ (Fig. llF), ATPDOC (Fig. llA), 8086 (Fig. llB), DMAHRQ (from DMA 221), DRQ (from F~C 220~, 20 EBREQ (from SIO 202), and READY and ABLOCK (from CP~ 201).
~he logic statements for qenerating the outputs from the ~'7~

inputs are given in Table 3, wherein an asterisk indicates a logical AND ope ration and a plus sign indicates a logical OR operation.

Outputs clocked by ALPHAP2MOS:

ARGRNT ~ READY * ABLOCK * BREQ * ARGRNT
~BREQ * ABGRNT
AT6GRNT = READY * ABLOCK * DRQ * AT6HLDA * AT6GRNT
+REP~DY * ABLOCX * EBREQ * AT6~LDA * AT6GRNT
+DRQ * AT6GR~T
+EBREQ * AT6GRNT
EGRNT - READY * ABLOCK * DMAHRQ * AT6HLDA * EGRNT
+DMAHRQ * EGRNT
DNA~LDP. = READY * ABL~CK ~ D~IAHRQ * EBREQ *
AT6HLDA * DMAHLDA * DRQ
+DRQ * DMAHLDA
~T6REQ = ATPDOC * AT6REQ
~AT~HLDA * AT6REQ
+AT6HLDA * AT6REQ * AREQ
FDCBSY = READY * ABLOCK * DMAXRQ * EBREQ *
AT6HLDA * DMAHLDA * DRQ
+DMAHRQ * DMAHLDA
Combinatorial Outputs:
BREQ - AT6REQ ~ EBREQ * DMAHRQ
EBLOCK = ABLOCK * AT6HLDA * FDCBSY

~L2~ 5 Fig. llH shows the logic for generating SYSMEMCY
(memory cycle indicator), SYSWH (write high byte), SYSWL
(write low byte) and SYSADREN (address enable) when AP
106 has bus control, indicated by 8086 being low. When 5 buf~er line driver 1192 is enabled by ~086 low, SYSMEMCY
has the same state as M/I0 from AP 106~ LBHE low, from latch 2093, indicates that a byte is to be transfe~red onto the most significant byte (86AD8-g6AD15) of the data bus. L86~D0 is analogous to LB~E for the lower 10 byte ~data on 86AD0-86AD7). Therefore, if M/IO is high~
indicatin~ a memory operation, and D~/R is high, indicating a data transmission, L86AD0 low will resul~
in SYSWH low and LBHE low will ~esult in SYSWL low. The meanings of SYSWH and SYSWL are reversed when AP 106 is 15 active because the 8086 processor used in this embodiment uses a different byte organization scheme I~ 8~RDY is low, indicating the AP 106 data transaction is not completed, SYSADREN will be held high by the output o~ flip flop 1191. As discussed above, PALE is 20 held low by 86RDY low. When 86RDY returns high, PALE
will go high at the next ALE (from AP 106) rising edge.

, ~5-At the next CLK8 rising edge after the ALE pulse, S~SADREN will be driven low.
Fig~ llI show three-state buffer 1195 which operates as a status register. Status of 86VP and 860~T
is read from this register by HP 101.
The invention may be embodied in yet other specific forms without departing from the spirit or essential char,acteristics thereo~ For example, the techniques and apparatus described herein can be adapted to handle 10 a host processor and a pluxali~y Oe attached processors.
The present embodiments are therefore to be considered in all respects as illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than by the foregoing 1~ description, and all changes which come within the meaning can range of equivalency are therefore intended to be embraced therein.

.

Claims (9)

We claim:

1. In a data processing system having a first processor, a second processor, a memory, and bus means interconnecting the first processor, the second processor and the memory, a method for controlling which of said processors is active on said bus means, said method comprising the steps of:
a) if said first processor is currently active, monitoring for a start command from said first processor to said second processor;
b) if said start command to said second processor is detected, holding said first processor and starting said second processor;
c) if said second processor is currently active, monitoring for an interrupt condition and monitoring for an attempt by said second processor to perform an input/output operation;
d) if an interrupt condition is detected while said second processor is active, holding said second processor, starting said first processor and handling said interrupt condition;

e) if an attempt by said second processor to perform an input or output operation is detected, holding said second processor, starting said first processor and performing the input or output operation;
f) repeating steps a)-e)

2. The method of claim 1 further comprising the steps of a) said first processor identifying certain locations in said memory which are protected from access by said second processor;
b) if said second processor is active, monitoring for an attempt by said second processor to access a portion of said protected memory locations; and c) if an attempt by said second processor to access a portion of said protected memory locations is detected, holding said second processor and starting said first processor.

3. A data processing system comprising:
memory means;

first processor means, said first processor means having means for executing computer programs under a first operating system and means for controlling all input and output operations of said data processing system;
second processor means, said second processor means having means for executing computer programs under a second operating system;
input/output device interface means;
bus means, connected to said memory means, said input/output device interface means, said first processor and said second processor; for transferring at least data and addresses and control means, connected to said first processor and said second processor, and said bus means for controlling which of said processors is allowed access to said bus means, said control means including means for detecting an input and output request by said second processor, means for holding said second processor when said second processor requests an input or output operation, and means for starting said first processor when said second processor requests an input or output operation.

4. The apparatus of claim 3 wherein said bus control means further comprises:
means responsive to a command from said first processor for resetting said second processor;
means responsive to a command from said first processor for starting said second processor;

means responsive to a command from said first processor for holding said second processor;
means for allowing access to said bus means by said first processor when said first processor is active;
means for precluding access to said bus means by said second processor when said first processor is running;
means for allowing access to said bus means by said second processor when said second processor is active and;
means for precluding access to said bus means and said memory means by said first processor when said second processor is running.

5. The data processing system of claim 3 wherein said control means further comprises means for monitoring processor interrupt conditions when said second processor is active, means, responsive to said interrupt condition monitoring means, for holding said second processor when an interrupt condition is detected and means for starting said first processor when a processor interrupt condition is detected by said interrupt condition monitoring means.

6. The data processing system of claim 3, further comprising:
means controlled by said first processor for mapping the logical addresses of said first processor and said second processor into the physical address space of said memory means; and means controlled by said first processor for identifying portions of said memory means as being protected from access by said second processor.

7. The data processing system of claim 6, wherein said control means further comprises means for detecting an attempt by said second processor to access a protected area of memory;
means, responsive to said memory access attempt detecting means, for holding said second processor and means, responsive to said memory access attempt detecting means, for starting said first processor.

8. A data processing system comprising;
memory means;
first and second processors, said first processor including means for running a first operating system, means for processing all system input and output operations, means for handling all system interrupts, means for generating hold commands to said second processor and means for generating start commands to said second processor, and said second processor means including means for running a second operating system;
bus means, connected to said memory means, said first processor and said second processor, for transferring at least data and addresses between said first processor and said memory and between said second processor and said memory;
control means, connected to said first processor, said second processor and said bus means, said control means including means for detecting an attempt by said second processor to perform an input or output operation, means, responsive to said detecting means, for holding said second processor, means, responsive to said detecting means, for starting said first processor, means, responsive to a hold command from said first processor, for holding said second processor, and means, responsive to a start command from said first processor, for starting said second processor.

9. The data processing system of claim 8, wherein said first processor also includes means for identifying certain portions of said memory as being protected from access by said second processor and wherein said control means also includes:
means for detecting an attempt by said second processor to access said protected portions of said memory, means, responsive to said access detecting means, for holding said second processor and means, responsive to said access detecting means, for starting said first processor.