CA1208796A - Loosely coupled multiprocessor system capable of transferring a control signal set by the use of a common memory - Google Patents
Loosely coupled multiprocessor system capable of transferring a control signal set by the use of a common memoryInfo
- Publication number
- CA1208796A CA1208796A CA000462209A CA462209A CA1208796A CA 1208796 A CA1208796 A CA 1208796A CA 000462209 A CA000462209 A CA 000462209A CA 462209 A CA462209 A CA 462209A CA 1208796 A CA1208796 A CA 1208796A
- Authority
- CA
- Canada
- Prior art keywords
- control signal
- processor
- processor unit
- memory
- processor units
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2043—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share a common memory address space
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2023—Failover techniques
- G06F11/203—Failover techniques using migration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2035—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant without idle spare hardware
Abstract
ABSTRACT OF THE DISCLOSURE
In a multiprocessor system comprising a plurality of processor units which are loosely coupled to one another and which individually carry out processing operations in accordance with control signal sets, respectively, a common memory comprises sub-areas assigned to the processor units and loaded with the control signal sets. Each control signal set is written into each sub-area from each main memory included in each processor unit whenever each control signal set is renewed. When a particular one of the processor units falls into disorder and interrupts the processing operation, another of the processor units accesses the sub-area assigned to the particular processor unit and loads its main memory with the control signal set of the particular processor unit.
Another processor unit thus takes over the processing operation interrupted by the particular processor unit.
In a multiprocessor system comprising a plurality of processor units which are loosely coupled to one another and which individually carry out processing operations in accordance with control signal sets, respectively, a common memory comprises sub-areas assigned to the processor units and loaded with the control signal sets. Each control signal set is written into each sub-area from each main memory included in each processor unit whenever each control signal set is renewed. When a particular one of the processor units falls into disorder and interrupts the processing operation, another of the processor units accesses the sub-area assigned to the particular processor unit and loads its main memory with the control signal set of the particular processor unit.
Another processor unit thus takes over the processing operation interrupted by the particular processor unit.
Description
3'7gt~
LOOSELY COUPLED MULTIPROCESSOR SYSTEM
CAPABLE OF TRANSFERRING A CONTROL SIGNAL
SET BY THE USE OF A COMMON MEMORY
Background of the Invention:
This invention relates to a multiprocessor system comprising a plurality of processor units which are loosely coupled to one another.
A conventional loosely coupled multiprocessor system of the type described is disclosed by James A.
Katzman in "A Fault-Tolerant Computing System" published on January, 1979 (first revision), by Tandem Computers Inc., California. The conventional loosely coupled multiprocessor system comprises a plurality of processor units having independent operating systems and a plurality of peripheral devices used by the processor units in common. At any rate, each of the processor units can individually carry out a processiny operation in accordance with a set of control signals.
When one of the processor unitsfalls into disorder as a result of occurrence of a fault, that processor unit .12~D~3796 interrupts the processing operation thereof. The processor unit may be called a faulty processor unit. Under the circumstances, another of the processor units, namely, a normal processor unit can take over the processing operation interrupted by the aulty processor unit.
Thus, the normal processor unit gives relief to the fault of the faulty processor unit.
In order to make another processor unit take over the processing operation of the faulty processor unit, the control signal set should be transferred from the faulty processor unit to the normal processor unit.
A transfer circuit may be placed between the processor units for use in transferring the control signal sets therebetween. Inasmuch as a great number of control signals should be transferred through the transfer circuit, it takes a long time to transfer all of the control signal set from the faulty processor unit to the normal processor unit. As a result, each processor unit is subjected to a heavy overload. Use of the transfer circuit is therefore not practicable.
A method has practically been adopted whereby transfer of the control signal set is carried out during a predetermined intermission in each processing operatlon.
With this method, the processing operation of the normal processor unit should be returned back to the predetermined intermission and reexecuted when one of the processor units falls into disorder. Therefore, the normal processor unit can not momentarily take over the processing operation 12C)t3796 of the faulty processor unit.
Summary of the Invention:
It is an object of this invention to provide a loosely coupled multiprocessor system wherein a normal processor unit is capable of rapidly taking over a process-ing operation interrupted in a faulty processor unit.
A multiprocessor system to which this invention is applicable includes first and second processor units coupled to each other loosely by a plurality of control signal sets which are renewed with time. Each processor unit is for carrying out a processing operation and for producing a fault signal when the processing operation falls into disorder. The fault signal is for making that one of the processor units take over the processing operation falling into disorder which does not produce the fault signal. According to this invention, the system comprises a common memory having a first and a second memory area assigned to the first and the second processor units, respectively. The first and the second processor units comprise write-in means for writing the control signal sets of the first and the second processor units in the first and the second memory areas, respectively, whenever each of the control signal sets is renewed. Each of the first and the second processor units comprises access means responsive to the fault signal for accessing a particular one of the first and the second memory areas to read the control signal set written therein. The particular one of the first and ~2~379G
the second memory areas is assigned to the processor unit producing the faul-t signal. Each of the first and the second processor units comprises operation means for carrying out the processing operation in accordance with the control signal set read out of the particular one of the first and the second memory areas.
Brief Description of the Drawing:
Fig. l is a block diagram of a multiprocessor system according to a first embodiment of this invention;
Fig. 2 is a block diagram for use in describing an area allocation of memories used in the multiprocessor system illustrated in Fig. li Fig. 3 is a flow chart for use in describing a part of an operation of the multiprocessor system illustrated in Fig. l;
Fig. 4 is a flow chart for use in describing another part of the operation of the multiprocessor system illustrated in Fig. l;
Fig. 5 is a flow chart for use in describing an additional part of the operation of the multiprocessor system; and Fig. 6 is a block diagram for use in describing a part of the multiprocessor system.
Description of the Preferred Embodiments:
Referring to Fig. l, a loosely coupled multi-processor system according to a first embodiment of this invention comprises first and second processor units ll and 12 ~hich individually have independent ~2~8796 operating systems in the manner known in the art. Each of the first and the second processor units 11 and 12 is operable in accordance with a predetermined program which is similar for the processor units 11 and 12.
The program of each processor unit 11 and 12 is executed by a set of control signals variable with time to process a job imposed on each processor unit 11 or 12. Therefore, the control signal sets of the first and the second processor units 11 and 12 are different from each other and will be referred to as first and second control signal sets, respectively. The first and the second processor units 11 and 12 are coupled to each other through a processor interface line 14.
A memory unit 15 is shared by the first and the second processor units 11 and 12 in common and is operable in a manner to be described later. The memory unit 15 may be called a common memory unit having a common memory area.
In Fig. 1, attention will mainly be directed to the first processor unit 11 because each of the first and the second processor units 11 and 12 is similar in structure and operation. Subscripts 1 and the word "first" will be attached to elements and parts of the first processor unit 11 in order to distinguish them from the elements and parts of the second processor unit 12 which will be specified by subscripts 2 and the word "second."
~L2~ 6 The first processor unit 11 comprises a first control processor 211 for controlling a whole operation of the first processor unit 11 as will become clear as the description proceeds and a first main memory 221 coupled to the first control processor 211 through a bus line (unnumbered).
A first processor connection circuit 231 is interposed between the processor interface line 14 and the first processor unit 211. A first memory connection circuit 241 is connected between the first processor unit 211 and the common memory 15.
Like the first processor unit 11, the second processor unit 12 comprises a second control processor 212, a second main memory 222, a second processor connec-tion circuit 232, and a second memory connection circuit 242 which correspond to the first control processor 211, the first main memory 221, the first processor connection circuit 231, and the first memory connection circuit 241, respectively.
In Fig. 1, each of the first and the second processor units 11 and 12 individually carries out a processing operation during a normal mode of operation and produces a fault signal in a usual manner when the processing operation falls into disorder as a result of occurrence of a fault. The fault signal is produced in each control processor 211 and 212 and transferred through the processor interface line 14 between the first and the second processor units 11 and 12. It -`` i2q)8~796 is possible for the first and the second processor units 11 and 12 to monitor the processing operations of the second and the first processor units 12 and 11, respec-tively, by detecting the fault signal. A message may be produced during the normal mode from each processor unit so as to indicate the normal mode and may be inter-rupted on occurrence of the fault. In this event, the interruption of the message serves to indicate occurrence of the fault and may therefore be used as the fault signal.
In the illustrated system, let one of the first and the second processor units 11 and 12 fall into disorder and produce the fault signal. In this case, the processing operation of that processor unit is interrupted in the processor unit and is taken over by the other processor unit.
Referring to Fig. 2 together with Fig. 1, the first main memory 221 has a first memory area divided into first, second, and third partial areas 261, 262, and 263 for storing the program of the first processor unit 11, the first control signal set of the first processor unit 11, and the second control signal set of the second processor unit 12, respectively. The program of the first processor unit 11 which may be called a first program is executed by the first control signal set in the normal mode. In other words, the processing operation proceeds in accordance with the first control signal set in the first processor unit 11.
12~8796 Likewise, the second main memory 222 has a second memory area divided into first, second, and third divi-sional areas 271, 272, and 273 for storing the program of the second processor unit 12, the ~irst control signal set of the first processor unit 11, and the second control signal set of the second processor unit 12, respectively.
The program of the second processor unit 12 may be referred -to as a second program and is executed by the second control signal set in the normal mode of the second processor unit 12.
In Fig. 1, the common memory unit 15 comprises a processor interface section 31 (will be described in detail) and a common memory 32 coupled to the first and the second processor units 11 and 12 through the processor interface section 31. As shown in Fig. 2, the common memory 32 has a common memory area divided into first and second sub-areas 331 and 332 which are loaded with the first and the second control signal sets, respectively, as suggested by solid lines. This implies that the first control signal set is stored in both the second partial area 262 and the first sub-area 331 and that the second control signal set is stored in both the third divisional area 273 and the second sub-area 332 Under the circumstances, the first control signal set is transferred from the first sub-area 331 to the second divisional area 272 when the fi:st processor unit 11 falls into disorder. Similarly, the second control signal set is transferred ~rom the :............................................ ,.. .. ~ ., O, ~
- 12~11875~6 second sub`~area 332 to the third partial area 263 when the second processor unit 12 falls into disorder.
Each of the first and the second control processors 211 and 212 cooperates with each of the first and the second main memories 221 and 222 so as to carry out the above-mentioned operations. More specifically, the first control processor 211 illustrated in Fig.
l comprises a first memory allocation controller 361 for allocating the second and the third partial areas 262 and 263 of the first main memory 221 to the first and the second processor units 11 and 12, respectively.
The first memory allocation controller 361 monitors an amount of the first program and the first control signal set to effectively carry out the allocation of the first main memory 221. A first common memory alloca-tion controller 371 allocates the first sub-area 331 of the common memory 32 to the first processor unit 11. The first ~ub-area 331 of the common area 32 is equal in size to the second partial area 262 of the first main memory 221. A first memory controller 381 is coupled to the first main memory 221 so as to carry out an access control operation of the first main memory 221. The first memory allocation circuit 361, the first common memory allocation controller 371' and the first memory controller 381 are coupled to a first main controller 411 to be put into operation under control - of the first main controller 411.
.
The first main controller 411 detects occurrence of a fault in the first processor unit 11 so as to transmit the fault signal through the first processor connection circuit 231 in the conventional manner and to interrupt the processing operation of the first processor unit 11. The first main controller 411 is coupled to a first fault detector 431 for detecting arrival of a fault signal produced by the second processor unit 12.
A first write-in control circuit 451 is coupled to the first main controller 411 to write the first control signal set in the first sub-area 331 of the common memory 32 through a first common memory controller 471 whenever the first control signal set is rene~ed. The first common memory controller 471 is coupled to the first fault detector 431 to access the common memory unit I5 through the first memory connection circuit 241 in a manner to be described.
The second control processor 212 is similar in structure and operation to the first control processor 211 and therefore comprises a second memory allocation controller 362, a second common memory allocation controllex 372' a second memory controller 382, a second main controller 412, a second fault detector 432' a second write-in control circuit 452' and a second common memory controller 472' Referring to Fig. 3 together with Figs. 1 and
LOOSELY COUPLED MULTIPROCESSOR SYSTEM
CAPABLE OF TRANSFERRING A CONTROL SIGNAL
SET BY THE USE OF A COMMON MEMORY
Background of the Invention:
This invention relates to a multiprocessor system comprising a plurality of processor units which are loosely coupled to one another.
A conventional loosely coupled multiprocessor system of the type described is disclosed by James A.
Katzman in "A Fault-Tolerant Computing System" published on January, 1979 (first revision), by Tandem Computers Inc., California. The conventional loosely coupled multiprocessor system comprises a plurality of processor units having independent operating systems and a plurality of peripheral devices used by the processor units in common. At any rate, each of the processor units can individually carry out a processiny operation in accordance with a set of control signals.
When one of the processor unitsfalls into disorder as a result of occurrence of a fault, that processor unit .12~D~3796 interrupts the processing operation thereof. The processor unit may be called a faulty processor unit. Under the circumstances, another of the processor units, namely, a normal processor unit can take over the processing operation interrupted by the aulty processor unit.
Thus, the normal processor unit gives relief to the fault of the faulty processor unit.
In order to make another processor unit take over the processing operation of the faulty processor unit, the control signal set should be transferred from the faulty processor unit to the normal processor unit.
A transfer circuit may be placed between the processor units for use in transferring the control signal sets therebetween. Inasmuch as a great number of control signals should be transferred through the transfer circuit, it takes a long time to transfer all of the control signal set from the faulty processor unit to the normal processor unit. As a result, each processor unit is subjected to a heavy overload. Use of the transfer circuit is therefore not practicable.
A method has practically been adopted whereby transfer of the control signal set is carried out during a predetermined intermission in each processing operatlon.
With this method, the processing operation of the normal processor unit should be returned back to the predetermined intermission and reexecuted when one of the processor units falls into disorder. Therefore, the normal processor unit can not momentarily take over the processing operation 12C)t3796 of the faulty processor unit.
Summary of the Invention:
It is an object of this invention to provide a loosely coupled multiprocessor system wherein a normal processor unit is capable of rapidly taking over a process-ing operation interrupted in a faulty processor unit.
A multiprocessor system to which this invention is applicable includes first and second processor units coupled to each other loosely by a plurality of control signal sets which are renewed with time. Each processor unit is for carrying out a processing operation and for producing a fault signal when the processing operation falls into disorder. The fault signal is for making that one of the processor units take over the processing operation falling into disorder which does not produce the fault signal. According to this invention, the system comprises a common memory having a first and a second memory area assigned to the first and the second processor units, respectively. The first and the second processor units comprise write-in means for writing the control signal sets of the first and the second processor units in the first and the second memory areas, respectively, whenever each of the control signal sets is renewed. Each of the first and the second processor units comprises access means responsive to the fault signal for accessing a particular one of the first and the second memory areas to read the control signal set written therein. The particular one of the first and ~2~379G
the second memory areas is assigned to the processor unit producing the faul-t signal. Each of the first and the second processor units comprises operation means for carrying out the processing operation in accordance with the control signal set read out of the particular one of the first and the second memory areas.
Brief Description of the Drawing:
Fig. l is a block diagram of a multiprocessor system according to a first embodiment of this invention;
Fig. 2 is a block diagram for use in describing an area allocation of memories used in the multiprocessor system illustrated in Fig. li Fig. 3 is a flow chart for use in describing a part of an operation of the multiprocessor system illustrated in Fig. l;
Fig. 4 is a flow chart for use in describing another part of the operation of the multiprocessor system illustrated in Fig. l;
Fig. 5 is a flow chart for use in describing an additional part of the operation of the multiprocessor system; and Fig. 6 is a block diagram for use in describing a part of the multiprocessor system.
Description of the Preferred Embodiments:
Referring to Fig. l, a loosely coupled multi-processor system according to a first embodiment of this invention comprises first and second processor units ll and 12 ~hich individually have independent ~2~8796 operating systems in the manner known in the art. Each of the first and the second processor units 11 and 12 is operable in accordance with a predetermined program which is similar for the processor units 11 and 12.
The program of each processor unit 11 and 12 is executed by a set of control signals variable with time to process a job imposed on each processor unit 11 or 12. Therefore, the control signal sets of the first and the second processor units 11 and 12 are different from each other and will be referred to as first and second control signal sets, respectively. The first and the second processor units 11 and 12 are coupled to each other through a processor interface line 14.
A memory unit 15 is shared by the first and the second processor units 11 and 12 in common and is operable in a manner to be described later. The memory unit 15 may be called a common memory unit having a common memory area.
In Fig. 1, attention will mainly be directed to the first processor unit 11 because each of the first and the second processor units 11 and 12 is similar in structure and operation. Subscripts 1 and the word "first" will be attached to elements and parts of the first processor unit 11 in order to distinguish them from the elements and parts of the second processor unit 12 which will be specified by subscripts 2 and the word "second."
~L2~ 6 The first processor unit 11 comprises a first control processor 211 for controlling a whole operation of the first processor unit 11 as will become clear as the description proceeds and a first main memory 221 coupled to the first control processor 211 through a bus line (unnumbered).
A first processor connection circuit 231 is interposed between the processor interface line 14 and the first processor unit 211. A first memory connection circuit 241 is connected between the first processor unit 211 and the common memory 15.
Like the first processor unit 11, the second processor unit 12 comprises a second control processor 212, a second main memory 222, a second processor connec-tion circuit 232, and a second memory connection circuit 242 which correspond to the first control processor 211, the first main memory 221, the first processor connection circuit 231, and the first memory connection circuit 241, respectively.
In Fig. 1, each of the first and the second processor units 11 and 12 individually carries out a processing operation during a normal mode of operation and produces a fault signal in a usual manner when the processing operation falls into disorder as a result of occurrence of a fault. The fault signal is produced in each control processor 211 and 212 and transferred through the processor interface line 14 between the first and the second processor units 11 and 12. It -`` i2q)8~796 is possible for the first and the second processor units 11 and 12 to monitor the processing operations of the second and the first processor units 12 and 11, respec-tively, by detecting the fault signal. A message may be produced during the normal mode from each processor unit so as to indicate the normal mode and may be inter-rupted on occurrence of the fault. In this event, the interruption of the message serves to indicate occurrence of the fault and may therefore be used as the fault signal.
In the illustrated system, let one of the first and the second processor units 11 and 12 fall into disorder and produce the fault signal. In this case, the processing operation of that processor unit is interrupted in the processor unit and is taken over by the other processor unit.
Referring to Fig. 2 together with Fig. 1, the first main memory 221 has a first memory area divided into first, second, and third partial areas 261, 262, and 263 for storing the program of the first processor unit 11, the first control signal set of the first processor unit 11, and the second control signal set of the second processor unit 12, respectively. The program of the first processor unit 11 which may be called a first program is executed by the first control signal set in the normal mode. In other words, the processing operation proceeds in accordance with the first control signal set in the first processor unit 11.
12~8796 Likewise, the second main memory 222 has a second memory area divided into first, second, and third divi-sional areas 271, 272, and 273 for storing the program of the second processor unit 12, the ~irst control signal set of the first processor unit 11, and the second control signal set of the second processor unit 12, respectively.
The program of the second processor unit 12 may be referred -to as a second program and is executed by the second control signal set in the normal mode of the second processor unit 12.
In Fig. 1, the common memory unit 15 comprises a processor interface section 31 (will be described in detail) and a common memory 32 coupled to the first and the second processor units 11 and 12 through the processor interface section 31. As shown in Fig. 2, the common memory 32 has a common memory area divided into first and second sub-areas 331 and 332 which are loaded with the first and the second control signal sets, respectively, as suggested by solid lines. This implies that the first control signal set is stored in both the second partial area 262 and the first sub-area 331 and that the second control signal set is stored in both the third divisional area 273 and the second sub-area 332 Under the circumstances, the first control signal set is transferred from the first sub-area 331 to the second divisional area 272 when the fi:st processor unit 11 falls into disorder. Similarly, the second control signal set is transferred ~rom the :............................................ ,.. .. ~ ., O, ~
- 12~11875~6 second sub`~area 332 to the third partial area 263 when the second processor unit 12 falls into disorder.
Each of the first and the second control processors 211 and 212 cooperates with each of the first and the second main memories 221 and 222 so as to carry out the above-mentioned operations. More specifically, the first control processor 211 illustrated in Fig.
l comprises a first memory allocation controller 361 for allocating the second and the third partial areas 262 and 263 of the first main memory 221 to the first and the second processor units 11 and 12, respectively.
The first memory allocation controller 361 monitors an amount of the first program and the first control signal set to effectively carry out the allocation of the first main memory 221. A first common memory alloca-tion controller 371 allocates the first sub-area 331 of the common memory 32 to the first processor unit 11. The first ~ub-area 331 of the common area 32 is equal in size to the second partial area 262 of the first main memory 221. A first memory controller 381 is coupled to the first main memory 221 so as to carry out an access control operation of the first main memory 221. The first memory allocation circuit 361, the first common memory allocation controller 371' and the first memory controller 381 are coupled to a first main controller 411 to be put into operation under control - of the first main controller 411.
.
The first main controller 411 detects occurrence of a fault in the first processor unit 11 so as to transmit the fault signal through the first processor connection circuit 231 in the conventional manner and to interrupt the processing operation of the first processor unit 11. The first main controller 411 is coupled to a first fault detector 431 for detecting arrival of a fault signal produced by the second processor unit 12.
A first write-in control circuit 451 is coupled to the first main controller 411 to write the first control signal set in the first sub-area 331 of the common memory 32 through a first common memory controller 471 whenever the first control signal set is rene~ed. The first common memory controller 471 is coupled to the first fault detector 431 to access the common memory unit I5 through the first memory connection circuit 241 in a manner to be described.
The second control processor 212 is similar in structure and operation to the first control processor 211 and therefore comprises a second memory allocation controller 362, a second common memory allocation controllex 372' a second memory controller 382, a second main controller 412, a second fault detector 432' a second write-in control circuit 452' and a second common memory controller 472' Referring to Fig. 3 together with Figs. 1 and
2, each of the first and the second processor units 11 and 12 is energized by the first and the second main lZ~ 796 controllers 4ll and 412 to carry out an allocation opera-tion of the common memory 32 in accordance with procedures shown in Fig. 3. At first, each of the first and the second memory allocation controllers 36l and 362 is enabled to look up a memory capacity of each of the first and the second main memories 22l and 222, as shown at a first step Sl. The first partial area 26l and -the first divisional area 27l are subtracted from the memory capaclties of the first and the second main memories 22l and 222, respectively. As a result, the second and the third partial areas 262 and 263 and the second and the third divisional areas 272 and 273 are determined in the first and the second main memories 22l and 222 so as to store the first and the second control signal sets, respectively. Thus, each of the first and the second memory allocation controllers 36l and 362 defines a control signal area for each control signal set in each of the first and the second main memories 22l and 222, as shown at a second step S2.
The second step S2 is followed by a third step S3 at which each of the first and the second memory allocation controllers 36l and 362 equally divides each control signal area into two areas, such as the second and the third partial areas 262 and 263 and the second and the third divisional areas 272 and 273.
Upon completion of the third step S3 in each of the first and the second memory allocation controllers 36l and 362, the first and the second main controllers 12~3796 411 and 412 enable the first and the second common memory allocation controllers 371 and 372~ respectively. Each common memory allocation controller 37i and 372 assigns the common memory 32 to both of the first and the second S control signal sets. Thus, the common memory area is defined on the common memory 32 at a fourth step S4 for the first and the second control signal sets. The common memory area is equal in size to the control signal area on each of the first and the second main memories 221 and 222. At a fifth step S5, the common memory ar~a is equally divided into the first and the second sub-areas 331 and 332 assigned to the first and the second control signal sets, respectively.
After completion of the fifth step S5, each of the first and the second processor units 11 and 12 individually carries out the processing operation.
When each of the first and the second control signal sets is renewed during the processing operation, the first and the second write-in control circuits 451 and 452 carry out write-in operations of writing the first and the second control signal sets in the common memory unit lS, respectively.
Referring to Fig. 4 afresh and Fig. 2 again, the first and the second write-in control circuits 451 and 452 monitor, through the first and the second main controllers 411 and 412, whether or not the first and the second control signal sets arë renewed, respectively, as shown at a first step SPl. If each control signal ,~ . .
~2~8796 set is not renewed, the write-in operation comes to an end. Otherwise, the first step SPl is followed by a second step SP2. It may be mentioned here that renewal of a control signal should be inhibited while renewal operation of the control signal is carried out in each main memory. Under the circumstances, each of the first and the second write-in control circuits 451 and 452 detects whether or not renewal is inhibited about each control signal of the first and the second control signal sets, as shown at a second step SP2.
If the renewal is inhibited, a third step SP3 succeeds the second step SP2 to wait for release of the inhibition of renewal. If renewal of the control signal under consideration is not inhibited, each of the first and the second write-in control circuits 451 and 452 renews the control signal in question and protects the renewed control signal from being renewed in each of the main memories 221 and 222, as shown at a fourth step SP4-After the fourth step SP4, a fifth step SP5 is carried out by each of the common memory controllers 471 and 472 to notify each memory connection circuit 241 or 242 of an address and a size of the renewed control signal. Each of the memory connection sircuit 241 and 242 energizes each main memory 221 or 222 and the processor interface section 31 of the common memory unit 15 to write the renewed control signal in the common memory 32, as shown at a sixth step SP6. In this event, the 1~8'796 renewed control signal of the first processor unit 11 is sent from the first main memory 221 to the first sub-area 331 while the renewed control signal of the second processor unit 12 is sent from the second main memory 222 to the second sub-area 332 in the manner described above in conjunction with Fig. 2. When the renewed control signal is stored in the common memory 32, each of the write-in control circuits451 and 452 releases inhibition of renewal of the renewed control signal, as shown at a seventh step SP7. Thus, the lnhibi-tion of renewal is released after the contents of each main memory are coincident with those of the common memory 32.
Referring to Fig. 5 anew together with Fig.
2, the common memory unit 15 is accessed for readout of the contents from the common memory unit 15 when a fault occurs in either one of the first and the second processor units 11 and 12. For brevity of description, let the fault have occurred in the second processor unit 12. The first processor unit 11 takes over the processing operation of the second processor unit 12.
In this case, occurrence of the fault is detected in the second processor unit 12 in a usual manner and is transmitted as the fault signal from the second procesSOr connection circuit 232 to the first fault detector 431 through the processor interface line 14 and the first processor connection circuit 231.
12q;B~3~796 Responsive to the fault signal, the first fault detector 431 detects the occurrence of the fault in the second processor unit 12, as shown at a first stage SSl to inform the first common memory controller 471 of the occurrence of the fault in the second processor unit 12, as shown at a second stage SS2. The first common memory controller 471 accesses the second sub-area 332 of the common memory 32 through the first memory connection clrcuit 241, as shown at a third stage SS3, when the second processor unit 12 falls into disorder.
Thus, the second sub-area 332 assigned to the second processor unit 12 is accessed by the first processor unit 11 which does not produce any fault signal. As a result, the second control signal set is read out of the second sub-area 332 to be sent through the first memory connection circuit 241 to the third partial area 263 of the first main memory 221, as shown at a fourth stage SS4. From the above, it is readily understood that a combination of the first fault detector 431 and the first common memory controller 471 serves to access the second sub-area 332 in response to the fault signal sent from the second processor unit 12 and may be called an access circuit.
The second control signal set is rapidly trans-ferred from the second sub-area 332 to the third partial area 263.
The second control signal set stored in the third partial area 263 is accessed by the first memory 8~96 controller 381 under control of the first main controller 411 together with the first control signal set stored in the second partial area 262, as shown at a fifth stage SS5. Thus, the first processor unit 11 deals with the second control signal set as a part of its own control signal set. The first memory controller 381 and the first main controller 411 are operable to carry out the processing operation of the second processor unit 12 in accordance with the second control signal set read out of the second sub-area 332' Inasmuch as the second control signal set is accessed by the first memory controller 381, it is possible to carry out the processing operation interrupted in the second processing unit 12. Thus, the first processor unit 11 takes over the processing operation of the second processor unit 12.
Similar operation is possible when the fault occurs in the first processor unit 11 with the second processor unit 12 operated in the normal mode.
Referring to Fig. 6, a common memory connection circuit denoted by 24 is usable as each of the first ..
and the second common memory connection circuits 241 and 242 and is coupled to the main memory 22 (subscripts omitted) and to the control processor 21 of each processor unit through a bus indicated at 51. The illustrated common memory connection circuit 24 comprises a bus control section 53 for carrying out an interface control operation so as to couple the control processor 21 with ~2C~8796 the common memory connection circuit 24. A buffer section 55 is for keeping or storing each control signal or each control signal set to carry out transfer operation between the common memory unit 15 and each processor unit in the manner described before. The bus control section 53 monitors an address of each control signal and the number of bytes to be transferred onto the bus 51. Each control signal or each control signal set stored in the buffer section 55 is transferred to the common memory unit 15 under control of a transfer controller 56 coupled to a first signal interface which is denoted by 57 and is common to both of the first and the second processor units 11 and 12.
In addition, a first interface controller 58 is included in the illustrated common memory connection circuit 24 and is connected to a second signal interface 59 which is common to both of the first and the second processor units 11 and 12.
In Fig. 6, the common memory unit 15 comprises a second interface controller 62 connected through the second signal interface 59 to the first interface con-troller 58 of each processor unit. A common buffer section 63 is connected through the first signal interface 57 to the transfer controller 56 of each processor unit.
Both of the second interface controller 62 and the common buffer section 63 are operable as the processor interface section 31. The second signal interface 59 is controlled by the second interface controller 58 and each first lZ~ 796 interface controller 58 to determine a specific one of the processor units that can be coupled to the common memory 32~ Each control signal or signal set is sent from the specific processor unit through the ~irst signal interface 57 to the common buffer section 63 and is thereafter stored in a specific one of the first and the second sub-areas331 and 332 that is assigned to the specific processor unit. To the contrary, each control signal or signal set is read out of the specific sub-area and is delivered through the common buffer section 63 and the first signal interface 57 to the buffer section 55 of another one of the first and the second processor units 11 and 12.
While this invention has thus far been described in conjunction with a preferred embodiment thereof, it will readily be possible for those skilled in the art to change the preferred embodiment to various other embodiments of the invention. For example, the processor units may be greater in number than two. In this event, the processor units are consecutively numbered to be divided into an odd number group and an even number one. The first and the second sub-areas 331 and 332 of the common memory 32 are assigned to the odd and the even number groups. In addition, the control signal area of each main memory is divided into two areas assigned to the odd and the even number groups. Thus, the second and the third partial areas 262 and 263 (Fig. 2) or the second and the third divisional areas 271 and 272 : . ~.
'796 may be assigned to the odd and the even number groups.
The control set includes operation codes, such as commands, instructions, and the like.
The second step S2 is followed by a third step S3 at which each of the first and the second memory allocation controllers 36l and 362 equally divides each control signal area into two areas, such as the second and the third partial areas 262 and 263 and the second and the third divisional areas 272 and 273.
Upon completion of the third step S3 in each of the first and the second memory allocation controllers 36l and 362, the first and the second main controllers 12~3796 411 and 412 enable the first and the second common memory allocation controllers 371 and 372~ respectively. Each common memory allocation controller 37i and 372 assigns the common memory 32 to both of the first and the second S control signal sets. Thus, the common memory area is defined on the common memory 32 at a fourth step S4 for the first and the second control signal sets. The common memory area is equal in size to the control signal area on each of the first and the second main memories 221 and 222. At a fifth step S5, the common memory ar~a is equally divided into the first and the second sub-areas 331 and 332 assigned to the first and the second control signal sets, respectively.
After completion of the fifth step S5, each of the first and the second processor units 11 and 12 individually carries out the processing operation.
When each of the first and the second control signal sets is renewed during the processing operation, the first and the second write-in control circuits 451 and 452 carry out write-in operations of writing the first and the second control signal sets in the common memory unit lS, respectively.
Referring to Fig. 4 afresh and Fig. 2 again, the first and the second write-in control circuits 451 and 452 monitor, through the first and the second main controllers 411 and 412, whether or not the first and the second control signal sets arë renewed, respectively, as shown at a first step SPl. If each control signal ,~ . .
~2~8796 set is not renewed, the write-in operation comes to an end. Otherwise, the first step SPl is followed by a second step SP2. It may be mentioned here that renewal of a control signal should be inhibited while renewal operation of the control signal is carried out in each main memory. Under the circumstances, each of the first and the second write-in control circuits 451 and 452 detects whether or not renewal is inhibited about each control signal of the first and the second control signal sets, as shown at a second step SP2.
If the renewal is inhibited, a third step SP3 succeeds the second step SP2 to wait for release of the inhibition of renewal. If renewal of the control signal under consideration is not inhibited, each of the first and the second write-in control circuits 451 and 452 renews the control signal in question and protects the renewed control signal from being renewed in each of the main memories 221 and 222, as shown at a fourth step SP4-After the fourth step SP4, a fifth step SP5 is carried out by each of the common memory controllers 471 and 472 to notify each memory connection circuit 241 or 242 of an address and a size of the renewed control signal. Each of the memory connection sircuit 241 and 242 energizes each main memory 221 or 222 and the processor interface section 31 of the common memory unit 15 to write the renewed control signal in the common memory 32, as shown at a sixth step SP6. In this event, the 1~8'796 renewed control signal of the first processor unit 11 is sent from the first main memory 221 to the first sub-area 331 while the renewed control signal of the second processor unit 12 is sent from the second main memory 222 to the second sub-area 332 in the manner described above in conjunction with Fig. 2. When the renewed control signal is stored in the common memory 32, each of the write-in control circuits451 and 452 releases inhibition of renewal of the renewed control signal, as shown at a seventh step SP7. Thus, the lnhibi-tion of renewal is released after the contents of each main memory are coincident with those of the common memory 32.
Referring to Fig. 5 anew together with Fig.
2, the common memory unit 15 is accessed for readout of the contents from the common memory unit 15 when a fault occurs in either one of the first and the second processor units 11 and 12. For brevity of description, let the fault have occurred in the second processor unit 12. The first processor unit 11 takes over the processing operation of the second processor unit 12.
In this case, occurrence of the fault is detected in the second processor unit 12 in a usual manner and is transmitted as the fault signal from the second procesSOr connection circuit 232 to the first fault detector 431 through the processor interface line 14 and the first processor connection circuit 231.
12q;B~3~796 Responsive to the fault signal, the first fault detector 431 detects the occurrence of the fault in the second processor unit 12, as shown at a first stage SSl to inform the first common memory controller 471 of the occurrence of the fault in the second processor unit 12, as shown at a second stage SS2. The first common memory controller 471 accesses the second sub-area 332 of the common memory 32 through the first memory connection clrcuit 241, as shown at a third stage SS3, when the second processor unit 12 falls into disorder.
Thus, the second sub-area 332 assigned to the second processor unit 12 is accessed by the first processor unit 11 which does not produce any fault signal. As a result, the second control signal set is read out of the second sub-area 332 to be sent through the first memory connection circuit 241 to the third partial area 263 of the first main memory 221, as shown at a fourth stage SS4. From the above, it is readily understood that a combination of the first fault detector 431 and the first common memory controller 471 serves to access the second sub-area 332 in response to the fault signal sent from the second processor unit 12 and may be called an access circuit.
The second control signal set is rapidly trans-ferred from the second sub-area 332 to the third partial area 263.
The second control signal set stored in the third partial area 263 is accessed by the first memory 8~96 controller 381 under control of the first main controller 411 together with the first control signal set stored in the second partial area 262, as shown at a fifth stage SS5. Thus, the first processor unit 11 deals with the second control signal set as a part of its own control signal set. The first memory controller 381 and the first main controller 411 are operable to carry out the processing operation of the second processor unit 12 in accordance with the second control signal set read out of the second sub-area 332' Inasmuch as the second control signal set is accessed by the first memory controller 381, it is possible to carry out the processing operation interrupted in the second processing unit 12. Thus, the first processor unit 11 takes over the processing operation of the second processor unit 12.
Similar operation is possible when the fault occurs in the first processor unit 11 with the second processor unit 12 operated in the normal mode.
Referring to Fig. 6, a common memory connection circuit denoted by 24 is usable as each of the first ..
and the second common memory connection circuits 241 and 242 and is coupled to the main memory 22 (subscripts omitted) and to the control processor 21 of each processor unit through a bus indicated at 51. The illustrated common memory connection circuit 24 comprises a bus control section 53 for carrying out an interface control operation so as to couple the control processor 21 with ~2C~8796 the common memory connection circuit 24. A buffer section 55 is for keeping or storing each control signal or each control signal set to carry out transfer operation between the common memory unit 15 and each processor unit in the manner described before. The bus control section 53 monitors an address of each control signal and the number of bytes to be transferred onto the bus 51. Each control signal or each control signal set stored in the buffer section 55 is transferred to the common memory unit 15 under control of a transfer controller 56 coupled to a first signal interface which is denoted by 57 and is common to both of the first and the second processor units 11 and 12.
In addition, a first interface controller 58 is included in the illustrated common memory connection circuit 24 and is connected to a second signal interface 59 which is common to both of the first and the second processor units 11 and 12.
In Fig. 6, the common memory unit 15 comprises a second interface controller 62 connected through the second signal interface 59 to the first interface con-troller 58 of each processor unit. A common buffer section 63 is connected through the first signal interface 57 to the transfer controller 56 of each processor unit.
Both of the second interface controller 62 and the common buffer section 63 are operable as the processor interface section 31. The second signal interface 59 is controlled by the second interface controller 58 and each first lZ~ 796 interface controller 58 to determine a specific one of the processor units that can be coupled to the common memory 32~ Each control signal or signal set is sent from the specific processor unit through the ~irst signal interface 57 to the common buffer section 63 and is thereafter stored in a specific one of the first and the second sub-areas331 and 332 that is assigned to the specific processor unit. To the contrary, each control signal or signal set is read out of the specific sub-area and is delivered through the common buffer section 63 and the first signal interface 57 to the buffer section 55 of another one of the first and the second processor units 11 and 12.
While this invention has thus far been described in conjunction with a preferred embodiment thereof, it will readily be possible for those skilled in the art to change the preferred embodiment to various other embodiments of the invention. For example, the processor units may be greater in number than two. In this event, the processor units are consecutively numbered to be divided into an odd number group and an even number one. The first and the second sub-areas 331 and 332 of the common memory 32 are assigned to the odd and the even number groups. In addition, the control signal area of each main memory is divided into two areas assigned to the odd and the even number groups. Thus, the second and the third partial areas 262 and 263 (Fig. 2) or the second and the third divisional areas 271 and 272 : . ~.
'796 may be assigned to the odd and the even number groups.
The control set includes operation codes, such as commands, instructions, and the like.
Claims (4)
1. A multiprocessor system including first and second processor units coupled to each other loosely by a plurality of control signal sets which are renewed with time, each processor unit being for carrying out a processing operation and for producing a fault signal when said processing operation falls into disorder, said fault signal being for making that one of said processor units take over the processing operation falling into disorder which does not produce the fault signal, wherein the improvement comprises:
a common memory having a first and a second memory area assigned to said first and said second processor units, respectively;
said first and said second processor units compris-ing write-in means for writing the control signal sets of said first and said second processor units in said first and said second memory areas, respectively, whenever each of said control signal sets is renewed;
each of said first and said second processor units comprising:
access means responsive to said fault signal for accessing a particular one of said first and said second memory areas to read the control signal set written therein, said particular one of the first and the second memory areas being assigned to the processor unit producing said fault signal; and (Claim 1 continued) operation means for carrying out the processing operation in accordance with the control signal set read out of said particular one of said first and said second memory areas.
a common memory having a first and a second memory area assigned to said first and said second processor units, respectively;
said first and said second processor units compris-ing write-in means for writing the control signal sets of said first and said second processor units in said first and said second memory areas, respectively, whenever each of said control signal sets is renewed;
each of said first and said second processor units comprising:
access means responsive to said fault signal for accessing a particular one of said first and said second memory areas to read the control signal set written therein, said particular one of the first and the second memory areas being assigned to the processor unit producing said fault signal; and (Claim 1 continued) operation means for carrying out the processing operation in accordance with the control signal set read out of said particular one of said first and said second memory areas.
2. A multiprocessor system as claimed in Claim 1, wherein each of said first and said second processor units comprises:
a main memory having a control signal area corres-ponding to said first and said second memory areas for storing the control signal set assigned to said each processor unit and the control signal set read out of said particular one of the first and the second memory areas.
a main memory having a control signal area corres-ponding to said first and said second memory areas for storing the control signal set assigned to said each processor unit and the control signal set read out of said particular one of the first and the second memory areas.
3. A multiprocessor system as claimed in Claim 2, wherein said operation means comprises:
means for accessing both of the control signal sets assigned to said each processor unit and read out of said particular one of the first and the second memory areas so as to carry out the processing operation in accordance with said control signal sets.
means for accessing both of the control signal sets assigned to said each processor unit and read out of said particular one of the first and the second memory areas so as to carry out the processing operation in accordance with said control signal sets.
4. A multiprocessor system comprising a plurality of processor units which are loosely coupled to one another in accordance with a plurality of control signal sets renewed with time, a first one of said processor units being normal and taking over processing operation of a second one of said processor unit in response to a fault signal representative of a fault occurring in (Claim 4 continued) a second one of said processor units, said system comprising:
a common memory accessible by said processor units in common and having a first and a second memory area assigned to said first and said second processor units, respectively;
said first and said second processor units comprising:
write-in means for writing said control signal sets of said first and said second processor units into said first and said second memory areas, respectively, each time when said each control signal set is renewed;
said first processor unit comprising:
access means responsive to said fault signal for accessing said second memory area to read the control signal set of said second processor unit; and means for carrying out said processing operation of said second processor unit in accordance with the control signal set of said second processor unit read out of said second memory area.
a common memory accessible by said processor units in common and having a first and a second memory area assigned to said first and said second processor units, respectively;
said first and said second processor units comprising:
write-in means for writing said control signal sets of said first and said second processor units into said first and said second memory areas, respectively, each time when said each control signal set is renewed;
said first processor unit comprising:
access means responsive to said fault signal for accessing said second memory area to read the control signal set of said second processor unit; and means for carrying out said processing operation of said second processor unit in accordance with the control signal set of said second processor unit read out of said second memory area.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58160522A JPS6054052A (en) | 1983-09-02 | 1983-09-02 | Processing continuing system |
JP160522/1983 | 1983-09-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1208796A true CA1208796A (en) | 1986-07-29 |
Family
ID=15716773
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA000462209A Expired CA1208796A (en) | 1983-09-02 | 1984-08-31 | Loosely coupled multiprocessor system capable of transferring a control signal set by the use of a common memory |
Country Status (5)
Country | Link |
---|---|
US (1) | US4709325A (en) |
EP (1) | EP0136560B1 (en) |
JP (1) | JPS6054052A (en) |
CA (1) | CA1208796A (en) |
DE (1) | DE3483636D1 (en) |
Families Citing this family (61)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6243766A (en) * | 1985-08-21 | 1987-02-25 | Hitachi Ltd | Control system for state of shared resources |
US5155678A (en) * | 1985-10-29 | 1992-10-13 | International Business Machines Corporation | Data availability in restartable data base system |
US4851988A (en) * | 1986-03-31 | 1989-07-25 | Wang Laboratories, Inc. | Loosely-coupled computer system using global identifiers to identify mailboxes and volumes |
US4815076A (en) * | 1987-02-17 | 1989-03-21 | Schlumberger Technology Corporation | Reconfiguration advisor |
US4926320A (en) * | 1987-04-07 | 1990-05-15 | Nec Corporation | Information processing system having microprogram-controlled type arithmetic processing unit |
US5201040A (en) * | 1987-06-22 | 1993-04-06 | Hitachi, Ltd. | Multiprocessor system having subsystems which are loosely coupled through a random access storage and which each include a tightly coupled multiprocessor |
AU616213B2 (en) * | 1987-11-09 | 1991-10-24 | Tandem Computers Incorporated | Method and apparatus for synchronizing a plurality of processors |
CA2003338A1 (en) * | 1987-11-09 | 1990-06-09 | Richard W. Cutts, Jr. | Synchronization of fault-tolerant computer system having multiple processors |
AU620063B2 (en) * | 1987-12-02 | 1992-02-13 | Network Equipment Technologies, Inc. | Method and apparatus for automatic loading of a data set in a node of a communication network |
US4847830A (en) * | 1987-12-02 | 1989-07-11 | Network Equipment Technologies, Inc. | Method and apparatus for automatic loading of a data set in a node of a communication network |
WO1989008883A1 (en) * | 1988-03-14 | 1989-09-21 | Unisys Corporation | Record lock processor for multiprocessing data system |
JPH01315836A (en) * | 1988-06-15 | 1989-12-20 | Nec Corp | Synchronizing system between central processing unit and pre-processor |
US4965717A (en) * | 1988-12-09 | 1990-10-23 | Tandem Computers Incorporated | Multiple processor system having shared memory with private-write capability |
AU625293B2 (en) * | 1988-12-09 | 1992-07-09 | Tandem Computers Incorporated | Synchronization of fault-tolerant computer system having multiple processors |
CA2011807C (en) * | 1989-03-20 | 1999-02-23 | Katsumi Hayashi | Data base processing system using multiprocessor system |
ATE179811T1 (en) * | 1989-09-08 | 1999-05-15 | Auspex Systems Inc | OPERATING SYSTEM STRUCTURE WITH SEVERAL PROCESSING UNITS |
US5295258A (en) * | 1989-12-22 | 1994-03-15 | Tandem Computers Incorporated | Fault-tolerant computer system with online recovery and reintegration of redundant components |
US5203004A (en) * | 1990-01-08 | 1993-04-13 | Tandem Computers Incorporated | Multi-board system having electronic keying and preventing power to improperly connected plug-in board with improperly configured diode connections |
WO1992006431A1 (en) * | 1990-09-28 | 1992-04-16 | Fujitsu Limited | Message control method for data communication system |
JPH04367963A (en) * | 1991-06-15 | 1992-12-21 | Hitachi Ltd | Shared storage communication system |
JPH0553848A (en) * | 1991-08-26 | 1993-03-05 | Mitsubishi Electric Corp | Fault tolerant system |
JP2500038B2 (en) * | 1992-03-04 | 1996-05-29 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Multiprocessor computer system, fault tolerant processing method and data processing system |
US5317739A (en) * | 1992-03-30 | 1994-05-31 | International Business Machines Corp. | Method and apparatus for coupling data processing systems |
JPH05342032A (en) * | 1992-06-10 | 1993-12-24 | Stanley Electric Co Ltd | Backup method for building managing system |
KR100302223B1 (en) * | 1992-06-12 | 2001-11-22 | 그래햄 이. 테일러 | The secret interface for the process control computer and the method of transferring its data |
JPH0713838A (en) * | 1993-06-14 | 1995-01-17 | Internatl Business Mach Corp <Ibm> | Method and equipment for recovery of error |
US5680536A (en) * | 1994-03-25 | 1997-10-21 | Tyuluman; Samuel A. | Dual motherboard computer system |
US5841963A (en) * | 1994-06-08 | 1998-11-24 | Hitachi, Ltd. | Dual information processing system having a plurality of data transfer channels |
GB2290141B (en) * | 1994-06-09 | 1998-03-25 | Smiths Industries Plc | Fuel-gauging systems |
US5566297A (en) * | 1994-06-16 | 1996-10-15 | International Business Machines Corporation | Non-disruptive recovery from file server failure in a highly available file system for clustered computing environments |
EP0690597A1 (en) * | 1994-06-30 | 1996-01-03 | Hughes Aircraft Company | A system utilizing built-in redundancy switchover control |
US5761403A (en) * | 1995-05-17 | 1998-06-02 | Nec Corporation | Failure recovery system and failure recovery method in loosely coupled multi-computer system, and medium for storing failure recovery program |
US5828889A (en) * | 1996-05-31 | 1998-10-27 | Sun Microsystems, Inc. | Quorum mechanism in a two-node distributed computer system |
EP0825506B1 (en) | 1996-08-20 | 2013-03-06 | Invensys Systems, Inc. | Methods and apparatus for remote process control |
US6691183B1 (en) | 1998-05-20 | 2004-02-10 | Invensys Systems, Inc. | Second transfer logic causing a first transfer logic to check a data ready bit prior to each of multibit transfer of a continous transfer operation |
US7013305B2 (en) | 2001-10-01 | 2006-03-14 | International Business Machines Corporation | Managing the state of coupling facility structures, detecting by one or more systems coupled to the coupling facility, the suspended state of the duplexed command, detecting being independent of message exchange |
WO2000070461A1 (en) * | 1999-05-13 | 2000-11-23 | Fujitsu Limited | Method for controlling inheritance information in combined computer system |
US6754885B1 (en) | 1999-05-17 | 2004-06-22 | Invensys Systems, Inc. | Methods and apparatus for controlling object appearance in a process control configuration system |
WO2000070531A2 (en) | 1999-05-17 | 2000-11-23 | The Foxboro Company | Methods and apparatus for control configuration |
US7089530B1 (en) | 1999-05-17 | 2006-08-08 | Invensys Systems, Inc. | Process control configuration system with connection validation and configuration |
US7096465B1 (en) | 1999-05-17 | 2006-08-22 | Invensys Systems, Inc. | Process control configuration system with parameterized objects |
US7272815B1 (en) | 1999-05-17 | 2007-09-18 | Invensys Systems, Inc. | Methods and apparatus for control configuration with versioning, security, composite blocks, edit selection, object swapping, formulaic values and other aspects |
US6501995B1 (en) | 1999-06-30 | 2002-12-31 | The Foxboro Company | Process control system and method with improved distribution, installation and validation of components |
US6788980B1 (en) | 1999-06-11 | 2004-09-07 | Invensys Systems, Inc. | Methods and apparatus for control using control devices that provide a virtual machine environment and that communicate via an IP network |
US6510352B1 (en) | 1999-07-29 | 2003-01-21 | The Foxboro Company | Methods and apparatus for object-based process control |
ATE390788T1 (en) | 1999-10-14 | 2008-04-15 | Bluearc Uk Ltd | APPARATUS AND METHOD FOR HARDWARE EXECUTION OR HARDWARE ACCELERATION OF OPERATING SYSTEM FUNCTIONS |
US6473660B1 (en) | 1999-12-03 | 2002-10-29 | The Foxboro Company | Process control system and method with automatic fault avoidance |
US6779128B1 (en) | 2000-02-18 | 2004-08-17 | Invensys Systems, Inc. | Fault-tolerant data transfer |
US20020073409A1 (en) * | 2000-12-13 | 2002-06-13 | Arne Lundback | Telecommunications platform with processor cluster and method of operation thereof |
US6874014B2 (en) * | 2001-05-29 | 2005-03-29 | Hewlett-Packard Development Company, L.P. | Chip multiprocessor with multiple operating systems |
US20030217054A1 (en) * | 2002-04-15 | 2003-11-20 | Bachman George E. | Methods and apparatus for process, factory-floor, environmental, computer aided manufacturing-based or other control system with real-time data distribution |
US8041735B1 (en) | 2002-11-01 | 2011-10-18 | Bluearc Uk Limited | Distributed file system and method |
US7457822B1 (en) | 2002-11-01 | 2008-11-25 | Bluearc Uk Limited | Apparatus and method for hardware-based file system |
US7761923B2 (en) | 2004-03-01 | 2010-07-20 | Invensys Systems, Inc. | Process control methods and apparatus for intrusion detection, protection and network hardening |
WO2007123753A2 (en) | 2006-03-30 | 2007-11-01 | Invensys Systems, Inc. | Digital data processing apparatus and methods for improving plant performance |
CN104407518B (en) | 2008-06-20 | 2017-05-31 | 因文西斯系统公司 | The system and method interacted to the reality and Simulation Facility for process control |
US8127060B2 (en) | 2009-05-29 | 2012-02-28 | Invensys Systems, Inc | Methods and apparatus for control configuration with control objects that are fieldbus protocol-aware |
US8463964B2 (en) | 2009-05-29 | 2013-06-11 | Invensys Systems, Inc. | Methods and apparatus for control configuration with enhanced change-tracking |
JP5644380B2 (en) * | 2010-11-04 | 2014-12-24 | トヨタ自動車株式会社 | Information processing device |
US10579489B2 (en) | 2015-07-30 | 2020-03-03 | Mitsubishi Electric Corporation | Program execution device, program execution system, and program execution method |
FR3076004B1 (en) * | 2017-12-27 | 2021-03-19 | Bull Sas | FAULT MANAGEMENT METHOD IN A NODE NETWORK AND PART OF THE ASSOCIATED NODE NETWORK |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL153059B (en) * | 1967-01-23 | 1977-04-15 | Bell Telephone Mfg | AUTOMATIC TELECOMMUNICATION SWITCHING SYSTEM. |
GB1163859A (en) * | 1968-07-19 | 1969-09-10 | Ibm | Data Processing Systems |
US3692989A (en) * | 1970-10-14 | 1972-09-19 | Atomic Energy Commission | Computer diagnostic with inherent fail-safety |
JPS5627905B1 (en) * | 1970-11-06 | 1981-06-27 | ||
GB1536853A (en) * | 1975-05-01 | 1978-12-20 | Plessey Co Ltd | Data processing read and hold facility |
US4212057A (en) * | 1976-04-22 | 1980-07-08 | General Electric Company | Shared memory multi-microprocessor computer system |
US4228496A (en) * | 1976-09-07 | 1980-10-14 | Tandem Computers Incorporated | Multiprocessor system |
JPS55102064A (en) * | 1979-01-31 | 1980-08-04 | Toshiba Corp | Backup system in composite computer system |
JPS55131853A (en) * | 1979-03-31 | 1980-10-14 | Toshiba Corp | Control method for multiple-system electronic computer |
US4318173A (en) * | 1980-02-05 | 1982-03-02 | The Bendix Corporation | Scheduler for a multiple computer system |
JPS6053339B2 (en) * | 1980-10-09 | 1985-11-25 | 日本電気株式会社 | Logical unit error recovery method |
US4371754A (en) * | 1980-11-19 | 1983-02-01 | Rockwell International Corporation | Automatic fault recovery system for a multiple processor telecommunications switching control |
JPS5886647A (en) * | 1981-11-18 | 1983-05-24 | Mitsubishi Electric Corp | Dual system |
US4547849A (en) * | 1981-12-09 | 1985-10-15 | Glenn Louie | Interface between a microprocessor and a coprocessor |
US4590554A (en) * | 1982-11-23 | 1986-05-20 | Parallel Computers Systems, Inc. | Backup fault tolerant computer system |
-
1983
- 1983-09-02 JP JP58160522A patent/JPS6054052A/en active Pending
-
1984
- 1984-08-31 CA CA000462209A patent/CA1208796A/en not_active Expired
- 1984-08-31 DE DE8484110388T patent/DE3483636D1/en not_active Expired - Fee Related
- 1984-08-31 EP EP84110388A patent/EP0136560B1/en not_active Expired - Lifetime
- 1984-09-04 US US06/646,966 patent/US4709325A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS6054052A (en) | 1985-03-28 |
US4709325A (en) | 1987-11-24 |
DE3483636D1 (en) | 1991-01-03 |
EP0136560A2 (en) | 1985-04-10 |
EP0136560A3 (en) | 1987-10-28 |
EP0136560B1 (en) | 1990-11-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA1208796A (en) | Loosely coupled multiprocessor system capable of transferring a control signal set by the use of a common memory | |
CA1171545A (en) | Peripheral systems employing multipathing, path and access grouping | |
US6141715A (en) | Method and system for avoiding live lock conditions on a computer bus by insuring that the first retired bus master is the first to resubmit its retried transaction | |
JPS6130310B2 (en) | ||
EP0671691A2 (en) | Storage controller and bus control method for use therewith | |
EP0397476B1 (en) | Error logging data storing system | |
JPH02310664A (en) | Communication system using shared memory | |
US5887182A (en) | Multiprocessor system with vector pipelines | |
EP0368655A2 (en) | Communication system using a common memory | |
Gibson | Time-sharing in the ibm system/360: Model 67 | |
US5089953A (en) | Control and arbitration unit | |
EP0323123A2 (en) | A storage control system in a computer system | |
JP2807010B2 (en) | Tape drive control unit for interconnection between host computer and tape drive and method of operating the same | |
JPH03150654A (en) | Preference control system for processor having cash | |
JP3364751B2 (en) | Data transfer system | |
JP3273191B2 (en) | Data transfer device | |
US6275915B1 (en) | Selective memory duplication arrangement | |
JP3403932B2 (en) | Data input / output device | |
JPH06259395A (en) | Process scheduling system | |
JPS58182737A (en) | Information processor | |
JP2752834B2 (en) | Data transfer device | |
CA1199122A (en) | Access control processing system in computer system | |
JP2837522B2 (en) | I / O instruction control method | |
JPH0319574B2 (en) | ||
JPS61131152A (en) | Dma buffer control system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MKEX | Expiry |