CA1211856A - Apparatus for reverse translation - Google Patents

Abstract

Abstract Disclosed is an apparatus for storing data wherein there are at least two storage units which are addressed by different addressing schemes. The primary storage unit is addressed with a unique addressing scheme while the other storage units are addressed with a scheme wherein more than one of the other addresses may map to a single unique primary address. The apparatus for storing data includes a mechanism for translating all of the unique primary addres-ses to all of the other addresses which map to that unique primary address.

Description

~Z1~8~6 APPARATUS FOR REVERSE TRANSLATION

Invented by: Gene Myron Amdahl Donald Laverne ~anson Ronald Kar~ Kreuzenstein Gwynne Lynn Roshon-Larsen Gary Arthur Woffinden Field of the Invention This invention relate~ to the storage of data in da~a proce~ing machines. Particularly the field of thi3 invention is addressing mechanisms for accessing data in storage facilit~es of data processing machines.

_ackqround of the Invention Large data proce~sing machines normally have more than one storage facility. Usually these $nclude a fast access bufer ~torage unit and an large capacity main storage unlt. The fast access buffer i8 used to decrease the apparent access time to da~a stored in the machine. The buffer operates by retrieving blocks of data from the main s~orage unit and holding the data ready for access by the central proce~sing unit of the machine. The machine acce~ses the data from the buffer and in turn may update the data stored in the buffer from the ma~n storage unit in an effort to keep curxently active data ~n the buffer.

AMDHll/VBA
AMD~ 3219 DEL/MAH
83/08/~7 ~ lZ~856 ,~

- 2 -In addition to having more than one storage facility in a data processing machine, often the machine will use more than one addressing scheme for accessing the data in the storage facilities. ~here is always the system address which uniquely locate~ a given set of data within the main storage facility of the data processing machine. In addition, there may also be other non-unique addressing schemes, referred to a~ virtual addresses, which are assigned to a given CPU within the machine or a given programmer. The virtual addresse3 can be used to increase the apparent allocated ~torage space to a given user by dis~ssociating the user to a certain degree from the system address. In this manner a given user may be actually allocated only a part of the system main storage facility while having at it6 disposal fo~ programminq a much larger set of virtual addresses. In thi~ type of addressing ~cheme, of course, more than one virtual address may actually acces~ the same set of data within the mainstore.
That is, more than one virtual address may translate into the same ~ystem addres6. Those virtual addresses which translate to the same sy~tem address are referred to as synonym virtual addre6ses.
Data processing machines which use virtual address to sy~tem addres~ addressing schemes normally include a tran~lation mechanism which stores tables that are acces-sible by the virtual address, or some function thereof, which keep information necessary to translate the virtual addre~s to the system address. In this manner, the main storage facility which i~ accessed only by the system addres~ can be accessed by the proqrammer using the virtual addres~ ,, Recause a given system address may be the translation of more than one virtual address, the need may arise for computing all the virtual addresses which map to the given system address. For instance, in a data processing machine which allows ~irect access to the fast access buffer using AMDRll/VBA

the virtual address, such a~ is described in the patent application entitl~d ~VIRTUA~Y ADDRESSED CACHE~ ~nvented by Gene Myron Amdahl, Donald Laverne Nanson~ and Gary Arthur Woffinden, filed contemporaneously herewith and owned by a common assignee, there is a need for a mechanism for translating the 6y~tem addre~ to all the synonym virtual addres~es which map to that given system address.
This need arises because data within the fast access buffer may be operated upon or changed in ~ome manner a~ one virtual addre~s location without d$rectly making the ~ame changes in all the 8ynonym virtual addresses. So the translation from system address to all synonym virtual addres~es must be performed ln order to as~ure that data contained in the fast acces~ buffer and all the 3ynonym 15 virtual address location~ i8 accurate.

SummarY of the Invention In accordance with the foregoing, the present inven-tion provldes a mechanism for carrying out the translat$on from the system address to all the ~ynonym v$rtual address-20 es for a given ~et of data. This function will be termedthroughout thi~ application as reverse translation in order to distinguish it from the translation of the virtual address to the sy~tem address.
Thus in a data processing machine, the present inven-25 tion provide~ an apparatu~ for storing data comprislng aprimary storage facility, such as a main storage unit, for ~toring data with ~ primary addressing mean~ for uniquely addre~sing the data within the primary storage means with unique primary addres~es. The apparatus for storing data 30 further includes a secondary Rtorage mean~, ~uch as a fast acce~s buffer unit, for storing data in communication with the primary storage means ~o that data may be transferred between the primary storage mean~ and the ~econdary st~rage means and vice ver~a. The ~econdary storage means i8 35 addressed with a secondary addressing means for addressing * S.N. 461,943 AMDHll/VBA

a3/os/27 , .

~; ' -- . ` M ~b, 12118~6 the data within the secondary storage means with secondary addresses that are not unique to a given set of data. Thus translation means are provided for translating the secondary addresses to the unique primary addresses to uniquely address the ~ets of data within the machine.
Finally reverse translation means are provided for t~anslating each of the unique primary addresses to all the synonym secondary addresses which map to the un~que primary address.
The prlmary sddresses include a page addres~, a line addre~s, and a byte address which uniquely identify the location of the data. The page addre~ may identify, for instance, blocks of 4,096 byte~ l4X bytes) of data while the line address identifies a block of 32 byte addre~ses;
and the byte address identifies the locat$on of a set of 8 bits. Other progressive breakdown~ of the s~ze of the sets of data identified by the page, line, and byte addresses can be used.
The translation mean~ include~ a page table storage means for storing the informatlon necessary to translate the ~econdary address to the page address of the primary address. The translation means further includes a line table storage means for storing the information neces~ary for assur~ng that the lnformat~on in the page table storage means matches the line ~ccessed in the secondary s~ora~e means. Thus the translation mean~ identifies the line of data within a primary addres8 page, and then uniquely identifies the unique primary address page, within the primary storage unit for the reque~ted line of data.
The reverse translation means includes a page table search means for searching the page table storage means for synonym secondary addresses along page boundaries. Further the reverYe translation mean~ include~ a line table search mean~ which searche~ the line table storage means for all ~ynonym seGondary addresses along line boundaries. Thus the reverse translation me~ns ~earches the page table AMDHll/V~A

83~08/27 ~ 1;Z:1~856 ~

~toraqe means for all tran~lation~ to a given page. Upon finding translation~ to a given page, the reverse translation means searches the line table storage means for the given line within the page.
Thu~ it can be seen that the present invention pro-vide8 a reverse translation means which first searche~
alonq page boundarie~ through a page table storage means for secondary addre~ses which translate to a given primary address page, and then upon finding a synonym page address, searche~ the line addre~es in the line table storage means for synonym lines to thereby identify all the secondary addresses which translate to a given unique primary address.

~rief Description of the Drawinqs FIG. 1 i~ a system overview of a data processing machine and includes present invention.
FIG. 2 18 a simplified schematic diagram showing the addres~ path~ of the present invention.
PIG. 3 ~ an expanded schematic diagram showing the address paths of the preferred embodiment of the present invention.
FIG. 4 is a schematic diaqram showing the TL~ address paths of the linked list implementation of the preferred embodiment.

Detailed Description With reference to the drawings, detailed description of the preferred embodiment of the present invention is provided.
FIG.I ~hows a block diagram of a system overv~ew of the data processing machine D which employ~ the present invention. $he present invention is most closely a~soci-ated with the central processing unit 2-01, the memory bus controller 2-02, and a primary storage means or main storage unit 2-03. The central processing unit 2-01 AMDHll/VBA

~ lZ118~6 ~

includes five subparts as follows: the instruction unit 2-04 (I-UNIT) which fetches, decodes, and controls in-structions and controls the central proce~sing unit 2-01;
the execution unit 2-05 (E-UNIT) which provides computational facilities for the data processing machine D;
the storage unit 2-06 (S-UNIT) which controls the data processing machine'~ instruction and operand storage and retrieval facilitiesS a secondary ~torage means or the instruction buffer 2-07 which provides high-speed buffer 8torage for instruction streams~ and a secondary storage means or the operand buffer 2-08 provides high-speed buffer storage for operand data.
Other major parts of a data processing machine as ~hown in ~IG.1 include the lnput-output processor (IOP) 2-10 which receive~ and proce~es input-output requests from the central proce~sing unit 2-01 and provides block multiplexer channelss the console 2-09 which communicates with the central processing unit 2-01 to provide system control and byte multiplexer channels; the memory bus controller IMBC) 2-02 which provides main memory and bus control, system wide coordination of functions and timing facilitiest and the main ~torage unit 2-03 which provides system large capacity memory. A second input-output processor 2-14 and additional multiplexer channels 2-15 may be included as shown in FIG. 1. Though not shown ~n the Figures, the data processinq machine D of the present invention may have additional CPU's.
The data processinq machine shown in FIG. 1 employs a dual bus ~tructure: the A-bus 2-16 and the B-bus 2-17.
The A-bus 2-16 carries addresses and data from the con~ole 2-09, the input-output processor 2-10, and the central processing unit 2-01 to the memory bus controller 2-02.
The B-bus 2-17 carries data from the memory bus controller 2-02 and the main storage unit 2-03 to the console 2-09, the input-output processor 2-10 and the central processing unit 2-01.

AMDHll/V~A

12~18S6 , For a more detailed de~cription of the system overview shown in FIG. 1 refer to the related application entitled ~VIRTUALLY ADDRESSED CACHE~ invented by Gene Myron Amdahl, Donald Laverne Hanson and Gary Arthur Woffinden, filed S contemporaneously herewith and owned by a common assignee.
The present application is concerned primarily with the addre~sing of data located in the secondary storage means or high ~peed buffers 2-07, 2-08 and in the primary ~torage means or mainstore 2-03, where the mainstore 2-03 10 i8 addre9sed with a primary addre~ing mean~ that un$quely addres~es the data in the mainstore 2-03; and the buffers 2-07, 2-08 are addres~ed with a secondary addressing mean~.
The ~econdary addresslng means of the buffer~ 2-07, 2-08 may allow more than one ~econdary address, or virtual address, to tran~late to a given unique primary address, or ~ystem addres~.
In thi~ situation, the need arises for a means for reverse translation whereby a primary addres~ is translated to all the ~econdary addresses which in turn will translate to that given unique primary address. The reverse translation means is necessary because the non-unique secondary addres~es, or virtual addre~ses, allow more than one copy of a given line of data to reside in the buf fers 2-07, 2-08. When additional CPU's Inot shown) are used, the given line may reside a~ well in buffers ass~ciated with the additional CPU. Further, because the buffers 2-07, 2-08 are acce~sed dlrectly in the preferred embodiment with the virtual address, more than one program may request the same line of data using different virtual addresses and process the llne of data. If one of the requested programs modifies the line of data, the other program~ using the same line at different virtual addresses must see the modification.
FIG. 2 is a simplified schematic diagram showing the 35 address path of the present invention where the need for reverse translation arises out of the use of a buffer 2-08 * S.N. 461,943 AMDHll/VsA
AMDH 3219 DELtMAH

~ lZ1~8~6 ~

which is addressed using a virtual address ~YA) while the ~ainstore 2-03 i5 addressed u~ing a system address (SA).
In thi~ situation, a requested virtual address 2-76 is presented at the virtual address selector 2-77 for accessing data from the buffer 2-08 ~in this example we will use only the operand buffer 2-08~. The virtual address selector 2-77 ~elect~ the requested virtual address 2-76 presented to it and addresses the buffer 2-08 for the line repre~ented by that virtual addre~ 2-76. Whlle the virtual address 2-76 i~ pre~ented in the buffer 2-08, the virtual address 2-76 is al~o presented to a translation mechanism 2-152 which searches tables present in the translation mechani~m 2-152 for the ~ystem address ~SA) corresponding to the reque~ted VA 2-76. If the line is pre~ent in the buffer 2-OB then it i~ presented to the requesting unit. If the tran~lation mechanism 2-152 has a translation to a sy~tem address $n its table~ and the data i~ not in the buffer 2-08, then the mainstore 2-03 i~
accessed for the data and a proces~ ls begun to move the data out of the mainstore 2-03 into the buffer 2-08 at the requested virtual addre~ 2-76. While the process i~ begun for retrieving the data from the ~ainstore 2-03, the system addre~s (SA) is presented to a reverse translation mecha-nism 2-153 where the virtual addresse~ are determined that are synonym~ to the requested VA 2-76, that i~ VA'~ which tran~late to the pre~ented sy~tem address. ~f a synonym virtual addres~ i~ found, then data in the buffers 2-08 at that synonym v~rtual address i~ examined in order to determine whether it i8 a more recen~ version of the reque~ted data.
In the preferred embodiment there are valid bits associated with each line of data in the buffer that indica~e the ~tate of the lina in the buffer 2-08 with re~pect to other ver~ion~ pre~ent in the ~y~tem. In the operand buffer 2-08, the data a~ indicated by the valid bits may be written in four states: ~invalid" meaning the AMDHll/V~A

~ 1211~ 6 ~
_ g _ data is not valid; ~public~ meaning the data i~ valid but may exist at other location~ so it may be only read ~private~ meaning that only one copy of the line exists outside the mainstore 2-03 and it may be modified; and ~modified~ meaning only one copy of the line exists outside the mainstore 22-03 and it i8 different than the line at its corresponding system address in mainstore 2-03.
Synonym virtual addresses are presented to the port 2-102 where they are held until the virtual address sele~tor 2-77 accept~ the synonym virtual address for presentation to the buffer 2-08. When the synonym virtual address is accessed in the buffer 2-08, and the valid bits indicate that it i8 modified data which i8 the mos~
up-to-date version of the data, the data is sent to the ~ystem addres~ in the mainstore 2-03 and provided at the requested virtual ~ddre~s in the buffer 2-08. If the data at the synonym virtual address ls no~ modified, then the version ln the mainstore 2-03 at the ~ystem address will be the same as data at the synonym virtual address; ~o the synonym virtu~l addres~ may be erased or left alone, depending on the purpose for which the requested virtual addre6s 2-76 will be u~ed as explained in more detail below.
Therefore the present invention prov$des an apparatus for reverse translation of a requested system address 2-76 to all synonym virtual addresses which include a copy of the data from the system address. The data at the virtual ~ynonym ~ddre~es may then be examined to determine the most up-to-date version of the data identified by the system address.
In the preferred embodiment, the reverse translation means 2-153 of the present invention is utilized in connection with the operand buffer 2-08 and instruction buffer 2-07. The instruction buffer 2-07 is set up in the preferred embodiment so that the valid bits only indicate whether the instruction is public or invalid. Because the s3/ns/27 .
~, lZ~8~6 ~

possibility of a modified line does not exist in the instruction buffer 2-07, the operation resulting from an access requiring a rever~e translation carried on in the instruction buffer 2-07 i~ somewhat simpler than that as~ociated with the operand buffer 2-08. Thus, the preferred embodiment will be described with reference ~o the operand buffer 2-08 in order to most completely describe the invention. ~ote that a virtual address in the operand buffer 2-08 may have a ~ynonym in the instruction buffer 2-07.
A more detailed schematic diagram showing the address path~ of the preferred embodiment of the present invention i8 shown in FIG.3. For the purposes of description, the ~ddress paths shown in FIG. 3 will be described with reference to the situation in which a data line at a virtual address is requested by the central processing unit 2-01 from the operand buffer 2-08 and it is found that the line of data at the requested virtual address 2-76 is not present in the buffer 2-08, but that the tran~lation means 2-152 include~ a translation to the system address for the.
requested virtual address 2-76. The translation may exist in the translation means 2-152 even when the data line is not present in the buffer 2-08. The det~ils of the translation mechanism 2-152 will be described as a request flow~ through the diagram.
A requested virtual ~ddre~ 2-76 i8 presented to a virtual address selector 2-77 which selects the virtual addres~ to be presented to the operand addre~s register 2-78 depending on control (not shown) which will calculate the priority of a given Fequest for data from the operand buffer 2-08. So as~uming our requested virtual addres~
2-76 i~ selected by the virtual address selector 2-77 for presentation to the operand address register 2-78, the data at the reque~ted virtual address 2-76 will be accessed in the buffer 2-08.

AMDHll/VBA

83/08~27 ~ lZ~8~6 ~

In the preferred embodiment, a system address page consi8t~ of 4096 bytes (4K page) or 204~ bytes (2K page) in lines of 32 bytes each. A sy~tem address is 31 bits long.
Bits 1-19 for a 4R page uniquely identify a page within the mainstore 2-03 while bits 20-31 will uniquely identifv the line and byte of the data. For a 2R page si~e the high order bit~ ne~e9~ary to identify the page of data within the mainstore will be bits 1-20. However for the purpose~
of this de~cription we will assume a 4~ page ~ize.
The reque~ted virtual address 2-76 in the operand addres~ register 2-78 will be bro~en down into the lower order bits, 18 to 26, which will be u~ed to locate ~he line within the operand buffer 2-08, and the high order bit~, I
to 19, which will be u~ed to locate the translation from the requested virtual addres~ 2-76 in the operand address regi~ter 2-73 to the ~ystem addre~s page. First the low order bits, 18-26, are used to ~ccess the operand buffer 2-08. The buffer 2-08 iB organized along line boundaries 80 it i8 a line table storage means. Each line of data acces3ed in the buffer 2-08 will have a~ociated with it the tag-l field 2-81 which will contain a TLB address for each page with a line entry in the buffer 2-08. The TL~, or translation lookaside buffer, consists in the preferred embodiment of a virtual addres8 portion, VA TLB 2-83, and a system addre~ portion, SA TLB 2-86, which together contain the virtual addre~s, system addres~, storage protect~on information, and other _information necessary for translating from a virtual to system address. Whenever there exists a line in the buffers 2-07, 2-08 that is accessible to the central proces~inq units, the VA TLB 2-83 and SA TLB 2-86 hold a tran~lat$on for the line. However a translation for the line may reside in the VA TLB 2-83 and SA TLB 2-86 when the line is not in the buffer~ 2-07, 2-08 becau~e the TLB operates on page boundaries and updating of entrie8 in the T~ is controlled differently than updating AMDHll/VBA

83/Of~/27 ~ lZ~18S6 ~

the line of data in the buffers 2-07, 2-08. The VA TLB
2-83 and SA TLB 2-86 are acce~sed using the same TL~
addres8, except that the SA TLB 2-86 requires an additional addressinq bit called the flipper bit described below. The TL~ i8 a page table storage means because it stores translations along page boundaries.
As the low order bits access the buffer 2-08, the high order bits 1-19 are presented to a T~B ha~h 2-80 which generates the TLL address for the given requested virtual address 2-76 located in the operand address register 2-78.
Upon output from the TLB hash ~-80, the TL8 address is compared with the TL~ address th~t i~ found in the tag-l 2-81 which wa~ associated with the data line in the buffer 2-08. If the line in the buffer 2-08 that was accessed with lower order bit8 18-26 of the requested virtual address 2-76 hss an entry in the tag-l 2-81 that matches the TLB address generated by the T~B hash 2-80 of the high order bits 1-19, then the line comparator 2-82 will indicate that the requested vlrtual ~ddress line may reside in the buffer 2-08. If the vlrtu~l address in the VA TLB
2-83 also matches the requested virtual address 2-76, then the line i8 present in th~ buffer 2-08. However, the present ex~mple concern~ the situation wherein the requested line of data i8 not in the buffer or the line is invalidS 80 the TLB address which results from the TLB hash 2-80 of the high order blts 1-19 doe~ not match the T~B
address found in the tag-l 2-81 associated with the data line in the operand buffer 2-08 that was addressed by the low order bits 18-26.
The virtual address acces~ed in the VA TL~ 2-83 by the TLB hash 2-~0 of the high order blts i8 compared with the requested virtual address 2-76 at the translation comparator 2-84. A match at the translation comparator 2-84 and at the line comparator 2-82 will occur if the requested line is in the buffer 08. The translation comparator 2-84, however may indicate that a translation AMDHll/V~A
AMDH 3219 DEL~MAH

lZ118~i6 exi~ts ln the VA TLB 2-B3 and SA TLB 2-86 even though the line comparator 2-82 fail~ to get a match. If the tran~lation exist~, then the ~ystem page address is read from the SA TL~ 2-86.
5The paqe translation present in the translation lookaside buffer (VA TLB 2-83 and SA TLB 2-86) iq ~ufficient to generate the complete ~ystem address in the preferred embodiment becau~e (assuming 4X page size) the low order bits 20-31 of the vlrtual address are the ~ame as the low order bit~ 20-31 of the ~y~tem addre~s. Thus if the lower order bits 20-31 of the vlrtual addres~ -are preserved, the translation mechani~m need only generate the high order bit~ l-l9 in order to complete the translation to the ~ystem address. The tran~latlon means 2-152 completes its task by del~vering the system page addreqs from the SA TLB 2-86 to the mainstore address regi~ter 2-91.
Thu~, if it has been discovered at the translation comparator 2-84 that a v~rtual-to-system page addre~s translation 1B prcsent in the VA TLB 2-83 and SA TLB 2-86, the TLD addre~ resulting from the hash 2-80 of the high order bits of the requested virtual address 2-76 in the operand addre~ register 2-78 is pre~ented along the line 2-113 to the TLB addres~ ~elector 2-B5. Al~o presented along with the TLB address i- a flipper bit 2-86, in the preferred embodlment. The fllpper bit 2-86 selects one of two system addre~se~ present in the SA TLB 2-86. The SA
TL8 2-B6 contains two system addresses at a given TL8 address, only one of which i~ a currently acce~s~ble ~yætem 30 addre~ for the purpose~ of translation. The flipper bit 2-86 select~ the activo ~y~tem address and i~ always used ln acce~ing the SA TLB 2-86. The inactive ~ystem addse~s i~ used in controlling the eviction of the TLB entrie~ a~
described in more detall in the related patent appl$cstion 35 entitled ~VIRTUALLY ADDRESSED CACHE~ invented by Gene Myron Amdahl, Donald Laverne Han~on and Gary Arthur Woffinden, aerial number 461,943, AMDHll/VBA

~ ~21~8~6 ~

filed contemporaneously herewith and owned by a common as~ignee.
Upon selection by the TL8 address selector 2-85, the TLB address resulting from the hash 2-80 of the high order bit~ 1-19 of the requested virtual address 2-76 along with the flipper bit 2-86 is latched in the TLB address register 2-87 and pre~ented to the SA ~ 2-86. The system addresg page bitg 1-19 for the translation are accessed at the TLB
addre~s from the SA TLB 2-86 and presented along the address line 2-88 to the selector 2-89 and selected for pres~ntation to the MBC register 2-90. The requested virtual address 2-76 is clocked over to the register 2-120 for timing purposes. Then the system line address con~isting of the low order bits 20-31 i~ presented to the M~C register 2-90 to complet~ the translation to the system addre~.
Upon generation of the sy~tem address, it is trans-ferred to the mainstore address register 2-91 and the data 18 acce~sed from the mainstore 2-03, presented to the data select 2-92 and then to the requested virtual address 2-76 in the buffer 2-08 along the data line 2-93.
So far we have demon~trated the mechanism for trans-lating a requegted virtual address 2-76 into a system addre~s for recovering the ~ata from the mainstore 2-03 and pre~enting it back to the buffer 2-08 at the requested virtual addre~# 2-76. In thi~ situation, a reverse translation i~ nece~ary in order to a~sure the integrity of the data presented from the malnstore 2-03 to the requested virtual addre~s 2-76. In other words, the machine must assure that the data written into the requested virtual addre~ 2-76 i8 the mo~t up-to-date version of the data. Because the data at the requested virtual addre~s 2-76 may have ~ynonym lines present in the operand buffer 2-08, instruction buffer 2-07, or other CPU'~ ~not shown) which have been operated on or modified in so~e way, as indicated by their valid bit~, the machine AMDHl I /VBA

~ lZ1~856 ~
_ ,,5 must search for those synonym~ and check the status of tho~e synonym~, and return data to requestor if the line i8 a more recent line than the one in main~tore 2-03. Further if the data once written at the requested virtual address 2-76 is to be modified or ope~ated upon by the user, then the machine must assure that data at all the synonym virtual addresses will be made unavailable for use by others. Thus there is a need for a reverse translation mechanism 2-153 in the preferred embodiment.
The rever~e translation mean~ 2-153 therefore starts at the main~tore addres~ register 2-gl with a system address and calculates all synonym virtual addresses. In the preferred embodiment, the reverse translation means 2-153 i~ implemented with a linked list searching means 2-llS associated with the SA TL~ 2-86. Because the SA TLB
2-86 is ut~lized, the ~earch proceeds along page boundaries at the fir8t level and can be termed a page table search mean~. Thus the high order bit~ 1-19 of the system address are pre~ented to a li~t ha~h 2-94 which generates a li8t header table addres~ for accessing a list header table 2-95. The 11st header table 2-95 contains the first TLB
address of a linked list of all system addresses in the SA
TLB 2-86 which hash to the ~ame list header table addres~.
Thus the first entry searched ~n the SA TL~ 2-86 will occur at the TLB address generated in the list header table 2-9S.
The TLB address from the list header table 2-9S is pre~ented to the TLB address selector 2-85 for access to the TLB addre~s register 2-87. Upon access to the TLB
address register 2-~7, the first entry in the ll~t will be accessed in the SA TLB 2-86. The system address located at the first list entry in the SA T~ 2-86 i~ then compared with the high order bits 1-19 of the system address in the mainstore address register 2-91 at the synonym page comparator 2-96.
Assuming that the first entry in the list is not the only entry in the list, the TLB address of the first entry AMDHll/VBA

~ ~Z1~856 ~

in the list will also acce~s a pointer TL~ address which consi~ts of a TLB address of the next entry in the linked list. ~he TLa addres~ of the next entry will be presented along the line of 2-122 through control shown ~n more detail in FIG. 4 back to the TL~ address selector 2-85.
Thus the next entry in the linked list is accessed in the SA TLB 2-86 and compared with the system address in the mainstore address register 2-91. Further details of the linked list implementation of the reverse tran~lation will be described below.
Upon discovering a synonym page at the synonym page comparator 2-96, the TLB address of the synonym paqe is pre~ented along with low order bit~ 20-26 of the system address in the mainstore addreR~ register 2-91 to the tag-2 address register 2-97. In the preferred embodiment the tag-2 2-99 contains a duplicate of information contained in the tag-l 2-81 that i8 used for the reverse translation.
Thus, the taq-2 2-99 is a line table storage means that is searched with line table search means described below.
Because the function of the ~L~ hash 2-80 which computes a TLB addres~ leaves bits 18 and 19 invariant from the virtual addre~s that generates the TLB addres3, the bits 18-28 written into the tag-2 address register 2-97 will be identical to the bits 18-28 of the synonym virtual address.
Because the reverse translation mechani~m 2-153 has discovered that a line from a synonym page may exist in the buffer 2-08 through it~ ~earch of the SA TLB 2-86, the search need only now search the operand buffer 2-08 for the line which matches on low order bit~ of requested virtual address 2-76 ~the reguested line in that synonym page). If the original request for data was generated by a line missing in a buffer, then the reverse translation means 2-153 will always find at least one synonym page address for which to search the buffer 2-08, as this system addresæ
was uæed to generate the request from mainstore 2-03.

AMDH11/V~A
AMDH 3219 DEL/MA~

12118S~

As mentioned above, the taq-2 2-99 in the preferred embodiment i8 an identical copy of the information in tag-1 2-81 which is as~ociated with the data lines in the buffer 2-08. Thus the rever~e translation means 2-153 only searches tag-2 2-99 for an entry which matches along the low order bits 18-26 with the address in the tag-2 address register 2-97. In thi~ manner, the tag-l 2-81 in the buffer 2-08 i8 available for use by other accesses to the buffer 2-08 while reverse tran~lation means 2-153 is using the tag-2 2-99.
Thus the bits 18-26 access the tag-2 2-99 in a process which duplicates the access of tag-l 2-81 by a requested virtual addreYs 2-76. At the tag-2 address determined by the bits lB-26 of the addre~s in the tag-2 address register 2-97, ~ TLB address will be read. If the TLL address located in the tag-~ 2-99 at the address generated by bits 18-26 matches the TLB address of the synonym page presented to the tag-2 address reqister 2-97 over the line 2-100, then the line exists comparator 2-101 indicates that a synonym line is present in the buffer 2-08.
Once the reverse translation means 2-153 determines the presence of a synonym line in the buffer 2-08, then control determines what mu~t be done w~th the synonym llne in order to assure the integrity of the data in the buffer 2-08. If the synonym line ls modified as indicated by the valid bits as~ociated wi~b it in the tag-2 2-99, then the synonym ~ine mu~t be provided to the reque~ted virtual address 2-76. If the synonym line is public or private and the reque~ted virtual address 2-76 is requested in the private state, then the synonym line must be written invalid or erased. If the synonym line is public and the requested virtual addres~ 2-76 is requested in the public ~tate, then the synonym line may be left alone. If the synonym line i9 private and the requested virtual address is requested public, then the synonym line must be changed to a public state or era~ed. Other control decisions may A~DH 1 1 /VBA

~21~8~6 be fashioned a~ the need arises for the u~er of the present invention.
To access a virtually addressed synonym line for operation upon, as determined by control, the addre~s bits 20-28 plus the TLB address that were presented to the tag-2 address register 2-97 are written into the data integrity port 2-102. The high order bits 10 to 19 of the synonym virtunl address in the tag-2 addre3s reg~ster 2-97 consist of the TLB address of the synonym ~irtual address. The low order bit~ 20 to 28 are the same for all synonymq in 4X
page size. Likewise the TLB address of the synonym virtually addressed line i8 written into the move-out ~LB
pointer register 2-103. If the synonym virtual address contain~ a modified version of the data line that exists in the system address in mainstore 2-03, then the move-out TLs polnter register 2-103 is ~elected at the TLB address selector 2-85 for the move-out procedures which update the data line in the mainstore 2-03, and return it to the requested virtual address 2-76.
As discussed above, if the synonym line is a modified line which 18 the most up-to-date version of the data requested by the reque~ted virtual ~ddress 2-76, then control present~ the synonym virtual address along synonym line 2-105 to the virtual address selector 2-77 for a presontatlon to the buffer 2-08 ln order to access thls mo~t ~p-to-date ver~ion of the line from the synonym address to be moved out of the buffer 2-08 and returned to the requestor. When the virtual address selector 2-77 present~ the synonym virtual addres~ to the operand address register 2-78, the hash 2-80 will see the TLB address in bit locations 10-l9 of the address in the operand address register 2-78. The hash 2-80 will pass this TLB address through the hash unaltered for pre~entation to the VA TLB
2-83 because of the function of the TLB address hash 2-80 ~the pointer TLB address stored in the SA TLB 2-86 is already hashed). The low order bits 18-26 wlll be the AMDHll/VBA
AMDH 32l9 DEL/MAH

,~ 121~L8S~

accurate copy of the low order bits of the synonym virtual addres~.
Meanwhile control w~ll direct the TLB address of the synonym virtual address from the move-out TLB pointer register 2-103 through the TLB address selector 2-85 to the TLB addres~ register 2-87 to access the system page address from the SA TLB 2-86 which passes through the system address save register 2-123 and through a error checking and correcting logic block 2-106. The system page address i9 ~elected by the sy~tem address selector 2-89 for presentation to the MBC register 2-90 to generate the system address page for acce~sing the mainstore 2-0~. The line present comparator 2-82 will signal the control to move the synonym virtual addre~s over to the regis~er 2-120 where the lcw order bits 20-31 are presented to the MBC
register 2-9~ to complete the 6y~tem address. If as in this example, the data of the ~ynonym virtual address is a modified ver~ion of the line, then control Inot shown) will direct data from the buffer 2-08 through the bypass register 2-107 from the ~ynonym virtual address and bypass the main~tore 2-03 to the data selector 2-92 from which this modified version of the data i8 read into the buffer 2-08 at the requested virtual addres~ 2-76. The mainstore 2-03 is acce~sed from the main~tore address.register 2-91 and the modified ver~lon of the data is written into the malnstore 2-03. Data ~elector 2-92 will not select data from the acces~ to the main~tore 2-03 that wa~ initiated when the requested virtual ~ddres~ translation was pre~ented to the mainstore addre~s register 2-91, and will allow the bypa~s from the synonym virtual address line containing the updated version of the data.
It therefore can be seen that the preferred embodiment includes a reverse translation means 2-153 for generating the synonym virtual addresses associated with a requested virtual address 2-76. Not described is the situation where a system address is generated and presented to the AMDHl 1 /VBA

lZ~

mainstore adaress register 2-91 from the system translator which includes the tables for translations of all virtual addresse~ to all system addre~ses. The system translator (not shown) will be used to generate the system address in the casè that a translation for a given page of system address data ~ not found in the ~L~ (VA TLB 2-83 SA TLB
2-86). (See, IBM*SYstem 370_Principles of Operation ~Ninth Ed~tion 1981, Flle No. S370-01, GA22-700~-8)).
The present invention pertains most directly to the reverse tran~lation means 2~153 descrlbed above with reference to FIG. 3. Reverse translation takes place in the preferred embodiment whenever the mainstore 2-03 is accessed for data from any source including the part~ of the CPU 2-01, other CPU's, the IOP's 2-10, 2-14 or console 2-09. The reverse translation beqins with a system address in the ma~nstore addres~ regi~ter 2-91, proceeds through a search of the SA TL~ 2-86, and then upon dlscovery of a synonym page proceed~ to search the tag-2 2-99 for synonym line. FIG. 4 shows a schematic diagram of the TLB address paths for the linked list implementation of the preferred embodiment. The linked list searching means 2~115 is implemented in the search of the SA TLB 2-86, ~o the diagram in FIG. ~ represent~ an expanded view of the addres~ paths including the SA ~LB 2-86 portion of the rever~e translation mean~ 2-153. The portions of the diagram ln FIG. 4 which appear in FIG. 3 will be given like numerals for corresponding part~.
Por purpoQes of the description of the linked list searching mean~ 2-115 for the search of the TL8, assume that a system addxess exi~tJ in the mainstore address register 2-91 for a line of data that is needed by a requestor from malnstore 2-03. ~s described with reference to FIG. 3, the system address whicb requires reverse translation first accesses the list header table 2-95 to 35 discover the fir~t entry ~ a list of system page addresse~
that are stored in the SA T~B 2-86. $he list header table * trade mark AMDHll/VBA

" ~

~ 121~856 ~--2-95 is accessed by hashing a subset of the high order bits 1-19 to produce a list header table address from the list header table hash 2-94. The linked lists are associated by the condit$on that each entry in a linked list must gen-erate the same list header table address upon hash of the subset of high order bits. The ordering of the list is then determined as suit~ the user. The list need not be kept in a specific order accept that by ordering a list the length of the search necessary can be decreased statistically.
At the address accessed from the hash 2-94 of the mainstore address register entry, a TLB address will be found pointing to the first entry in the list of system page addres3es stored in the SA TLB 2-86 with which list the mainstore address register entry i~ associated. The TLB address from the list header table 2-95 is presented to the first TLB list selector 2-110 which will select the list header table TLB address to the second l~st selector 2-111. From the second list selector 2-111 the TLB address is presented to the pointer ~elector 2-124 and stored into the TLB address register 2-87. The first list selector 2-110, second list selector 2-111, and pointer selector 2-124 correspond to the TLB address selector 2-85 shown in FIG. 3.
The SA TLB 2-86 is then accessed from the TLB address register 2-87 and a system page address is read out and ~natched with the page address in the mainstore address register 2-91 at the system ~ddress comparator 2-96 to determine whether a synonym page is present at the TLB
address. The search proceeds to the next entry until the end of the list or the énd of the search.
Associated with each system address entry in the SA
TLB 2-86 is the pointer TLB address of the next entry in a associated list. Thus the TLB address of the next entry in the list is presented to the first list selector 2-110, proceeds across the list line 2-122 to the second list AMDHlllVBA

83tO8/27 121î8~6 selector 2-111 and into the pointer selector 2-124, and so on for each entry list until the search is stopped.
The linked list search will stop when the system addres~ found that is according to the list orderinq greater than the system address in the mainstore address register 2-91, when the end of the list is found, or when a synonym i~ found which i~ modified. Other end of list condition~ exist such as error conditions, or other search interruption~. ~
The li~t has a specific order so that once the search proceeds through the li3t past the point at which the searched for entry ~hould reside, the search can ~top.
Likewise in the preferred embodiment, associated with the pointer TLB address in the SA TLB 2-86 is an end bit which if activated indicates to control (not shown) that the end of the li~t has been reached. The ~ontrol of the reverse translation mean~ 2-153 further monitors the status of the synonym lines found in buffers 2-07, 2-08, and the type of request generated for the address being searched in order to determine list end conditions.
Because in the preferred embodiment the list entries are aæsociated in a prescribed order, when a new translation must be added to, or an old translation deleted from, the translation means 2-152, the list searching means must search the SA ~LB 2-86 to find the proper position in the list. The proper positioning of an entry in the li~t is determined by manipulation of the pointer TLB addre~ associated with each entry in the SA TLB 2-86.
For the purposes of the description assume that a new translation, system address N, is to be added to the SA TLB
2-86. The TLB address to be a~sociated with the system address N will be determined by the hash of the address and presented to the TLB address selector 2-85 along line 2-113 from the S-unit 2-06. The entry in the list that will precede system address N in the list, the address of system address A, will need to be rewritten so that the pointer AMDHll/VBA

~ lZ1~8~

TLB address associated with system address A in the SA ~LB
2-86 will be the TLB address of the new system address N.
Likewise the pointer TL~ address to be written with system address N in the SA TLB 2-86 must be the TLB address of the entry that will follow in the list, the addre~ of sy~tem address B. The pointer TL~ address to the system address B
in the SA T~B 2-86 will reside at the entry of system address A. Thus the pointer TLB address associated with system addres~ A should be written into the SA T~B 86 along with system addre~s N in order to preserve the continuity of the list. The diagram below shows a portion of the linked list schematically before and after the addition of the translation for new sy~tem address N.

Before:-> Addr. A/Ptr B -> Addr. B/Ptr X ->

After:-> Addr. A/Ptr N -> Addr. N/Ptr B ->
Addr. B/Ptr X ->

Likewise when entries in the SA TLB 2-86 of the TLB
are to be deleted, the TLB addresfi pointer stored with the entry to be deleted, system addregs D, must be written into the pointer TLB address location stored with the preceding entry in the list, system address A. In this manner, the TLB address pointer stored with system address A after system address D has been deleted will point to the entry following system addre~s D in the list.
With reference to FIG. 4 the update ~eans for adding and deleting entries in the SA TLB 2-86 linked list and preserving the ~ntegrity of the linked list will be described. The mainstore address register 2-91 holds the system address entry to be ~dded or deleted from the SA TLB
2-86.
In the ca~e of addition to the SA TLB 2-86, the ~LB
address of the system address to be added i9 presented from the S-Unit 2-06, along line 2-113 through the pointer selector 2-124 into the TLB address register 2-87. The AMDHll/VBA

r ~A~
" ~ 1211856 ~ 24 ~
system address from the mainstore address register 2-91 will eventually be written at the TL~ address pre~ented from ~he S-Unit 2-06 when the entry is to be added to the TLB. The TLB address of the entry to be added i~ stored in one of the pointer storage registers 2-112. The linked list of the system address to be added is accessed through the list header table 2-95 and the list is searched. The search which has been started from the list header table 2-95 proceeds through each entry in the list in order. The TLB address of the first entry in the list is read from the list header table 2-95 selected around to the TEB addre~s register 2-87 and stored in one of the pointer storage registers 2-112. A compar~son of the system address in the mainstore address register 2-91 to be added to the list is made with the system address at the TLB address accessed by the list search. If the system address in the main storage address regi~ter 2-91 would reside at a position further down the list than accessed, then the search proceeds, using the pointer storage registers 2-112 to save the previous entrys' addresses. The TLB address pointer of the second entry in the list read out of the location of the fir~t entry in the list i9 then selected around to the TLB
addres~ register 2-87 and stored in the pointer storage regi~ters 2-112 while the SA TLB 2-86 is accessed to read the second system address. A comparison is made of the second system address with the system address in the mainstore addre~s register 2-91 to determine whether the search should continue. If the search has not yet reached an entry in the SA TLB 2-86 which would be at a location further down the list than the address in the mainstore address register 2-91, the search o$ the linked list proceeds, unless the end bit is encountered. The third TLB
address will be read out of the SA TLB 2-86 and accessed around to the TLB address regi~ter 2-87 where the third T~B
addre~s in the list will be ~tored in the pointer storage AMDHll/VBA

r ~ 1;~118~6 register 2-112 replacing the address of the first entry in the list, and ~o on.
Thus when the entry in the mainstore address register 2-91 $s to be added to the 11st, the pointer storage registers 2-112 will contain the ~L~ address of system address A which is the entry in the list immediately preceding in the linked list order system address N, the TL~ addre~s to sy~tem address ~ which i~ the entry following 8y8tem address N, and the TLB addres3 to the sy~tem address N which is the address in the mainstore address register 2-91 to be added to the list. Upon access to system address B, ~he control (not shown) will indicate that sy~tem addres~ N should be written in the list before it. Thus the pointer TLB address to system address B is written into the SA TLB 2-86 along with system address N at the TLB addres~ stored in the TLB pointer storage registers 2-112 for system addres~ N. Then the TLB address of the immediately preceding entry, the address of system address A, is accessed snd the pointer TLB address to the system address to be added, system addre~s N, iB written into the SA TLB 2-86 at the TLB address of the preceding entry in the list, the TLB address of system address A. The information for the VA TLB 2-83 is also written into the VA
TLB 2-83 when a new entry is added to the translation means 2-152. Therefore, when system address N i8 added to the SA
TLB 2-86, the pointer TLB address stored with system address A will direct the search to system address N.
Further, the pointer TLB address stored with ~ystem addres~
N will direct the search to system address ~. With the proper information written into the VA TLB 2-83 and SA TLB
2-86 including the updat~ng of pointer TLB addresses, the new translation is completely stored in the translation means 2-152.
For deletion of an entry, the pointer TLB address ln the entry to be deleted is simply written back to replace the pointer TLB address of the preceding entry in the list.

AMDHll/VBA
AMDH 3219 DEL/MA~

` ~ lZ1~8S6 Thi~ entry is accessed by reading the pointer for the preceding entry from the pointer storage registers 2-112 and searching the list to find the entry. The stored pointer selector 2-116 controls the operations of adding and deleting entries in the SA TLB 2-86 along with the second list 5elector 2-111.
If the system address to be added to a list in a mainstore address register 2-91 should be the first entry in the list, then the entry accessed from the list header table 2-95 will indicate to the controller that the TL~
address pointer ~n the list header table 2-95 should be replaced by the TLB address of system address in the mainstore address register 2-91 to be added to the list.
The T~B addre~ pointer to be stored with the system address to be added to the list i8 w~itten with the ~L8 addres~ pointer that had been previously in the list header table 2-95. If the first entry in the li~t is to be deleted, then the pointer TLB address from the entry acces~ed by the list header table 2-95 address is written into the list header table 2-95.
When any list search for adds, deletes, or data request is interrupted by higher priority access to the SA
TLB 2-86, euch a~ a request for move-in of data to the buffer 2-08 or the move-out of data from the buffer 2-08, the pointer selector 2-124 doe~ not select the TLB address from the second list pointer ~elector 2-111. In that case the interference register 2-114 stores the TLB address of the next TL8 addre~s to be acce~sed in a list ~earch for presentation back to the ~tored pointer ~elector 2-116 for continuat~on of the search, The use of the interference register 2-114 i~proves the linked list search~ng means by preventing duplication of effort that would be required if the search had to begin over after an interruption.
Thu~ the linked list implementation of the reverse translation means shortens the length of the average search of the SA TLB 2-86 so that a search for synonym pages may AMDHll/VBA

83/08~27 - ~ 12118~6 _ 27 -be accomplished more quickly. ~hu~ it can be seen that the reverse translation means of the p~esent invention provides a means for a~suring that the data delivered at a requested virtual addre~s 2-76 represents the mo~t up-to-date version of the line of data when the data may exist in other storage units in a modified form.
An additional benefit of the preferred embodiment arises ~rom the performance of reverse translation and linked list searching along page boundaries. Some operations of a data proces~ing machine require access to all lines of data with a secondary storage unit which corre~pond to a given page in the primary storage un$t.
With the page table storage means of the preferred e~bodiment, page translations may be quickly accessed in the translation lookaside buffer ~VA TLB 2-83 and SA TI.B
2-86).
A number of operation~ ~re performed along page boundaries (se~ M System 370 Principle~ of Operation, Id.~ An example which demonstrates the preferred embodiment of the pre~ent invention i~ the key update operation. Pages of data are stored in the mainstore 2-03 along with a code called a key which is u~ed to control access to the page of data in the mainstore 2-03. In the preferred embodiment of the present invention when a line from a page i8 wrltten into the bu f fer~ 2-07, 2-08, the key or the p~ge i~ stored in the TLL.
Thus in the preferred embodiment, when a key for a page must be updated, the page information o~ all synonym page~ in the TLB must be accessed 80 the key may also be updated. The reverse translation means 2-153 i8 used to generate TL~ addresses for all pages having the key updated. Control allows access to the VA TLB 2-33 and SA
~LB 2-86 through the tag-2 2-99 for performance of the key update while ignoring line address information from the tag-2 2-99 and the buffers 2-07, 2-08. In thi~ manner, all the entries in the TLL need not be searched for operations AMDHll/VnA
AMDH 3219 DEL~MAH

`` ~Zl;1856 on page boundaries, ~uch key update operat~ons, becau~e the l~n~ed list ~earching means of the present invention allow~
acces~ only to the needed ~ynonym page entr~e~.

While the invention ha~ been particularly ~hown and de~cribed with reference to the preferred embodiment~
thereof, it will be understood by tho~e ~killed in the art that variou~ change~ in form and in detail may be made therein without departing from the spirit and wope of the invention,

Claims (17)

Claims:

1. In a data processing machine, an apparatus for storing data, comprising:
a primary storage means for storing data;
primary addressing means for uniquely addressing said data with unique primary addresses;
secondary storage means for storing date in communication with said primary storage means so that data may be transferred between said primary storage means and said secondary storage means, secondary addressing means for addressing said secondary storage means with secondary addresses;
forward translation means for translating said secondary addresses to said unique primary addresses to uniquely address said data; and reverse translation means for translating said unique primary addresses to synonym secondary addresses which translate to said unique primary addresses.

2. The apparatus of claim 1, wherein:
said primary addresses includes page addresses;
and said primary addressing means addresses said primary storage means by page addresses;
said forward translation means translates said secondary addresses to said unique primary addresses on page boundaries; and said reverse translation means translates each said unique page primary address to secondary page addresses.

3. The apparatus of claim 1, wherein:
said primary addresses include page addresses;
page table storage means for storing the translation of said secondary addresses to said page address; and said reverse translation means includes page table search means for searching said page table storage means for said synonym secondary addresses along page boundaries.

4. The apparatus of claim 3, wherein:
said reverse translation means further includes list means for associating groups of said page addresses in said page table storage means; and said page table search means includes list search means for limiting said page table search to said page addresses associated by said list means.

5. The apparatus of claim 3, wherein:
said secondary storage means stores line of data; and said page table storage means is associated with each line of data in said secondary storage means.

6. The apparatus of claim 3, wherein:
said reverse translation means includes page addressing means for accessing lines of data in said secondary storage means which translate to a selected primary page address.

7. The apparatus of claim 2 wherein:
said reverse translation means further includes list means for associating groups of said page addresses in said page table storage means; and said reverse translation means includes list search means for searching for said page addresses associated by said list means.

8. The apparatus of claim 2, wherein:
said primary addresses include page and line addresses;
said forward translation means includes line table storage means for storing the translation of said secondary addresses to said line addresses; and page table storage means for storing the translation of said secondary addresses to said page address; and said reverse translation means includes page table search means for searching said page table storage means for said synonym secondary addresses along page boundaries; and line table search means for searching said line table storage means for said synonyms secondary addresses along line boundaries.

9. The apparatus of claim 1, wherein:
said primary addresses include page and line, and byte addresses; and said reverse translation means includes a page table storage means for storing translations to a primary page address for each said secondary addresses that address data in said secondary storage means.

10. The apparatus of claim 1, wherein:
said secondary storage means includes a plurality of fast access storage units.

11. The apparatus of claim 9, further including:
a tag field associated with said secondary storage means for identifying the entries in said page table storage means which store the primary page address of the data line in said secondary storage means; and said reverse translation means includes tag search means for searching said tag field to detect said secondary addresses which translate to a chosen one of said primary page addresses.

12. The apparatus of claim 9, further including:
a tag field associated with said secondary storage means for identifying the entries in said page table storage means which store the primary page address of the data lines in said secondary means; and said reverse translation means includes a duplicate tag storage means for storing a duplicate of said tag field for access by said reverse translation means; and tag search means for searching said duplicate tag storage means to detect said secondary addresses which translate to a chosen one of said primary page addresses.

13. The apparatus of claim 1, wherein:
said secondary storage means is a fast access buffer storage unit; and said primary storage means is a large capacity mainstore.

14. The apparatus of claim 1, further including:
first tag storage means for storing a tag field associated with said secondary storage means for identifying primary page addresses of data in said secondary means; and said reverse translation means further including second tag storage means for storing a duplicate of said tag field in said first tag storage means whereby said second tag storage means can be searched in the background without interfering with the operation of said first tag storage means.

15. The apparatus of claim 1, further including:
a tag field associated with said secondary storage means for identifying entries in said secondary storage means; and said reverse translation means includes tag search means for searching said tag field to detect secondary addresses which translate to said primary addresses.

16. The apparatus of claim 15, wherein:
said secondary storage means includes two or more buffers each having entries identified by said tag field.

17. The apparatus of claim 15, wherein:
said buffers include an instruction fetch buffer and include an operand fetch buffer.