CA1216958A

CA1216958A - Voice/text storage and retrieval system

Info

Publication number: CA1216958A
Application number: CA000467931A
Authority: CA
Inventors: Donatas V. Gasiunas; G. Burnell Hohl
Original assignee: Pitney Bowes Inc
Current assignee: Pitney Bowes Inc
Priority date: 1983-11-25
Filing date: 1984-11-15
Publication date: 1987-01-20
Also published as: GB2150326B; US4523055A; GB8429478D0; GB2150326A

Abstract

VOICE/TEXT STORAGE AND RETRIEVAL SYSTEM
ABSTRACT OF THE DISCLOSURE
A Voice/Text Storage System is disclosed. The system provides for the storage of digital data and digitized voice signals and is particularly suited for applications such as voice mail and voice annotation of text. The system includes a first bus operatively connecting a storage/network processor which controls access to a mass storage device, a host processor which provides overall control for the system and a communications processor. All processors have private memories connected to the processor CPU's directly so that the processors may continue to operate when the first bus is busy. The system also includes a second bus operatively connecting the storage/network processor, a voice transfer control unit, a buffer and voice transfer unit for receiving, digitizing and storing voice signals received over a plurality of telephone lines. The voice transfer unit also includes a switch and data carrier detection apparatus for selectively connecting digital data signals transmitted over the telephone lines to the communications processor.

Description

VOICE/TEXT sr_~ G~ AND RETRIEVAL SYSTEM

BACKGROUND OF Ti~E INVENTION
This invention relates to a data proeessing system and more pnrtieulnrly to a system partieularly adopted to store, process and distribute digital datn includlng both textual data and digitized voice signals, Sueh systems should be eapable of handling n multiplicity of voice inputs and outputs, prefernbly over telephone lines, and have a cnpncily for storing n substantinl qunntity of digitized voice signnls.
Further, such a system should hnve the enpaeity for correlntlng such stored voice signnls with digital aignals representing textual dntn and eommands so that functions such as "voice maiJ", i.e., storing and forwarding voice messnges, eentralized dietation Hnd "voice annotation of text", i.e., eorrelated storage of verbal eomments and eorreetions with storcd textual material, so that word processing operntor mny updnte the text from voice.
While systems whlch hnve some integrnted cnpacity for hnndling both voice signals and textual data nre known, none have as yet provided the full rmlge of voice functions described nbove in a mnnner which is eompntible and rendily intergratnble with eonventional locai dntn processing networks. A particulnr problem has been that the high datn rates necessary to handle multiple simultaneous digitized voiee signAls ereate a need for a multiple proeessor nrehiteeture, while the need for complex and frequent eommunieatlons between processors, required to maintnin eoordination between various tasks involving both digitized voice signals and textual data, tended to place a large communications burden on each processor and so reduee its effeetive eomputing power. Even in systems where u separate busses were provided ior voiee data nnd digital ,, ~

datu use of the digital d~ta bus for interprocessor communications 5tili significsntly reduced effective processing power.
In other systems where memory and processors shQred the same bus, access by one processor to memory would necessarily in~errupt the operations of other processors requiring access to memory, while other srchitectures where each processor had oniy private memory and the bus carried only 1/0 communications between processors were too slow when blocks of dAta had to be transferred between processor memories.
Further prior art bus structures were normally adapted for a pRrticular processor or family of processors and choice of a bus structure tended to limit Q system and further developments of thRt system to a particular family of processors.
Thus, it is an object of the subject Invention to provide r~ data processing system having the capability to receive, store, process and transmit digital data were 8uch dQta m~y be elther textuAI datQ or dlgitized voice signals.
It is a further object of the 9ubject Invention to provlde such a system where digitQI datR nnd digitized voice signQls may be stored in a correlaled manner so as to provide for functions such as voice Qnnotation of text.
It is aiso an object of the subject invention to provide such a system using R multiprocessor architecture where the interprocessor communications burden is substantially reduced.

~F THE INVENTION
The above objects are Qchieved and the disndvantages of the prior art are overcome by a Voice/Text Storage and Retrieval Appnratus ~iL~ 5~

which inciudes a digital m~ss storage device for storuge and retrievQI Or digital dntfl nnd digitized voice signRI data, D first processor unit for controiling access to the mass storage device, a host processor unit for monitoring, coordinnting and supervising the over~ll oper~tion of the epparatus, a communications processor unit for reception Dnd retransmission of digitnl d~ts, r~nd an interface for receiving and retransmitting digital data and nnQlog voice signais. The interface includes detection circuitry for detecting the presence Or digital data signals und switch circuitry controlied by the detection circuitry to separDte the digital data sign~ls from the annlog voice signals and to route the digital datu signals to the communications processor unit for transmission and reception, The appAratus Also includes a converter which is connected to the switch circuitry so that the nnalog voice signals are routed to Jt for reception and trAnsmission. The converter digitizes received analog voice signals and gener~tes anfllog voice sigrlals to be transmitted from a digit~l input. Still further, the subject apparetus includes, D buffer for buffering the flow of data to and from the converter, voice trQnsfer conttol circuitry for controlling the transfer between the buffer and the converter; for signalling the host processor unit when n block of digitized voice signnl data must be trnnsmitted between the buffer and the mass storage device and for controlling that block transfer in response to signals from the first processor unit, a first bus interoonnecting the first processor unit; the communicntions processor unit and the host processor unit so that digitnl dDta may be transferred between the comrnunications processor unit and the mass storage device under control Or the first processor unit ~nd in response to commDnds from the host processor unit, ~nd ~ second bus interconnecting the first ,, . . .. _ . .. . .. . _ _ .. . . .. . , . . . . . .. _ processor unit; the voice trnnsfer control circuitry; the buffer and the conversion means, so thnt digitized voice signal duta may be trnnsferred between the converter and so that the buffer under control of said voice transfer control circuitry ~nd blocks of digiti~e voice signal data may be trnnsferred between the mass storage device and the buffer under control of the voice transfer control circuitry and the first processor unit. The first bus is also connected to the voice transfer control cirauitry so that the host processor unit may initiate transfer of digiti~ed voice data signal transfers to and from the converter.
In a preferred embodiment the interfnce comprises a plurality of interface units each operatively connected to an associated telephone line to recelve and transmit both voice and datQ signals. (As used hereinbfter, the term "telephone line" is intended to include two wire lines from the switched telephone network, four wire private lines leased from telephone companies, privately installed lines such as those used for centrai dictation systems, and the like. Except ior well understood differences in the anaiog circuitry needed to make connectlon to the line, such lines perform essentially the sQme function in the snme WQy and a more detailed description of their operation Is not necessary for an understnnding of the subject invention.~
In nnother preferred embodiment the converter comprises a plur~lity of converter units each operatively connected to switch circuity comprised in an associQted Interface unit for the reception and transmission of voice signals over the nssociQted telephone line.
The ~bove objects may aiso be achieved and the above disadvantQges also overcome in accordance with the subject invention by means of a voice/text storage and retrleval apparatus comprising a mass - s -storage device for storage and retrievAI of boti) digital dnta and digitized voice signal dnta, communicatlons flnd control circuitry for the generation and trflnsfer of digltMI command and data siKnals, voice transfer circuitry for converting voice slgnals between digltal flnd flnfllog form and for transferring said voice signais to and from said mass storage means, en interfsce for interfacing a plurality of sienal lines to the apparatus, the lines having the cflpability of transmitting both analog voice signals and serial digital data signals and the interface including detection circuitry and switch circuitry for separately routing the annlog voice signals and digital dnta signals, ~nd the voice/text apparatus further including a storage/network processor unit for controlling access to sl~id mass storage device.
The communications and control circuitry and the voice transfer circuitry eflch include sepnrate buses operatively connected to the storage/network processor unit for the transmission of digital command and dsta signals and of digitized voice signal data, respectively. Command signals for the overall control of the sppRrAtus are genernted by a host processor unit operatively connected to the communications and control bus and digital data signQls are transferred between the interface and the storage/network processor unit by a communlcations processor unit operatively connected to the communicfltions and control bus, flnd which includes serial signfll lines operatively connected to the switch circuitry of the interface for the receiption and transmlssion of serial digital data signals.
In fl preferred embodiment the storage/network processor unit further includes, a central processing unit having a private memory, flrst direct memory access device operatively connecting said storage/network processor unit to the communications and c~ontrol bus, a second direct memory access device connect1ng snid storuge/network processor unit to the voice bus, and stnrsee/network switch circuitry, controlled by the central processillg unit, for connecting the first direct memory sccess device to the private memory, whereby the command signals may be transmitted between the central processing unit and the host processor unit, and for connecting either the first or second direct memory access device to the mass storage device, whereby either digital data or digitized voice signals may be stored on snd retrieved from the mass storage device.
In another preferred embodiment the voico trr,nsfer circuitry Is operatively connected to the communioations and control bus and the voice transfer circuitry responds to command sigmlls from the host processor unit to activate nnd de-nctivate communications with particulnr signal lines nnd to determine the direction of voice signnl flow between the npparatus and particulnr ones of the signal lines nnd to selectivoly access segments of digitized volce data stored in the buffer for the creation of concalenated voice prompting messages.
In another preferred embodiment the host processing unit and the communications processing unit communicate by transi`erring n block of data over the communicntions nnd control bus to the storage/network private memory for retransmittai by the stornge/network processor unit to the other processing unit.
Thus, it may be seen thnt the subject invention ndvnntngeously provides an npparatus useful for the stornge of both digital data and digitized voice signal data in a common mass storage device.

, . _ . _, ,, ., .. . , . , . ... , .. _ .. . .. . .

~l6~

It i9 Rnother advantnge of the subject invention that the apparnlus provides for the resolution of aonflicts for access to the mass storage device and for the corre]ated storaee of digital data nnd relnted digitized voice signal datn by a means of a processor unit which controls access to the mMss storage device, so thnt a single processor mMy maintaln a data base describing storage ~Ltlocation on the mass storage device.
it is another advantage of the subject invention that the appnr~tus provides for receipt and transmission of bolh digital data and voice signMls over common signal line, svhich is preferably n telephone line.
It is still ~nother advantMge of the subject invention thnt the appnratus provides a multiprocessor ~rchitecture suitable for use with a variety of microprocessor types on a common bus, and wherein interprocessor communications Mre aLt routed through and controlled by one particulnr processor.
Other objects and advantages of the subject invention will be apparent to those skilled in the nrt îrom considerntion of the detailed description set forth below and of the attached drawings.

- B -Figure 1 is a schemnlic block dillgram of a voice/text storage and retrieval apparatus in accordnnce with the subject invention.
Figure 2 Is a more detailed schemlltic block diRgram of the Storage/Network Processor of the subject npparatus.
Figure 3 is s more detailed schem~tic block diErgr~m of a typical Host, Auxillary Host or Communicfltions Processor of the subject Invention.
Figure 4 is a diagram of the structure of the bus connecting tlle Storage/Network Processor the Rost Processor and the Voice Transfer Controller.
Figure 5 is a schematic block diagram showing the structure of the bus connecting the Voice Transfer Controller, the Voice Buffer Memory and the Voice Digitizer Generator.
Figure 6 i9 ~I more detQiled schematlc b;ock diagram of a typical Telephone Interface.
Figure 7 Is a more detailed schematlc block dlagr~m of a typical Voice Digitizer/Generator.
Figure 8 Is a more detslled schemstic block di~lgram of the Voice Transfer ControIier.
DETAlLeD DESCltlPTlON OF A PREFERRED
.
EMBODIMENT OF TIIE INVENTlOiN
Figure 1 shows a schematic block diagram of a datM processing system in accordance with the subject invention, R system particularly adapted for the storage, retrieval and processing of both text and digitized voice signais. The system comprises Storage/Network Processor 100 which is operatively connected to Host Bus 10 and Yoice Bus 20 for ~6~

the transmission and reception of digitnl dntn, Including textual dQtQ, nnd digitized voice signals. Also operatively connected to Stornge/Network Processor 100 Hre Q Hnrd Disk Controller 500, controlling one or more Winchester Disk Drives 502 and a ~loppy Disk Controller 520, controlling a Floppy Disk Drive 522. Optionally StorQge/Network Processor 100 msy nlso include a commun;cations port ior interconnection with 8 High Speed Network Interface 540, which may control Q number of Intelligent Secretarinl Work Stations 542 Hnd Printers and other high speed ievices 544, and a bnck-up device port for interconnection to a Tape Controller SS0 which controls Tape Drive 562.
Also operatively connected to Host Bus 10 are Communications Processor 250 and Host Processor 200. Optionnlly ndditional Auxiliary Host Processors 210 Hnd 220 may also be connected to Host Bus 10. In the embodiment described below provision is mnde for a total of up to sixteen (16~ host processors to be connected to Host Bus 10.
Operntively connected to Voice 8us 20 are Voice TrQnsfer Controlier 300, Voice Buffer Memory 320 and H number of Voice Digitizer/Generator Circuits 340, esch operatively connected to one of Telephone Interfaces 400. Provision is made for up to 32 telephone lines in the embodiment described below.
Telephone Interfaces 400 Hre capable of handling both voice and digitai dflta nnd transmit digitai data to Communications Processor 250 through dedicated asynchronous ports 256, using a standard interface such as the RS232 interface. Note that unused ports can be connected to devices such as Dumb Terminals 252 and Printers 254 to provide an alternative menns for input or output of textual data to or from the system.

.. ..... . . . .. . .. .

,r~

Telephone Interfaces 400 flre essentially standard modems with the ndditional cspability to switch the signal to Voice Digitizer/Generstor when it recognizes a voice signal, i.e., detects the absence of a cnrrier.
Their design and construction would be readily apparent to a person skilled in the art and need not be discussed further here for an understsnding of the subJect invention.
Storage/Network Processor 100 provides and controls three major data paths as well as others less often used, or optional, data paths. The first major data palh uses Host Bus 10 to transfer data between the memory of Storage Network/Processor lO0 arld the memories of any Host Processors 200, 210, 220, etc. or the memory of Communications Processor 250. (It is s feature of the subject invention that this data path provides the only method of interprocessor communications in the system.) The second main dnta path uses Host 8us 10 to transfer data between Winchester Disks 502 and Host Processor aoo. This data path QllOwS Host Processor 200 to operate on digital data stored on Winchester Disks 502 under control of an applications program stored in Host Processor 200.
The third major dats pflth uses Yoice 8us 20 to transfer digitized voice data between Winchester Disks 502 and Voice Buffer Memory 320. This data path flllows voice signals to be stored on and retr3eved from Winchester Disk 502.
A less frequently used data path is provided for transferring digital data between Flopw Disk 522 Rnd the memory of Storage Network Processor 100. This data path may be used for loading programs or other data into the system from a portable medium, i.e., floppy disks.
The data paths provided for optional High Speed Network Interface 540 and 8ack-up T~pe Controller 560 are essentially ~L~

conventionAI and are not necessary for rn understanding of the clslmed invention and so will not be described further here. Similarly, the connection of Dumb Terminals 252 and Printers 254 through Asynchronous Ports 256 are conventionnl and a further description of their operation is unnecessary to an understanding of the clalmed invention ~nd so wili not be discussed further here.

Storage/Network Processor Figure 2 shows a more detailed schematic block diagram of Storage/Network Processor 100 which comprises a central processing unit (CPU) 102, having an I/O Port 102a for communications with external devices. Operatively connected to CPU 102 is a Private Memory 104, including ~ direct memory access (DMA) port 104a, for storing data llnd program instructions for processing by CPU 102. Data may be transferred to and from memory 104 through locai DMA controlier 110a. (Because of the heavy processing load on Stornge/Network Processor 100 a powerful microprocessor, such as Q Motorola 68000 model microprocessor is preferred for use as CPU 102.) Two registers, 106a and 106b are operatively connected to l/O
port 102a and to the ]/O read, i/O write, B low order word address lines and 8 data lines Or the Host Bus for l/O communications bet.veen Storage/Network Processor nnd Host Processor 200, Communications Processor 250 ~nd optionai Auxiliary Host Processors 210, 220, etc., as wili be described further below.
Storage/Network Processot 100 is operatively connected to Host Bus 10 for memory-to-memory transfer through Host DMA Controller 110.
DMA Controller 110 is connected to the DMA memory read, DMA memory .. _ . . .. . ..

write, 20 word nddress lines, 4 processor lines, address lines, and 8 data lines of Host Hus 10. DMA controller 110 provides a dntQ output to Switch Logics 114 and 116 which mny route the data flow from DMA
controller 110 either to conventionlll disk controllers (either ilard Disk Controlier 500 or Floppy Disk Controller 520~ or to Private Memory 104 through IOCQI DMA controller llOa, as will be more fuDy described below.
DMA controLier 110 is operatively connected to l/O port 102Q
through the internal l/O Bus. Address boundaries and word counts nre initialized in DMA controlier 110 by l/O commnnds from CPU 102.
In the embodiment shown, timing and control circuitry for Host DMA 110 and LOCQI DMA IlOa are shared and incorporated in host DMA
110 for design convenience.
Storage/Network Processor 100 is operatively connected to Voice Bus 20 through Voice DMA Controller 112. Voice DMA Controller 112 is connected to the DMA reQd, DMA write, 5 ChQnnel Address lines, B Volae DatQ Lines and the Cycle Control Line of Voice 8us 20 to provide Q d~ta path for digitized voice data to Hard Disk Controller 500. Voice DMA
Controller 12 provides nn eight bit dQta path to switch logic 114 to provide fl data path to Hard Disk Controller 500, as described further below.
Voice DMA Controller 112 Is operatively connected to l/O port 102a through the internal l/O Bus. Address boundaries and word counts are initialized by l/O commands from CPU 102.
As described above LOCQj DMA Controller llOa controls DMA
port 104a. It is operatively connected to l/O port 102a through the Internal l/O Bus. Address boundar,es and word counts are initialized for Local DMA IIOa by l/O commands from CPU 102.

3~

The above DMA Controllers are interconnected to each other snd to disk controllers 500 and 520 by Switch Logics 114 and 116, esch of which establishes one of two dAta paths. Logic 114 either establishes a data pllth between Voloe DMA Controller 112 Qnd hard Disk Controller 500 or it establishes a path between host DMA 110 and Disk Controllers 500 and 520. Thus, the Storage/Network Processor 100 allows either the transfer of digital dstQ between host computer private memories and the disks or the transfer of digitized voice data between Voice Dl~qA 112 and the hard disk, under control of CPU 102, through switch logic 114.
normally such transfers would consist of the transfer of voice and text dnla to the hQrd disk, though datQ transfers between the floppy disk and Host Processor 200's private memory, or the privste memories of Auxiliary Host Processors 210, 221, etc. may be used, for example, for loading initial programs into these processors.
Switch Logic 116 either establishes a data path between Host DMA Controller 110 and Local DMA Controller 11OQ or est~blishes a path between Disk Controllers 500 nnd 520 and LOOQI DMA Controller 110.
The first path allows memory-to-memory communication between Storage/Network processor 100 and Host Processor 200 as described further below while the second would typically be used to initially load Private Memory 104 with the operating system for Storage/Network Processor 200.
Switch Logics 114 and 116 are both operatively cormected to l/O
port 102a through the Internal l/O Bus Qnd data paths are established by l/O commands from CPU 102.
Though many methods for implementing Switching Logics 114 and 115 would be appQrent to Q person skilled in the art a preferred method makes use of tri-stRte buffers coupled to busses to form the dats puths.
~Tri-state devices are digitQl circuits which, in eddition to normul ~D" und "I" output vulues in uccordance with the digital input value, huve u third state, entered in accordRnce with the state of un enable/disable input, where a high impedancc is coupled into the output of the device, effectively removing the device from a circuit,) In the Storage/Network Processor of Figure 2, 8 sets of buffers ure used. Voice-Disk buffers carry signuls from Voice DMA Controller 112 to Disk Controllers 500 and 520; Host-Disk buffers cRrry sisnals from ilost DMA Controller 110 to Disk controller 500 und 520 and Local-Disk buffers curry signuls from Locul DMA Controller 110a to Disk Controllers 500 und 520. Disk-Voice, Disk-Host and Disk LOCDI buffers curry the corresponding signals in the opposite direction. PinaUy, the Host-Local and Locul-Host buffers curry signals between Host DMA Controller 110 and LOCQI DMA ControUer 110a.
Tuble 1 below shows the enable/disable (E/D) state of the drivers for vsrious path conditions:

T A B L E I

2 3 -Voice-Disk E D D
Host-Disk D E D
Locul-Djsk D D
Disk-Voice E D D
Disk-ilost D E D
Disk-Loc~i D D E
Host-Locel X D D
Locul-ilost X D D

.. , . . . ~

Column I shows the conditions for establlshing the Volce-Disk dat~ pnth, Notc that the Host-Locnl data peth is independent of the Voice-Disk path l~nd may be used simultaneously with the Volce-Disk pnth.
Column two shows the Host-Disk path conditions nnd Column three shows the Locai-Disk pRth conditions.
Those skilled in the art wiii recognize that the above switching scheme mny readily be used with bi-directional lines by combining rend/write signQls with the switching state established by CPU 102 so that only buffers in one direction are enabled at any instunt.
Bus arbitration logic 122 is operntively connected to and controiled by Host DhiA Controller 110. When Host DMA 110 receives a Bus Request from Host Processor 100, or Auxiliary Host Processors 210, 220, etc., requesting that thnt processor be aliowed to control llost Bus 10, if Host DMA Controller does not wish to control 8us 10 it releases Bus Arbitration Logic 122. When Logic 122 sees that the bus is not busy it generntes n Bus Grsnt Out sign~l which Is used, as described further below, to determine priority between competing host processors. When one of the Host Processors 200, 210, 220, etc" or Communication Processor 250, which is requesting Host Bus 10, receives the Bus Grant Out signal it returns a Bus Acknowlege signal to Bus Arbitration Logic 122, which clears the Bus Grnnt Out signai in response.
Storage/Network Processor 100 Mlso includes Interrupt Logic 120 which provides nn interrupt on one of the S Interrupt lines of Host Bus 10, a reset signnl and a 4 bit processor address to select one of Host Processors 200, 210, 220, etc. In(errupt Logic 120 is operatively connected to l/O port 102r, through the Internal l/O Bus and interrupt and reset signals are generated in response to l/O commands from CPU 102.

~iost nnd Communications Processors Figure 3 shows ~ more detailed schematic block diagram of Host Processor 2D0 (or of AuxilHIry Host Processors 210, 220, etc.) and of Communications Processor 250.
Host Processor 200 is based on any of several commercislly Hvrilabie microprocessors 202. As noted sbove it is sn sdvsntsge of the subject invention th~t the ~rchitecture is not processor dependent and wil3 support any microprocessor as CPU so long as that processor supports a private rsndom access memory (RAM) hsving a DMA port and sn l/O port.
Preferably the chosen microprocessor would hsve an interrupt capability.
Private memory 204 is direcLly accessable to CPU 202 in ~
conventionsl manner, which depends on the selection of microprocessor made, and includcs DMA port 204A which is operatively connected to Host Bus 10.
The l/O port of CPU 202 is slso connected to Host Bus 10, providine the cspability for l/O tr~nsfers of 8 dntn bits on the dntn lines sddressed in 0ccordance wlth the low order 8 address bits: and, for Communlcatlons Processor 260, the l/O port of CPU 202 is also connected to Communicrtion Ports and MU~ 212, providing the capabillty ~or dsts transfers over Q plurRlity of serial communications lines.
Bus arbitration logic 206 i9 operatively connected to CPU 202 to provide a means whereby CPU 202 may gain control of Host ~us 10. In response to a request from CPU 202 logic 206 will assert a Bus Request signal on Host Bus 10. The Bus Request signsl is received by Host DMA

t~

Controller llO. If Controller 110 is not using, or when it i9 fini3hed using, Host Bus 10 it signals bus arbitration logic 122 which In turn flsserts Bus Grant Out. The Bus Grant slgnal line on Host Bus lD is daisy-chnined through the bus arbitration logic of each processor on Host Bus 10. When Bus Arbitration Logic 206 receives Bus Grant In, it returns n Bus Grant Acknowledge li3ACK) signal. (If Logic 206 had not been requesting the bus it would have passed on the Bus Grant to the next device on its Bus Grant out line.) When Logic 206 then sees thut the Bus i3usy signnl is not asserted! indicating the bus is free, it asserts Bus i3usy, capturing the bus and signals CPU 202 that it may make an l/O
transfer on Host Bus 10. When CPU 202 is finished it signals logic 206 which then removes Bus Busy, freeing the bus.
Interrupt/Reset Logic 208 responds to B levels of prioritized, addressed interrupt signals and an addressed reset signal generated by Storage/Network Processor Interrupt Logic 120 to interrupt or reset CPU
202. Interrupts are acknowledged on receipt by an Interrupt Acknowledge (INTER ACK) signai Hnd Interrupt Logic 208 includes storage so that lower priority interrupts may be held until they cnn be processed.
Communications Processor 250 is dedicated to handling low speed data communications, either from telephone interfaces 400 or terminnls 252 and printers 254. It differs from Host Processor 200 only in the sdditionlll Communicstions Ports and Multiplexer 212 comprising conventional asynchronous dats ports, such as RS 232 ports, and a multiplexer interconnecting the data ports and the l/O port of CPU 202.
Those skiLied in the art wiii recognize that the detailed design of the nbove described Host Processor 200, and other processors, is r~

~ 18 -conventionAI and well within the ordinary skill, and that the design wili vary depending on the particular microprocessor chosen.

STORAGE NETWORK/HOST MEMORY-TO-MEMORY DATA TRANSFERS
tUnless otherwise noted references to llost Processor 200 ~tso apply to Auxillary Processor 210, 220, etc. and Communicutions Processor 250.) Figure 4 shows the details of Host Bus 10 used for memory to memory-to-memory transfer. ilost Bus 10 comprises:
B bi-directional data lines, for the transfer of datn.
g processor address lines, which are asserted by Storage/Network Processor 100 to identify the addressed llost Processom 20 byte address lines, the low order 8 of which are bi-directional and may be used by the Host Processor 200 for l/O
transfers and the high order 12 of which are asserted oniy by Storage/Network Processor 100, in conJunction with the low order 8, to define the byte address.
A bus grant in/out line, which, in contrast to the other lines, is not connected Jn paralJel but is connected sequentially to the bus arbitration logic of each processor operatively connected to Host i3us 10. A bus grant out signal is generated by the bus arbitration logic of a processor, and becomes the bus grant in of the next processor on the bus, when a bus grant in signal Is recoived from the procedln~ processor ~nd the recelvlng processor _, .. . . . ..

6~

is not requesllng the bus, ~The Inillal bus grant out signal i9 generated by 13u5 Arbitration Logic 122 in response to a bus request signMI gcnerated by e processor which wants control of the bus.) A bi-directional bus busy signal which Js assQrted by any device which is using the bus.
A DMA memory read strobe, which is asserted by Storage/Network Processor 100 when a byte is read from a Private Memory 204.
A DMA memory write strobe, which is asserted by Storage/Network Processor 100 when writing n byte to a PriYate Memory 204.
An l/O read strobe which is esserted by Host processor 200 when it wishes to read a byte in through l/O Port 200-1.
An l/O write strobe which is asserted by Host Processor 200 when it wishes to write a byte through l/O Port 200-1.
8 priority interrupt lines which may be asserted by Storage/Network Processor 100 to interrupt Host Processor 20i).
An interrupt acknowledge line which is asserted by Host Processor 200 to acknowledge receipt oi! an interrupt.
An addressed reset line which is asserted to reset selected processors.
A bus request line which may be asserted by any processor to request control of Host ~us 10.
A bus acknowledge signal which is asserted by any processor to acknowledge receipt of bus control.

, . . , . _ . _, _ ... . .. . _ ., . _ .. . .. . _ ~

Two clocks which are used us system clocks nnd distributed on the bus as a mntter of design convenience. (note that trnnsRctions on Host Bus 10 nre nsynchronous.) For n datn transfer from the Storaee/Network processor 100 to Host Processor 200 Storage/Network CPU 102 sets up the dntn to be trnnsferred ns a block in Privnte Memory 104 nnd initinlizes Host DMA
Controtier 110, Switch Logic 11S and Local DMA Controller 110a for a Stornge/Network to Host datn transfer. Host DMA Controller 110, which has the highest priority for Host Bus 10, then takes control of Host Bus 10 and trnnsfers the dntn into R preselected region of Privnte Memory 204. Host DMA Controller llû then trnnsfers a second block deta, elso set up by CPU 102, to a particular region oi Private Memory 204; the second block containing the necessnry Information defining the location, size and iormat of the first block.
When the transfer is finished, Controller 110 signals CPU 102 which in turn signals Interrupt Logic 120 to address llost Processor 200 on the 4 processor address lines on Host i-3us 10 and assert one of the B
levels of interrupts. In response to the interrupt Host Processor 200 will access and process the data in the first block in accordAnce with the information in the second block stored in the particular region oi Memory 204.
For a dnta trensfer from Host Processor 200 to Storage/Network processor 100, Host CPU 202 sets up the dntn to be transferred ns n block in Host Privnte Memory 204 nnd sets up n second block of dnta contnining the necessary locational, iength nnd formatting information for the first block in n particular region of Memory 10~. CPU 202 then slgnals Bus Arbitration Logic aoB to request control of Host Bu~ 10 ns described nbove. When It gnins control of Host Bus 10 CPU 202 executes nn l/O rend operntion to Stornge/Network Communcntions Stntus Reg;ster 106R to determine if CommunicRtions Address Register 106b is cle~r. If Register 106b is clenr logic nssocinted with l~egister ID6n sets thnt register to show Register lD6b busy 60 thnt no other processor mny nccess Reglster 106n nnd Host Processor 200 writes its Qddress into Register 106b nnd relenses Host 8us 10. (If Host Processor 200 finds Register 106b busy it relenses the bus to avoid locking up the system and then retries.) Periodicnlly, under its own control progrnm, Stornge/Network Prooessoi 100, rends Reglster 106b and sels CommunicRtions Register 106n to clenr stntus. It then sets up A dntR p~th from Host Processor 200 to Privnte Memory 104 exnctly, except for the direction Or d~sts flow, ns described above Qnd Host DMA Controller 110 trnnsfers the dutn block stored in n pnrticulnr region of Memory ao4 ~nd contnining the location, size and formnt informntion to Priv~te lUiemory 104. CPU 102 uses this informntion to reinitinlize ilost DMA controller 110 ~nd trnnsfer the dnts block to Memory 104 for processing.
In response to such a memory to memory dntR trnnsfer Stornge/Network Processor 100 may establish R Host-Disk datn pnth as described nbove nnd set up Host CMA Controller 110 to trnnsfer n block of dntR, described in the messnge from PrivQte Memory 204, to Disks 500.
Conversely, Stornge/i-~etwork Processor 100 mny establish a Disk-Host dst~
path, set up Host DMA Controller llû und transfer n block of DatR from Disk 500 to Host Private Memory 204. StorAge/Network Processor may then initinte n memory to memory trnnsfer to Host Processor 200 to signnl . _ _ . . . . . .

thut such a trnnsfer hus been made nnd to provide other ;nformutlcn needed by Host Processor 200 to proeess the duta trQnsferred.
Communicstions between Host Processor 200 nnd, for example, Communications Processor 250 flre carried out by trunsrnitting u messuge to Storage/Network proeessor 100 for retransmission to u designuted recipient on Host Bus 10.
Other bus structures ure uiso within the contemplation of the subject ivention. Thus, in unother embodiment of the subject invention Host Bus 10 muy not include address lines and datu may be trunsferred between the vurious processors in the form of sddressed dutrl puckets using techniques similur lo those used for interproeessor communic~tions in Locel Areu Networks. Such a bus structure would be udvnntugeous in that it would simplify eonnection of the system of the present invention to u Local Area Network.

Voice Bus and Associuted Subsystems Pigure 5 shows a more detuiled schematic block diugrum of Yoice i3us 20 und its ussociuted subsystems. Up to 32 chunnels of voiee signuls cun be coupled to Voice Bus 20 through Telehone Interfllces 400, nnd Voice Digitizers/Generators 340. Sepnrate Telephone Interfuces 400 ure provided for each telephone line connected to the system as shown in Figure 6. Fuch InterfAce 4i00, us shown in Figure 6, is primarily made up of A coventionai Modem 410 which interfuces the telephone lines to the usynchronous ports of Communlcations Controller 250, conYentional Currier Deteetion Circuitry 420a und u switoh 43Uu, controlled by Circuitry 420a which connects the telephone aignnl input to Digitizers/Generutors 340 in the absenee of Q duta currier for voice trunsmission onto Voice Bus 20, and to modem 410 when Q datn cnrrier Is present for transmission of digital dnta to Communications Controller 150. Circuit 420b nnd Switch 430b function in substQntially the same way to control voice nnd data output to the telephone lines. ~Note thnt Interfaces 400 may operate full duplex.) Interfaces 400 mny nlso include conventionnl circuitry for recognition and trnnslntion of "Touch-Tone" type signals generated by push-button type telephones. (Touch-tone" is a Trademnrk of the Bell System for a technique wherein each button on n push botton phone trnnsmlts a unique identifying tone over the phone llnes when pressed.) The digitnl datA transmitted to Controller 2S0 may be stored In the systcm In Q
conventional mnnner but also mny serve to identlfy So the system that a channel is nvailsble for receipt or trnnsmission of Q voice message.
Voice Digitizers/Generators 340 comprise sepnrate digiti2ers/generntors as shown in Figure 7 for ench of Interfnces 400 and its associated telephone line. Each digitizer/generator comprises a conventional incremental trncklng amllog to digitnl (A/D) converter 342 flnd a conventional incremental tracking digital to analog (D/A) converter 344. ~By "incrementnl trncking" herein is mennt an A/D or D/A converter which ou:puts or inputs, respectively, n series of digital signals representing binary numbers, of a predetermined length, proportional tD
the an incremental increase or the incremental decrease in the corresponding analog signal.) The A/D and D/A Converters 342 and 344 output anù input digital data to and from Buffer 346, respectively, depending on the direction of signal flow. The direction of dnta fiow is established in each digitl2er/generator by Control Logic 348 in accordance with the channel select and channel Read and Write signals. Buffer 346 acts as ~ serial-to-.. _ . . _ . . . ..

parnllel or psrnllel-to-serial converter to transfer digitnl dsta to or from Voice Bus 20 in accordnnce with the direction of signnl flow. Control Logic 348 strobes dntn to or from Buffer 346 in accordnnce wi~h the chnnnel select signnl nnd then serinlly shifts dntn from A/D Converter 342 or to D/A Converter nt npproximntely Q Z4-32 kilobit/sec rnte.
Prefernbly, A/D Converter 342 will include conventionnl Qutomutic gnin control circuitry to normnlize the nnalog voice signnl received from the telephone lines.
Dntn is transferred from Buffer 346 over Voice Bus 20 to Voice Buffer Memory 320 under control Voice Trnnsfer Controller 300 described more fully below. Memory 320 is conventionnl RAM and orgnnized to form n double buffer for ench voice chnnnel. The buffers in Memory 320 are progrnmmnble by Host Processor 200 nnd typicnlly ere esch npproximntely 14 kilobytes long to provide approximntely 3.3 seconds of storage for a voice signnl. (By "double buffering" herein is mennt that each chnnnel is provided with two buffers, one of which may be emptied while the other is being filled ~nd which then switch roles Controller 300 maintains the status of all buffers and the current addresses to used for the next byte to be transferred to or from Memory 320 and maintnins the current byte count. Controller 300 also mnintnins n current nddress pointer which mny be read by Host 200, for each buffer.
Voice Transfer Controller 300 Is aiso operstively connected to Voice DMA Controller to transfer duta between buffers in Voice Buffer Memory 320 nnd Disk Drives 502 through Stornge network Processor 100 nnd hsrd Disk Controller 500. To trensfer data to Disk Drives 502 Voice Trnnsfer Controller time shares Voice Bus 20 on e byte by byte basis between Voice DMA Controller 112 snd Voice Digitizers/Generators 340.

The BLIS Cycle Control signnl is nsserted by Voice 'I'rnnsfer Conlroller 300 for one hnlf of each bus cycle ~nd during that hnlf cycle Controlier 300 nccesses the appropri~te memory locDtlon in Memory 320 to trnnsfer dntn between DMA Controller 112 nnd the next nvnilnble location in the buffer for the channel defined by Voice Transfer Controller 300 on the 5 Chnnnel Address Lines. During the other half cycle Voice Trnnsfer ControBier 300 sequentially selects nnd trnnsfers dntn between Buffers 346 of Voice Digitizers/Generators 340 nnd Buffer Memory 320 for chnnnels thnt are sctive.
Turning to Figure 8 n more detailed schematic block dingram of Voice Transfer Controller 300 is shown. Controller 300 comprises high speed Scr~tchpad Memory 302 which stores dnta defining the stlttus of ench chnnnel buffer estnbllshed In Buffer Memory 320. Ench such buffer is defined by 8 guQdruplet of dat~ words ns shown In Plgure 8n; one word defining the starting nddress of the nssoclated bufrer the next sequential word defining the starting ~ord count of the essociited buffer and the next two locations deflning the ourrent eddress to be nddressed nnd current word count in the buffer. In normnl OperQtiOn the starting nddress nnd count wiLi remnin fixed however if necessary buffer nilocation may be dynamically nltered under control of A host processor QS
wili be described below.
Scrntchpnd Memory 302 operntes under control of Control Logic 304. Control Logic 304 synchronizes e high speed VMA block dntR
trnnsfer to or from Disk Drives 502 through Voice DMA Controller 112 end uses the buffer stntus dntn stored In Scr~tchpad 302 to control ù low speed tr~nsfer of dnts words between ench nctive Digitizer/GenerQtor Buffer 346 nnd its essocinted buffer in Buffer Memory 320. Voice Bus 20 is multiplexed between these modes Cll n word by word basis under control of the Bus Cycle Control signnl genernted by Voice Transfer Controller 300 snd received through ~MA Port 3043. For one hnlf of the bus cycle the 8 Voice Dntn lines on Volce Bus 20 nre used to trnnsfer n dntn word between voice DMA Controller 112 nnd 8uffer Memory 320. During the other hnlt of the Bus Cycle control Logic 309 cycles sequentinlly though the active channels trnnsferring dnta words between Digitizer/Generstor Buffers 346 nnd their nssocisted buffers in Memory 320.
(Those skilled in the art will recognize thnt typicnl hnrd disk trnnsfer rQtss of approximately 3 Megnbits per second, require thnt Scratchpad 302 hnve an access time on the order of 10's of nnno seconds in order to successfully sequence the nctive chnnnels nnd multiplex Voice Bus 20. A suitnble high-speed memory would be n Model 93422 mnnufnctured by Pnirchild C~mera dnd Instrument Corporntion of Mountain View, CA.) When ~ buffer in memory is either full (or empty) or hnlf full (or empty) Logic 304 nctivntes Interrupt Logic 306 to generste sn interrupt over HQSt Bus 10, in Q mnnner substnntinlly similnr to the interrupt process described nbove for Stornge/Network processor 100, to llost Processor 200 (or other Auxillnry Host Processors 210, 220, etc.). Logic 304 then londs information identifying the full hnlf buffer into an l/O
buffer in l/O Port 3045 snd Host Processor 2û0 performs nn l/O Rend Operntion through l/O Port 3045 to identity the full (or empty) hnlt buffer which must be emptied to (or filled) from disk drive 502. Host 200 then cornmunicates with Storage/Netv-ork Processor 100 flS described nbove to inform Processor 100 that dat~ must be trnnsferred between Q buffer ir. Memory 320 nnd Disk Drive 502. Processor 100 then initinlizes Hnrd s~
- a7 -Disl~ Conlroller 500 and Voice DMA Controller 112. Controller 112 then puts the appropriate memory address and a DMA Read or Write signal as npproprinte on Voice Bus 20 to DMA Port 3D43 to initiate a block transter from or/to Disk Drive 502 to filJ or empty the half buffsr.
During the DMA half cf each bus cycle, 8S indicnted by the Bus Cycle Control signal, Voice DMA Controller 112 transfers 8 byte of digitized voice data from the selected buffer in Buffer Memory 32û. The current address register is then incremented and the current count is decremented and the cycle repeated during each successive DMA half-cycle on Voice Bus 20 until the entire datM block has been transferred between Disk Drive 502 and the appropriate half-buffer.
During some of Ule channel half-cycles of ~oice Bus Control Logic 304 sequentially and cyclically services each active channel, transferring data words between the Digltizer/Generator Buffers 346 and the current nddress of the ~ssocisted buffer in Buffer Memory 320.
During each channel half-cycle of Voice Bus ao, Control Logio 304 transfers the current address and current count Informntion for the buffer in Buffer Memory 320 into 8uffer Address Reglsters 3044 and puts the address on Voice Bus 20 through Buffer Port 3049. Then in response to A
channel P~esdy, which Indicates dRta availability in buffers 346, Signnl Logic 304 asserts a Channel Read or Channel Write signai as appropriate while simultaneollsly accessing Buffer Memory 320 through Buffer Port 3047 to transfer roice data over Voice Bus 20 between Memory 320 and the appropriRte Buffer 346. The current address is then Incremented and the count decremented and the information is restGred in Scratchpad 302.
On successive channel half-cycles successive active channels are serviced, snd, as described above as esch half-buffer is filied Logic 304 initiates an - 2~ -interrupl of Host Processor 200, or other appropriste processor, through Interrupt Logic 306.
Control Logic 304 also, in the present embodiment, uses every fourth channeJ half-cycle for memory refresh for Buffer Memory 320.
Control Logic 304 is also connected to host Bus 10 through l/O
Port 3045 so that Host Processor 200, or other Rppropriate processor, may perform l/O operations to Logic 309 in a manner substantially similar to that described for l/O operations between Nost Processor 200 end Storage/network processor 100 I/O Write operations may be used by Host Processor 200 to estaolish and reallocate buffer arens in Memory 320 and to actiYate or innctivate vnrious channels. I/O Read operations, in addition to being used by Host Processor 200 in response to an interrupt to determine which channel buffer requires service, also may be used to read the current location pointers for each channel stored in Bufrer il1emory 320.
Iiost Processor 200 may use its capability for l/O access to Voice Transfer ControLier 300 to not only eontrol transfers of digitized voice data between Disks 500 and Buffer Memory 320 but may also control Voice Transfer Controller 300 to transfer selected blocks of pre-stored digitized voice data from Buffer Memory to Digitizer/Generators 340.
This allows Host 200 to concatennte various voice prompting messnges for transmission over the telephone lines. As an example, Host 200 could prompt R user when connection was flrst established through interfaces 400.
Prefernbly ench channel buffer in Buffer Memory 320 comprises two approximately 14 kilo byte half-buffers and the voice sign~i is digitized at npproximntely 4 kilo byte/sec rate, so that e~ch half-buffer - 2g -provides Rpproximstely 3.3 seconds Df storMge. Also, preferebly up to 32 chunnels flre provided Qnd Disk Drive 502 is Q conventionul Winchester type disk hnving approximately n 8 megn bits/sec trQnsfer rQ~e so thst the total time to eccess 32 hali-buffers is spproximQtely 128 milJiseconds per

3.3 seconds and the disk is used for voice trQnsfers leæ thQn .3 percent of the time.

VOICE STORAGE AND RETRIEVAL OPERATION
In operstion n user would establish contect with one of Telephone InterfQces 400 over telephone lines, either IOCQI or disl-up. Typicnlly the user would first send dnt~ to the system providing identifying informntion end/or defining n request. (Altern~tively it is within the contemplntion of the subject invention that the system detect and respond to circuit completlon Qnd first trsnsmit, either d digitQI or voice signQI, typicnlly to provlde Instruction for a user.) Communicntions Processor 25n would receivd the dnt~l from the oontncted Telephone Inter~cQ 400 snd would trsnsmlt It to llost Procesoor aoD over llost Bus 10, flS desoribed ~bov0 In the section entieled StorAge/Network Memory-to-Memory DutQ TrQnsfers.
Host Processor 200 would iæue instructions to Stornge/~etwork Processor 100, agnin as a Memory-to-Memory Data TrQnsfer, to estsblish nn sppropriate storage region on Disk 502. Processor 200 would then Issue nn 1/0 Write to Voice Trunsfer Controller to turn on the ~ppropriate chnnnel in the QpprOpri~te direction Qs defined by the dstQ sent by the user. (While hereinafter, for ellse of description, trnnsmission from the user for recording wiIi be described, tilose skilled in the ert will relldily recognize the minor chAnges needed to plsy back recorded voice signQls.) Host Processor 200 mey then relellse Voice Trunsfer Controiier 300 and is ,5~

free to pertorm other processlng tasks. When Controller 300 senses thQt an associated half-buffer in Memory 320 is fuli It generates an interrupt on Host Bus 10 addressed to Processor 200. Processor 200 then performs on l/O Read operation from controller 300 to de~ermine which channel require service. Processor al)o then instruots Storflge/Network Processor 100 to service the interrupting channel. CPU 102 in Storage/Network Processor 100 then initializes Disk Controller 500, sets up Switch Logic 114 to transîer data from Yoice DMA Controller 112 to Disk controller 500, and initializes a block data transfer from the channel requesting service through DMA Controller 112.
Such a block transfer ~vould require less than 4 milliseconds at the disk rate of 8 megabits per sec. ~Ind tllose skilled in the ert wiii recognize that multiple chflnnels of voice alld duts msy be muitiplexed to Disk Drive 502 without over loading the drive.
lt is particularly withln the contemplation of the subject invention to interface voice and text messsges and associate such voice messages with p~rticular points In such text messages so thflt such voice messages may be played baok in association with such points.
The embodiments described above and shown in the attached drawings h~lve been described for purposes of illustrQtion only and those skilled in the art will recognize many other possible embodiments within the eontemplation oî the subject invention. Thus limitations on the scope of the subject invention are to be found oniy in the claims set forth below.

Claims

WHAT IS CLAIMED IS:

1. A voice/text storage and retrieval apparatus comprising:
a) digital mass storage means for storage and retrieval of digital data and of digitized voice signal data;
b) first processor means for controlling access to said digital mass storage means;
c) host processor means for monitoring, coordination and supervision of the operation of said apparatus;
d) communications processor means for reception and retransmission of digital data;
e) interface means for receiving and transmitting both digital data signals and analog voice signals, said interface means further comprising detection means for the detection of digital data signals and switch means responsive to said detection means for separating said digital data signals from said analog voice signals, said switch means operatively connecting said communications processor means to said interface means for transmission and reception of said digital signals;
f) conversion means operatively connected to said interface switch means for the reception and transmission of said analog voice signals, said received analog voice signals being digitized by said conversion means and said transmitted analog voice signal being generated by said conversion means in response to a digital input;
g) buffer means for buffering the flow of data to and from said conversion means;

h) voice transfer control means for controlling the transfer of data between said buffer means and said conversion means and for signaling said host processor when a block of said digitized voice signal data must be transferred between said buffer and said mass storage means and in response to signals from said first processor means controlling such block transfers;
i) a first bus operatively interconnecting said first processor means, said communications processor means and said host processor means, whereby digital data received by, or to be transmitted by said communications processor may be transferred between said mass storage means and said communications processor means under control of said first processor means and in response to commands from said host processor means;
j) a second bus operatively interconnecting said first processor means, said voice transfer control means said buffer means and said conversion means, whereby said digitized voice data may be transferred between said buffer means and said conversion means and blocks of said digitized voice data may be transferred between said mass storage means and said buffer means under control of said first processor means and said voice transfer control means; and k) said first bus being further operatively connected to said voice transfer control means whereby said host processor means may initiate or half digitized voice data signal transfers to and from said conversion means.

2. A voice/text storage and retrieval apparatus as described In Claim 1 wherein said interface means further comprises a plurality of interface units each operatively connected to an associated telephone line to receive find transmit both digital data signals and analog voice signals over said telephone lines.

3. A voice/text storage and retrieval apparatus as described in Claim 2 wherein said switch means further comprises a plurality of switch units each operatively associated with an interface unit and said conversion means further comprises a plurality of conversion units such operatively connected to one of said switch units for the reception and transmission of analog voice signals over its associated telephone line.

4. A voice/text storage and retrieval apparatus as described in Claim 3 wherein said conversion units further comprise input/out buffers operatively connected to said second bus for the receipt and transmission of digital representations of said analog voice signals to and from said buffer means.

5. A voice/text storage and retrieval apparatus as described in claim 4 wherein said voice transfer control means sequentially and cyclically performs input/output operations between said buffer means and said conversion unit input/output buffers.

6. A voice/text storage and retrieval apparatus as described in Claim 5 wherein said voice transfer control means generates a bus cycle control signal to divide each cycle of success to said second bus into two portions one of said portions being available for said input/output operations between said buffer means and said conversion unit input/output buffers and the other of said portions being available for transmission of word of said block transfers of digitized voice signals to said mass storage means.

7. A voice/text storage and retrieval apparatus as described in Claim 3 wherein said conversion units further comprise incremental tracking analog-to-digital and digital-to-analog converters for converting and generating said analog voice signals.

8. A voice/text storage and retrieval apparatus as described in Claim 4 wherein said conversion units further comprise incremental tracking analog-to-digital and ditigal-to-analog converters for concerting and generating said analog voice signals.

9. A voice/text storage and retrieval apparatus as described in Claim 5 wherein said conversion units further comprise incremental tracking analog-to-digital and digital-to-analog converters for converting and generating said analog voice signals.

10. A voice/text storage and retrieval apparatus as described in Claim 6 wherein said conversion units further comprise incremental tracking analog-to-digital and digital-to-analog converters for converting and generating said analog voice signals.

11. A voice/text storage and retrieval apparatus as described in Claim 2 wherein said buffer means comprises a random access memory operatively connected to end controlled by said voice transfer control means and operatively connected to said second bus for the transfer of digital representations of said analog voice signal, said voice transfer control means selecting particular areas of said memory as buffer areas for data to be received from or to be transmitted through an associated one of said telephone interfaces.

12. A voice/text storage and retrieval apparatus as described in claim 11 wherein said host processor means may access said voice transfer control means to initiate transfers of selected segments of pre-stored voice data from said buffer means to said conversion means whereby said host processor means may concatenate said segments to form preselected voice messages for transmission as analog signals over said associated telephone lines.

13. A voice/text storage and retrieval apparatus as described in claim 12 wherein said host processor means accesses said voice transfer control means in response to a signal received over a particular one of said telephone lines and a preselected voice message is transmitted over said particular line.

14. A voice/text storage and retrieval apparatus as described in Claim 3 wherein said buffer means comprises a random access memory operatively connected to end controlled by said voice transfer control means and operatively connected to said second bus for the transfer of digital representations of said analog voice signal, said voice transfer control means selecting particular areas of said memory as buffer areas for data to be received from or to be transmitted through an associated one of said telephone interfaces.

15. A voice/text storage and retrieval apparatus as described in Claim 4 wherein said buffer means comprises a random access memory operatively connected to and controlled by said voice transfer control means and operatively connected to said second bus for the transfer of digital representations of said analog voice signal, said voice transfer control means selecting particular areas of said memory as buffer areas for data to be received from or to be transmitted through an associated one of said telephone interfaces.

16. A voice/text storage and retrieval apparatus as described in Claim 5 wherein said buffer means comprises a random access memory operatively connected to and controlled by said voice transfer control means and operatively connected to said second bus for the transfer of digital representations of said analog voice signal, said voice transfer control means selecting particular areas of said memory as buffer areas for data to be received from or to be transmitted through an associated one of said telephone interfaces.

17. A voice/text storage and retrieval apparatus as described in Claim 6 wherein said buffer means comprises a random access memory operatively connected to and controlled by said voice transfer control means and operatively connected to said second bus for the transfer of digital representations of said analog voice signal, said voice transfer control means selecting particular areas of said memory as buffer areas for data to be received from or to be transmitted through an associated one of said telephone interfaces.

18. A voice/text storage and retrieval apparatus as described in Claim 7 wherein said buffer means comprises a random access memory operatively connected to and controlled by said voice transfer control means and operatively connected to said second bus for the transfer of digital representations of said analog voice signal, said voice transfer control means selecting particular areas of said memory as buffer areas for data to be received from or to be transmitted through an associated one of said telephone interfaces.

19. A voice/text storage and retrieval apparatus as described in Claim 8 wherein said buffer means comprises a random access memory operatively connected to and controlled by said voice transfer control means and operatively connected to said second bus for the transfer of digital representations of said analog voice signal, said voice transfer control means selecting particular areas of said memory as buffer areas for data to be received from or to be transmitted through an associated one of said telephone interfaces.

20. A voice/text storage and retrieval apparatus as described in Claim 9 wherein said buffer means comprises a random access memory operatively connected to and controlled by said voice transfer control means and operatively connected to said second bus for the transfer of digital representations of said analog voice signal, said voice transfer control means selecting particular areas of said memory as buffer areas for data to be received from or to be transmitted through an associated one of said telephone interfaces.

21. A voice/text storage and retrieval apparatus as described in Claim 10 wherein said buffer means comprises a random access memory operatively connected to and controlled by said voice transfer control means and operatively connected to said second bus for the transfer of digital representations of said analog voice signal, said voice transfer control means selecting particular areas of said memory as buffer areas for data to be received from or to be transmitted through an associated one of said telephone interfaces.

22. A voice/transfer storage and retrieval apparatus as described in Claim 11 wherein said voice transfer control means further comprises a scratchpad memory, said scratchpad memory containing information defining the location, extent and current status of each of said buffer areas, said voice transfer control means accessing said information to determine the appropriate location in said random access memory for each input/output operation with said conversion unit input/output buffers, and said voice transfer control means still further comprising interrupting means for generating a signal each time one of a plurality of preselected portions of said buffer means is filled and block transfer means responsive to signals from said first processor means for block transferring the information in said full portion to said digital mass storage means under control of said first processor means.

23. A voice/transfer storage and retrieval apparatus as described in Claim 14 wherein said voice transfer control means further comprises a scratchpad memory, said scratchpad memory containing information defining the location, extent and current status of each of said buffer areas, said voice transfer control means accessing said information to determine the appropriate location in said random access memory for each input/output operation with said conversion unit input/output buffers, and said voice transfer control means still further comprising interrupting means for generating a signal each time one of a plurality of preselected portions of said buffer areas is filled and block transfer means responsive to signals from said first processor means for block transferring the information in said full portion to said digital mass storage means under control of said first processor means.

24. A voice/transfer storage and retrieval apparatus as described in Claim 15 wherein said voice transfer control means further comprises a scratchpad memory, said scratchpad memory containing information defining the location, extent and current status of each of said buffer areas, said voice transfer control means accessing said information to determine the appropriate location in said random access memory for each input/output operation with said conversion unit input/output buffers, and said voice transfer control means still further comprising interrupting means for generating a signal each time one of a plurality of preselected portions of said buffer areas is filled and block transfer means responsive to signals from said first processor means for block transferring the information in said full portion to said digital mass storage means under control of said first processor means.

25. A voice/transfer storage and retrieval apparatus as described in Claim 16 wherein said voice transfer control means further comprises a scratchpad memory, said scratchpad memory containing information defining the location, extent and current status of each of said buffer areas, said voice transfer control means accessing said information to determine the appropriate location in said random access memory for each input/output operation with said conversion unit input/output buffers, and said voice transfer control means still further comprising interrupting means for generating a signal each time one of a plurality of preselected portions of said buffer areas is filled and block transfer means responsive to signals from said first processor means for block transferring the information in said full portion to said digital mass storage means under control of said first processor means.

26. A voice/transfer storage and retrieval apparatus as described In Claim 17 wherein said voice transfer control means further comprises a scratchpad memory, said scratchpad memory containing information defining the location, extent and current status of each of said buffer areas, said voice transfer control means accessing said information to determine the appropriate location in said random access memory for each input/output operation with said conversion unit input/output buffers, and said voice transfer control means still further comprising interrupting means for generating a signal each time one of a plurality of preselected portions of said buffer areas is filled and block transfer means responsive to signals from said first processor means for block transferring the information in said full portion to said digital mass storage means under control of said first processor means.

27. A voice/transfer storage and retrieval apparatus as described in Claim 18 wherein said voice transfer control means further comprises a scratchpad memory, said scratchpad memory containing information defining the location, extent and current status of each of said buffer areas, said voice transfer control means accessing said information to determine the appropriate location in said random access memory for each input/output operation with said conversion unit input/output buffers, and said voice transfer control means still further comprising interrupting means for generating a signal each time one of a plurality of preselected portions of said buffer areas is filled and block transfer means responsive to signals from said first processor means for block transferring the information in said full portion to said digital mass storage means under control of said first processor means.

28. A voice/transfer storage and retrieval apparatus as described in Claim 19 wherein said voice transfer control means further comprises a scratchpad memory, said scratchpad memory containing information defining the location, extent and current status of each of said buffer areas, said voice transfer control means accessing said information to determine the appropriate location in said random access memory for each input/output operation with said conversion unit input/output buffers, and said voice transfer control means still further comprising interrupting means for generating a signal each time one of a plurality of preselected portions of said buffer areas is filled and block transfer means responsive to signals from said first processor means for block transferring the information in said full portion to said digital mass storage means under control of said first processor means.

29. A voice/transfer storage and retrieval apparatus as described in Claim 20 wherein said voice transfer control means further comprises a scratchpad memory, said scratchpad memory containing information defining the location, extent and current status of each of said buffer areas, said voice transfer control means accessing said information to determine the appropriate location in said random access memory for each input/output operation with said conversion unit input/output buffers, and said voice transfer control means still further comprising interrupting means for generating a signal each time one of a plurality of preselected portions of said buffer areas is filled and block transfer means responsive to signals from said first processor means for block transferring the information in said full portion to said digital mass storage means under control of said first processor means.

30. A voice/transfer storage and retrieval apparatus as described in Claim 21 wherein said voice transfer control means further comprises a scratchpad memory, said scratchpad memory containing information defining the location, extent and current status of each of said buffer areas, said voice transfer control means accessing said information to determine the appropriate location in said random access memory for each input/output operation with said conversion unit input/output buffers, and said voice transfer control means still further comprising interrupting means for generating a signal each time one of a plurality of preselected portions of said buffer areas is filled and block transfer means responsive to signals from said first processor means for block transferring the information in said full portion to said digital mass storage means under control of said first processor means.

31. A voice/text storage and retrieval apparatus comprising:
a) digital mass storage means for storage and retrieval of digital data and of digitized voice signal data;
b) communications and control means for the generation and transfer of digital command and data signals, said communications and control means further compromising b.1) a first bus;
b.2) host processor means operatively connected to said first bus for the generation of digital command signals for the overall control of said apparatus; apparatus b.3) communication processor means operatively connected to said first bus and to a plurality of serial data lines for controlling the transmission of digital data between said first bus and said serial data lines.
c) voice transfer means for converting voice signals between digital and analog form and for transferring said voice signals to and from said mass storage means, said voice transfer control means including a second bus for the transfer of digitized voice signals;
d) interface means for interfacing a plurality of signal lines to said apparatus, said lines having the capability to carry both analog voice signals and serial digital data, said interface means including switch means for distinguishing between said analog voice signals and said serial data signals and for routing said analog voice signals between said signal lines and said voice transfer control means and for routing said serial data signals between said signal lines and said serial data lines;

e) storage/network processing means operatively connected to said first and second busses for controlling access to said mass storage means, said storage/network processor means further comprising:
e.1) a central processing unit having a private memory;
e.2) first direct memory access means operatively connecting said storage/network processing means to said first bus;
e.3) second direct memory access means operatively connecting said storage/network processing means to said second bus;
e.4) storage/network switch means, controlling by said central processing unit, for operatively connecting said first direct memory access means to said private memory, whereby said command data signals may be transmitted between said central processing unit and said host processing means, and for operatively connecting either said first or said second direct memory access means to said mass storage means, whereby either digital data or digitized voice may be routed to said mass storage means for storage or retrieval.

32. A voice/text storage and retrieval apparatus as described in Claim 31 wherein said voice transfer means is operatively connected to first bus to respond to commands from said communications and control means to activate or inactivate communications with particular ones of said signal lines and to determine the direction of voice signal flow between said apparatus and said particular ones of said signal lines.

33. A voice/text storage and retrieval apparatus as described in Claim 31 wherein said host processor means and said communications processor means communicate by transferring a block of data to said private memory of said storage/network central processing unit, under control of said first direct memory access means, for retransmittal by said storage/network processing means to the other of said communicating processor means.

34. A voice/text storage and retrieval apparatus as described in Claim 32 wherein said host processor means and said communications processor means communicate by transferring a block of data to said private memory of said storage/network central processing unit, under control of said first direct memory access means, for retransmittal by said storage/network processing means to the other of said communicating processor means.

35. A voice/text storage and retrieval apparatus as described in Claim 31 wherein said storage/network processing means further comprises a high-speed data communications port for connection to a high-speed parallel digital data network, and associated switch means, operating under control of said central processing unit, for providing a high-speed digital data path between said mass storage means and said network.

36. A voice/text storage and retrieval apparatus as described in Claim 32 wherein said storage/network processing means further comprises a high-speed data communications port for connection to a high-speed parallel digital data network, and associated switch means, operating under control of said central processing unit, for providing a high-speed digital data path between said mass storage means and said network.

37. A voice/text storage and retrieval apparatus as described in Claim 33 wherein said storage/network processing means further comprises a high-speed data communications port for connection to a high-speed parallel digital data network, and associated switch means, operating under control of said central processing unit, for providing a high-speed digital data path between said mass storage means and said network.

38. A voice/text storage and retrieval apparatus as described in Claim 34 wherein said storage/network processing means further comprises a high-speed data communications port for connection to a high-speed parallel digital data network, and associated switch means, operating under control of said central processing unit, for providing a high-speed digital data path between said mass storage means and said network.

39. A voice/text storage and retrieval apparatus as described in Claim 31 wherein said storage/network processing means further comprises a back-up data communications port for connection to a back-up storage device such as a tape drive and associated switch means, operating under control of said central processing unit, for providing a back-up data path whereby overflow data from said mass storage means may be saved on said back-up storage device.

40. A voice/text storage and retrieval apparatus as described in Claim 32 wherein said storage/network processing means further comprises a back-up data communications port for connection to a back-up storage device such as a tape drive and associated switch means, operating under control of said central processing unit, for providing a back-up data path whereby overflow data from said mass storage means may be saved on said back-up storage device.

41. A voice/text storage and retrieval apparatus as described In Claim 33 wherein said storage/network processing means further comprises a back-up data communications port for connection to a back-up storage device such as a tape drive and associated switch means, operating under control of said central processing unit, for providing a back-up data path whereby overflow data from said mass storage means may be saved on said back-up storage device.

42. A voice/text storage and retrieval apparatus as described in Claim 34 wherein said storage/network processing means further comprises a back-up data communications port for connection to a back-up storage device such as a tape drive and associated switch means, operating under control of said central processing unit, for providing a back-up data path whereby overflow data from said mass storage means may be saved on said back-up storage device.

43. A voice/text storage and retrieval apparatus as described in Claim 35 wherein said storage/network processing means further comprises a back-up data communications port for connection to a back-up storage device such as a tape drive and associated switch means, operating under control of said central processing unit, for providing a back-up data path whereby overflow data from said mass storage means may be saved on said back-up storage device.

44. A voice/text storage and retrieval apparatus as described in Claim 36 wherein said storage/network processing means further comprises a back-up data communications port for connection to a back-up storage device such as a tape drive and associated switch means, operating under control of said central processing unit, for providing a back-up data path whereby overflow data from said mass storage means may be saved on said back-up storage device.

45. A voice/text storage and retrieval apparatus as described in Claim 37 wherein said storage/network processing means further comprises a back-up data communications port for connection to a back-up storage device such as a tape drive and associated switch means, operating under control of said central processing unit, for providing a back-up data path whereby overflow data from said mass storage means may be saved on said back-up storage device.

46. A voice/text storage and retrieval apparatus as described in Claim 38 wherein said storage/network processing means further comprises a back-up data communications port for connection to a back-up storage device such as a tape drive and associated switch means, operating under control if said central processing unit, for providing a back-up data path whereby overflow data from said mass storage means may be saved on said back-up storage device.