CA1217288A - Digital voice transmission having improved echo suppression - Google Patents
Digital voice transmission having improved echo suppressionInfo
- Publication number
- CA1217288A CA1217288A CA000448667A CA448667A CA1217288A CA 1217288 A CA1217288 A CA 1217288A CA 000448667 A CA000448667 A CA 000448667A CA 448667 A CA448667 A CA 448667A CA 1217288 A CA1217288 A CA 1217288A
- Authority
- CA
- Canada
- Prior art keywords
- talker
- gain parameter
- digital
- gain
- far
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/20—Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other
Abstract
ABSTRACT OF THE DISCLOSURE
Digital communication apparatus for improving digital voice transmission over telephone lines by increasing echo suppression is described. The apparatus comprises a transmission gain detector which detects the gain of the near talker signal, a receiver detector for detecting the gain of the far talker signal, and an echo suppression circuit which is partially software implemented, for comparing the gains of the far and near talkers and for suppressing the gain of the lesser value by balancing the impedances in the telephone and in the load balancing circuit.
Digital communication apparatus for improving digital voice transmission over telephone lines by increasing echo suppression is described. The apparatus comprises a transmission gain detector which detects the gain of the near talker signal, a receiver detector for detecting the gain of the far talker signal, and an echo suppression circuit which is partially software implemented, for comparing the gains of the far and near talkers and for suppressing the gain of the lesser value by balancing the impedances in the telephone and in the load balancing circuit.
Description
DIGITAL VOICE TRANSMISSION HAVING
IMPROVRD ECHO SUPPRESSION
1. Field of the Invention The present invention relates to a digital communication apparatus for transmitting and receiving a compressed digital representation of speech produced by a near talker and a far talker respectively, and to a method of echo suppression in a digital communication link, and digital communication link communicating a compressed digital representation of speech produced by a near talker and a far talker. Thus, the invention relates to digital voice transmission over telephone lines and is particularly useful in digital voice transmission in which a digitized voice signal or, e.g. 64~000 bits per second (bps) is compressed to, e.g. 2,400 bps for transmission over the telephone bandwidth~ with improved echo suppression being used to improve system operation.
IMPROVRD ECHO SUPPRESSION
1. Field of the Invention The present invention relates to a digital communication apparatus for transmitting and receiving a compressed digital representation of speech produced by a near talker and a far talker respectively, and to a method of echo suppression in a digital communication link, and digital communication link communicating a compressed digital representation of speech produced by a near talker and a far talker. Thus, the invention relates to digital voice transmission over telephone lines and is particularly useful in digital voice transmission in which a digitized voice signal or, e.g. 64~000 bits per second (bps) is compressed to, e.g. 2,400 bps for transmission over the telephone bandwidth~ with improved echo suppression being used to improve system operation.
2. Back~ nd and Summar~ of the_Invention It is well known in the prior art to digitize the analog signal output of, e.g., a telephone microphone, representing a voice signal, in order to transmit the digital data over a telephone line. The digitized siginal, which may be converted back to an analog representation of the digital data for the purpose of transmission over the telephone linesl as is also well known in the art, is less susceptable to noise on the telephone line, is capable of multiplexed channel operation in the telephone bandwidth, reduces crosstalk and enables relatively easy digital encryption for secure transmission.
The digitized voice signal, which typically is at e.g., 64,000 bps, cannot be readily sent within the available approximately 3,000 Hz bandwidth of the telephone lines or be readily sent multichannel at that bit ~-~,~
`' rate within the available telephone line bandwidth. Toenable more convenient trans~ission and/or multiplexed transmission, compression of the 64,0~0 bps digitized voice signal is e~ployed, as is known in the art. One 5 method of compressing the 64,000 bps t:o, e.g., 2~400 bps is to use a linear predictive coding technique known in the art, a discussion of which is found, for example, in Markel, Grey, Jr. & Wakita, ~Linear Prediction of Speech Theor~ and Practice,~ Speech Communication Research 10 Laboratory, Inc. Monograph No. 10 (1978). With co~pression to 2,4~0 bps, four simultaneous channels of 2,400 bps each can be mnultiplexed via a modem onto a 9,600 bps data stream transmitted over the bandwidth of the analog telephone lines.
lS
The linear predictive coding technique employs digital Eiltering o~ the 64,000 bps digitized voice in digital resonating filters. Only digits representatLve of fundamental requencies within thc analog voice 20 signal are selected in the compression to 2,400 bps.
Speech is made up of pitch (voiced and unvoiced) and amplitude components, with the pitch being derived from the action o~ the human vocai cords. Pitch ranges vary from adult males, 50-150 Hz, adult females, 90-450 Hz 25 and children, 125-575 Hz. Thus, much o the ~undamental fre~uencies in the voice o~ a telephone talker is eliminated ~rom the approximateLy 300-3000 Hz telephone bandwidth. However, fundamental pi~ch frequencies can be determined from, e.g., second or third harmonics.
30 Thus, e.g., 360 Hz is the second harmonic o 180 Hz and the third harmonic of 120 Hz. It is thus possible in the linear predictive compression technique to transmit a compressed form o digitized speech representing the ~undamental pitch frequencies, the voiced speech component, an~ the unvoiced speech component to synthe-si~e these at the receiver end to simulate actual speech, as is all well known in the art. In synthesi~-ing speech at the receiver end, the unvoiced components are represented by white noise, i.e., ran~om binary bits, ~hich, when synthesized with the voiced co~onents in the proper proportion, result in simulating actual speech, when t~e resulting synthesized digital signals at the receiver end, now expanded to 64,000 bpsr are passecl throuyh a digital-to-analog converter, as is also known in the art. The linear predictive coding tech nique uses a linear predîction algori~hm, eOg., LPC 10.
Fundamentally what the linear predictive coding does is to generate a set o, e.y., 10 numbers (envelope prediction ~actors) per frame at the trans-mitter, based ~QOn the actual data taken from the analog-to-digital conversion of the analog speech signal, at 64,000 bps. These 10 numbers enable the receiver end to generate by use of the linear ~redictive algorithm a full set of, e.gO, 180 Qoints ~er frame, e.~., 64,000 bps digitized voice. The 10 numbers per frame, plus six bits representing pitch, six bits representing RMS gain and a sync bit are transmitted every frame, which amounts to 2400 bps. A frame in the example of 25 the present invention is 22.5 millisecon~s. The 10 numbers are generated in the translnitter from an analyr sis of the envelope of the digitized voice signal in the frequency domain, and enable the reconstruction of the envelope at the receiver end.
There are presently in use both two-wire and four-wire telephone transmission links. In the two-wire system~ analog speech or data signals are transmitted in both directions with two wires. In the Eour-wire system there are two wires, each with an associated ground 35 wire, e.g., one for transmitting an~ one for receiving.
The digitized voice signal, which typically is at e.g., 64,000 bps, cannot be readily sent within the available approximately 3,000 Hz bandwidth of the telephone lines or be readily sent multichannel at that bit ~-~,~
`' rate within the available telephone line bandwidth. Toenable more convenient trans~ission and/or multiplexed transmission, compression of the 64,0~0 bps digitized voice signal is e~ployed, as is known in the art. One 5 method of compressing the 64,000 bps t:o, e.g., 2~400 bps is to use a linear predictive coding technique known in the art, a discussion of which is found, for example, in Markel, Grey, Jr. & Wakita, ~Linear Prediction of Speech Theor~ and Practice,~ Speech Communication Research 10 Laboratory, Inc. Monograph No. 10 (1978). With co~pression to 2,4~0 bps, four simultaneous channels of 2,400 bps each can be mnultiplexed via a modem onto a 9,600 bps data stream transmitted over the bandwidth of the analog telephone lines.
lS
The linear predictive coding technique employs digital Eiltering o~ the 64,000 bps digitized voice in digital resonating filters. Only digits representatLve of fundamental requencies within thc analog voice 20 signal are selected in the compression to 2,400 bps.
Speech is made up of pitch (voiced and unvoiced) and amplitude components, with the pitch being derived from the action o~ the human vocai cords. Pitch ranges vary from adult males, 50-150 Hz, adult females, 90-450 Hz 25 and children, 125-575 Hz. Thus, much o the ~undamental fre~uencies in the voice o~ a telephone talker is eliminated ~rom the approximateLy 300-3000 Hz telephone bandwidth. However, fundamental pi~ch frequencies can be determined from, e.g., second or third harmonics.
30 Thus, e.g., 360 Hz is the second harmonic o 180 Hz and the third harmonic of 120 Hz. It is thus possible in the linear predictive compression technique to transmit a compressed form o digitized speech representing the ~undamental pitch frequencies, the voiced speech component, an~ the unvoiced speech component to synthe-si~e these at the receiver end to simulate actual speech, as is all well known in the art. In synthesi~-ing speech at the receiver end, the unvoiced components are represented by white noise, i.e., ran~om binary bits, ~hich, when synthesized with the voiced co~onents in the proper proportion, result in simulating actual speech, when t~e resulting synthesized digital signals at the receiver end, now expanded to 64,000 bpsr are passecl throuyh a digital-to-analog converter, as is also known in the art. The linear predictive coding tech nique uses a linear predîction algori~hm, eOg., LPC 10.
Fundamentally what the linear predictive coding does is to generate a set o, e.y., 10 numbers (envelope prediction ~actors) per frame at the trans-mitter, based ~QOn the actual data taken from the analog-to-digital conversion of the analog speech signal, at 64,000 bps. These 10 numbers enable the receiver end to generate by use of the linear ~redictive algorithm a full set of, e.gO, 180 Qoints ~er frame, e.~., 64,000 bps digitized voice. The 10 numbers per frame, plus six bits representing pitch, six bits representing RMS gain and a sync bit are transmitted every frame, which amounts to 2400 bps. A frame in the example of 25 the present invention is 22.5 millisecon~s. The 10 numbers are generated in the translnitter from an analyr sis of the envelope of the digitized voice signal in the frequency domain, and enable the reconstruction of the envelope at the receiver end.
There are presently in use both two-wire and four-wire telephone transmission links. In the two-wire system~ analog speech or data signals are transmitted in both directions with two wires. In the Eour-wire system there are two wires, each with an associated ground 35 wire, e.g., one for transmitting an~ one for receiving.
3~
In accordance with the present invention there is provided a digital communication apparatus for transmitting and receiving a compressed digital representation of speech produced by a near talker and a far talker respectively, said compressed digital speech representation including a coded gain parameter related to speech energy~ said apparatus comprising:
transmission gain detection means for reading the gain parameter of said near talker's digital speech representation;
receiver gain detection means for reading the gain parameter of said ar talker's digital speech representation;
means for reducing the gain parameter of said far talker's digital speech representation when a recent peak gain parameter in said near talker's speech representation is greater than both (1) a first selected threshold and 12) the gain parameter of said far talker's speech representation plus a selected nonzero compensation value; and means for reducing the gain parameter of said near talker's digital speech representation when a recent peak gain parameter in said far talker's digital speech representation is greater than both (1) said first selected threshold and (2) the gain parameter of said near talker's digital speech representation plus said selected nonzero compensation value.
Preferably the said apparatus also comprises a near talker interrupt detection means for removing the reduction of the gain parameter of the near talker digital speech representation responsive to detecting whether the gain parameter of the near talker's digital speech representation exceeds a seco~d selected threshold; and, a far talker interrupt detection means for removing the reduction of the gain parameter of the far talker's digital speech representation responsive to detecting whether the gain parameter of the far talker's digital speech representation exceeds the second selected threshold.
~ ' - 4a -Also in accordance with the invention there is provided a method of echo suppression in a digital communication link, said digital communication link com~unicating a compressed digital representation of speech produced by a near talker and a far S talker, said compressed digital speech representation including a coded gain parameter related to speech energy, ~he method comprising the steps of:
reducing ~he gain parameters of said near talker or far talker digital spee~h representation of one end of the communication link in accordance with which of said gain parameters has the lesser magnitude;
reducing the gain parameter of said near talker or far talker digital speech representation at the other end of the communication link in accordance with which of said gain parameters has the lesser magnitude;
the reducing steps including the steps of:
reducing the gain parameter of said far talker's digital speech representation when a recent peak gain parameter in said near talker's digital speech representation is greater than both (1) a first selected threshold and (2) the gain parameter of said far talker's digital speech representation plus a selected nonzero compensation value and reducing the gain parameter of said near talker's digital speech representation when a recent peak gain parameter in said far talker's digital speech representation is greater than both (1) said first selected threshold and (2) the gain parameter of said near talker's digital speech representation plus said selected nonzero compensation value.
A preferred embodiment of the invention will now be described in connection with the accompanying drawings, wherein like reference numerals have been applied to like elements, in which:
3~
BRIEF DESCRI PTION OF THE DRAWINGS
~ IGURE 1 shows a ~lock dia~ram o~ an ~nalog input/output circuit foe digitized voice compression/
expansion and employing the automatic gain controL and 5 echo suQ)ression features of the present invention;
FIGURES 2 and 2~ are a more detailed schematic diagram o the circuit o~ Figure l;
FIGUR~ 3 shows a block diagram of a digital voice synthesi7er employed in the receiver o~ a voice 10 transmission link using the present invention;
FIGURE 4 sho~s a flow chart for sotware implementation o autom~ic gain control in accordance with the present invention;
FIGURES 5 and SA show a flow chart for soft-15 ~are implementation o echo suppression in accordance with tlle present invention.
FI~URE 6 shows a further de~ail of the auto-matic gain control circuit according to the present invention; and, FIGURE 7 shows the timing o~ an analog-digital/di~ital-analog converter in accordance with the present invention.
Shown in ~i~ure l is a bloc~ diagram of an analog input~output circuit 10 for digitized voice co~-25 pression and expansion in accordance with the present invention. The circuit 10 is adapted for connection either to a two-wire or ~our-wire telephone transmission link and thus has a two-wire to four-wire intera~e 12 and a ~our-wire inter~ace l~. The two-wire to four-wire 30 inter~ace L2 is connected ~o two-wire telephone trans-mission lines 14 and i6. The ~our-wire inter~ace l~ is connected to a telephone receive lin~ 20, having an associated ground connection 22, and a telephone trans~
mission link 24, having an associated ground connec-35 tion 26.
t ^ ~ ~r :~, : -6-Each o~ the two-wire ~o Eour-wire inter~ace 12 and ~our-wire interface 18 is connected to a spectrum shapin~ am~lifier 32. The s~ectrum shaping ampliÇier 32 is connec~ed throu~h a suitcase strap or a selector 5 switch 34 to an automatic gain control (AGC) section 36, with the switch 3~ also having a position selecting an AGC 3G bypass throug~l a 47 Kohm bypass resistor 380 The OUtQUt of the AGC 36 section an~ the bypass resistor 38 are connected to the input filter half 46 of the band-10 pass filter 44 which passes only ener~y.in the telepho~eline bandwidth from about 300-3000 Hz. The outpu~
filter half 48 of the same bandpass filter 44 is connected to the telephone handset speaker input ~9.of the two-wire to four-wire inter~ace 12 and to the .15 telephone handset speaker input 51 of the four-wire in~erEace 18.
The input filter 46 is connected to an analog-to-diyital converter half 52 of an analog-to-digital/
digital-to-analog converter 50 (~/D/A converter), the 20 output of which is serialized digital data at 64,000 bps, re~resentative of the analog input to the analog-to-digital half 52. This serialized data at 64,000 bps is passed to a serial~to-parallel converter 58 which provides an 8-bit word on output line 62 to an RMS
25 linear prediction analyzer portion o~ a linear predic-tion processor 41. The linear prediction analyzer portion of the processor 41 per~orms the compression of the 64,000 bps output o~ the serial-to-parallel con verter 58 to 2,400 bps for transmission and a linear 30 prediction synthesizer portion oE the processor ~1 perEorms an expandin~ conversion o~ 2,400 bps received data to eigllt-bit words at 64,000 bps, which is an input on line 64 to a parallel-to~serial converter 60. The 2,400 bits as compressed by the processor 41 is trans-35 mitted via, e.g., a modem (not sho-ln) to a remote l~z~'7;~
location, and th~ 2,400 bps as expanded by the synthe-sizer portio~ o the processor ~1 is that wl~ich has been .received ro~ a remote location, e~g.' through a modem, ,(not sho~n) and the expanded 64,000 bos is used locally 5 to drive, e.g., a tele~hone handset s~ea~er (not shown~.
The parallel-to-serial converter 60 is col~nected through a di~ital-to-analog conver~er 54 half o~ the A/D/~
converter 50 and a suitcase strap 56 to the out~ut Eilter half 4~.
The RMS analyzer ,oortion of the processor ~1 has a PDI section wllich provides an eight-bit control signal on line 42 to the A~C section 36, deQending upon the value of the root mean square (RMS) determined in the processor 41 during the compression ~unction, as 15 will be more fully ex21ained below.
Shown in ~igures 2 and 2A is a more detailed schematic view of the circuitry of ~igure 1. The ~wo-wire to four-~ire inter~ace contained with;n phantom lines 12 is shown to have an off-hook detector am~
20 ~ier 66, the negative in~ut 68 of which is connected to RING line 16 through a 160 Kohm resistor 72. The RING
line is connected to system ground, through a 47 ohm resistor 70. The negative input 68 of the am~lifier 6 is connected to system ground through a 1 microfarad 25 capacitor 74.
The positive input 76 of the amplifier 66 is connected to system supply voltge Vcc throu~h a 10 Kohm resistor 7~ and is connected to system ground through ~he parallel connection o a 1.6 Kohm resistor 80 and a .01 micro~arad capacitor 82. The output of ampliier 66 is connected to an OFF ~oo[~ line, whi~h gives an OFF
HOOK enabling sign~l to the analyzer 41 so~tware.
The two-wire to our-wire interface 12 i5 also shown to have a high voltage ringing circui~ connected 35 to 1~0V through a diode a4. The diode ~ is a lN4004 ... . , . ... . . _ _ , . , . _, . ..... _, .. , . ~ .. .
'7~
rectifier diode. The high volta~e ringing circuit includes transistors 86, B8 and 90O Transistor 86 is a PNP transistor, e.g., a 2N541S, having its base con-nected throu~h a 4.7 l~ohm resistor 92 to the diode 84 S and throu~h a 27 Kohm resistor 94 to the collector o~ an NPN transistor 90, e.g., a 2N3439 the elnitter of which is connected to ground. The emi~ter of the tran-sistor 8G is connected to the diode 84 through a 47 ohm resistor 98 and the collector o~ the transistor 86 is 10 connected through a 47 ohrn resistor 100 to the collector of an NPN transistor 88, e.g., a 2N3439, the emitter of which is connected to ground.
The bases o transistors 88 and 90 are connected to TTL level signals Ql~N~I and Q20NH through, 15 respectively, an 82 Kohm resistor 91 and a 360 ohm resistor 93.
A node 102 between the cbllector of the transistor 8~ and the resistor 100 is connected to a node 104 between the anode o~ a diode 106 and cathode of 20 a diode 108. The cathode o the diode 106 is connected to the cathode of the diode 84 and the anode of diode 108 is connected to ground, T'ne node 104 is connected to the TIP line and to the cathode o~ a diode 110, the anode of which is connected to a 25 node 112. Each of the diodes 106, 108 and llO are IN4004 diodes.
Node 112 is connected to a ~l2V bias supply through an 82 ohm resistor 11~ and an 82 ohm resis-tor 11~, a node 118 between which is connected to ground 30 through a .01 micro-farad capacitor 120. Node 112 is connected to the positive input 122 of an impedance matching hybrid o~erational amplifier 124 (hereina~ter n the hybrid operational ampliEier"). The negative input 125 o~ the hybrid operational ampli~ier 124 is 35 connected to node 112 through a 1.2 Kohm resistor 128 f~
and a 1.~ Kohm resis~or 126. The llybrid operational amplifier 124 has a negative feedback loop consisting o~
a Z7 ohm resistor 130, a 100 oh~ vari~ble resistor 132, a second lQ0 ohm variable resis~or 13~ and a second 5 27 ohm resistor 136, with a 55 millihenry inductor 138 connected between the varia~le resistors 132t 134 and the output o~ the hybrid operational amplifier 124. The output oE the hybrid o~erational amplifier 124 is con-nected to a node 144 through a 0.06~ microfarad capaci-10 tor 146 and a 9.1 Kohm resistor 148. ~ode 144 is theoutput 28 of two~wire-to-~our-wire inter~ace 12 and is connected to the output 30 of the four-wire interface 18, described in further detail below, through a 0.033 microEarad capacitor 140 and an 18 I'Co~-m resistor 142 Node 144 is connected to the negative input 150 of the spectrul~ shaping oper~tional ampli-ier 152 contained within section 32, the positive input 151 of which amplifier 152 is connected to ground.
The operational amplifier 152 has a negative ~eedback 20 loop to the negative input 150 through a 39.2 Kohm resistor 154. The output of the operational ampli-ier 152 is connected to switch 34, shown in Figure 2A, through a 0.068 microfarad capacitor 153.
One position of switch 34 directs the output 25 of operational amplifier 152 to the AGC circuit 36 and a 47 'Kohm ~GC input resistor 156 connected to ground. The AGC circuit 36 is, e.g., an AD7524 made by ~nalog Devices of Norwood, Massachusetts. The AGC circuI~ 36 has inputs D7-D0 from PDI pins PDI07-00 froln the 30 analyzer 41 (shown in Figure 1) and CS and WR inQutS
fro~ PDICS3 and PDI WRTL froM the analyzer 41, with the CS and ~R inputs also connected to Vcc through 1 Rohm resistors 155 and 157, respectively.
The output, OUT 1, of the AGC circuit 36 is connected to the VFXI input of an Intel 2912 filter 44, which V~XI- input is also connected to a second position o~ switch 3~ thro~gh the 47 Kohm ~GC bypass resis-tor 38. The output, OUT 1 of the AGC 36 is als? con-nected to ground through a zener diode 158 9 e.g., a lN57.11 diode made by Hewlett-Packard. The VFXI~ input to the filter 44 is groun~ed. The GSX pin oE the filter 44 is connected to RFB in the AGC circuit 36 through a 39 Kohm resistor 160. The Vcc pin oE the filter 44 is connected to YCC and also is connected to ground through a .01 Inicrofarad capacitor 162. The CLKO
pin o the filter 44 is connected to Vcc through a 1 Xohm resistor l66. The VFX output pin VFX0 of the 15 f ilter 44 is connected to the vFx in~ut of the analog-to-digital half 52 o~ the A/D/A converter S0 through a .3 micro~ara~ cap~citcr 164 and to th~ AUTO input pin o~
the A/~ converter through voltage dividing resis-tors 170, a 150 Kohm r~sistor, and 172, a 332 ohm resis-tor, and through a 475 ~ohm resistor 176, connected totne node 174 between the resistors 170 and 172. l'he A/D
converter 50 is an Intel 2911.
The V~RI input pin of the output hal~ 48 of the f ilter 4~ is connec~ed ~hrougll a switchcase strap or a switch 5O to either the VFX pin or the VFR pin o~ the A/D/A converter 50. The ClX and C2X pins of the A/D/A
converter are connected through a 2200 picofarad capaci-tor 178.
The CLKC pin of the filter 44 is connected to the IOCL~ line. The CLKC pin on the A/~ converter 50 is connected to Vcc through a l iCohm resistor 180. The TSX
pin on the A/D/A convert~r 50 i~ connected to the RE pin on the serial-to-parallel converter 58 and the CI pin on the parallel-to-serial converter 60, and also is con-35 nected to a +Sv source through a 1 l~ohm resistor lB6.
The C~x pin on the A/D/~ converter 50 is connecte~through an inverter lB2 to the CP pin on thc serial-to-parallel converter S8 and to the CLKR pin o~ the A/D/A
converter 50. The QH pLn of the parallel-to serial 5 converter 60 is connected to the DR pin of the A/D/A
converter 50. vcc o~ the A/D/A converter 50 is con-nected to Vcc across a .01 microfarad capacitor 184.
The Dx pin of the ~/D/A converter 50 is connected to the DA pin of the serial-to-parallel converte~r 580 The D~ pin o the serial-~o-parallel con-verter 53 is connected to the AD & NL line. The S/P, SE
and C~R pins of the serial-to-parallel converter 58 are connected to the PULLUP 2 line. A pair of flip-flops 188 and 190 serve to generate an interrupt signal 15 on the ADINT line and a reset signal on the ADRST line in response to a clock signal on the SRCLK line. This is a timing function to inform the analyzer 41 when data is ready to be sent from the serial-to-parallel con-verter 5~ and data is ready to be received by the 20 parallel-to-serial 60. Also the flip-flops 188 and 190 control the timing oE transfer of data from the A/D/A
converter 50 to or from the converters 58 and 60. The flip-flops 188 and 190 are connected to Vcc tl~rough a 1 Rohm resistor 191.
Negative voltage of -5v is supplied ~o VB~ of the filter 44 across a 1 microarad capacitor 192, and to VBB of the A/D/A converter 50, from an A79~105 volta~e regulator 194 (shown in Figure 2) made, ~or example, by Fairchild o~ Mountain View, California, which is sup-30 plied with -12v across a 2 microEarad capacitor 196.
As shown in ~igure Z the output VFR0 of filter 4~ ~or dri Ying the speaker in the telephone handset is connected throu~h a 10 Kohm variable resis-tor 198 and a 10 Xohm resis~or 200 to the ne~ative 35 input 202 of an operational amplifier 204, the positive ~$~
-12~
in~ut 206 o~ which is connected to ground through an 8.2 Xollm resistor 20~. The operational amplifier 204 has a feedback looo to the negative input 202 thereo throu~h a 27 Xohm resistor 210.
S ~he output of the operational amplifier 202 is connected to a node 212, which is connected to a node 214 bet~een the resistors 126 and 128, and forms the out2ut for the siynal to be passe~ throu~`n the t~o~
wire to four-~ire inter~ace to the TIP line 14 for 10 driving the tele~hone spea~er in the full duplex system on the tip line 14. Node 21~ is also connected to the four-wire interface 1~ through an 18 Rohm resistor 216.
The tele~hone speaker drive line 24 is connecte~ through a 619 ohm resis~or 230 to the output 15 Oe an operational amplifier 220, a negative in~ut 218 of which is connected to the resistor 216 and a positive in~ut 221 o~ which is connected to ground through a 13 Xohm resistor 2220 The operational amplifier 220 has a feedbacl~ loo~ connected to the negative in~ut 218, 20 including the parallel connection o~ ~ 9.1 Kohm resistor 228.
FIGURE 3 shows a block diagram of a synthe-si~er 249 contained in the processor 41 in the present invention. Durin~ each frame o~ 54 bits contained 25 within the 2,~00 bps received from the remote location via, e.g~, a modem (not shown), the synthesizer ~ortion o~ the processor 41 receives through a decoder 240 six bits of data re~resenting pitch, six bits of data`
representing gain, 1 sync bit, and 10 words of variable 30 bit length ~rom 5 to 2, totalling 40 bits of data erom which the synthesizer 249 contained in the processor 41 sotware, using the linear predictive algorithm, generates 180 ~oints defining the frequency spectrum envelope o~ the analog speech to he s~nthesize~. The 35 ~itch data is employed to drive an oscillator 250 at the -l3-~roper pitch. If pitch ~or that ~rame is 0, then an elec~ronic switch 252 in the synthesizer 249 is in the position to be supplied with random digital numbers, i.e., noise, Erom a random num~er generator 254. The 5 oscillator 250 is connected to the switch 252 through a filter 256 W)liC51 spreads the spectrum oE the oscil-lator 250 about its oscillating ~requency for better approximation of speech by tlle synthesizer 249. ~7hen the switch 252 is the ~osition si~own in ~GURE 3, the 10 voicing decision is a voiced decision and when it is in the pos ition to receiv~ noise, it is an unvoiced decision.
A filter 25~ is an adjustable digital Eilter, the outout of which is controlled ~y the 10 num~ers 15 de~ining the ~requency s~ectrum envelope for that frame, as generated by the synthesizer ~ortion of the processor 41. This results in an output of the filter 58 which corresponds quite closely to the analog speech signal in the time domain originally digitized 20 and compressed ~or transmission. This signal is amplified in a gain amplifier 260 accordin~ to the value of the gain (RMS) for tnat frame. Tilis value is equal to the measured RMS, which the analyzer 41 at a remote location com~uted in per~orlning the linear prediction 25 coding, ad~usted or the gain or attenuation, if any, introduce~ in the AGC section 32 at the remote location to ensure proper operation of the analyzer ~l at the remote location in compresslng the digitized voice at 64,000 bps to 2,400 bps by use o~ the linear prediction ~0 algorithm. There~ore it is the true gain necessary to duplicate the original analog speech in volu,~e.
The software implementation o~ automatic gain control at the speaker's end o~ the transmission link provided by the analyzer 41 at that end during voice 35 co,n~ression is shown in the ~low chart oE FIGUR~ 4.
,~odif ication of ~he yain in the AGC 3~ is dependent upon the RMS value in the analyzer 41. A programmed data processor or ilard wire~ large scale i,ntegrated circuit, e.g., a ~nicroprocessor controller in the analyzer 41 5 starting at start 300 (.~GAINC) f irst sets the valu2s for V~AX = 85, RANGE = .63096, IDE.~L = 512 and VINC = ~ in block 302. A decision is then made in block 3Q~ between whether the voicin~ decision in a given frame is a voiced decision or unvoiced decision, i.eO ~ is there a 10 pitch value or is pitch = 0. If it is unvoiced t'n~
count VCNT in an AGC accumul~tor within the micro-processor in the analyzer 41 is decremented by l in bl.ock 305. The count VCNT in the accumulator is then checked in bloc~ 306 to see if it is greater than or 15 equal to zero. If it is not greater than or equal to zero the count VCNT is set at zero in block 30~.
Returning to block 304, iE the decision is a voiced decision the AGCl loo~ is started at 310. The VCNT is incremented in block 312 by VINC which equals 4.
The present value of RMa i,n the analyzer 41, ARMS, is then compared in block 314 to see if it is ~reater than the most recent pe~k value ~VENG of ARMS. If it is greater, then AVENG is set to equal present AR~S in block 316 representiny now the most recent peak.
Regardless of whether AV~NG needs to be reset, the accu~ulated value oE the A~C accumulator VCNT is then compared in decision block 31a to see if it is less than the preselected value of VMAX, in this case 85~ it is, the no change T~OCHNG ins.ruction is initiated in block 320. The result oE the unvoiced instruction~ in blocks 305, 306 and 308 is also to ultima~ely initiate NOCHN~, as shown in ~IGURE 4.
Returning now to bloc~ 318, if VCNT is not less than VMAX~ VCNT is set to zero in block 320 and a decision is made whether ~o adjust the ~ain o~ the :~2~7~
AGC 36~ The most recent peak A~MS, AV~NG, is compared in block 322 to see if it is greater than or equal to ~enerally a midpoint selected value, IDEAL~ in this case 512, and also if the dif~erence between A~E~1G and IDEAL is less than or equal to some value, RANG~ If it is not > to ID~AL and the di~erence is not ~ RAtlGE then value GCNT in the gain accumulator is incremen~ed in block 32~ to GCN~ A~ter this, or if the decision in block 322 is a yes decision, then the DNTST instruc-tion is started in block 326~ In block 328 IDEAL iscompared to see if it is greater than or equal to AVENG
and if the difference between the AVENG and IDEAL is less than or equal to RANGE. If IDEAL is not less than or equal to AVENG, and tlle di'ference is not less than RANGE, the count GCNT is decremented by 1 in block 330.
Regardless of whether GCNT is decremented, the next instruction executed is to start NOCHNG at block 320.
If the count in the gain accumulator GcNr is less than 0 it is reset to 0 by the combin~tion of the steps in blocks 332 and 334. If GCNT is not less than 16 it is reset to 15 by the combination o the steps in blocks 336 and 338. The next instruction in block 339 provides for a look u~ in a memory table in the analyzer 41 of a gain control signal to be provided to the AGC 36 on lines PDI07-00 from the analyzer 41, based upon the value o~ GCNTo Thus the AGC controller in the analyzer 41 microprocessor assigns a value of -1 to unvoiced.deci- !
sions and +4 to voiced decisions. These are accumulated rom frame to frame during the processing by the ana-lyzer 41 for making gain adjustment decisions Eor use in the ~GC 36 and correspon~ to whether there was data in the respective ~rame indicating that pitch was present in the frame, as transmitted ~o the remote location in the Erame data. Only if VCNT e~ceeds V~AX is a gain ~'7 ~l~S~
change permitted. This ensures tnat a speech-li'~e si(~nal is present and that enough intervals have occurred on which to base a gain decision. Thus the AGC 36 in the apparatus oE the present invèntion i5 5 adjusted only in response to spe~ch signals and only to keep these signals within the range necessary for proper proc~ssing by the analyzer 41 in accordance with the linear predic~ive algorithm.
Once VCNT exceeds V~AX, an AGC 36 gain deci-10 sion is made and VCNT is then ~et to ~ero to preventrapid gain changes in the ~GC 36. The parameter used durin~ voiced intervals is the most recent ~eak ARMS in the analyzer 41 (AVENG) which is compared with the value representative of ~he desired RMS. The sign of the dif-15 ference, as determined in the software, determines thedirec~ion of the ~ain change~ No change is made if the magnitude of the difference is less than a preselected value, RANGE, since no change is needed if the magnitude of the difference is such that ~he measured ARMS energy 20 is close to the selected ID~AL. If the difference is yreater than the selected R~NGE then a one-step change of 2 db is made in the AGC 36, and AVENG is reset to zero so t~at the next measured ARMS will become AVENG.
The gain change is made by incrementing or 25 decrementing by one a four-bit counter GCNT within the micro~rocessor in the analyzer 41. The count GCNT in this counter is used witllin the so~tware in the ana-lyzer 41, used for controlling the AGC 36, to address a corresponding memory location and the new gain setting 30 contained therein is written to the AGC 36 on lines PDI07-00.
IDEAL is set at 512, which is half scale ~or the RMS parameter. RANGE is a multiplier ~63096 which corresponds to 4 db (~ = 20 lo~ ~1/o63096)~ V.YAX is 3s empirically set at 85.
, fY' 2~
The analyzer 41 receives data at 64,000 bps from the serial-to-parallel converter 58 and compresses this da~a according to the linear oredictive algorithm.
In the process it complltes RMS on a frame~by-~rame basis 5 and pereorms the decision-mal~ing process of ~rhether to adjust the ~ain of the AGC 36. The gain of the AGC 36 is thus a~ailable data ~or the anal~zer 41, whicn transmits, via, e.~, a modem (not shown~, the true yain (i.e~, the ARMS adjusted by whatever value the AGC 36 10 gain has been adjusted -to maintain the analyzer 41 in~
the proper range for accurately perforlning the linear prediction algorithl~) as par~ of the frame data, to an analyzer 41 a~ a remote location. Using the actual data or a rame, the analyzer 41 computes the best set of r 15 e.g~, 10 linear prediction algorithm factors, ~rom which the remote analyzer 41 can reconstruct the ~ull 1~0 poin~s o diqital data representing the frequency domain spectrum envelope or synthesis by a synthesizer 249 contained in the remote analyzer 41 to simulate a voice 20 si~nal which is an analog signal~
The analyzer 41 also receives compressed 2,400 bps data from a remote analyzer 41 via, eO~., a modem (not sho~n). Using this data, and the linear predictive algorithm, it generates a frequency domain 25 spectrum envelope for each frame. It also receives pitch and gain data for each frame and from the pitch, ~ain and envelope data it synthesizes in its synthesizer portion 24~ a 64,000 bps digital voice signal which is converted in the A/D/A convert~r 50 to drive the speaker 30 in the locaL telephone handset.
Echo suppression of the present inv~ntion is partially software implemented an~ includes also circuitry within the two-wire-to~our-wire interace 12 which unctions as an echo suppressor in the manner o~
35 balancing network couplers in the prior art. These employ transformers ~o accomL~lish echo suppression by balanciny impedances. The echo suppressor oE the present invention is particularly suited to the present system employing diyitized voice. In the inter~ace circuitry of the present invention the hybrid coupler of tlle prior art is replace~ with a hybrid coupling operational amplifier 124.
The source of echo in the interface circuitry of the present inven~ion is the two-wire to four-~ire load balancing circui~ including operational a~pli-fier 124. As the impedance of the two-wire load, i.e., the telephone, varies from the impe~ance ~ne balancing circuit expects to see, a larger amount of the synthe-sizer 249 output signal at node 21~ is re~lected into 13 the analog inQut to the analy~er ~1 through the soectrum shaping amplifier 32.
Because of the processing delay inherent in digital voice ~ransmission, especially employing data comQression and expansion, even small amounts of echo are annoying to the talker. The e~ho suppression em~loyed in the present invention effectively eli~inates this residual echo, and the flow chart for the software implementation is shown in ~IGURE 5 Echo suppression is carried out by a combina~
tion of the use of the balancing hybrid operational amplifier 124 and softwaee analysis of the near talker RMS in the analyzer 41, A~lS, and the far talker RMS in the synthesizer, 249, SR~S. Tllis d~termines whe~her the user at the respective end of the transmission link is tal'~ing or listening duriny each frame and accordingly attenuates ARMS or S~IS. This process begins in soEt-ware, e.g., in the analy~er 41, at STA~T 350. In deci-sion block 352 the ARMS is compared to see if it is greater tllan the most recent peak ARMS, iOe~ ~ ARMSP. If it is then the ARMSP value is set to the present ~R~S
~ 3 --1.9--value in block 3S4. Since decisions are made each Erame regarding which signal to suppress in order ko suppress echo effectively ~uring pauses and at the end o talk-ing, two delay functions are employed~ The first is to 5 hold ARMSP at its mos~ recent value ~or a selected timeO
This is done in block 354 hy setting the coun~ CACNT in an accumulator in the analy~er 41 to DCNT, equal to 16, and which CACNT is decremented by 1 each frame for a total of 16 frames, as long as ARMS is less than or 10 equal to ARMSP.
In decision block 356 SRMS is compared to SR~ISP, the most recent peak SRMS. If it is greater, then SRMSP is set to equal th~ present SRMS in ~_ ~ block 358. Also for the reasons explained above a delay 15 counter accumulator count CSCNT in an accumulator in the analyzer 41 is set to equal DCNT and is d~cremented by 1 once each frame for 16 frames as long as SRMS is less than or equal to SRMSP~
In decision block 360 CACNT is compared to 0 ~ and if less than or equal to 0 ARMSP is set at th~
present value o ARMS in block 362. This same function is performed in decision block 364 and block 366 with respect to CSCNT and SRMSP equal to the present SRMS.
A decision whether to at~enuate S~S is made 25 in decision block 368 by comparing ~RMSP to a value THRONE set at two-~iths scale, and also comparing to . _ .
see if ~RMSP is greater than or equal to SRMSP plus a raction of the hybrid loss HLOSS. The first condition makes certain that a reasonable volume of speech is 30 beiny transmitted/received and the second condition makes certain that the received energy is smaller, even when a correction is made for hybrid impedance mismatch.
I~ these conditions are met an attenua~ing counter for .
the synthesizer CNTA is set in block 370 at MAXCNT, 35 e.g., 16 and an attenuating counter ~or the analyzer ~ ~ 7 ~
CNTS is set to zero. This results in SRMS atten~ation at, e~g., 12 db each frame for as long as CNTA ls greater than 0.
Similarly if SRMSP is greater than THRONE and 5 S~1SP is greater than ARMSP ~ RLOSS a decision is made an decision block 372 which results in block 374 in the setting of an attenuating counter CNTS for the analyzer at MAXCNT and the attenuating counter C~TA for the synthesizer at 0, to attenuate ARMS for a selected 10 number of frames as C~lTS decrements each frame from ~ MAXCNT which may be, e.g., 16.
Moving on to FIGURE SA it is seen that ARMSP
and SRMSP are then com~ared in decision blocks 376 and 380, respectively, with a second threshold value THRTWO, 15 equal to four-fifths scale. If either is greater than this value then, respectively, the far talker or near talker is interrupting and attenuation must be accord-ingly removed. This is done in blocks 378 and 382 by setting, respectively, CNTS or CNTA equal to 0.
Decision blocks 384 and 386 control the actual attenuation so long as, respectively, CNTA is greater than 0 or CNTS is greater than 0. In the former event SRMS is set in block 386 to equal S~MS minus, e.g., 12 db and in the latter event ARMS is set in block 390 25 to equal ARMS minus, e.g., 12 db.
The decrementing ~unction is performed in block 392 by setting CNTA, CNTS, CACNT and CSCNT each equal to their respective values minus 1. The program then returns to ST~RT from RETURN 394, to begin process-3Q ing the data for the next frame.
Thus it can be seen that the software at eachend of the transmission link functions to attenuate the proper value, either SRMS or ARMS dependin~ on whether the near talker or far tal~er, as perceived by each 35 respective end of the transmission link, is the actual ~7,~
talker, the other signal~ either SR~S or ARMS, being thereby deter~ined to be echo and being attenuated to suppress the echo.
Echo suppression also occurs in the four-wire 5 interface section o~ the two-wire to four-wire con-verter. The voltage at node 112~ V112 is given by equation 1, ~T~126 ~ VSZT (1) V112 =
where: VT - telephone~MIC output voltaye ZT ~ telephone impedance VS = voltage at the output of operational amplifier 204 (the synthesizer output) Since ~he operational amplifier 124 is operat-ing with negative feedback, its negative input will track the positive input. A second node equation at the output of the ampliier 124 yieldsO-V112 - ~o + V112 ~ VS
Rf R128 -- (2) where. Vo is ~he voltage at the output o the operational amplifier 124 (the analyzer input) Rf is the equivalent resistance of the feed-back resistance inductance network o the operation amplifier 124~
, .. . . .
7~
Substitutin~ for Vllz from equation 1 yieldsO
= Vs [(~; ) ( f 128) R128 T (R 12 6 + Z T ) (Rf Rl 28) For proper operation there should be no Vs signal componen~ in Vo. For ~his ~co occur, the first 10 term on the right side o~ equa~ion 3 must equal zero.
That term equals zero when:
ZT Rf R126 + ~T R128 ~ Rf .15 In the design o the present invention, th.is requirement is sa'cisf ied u~ing Rf = ZT and R128 ~ R126 ~
Substituting these values into equation 3 yields V~ as a function of the microphone signal:
V~ - VT
In order to empirically match ZT~ measurements were taken of the telephone im~edance over the range oE
25 about 100 to 4000 Hz at a bias current of 16 ma. From tlliS data a matchin~ network according to the present invention was synthesized. Since telephone impedances vary from unit to unit, two adjustments are included in the network by way o the variable resistors 132 and 134 30 and 198 in order to improve the nominal matching.
The per~ormance o~ the two-wire to four-wire converter 12 is more critical in the present invention than in a normal telephone channel since the processing delay inherent in the use o~ digitized voice 1,rill produce suff icient delay in the ect~o path oE the con-verter 12 (synthesizer out to analyzer in) to ~isturb the normal cadence of the talker.
Once adjusted, the circuit yields approxi-mately 40 dB of loss in the echo pat~l across the 100 to 4000 ~z spectrum. To null ~he circuit a signal (1000 Hz, sinusoidal, .814 VRMS~ is inser,~ed at the center ~ost o~ suitcase strap 56 (with the strap 10 removed). V~riable resistor 198 is adjusted (Rx Gain~
Pot) to produce 1.1 * .2 VRMS at tlle output of ampli-fier 2Q4. This adjusts the receive gain and provides a re~erence signal ~or the two-wire to four-wire balance adjustment. The balance adjustment must be made with 15 the telephone connected to the RING and TIP lines an~
with OFF ~00~ activated. ~onitoring the output of the amplifier 152, varia~le resistor 132 and 134 are adjusted to null the signal at that point. The signal level at that point should be at least 35 dB lower than 20 at the output of amplifier 2040 The principal features of the operation oE the present invention will be no~ described with re~erence to FIGURES 2 and 2A. Bias current for the teleæhone is produced using a series resistor network 116 and 114 to 25 +12 volts with a decoupling capaeitor 120 to qround.
The ring driver 15 consists o~ a totem pole driver circuit which includes transistors 86, 88 and 90 and associ~ted discrete components. The circuit uses the TTL level signals QlONH and Q20NI{ to alternately 30 switch the TIP line between 180V and ground. The design of the TTL drive signals includes a "dead time" be~ween state chan~s in which both transistor 88 and transis-tor 86 are o~f.
Diodes 108 and 106 limit the spiking whic~
~ccurs when the current in the bell coil of the tele-phone (not shown~ tries to change ra~idly. Diode 110 isolates the ringing voltage from the two-wire to four 5 wire converter 12. When the rin~ driver 15 is active the voltage at node 112 will swing from 0 to ~12~, at which point diode 110 turns off, w~ile the cathode side of diode 110 continues toward 180V.
When the ring driver 15 is inactive both halves of the totem pole driver circuit are of, thereby presenting a very high i~pedance to the TIP line and having no e~ect on the two-wire ~o four-wire conver-ter 12 balance.
_~ The hookswitch status detection is accom-15 plished by the amplifier 6~ and its associated discrete components. Resistor 70 is a ~C current sense resistor.
The voltage across resistor 70 is low pass filtered at 1 Hz by resistor 72 and capacitor 74 and compared ~via amplifier 66) to a fixed threshold at the junction o~
resistors 78 and 80. In operation there are four combinations of ring state and hookswitch status which the status detection circuitry must recognize. Each combination is descri~ed below.
1. Ring Active, ON HOOK - for this state (which occurs when a call is received) the TIP and RING
leads are AC coupled through the telephone bell circuit, The voltage across the sense resistor 70 is therefore an AC slgnal ~f approximately 20 Hz). The 1 H~ LPF (resis-tor 72 and capacitor 74) prevents excursions of this signal from exceeding the threshold and the ONHOOK
status does not change.
2. Rinq Active, OFF HOOK - in this state (which occurs when a call is answered) the TIP and RING
lines are DC coupled throu~h the telephone. The LPF
3S capacitor ~ charges to the average value o the ring signal, which exceeds the preselected threshold and generates the OFF~OOK status, which should then be sensed by software to turn o~f the rifig signal.
3. Ring Inactive ON HOOK - in this state S (which occurs when the telephone is no longer being used) the TIP and RING lines are again AC c.oupled . No bias current can flow through the TI~ and RING lines and the vol~age across resistor 70 dro~s belo~ the threshold (to ~V) producing the ON HOOIC indic~tion.
- 10 4. R ng Inactive,_OFF HOO~ - in this state -tWhiCh occurs when a call-is initiated or in-progress) the TIP and RING lines are DC coupled. Bias current flows throuyh resistor 70 producing a voltage approxi-mately twice the thresllold voltage at the LP~ capaci-15 tor 82 output which ~roduces the OFF HOgK status.
The sp~ctru~ shaping ampliEier 32 provides anyanalog pre/de-emphasis which may be desirable for the transmit audio~ It also sums the transmit analog signals from both the two-wire and four-wire inQUts.
20 The circuit is AC coupled, via capacitors 1~6 and 140 to, respectively, the interfaces 12 and 1~ to remove the DC volta~e resulting ~rom the telephone bias currents.
The gains oE the two-wire and four-wire transmit paths can be set independently using resistor 148 and resis-25 tor 142 respectively. The nominal gain of the inteL-faces are 14.3 dB for the two-wire path in interface 12 and 3 dB for the four-wire path in interface 180 The gains are set so that the signal peaXs between capaci-tor 153 and swi~ch 34 reacil approximately 3 volts when 30 speaking at a normal level. The output oE the spectrum shaping amplifier 152 is AC couple~ through capaci-tor 153 to the AGC circuit 36 to prevent a DC offset voltage from causing unnecessary transitions in the AGC 36 output signal as the gain is changed.
'7~
The AGC circuit 36 and input filter 46 portion of the filter 44 are described together in f~rther detail here, as shown in FIGURE 6, because a ladder network contained in the AGC 36 circuit and an input 5 operat;onal amplifier 375 contained in the filter 44.are interconnected to ~orm a composite gàin block. The equi~alent circuit for the AGC 36 and a portion of the input filter 46 circuit within the filter 44 is shown in YIGURE 6.
Within the AGC circuit 36 is a eedback resistor 376 which, toget~ler wi~h feed~ack resistor 160 acts as a negative feedback loop for operational ampli-fier 375. The AGC circuit 36 and the operational am~
fier 375 also have an input resistor 378.
The gain of this AGC 36 and filter 44 circuit from EIN at switch 34 to Eo at V~x at the output of the operational ampli~ier 375 in the filter circuit 44 VFxOis Eo D /R160 ~ R376 G EIN 256 \ R378 where D is the digital code loaded into the AGC 36 (0 <
D < 255) on pins PDI07-00 and resistors 3~6 and 378 are 25 nominall~ 10 Kohms~ A digital-to-analog converter 380 in the AGC 36 circuit is connected to a precision refer-ence voltage Vref and provides a current output repre-sentative oE the value 256 ~ 1 where D is ~he digital input to the AGC 36 on PDI07-00 from the analyzer 41.
In operation the AGC 36 and input filter 46 circuits cover a gain range of 30 d~ ~14 dB to 16 d~)~
in 2 dB steps, although the hardware is capable o~
greater range and finer resolution. Table 1 lists the values of D stored in the memory in the analyze~ 41 ~27-corresponding to respective ~our-bit counts t0-15 decimal) from the AGC controller accumulator GCNT in the analyzer 41/ along with the-corresponding gains based on ~he component values used in the A~C 36 and the 5 input fal~er 46 circuits.
The remainder o~ the in~ut ilter 46 inte-grated circuit.actually per~orms the low pass filter function in filter 3B0 and introduces ~3 dB gain in the passband. The inout filter 46 output on pin 16 (VFxO) 10 of f ilter 44 is therefor~ 3 dB higher than the values shown in Table 1.
Table 1. ~GC/Filter Gain Set~ings . GCNT D Gain in dB
0 255. ~ 13.8 1 203. ~7 2 162. +9.8 3 12~. ~7.8
In accordance with the present invention there is provided a digital communication apparatus for transmitting and receiving a compressed digital representation of speech produced by a near talker and a far talker respectively, said compressed digital speech representation including a coded gain parameter related to speech energy~ said apparatus comprising:
transmission gain detection means for reading the gain parameter of said near talker's digital speech representation;
receiver gain detection means for reading the gain parameter of said ar talker's digital speech representation;
means for reducing the gain parameter of said far talker's digital speech representation when a recent peak gain parameter in said near talker's speech representation is greater than both (1) a first selected threshold and 12) the gain parameter of said far talker's speech representation plus a selected nonzero compensation value; and means for reducing the gain parameter of said near talker's digital speech representation when a recent peak gain parameter in said far talker's digital speech representation is greater than both (1) said first selected threshold and (2) the gain parameter of said near talker's digital speech representation plus said selected nonzero compensation value.
Preferably the said apparatus also comprises a near talker interrupt detection means for removing the reduction of the gain parameter of the near talker digital speech representation responsive to detecting whether the gain parameter of the near talker's digital speech representation exceeds a seco~d selected threshold; and, a far talker interrupt detection means for removing the reduction of the gain parameter of the far talker's digital speech representation responsive to detecting whether the gain parameter of the far talker's digital speech representation exceeds the second selected threshold.
~ ' - 4a -Also in accordance with the invention there is provided a method of echo suppression in a digital communication link, said digital communication link com~unicating a compressed digital representation of speech produced by a near talker and a far S talker, said compressed digital speech representation including a coded gain parameter related to speech energy, ~he method comprising the steps of:
reducing ~he gain parameters of said near talker or far talker digital spee~h representation of one end of the communication link in accordance with which of said gain parameters has the lesser magnitude;
reducing the gain parameter of said near talker or far talker digital speech representation at the other end of the communication link in accordance with which of said gain parameters has the lesser magnitude;
the reducing steps including the steps of:
reducing the gain parameter of said far talker's digital speech representation when a recent peak gain parameter in said near talker's digital speech representation is greater than both (1) a first selected threshold and (2) the gain parameter of said far talker's digital speech representation plus a selected nonzero compensation value and reducing the gain parameter of said near talker's digital speech representation when a recent peak gain parameter in said far talker's digital speech representation is greater than both (1) said first selected threshold and (2) the gain parameter of said near talker's digital speech representation plus said selected nonzero compensation value.
A preferred embodiment of the invention will now be described in connection with the accompanying drawings, wherein like reference numerals have been applied to like elements, in which:
3~
BRIEF DESCRI PTION OF THE DRAWINGS
~ IGURE 1 shows a ~lock dia~ram o~ an ~nalog input/output circuit foe digitized voice compression/
expansion and employing the automatic gain controL and 5 echo suQ)ression features of the present invention;
FIGURES 2 and 2~ are a more detailed schematic diagram o the circuit o~ Figure l;
FIGUR~ 3 shows a block diagram of a digital voice synthesi7er employed in the receiver o~ a voice 10 transmission link using the present invention;
FIGURE 4 sho~s a flow chart for sotware implementation o autom~ic gain control in accordance with the present invention;
FIGURES 5 and SA show a flow chart for soft-15 ~are implementation o echo suppression in accordance with tlle present invention.
FI~URE 6 shows a further de~ail of the auto-matic gain control circuit according to the present invention; and, FIGURE 7 shows the timing o~ an analog-digital/di~ital-analog converter in accordance with the present invention.
Shown in ~i~ure l is a bloc~ diagram of an analog input~output circuit 10 for digitized voice co~-25 pression and expansion in accordance with the present invention. The circuit 10 is adapted for connection either to a two-wire or ~our-wire telephone transmission link and thus has a two-wire to four-wire intera~e 12 and a ~our-wire inter~ace l~. The two-wire to four-wire 30 inter~ace L2 is connected ~o two-wire telephone trans-mission lines 14 and i6. The ~our-wire inter~ace l~ is connected to a telephone receive lin~ 20, having an associated ground connection 22, and a telephone trans~
mission link 24, having an associated ground connec-35 tion 26.
t ^ ~ ~r :~, : -6-Each o~ the two-wire ~o Eour-wire inter~ace 12 and ~our-wire interface 18 is connected to a spectrum shapin~ am~lifier 32. The s~ectrum shaping ampliÇier 32 is connec~ed throu~h a suitcase strap or a selector 5 switch 34 to an automatic gain control (AGC) section 36, with the switch 3~ also having a position selecting an AGC 3G bypass throug~l a 47 Kohm bypass resistor 380 The OUtQUt of the AGC 36 section an~ the bypass resistor 38 are connected to the input filter half 46 of the band-10 pass filter 44 which passes only ener~y.in the telepho~eline bandwidth from about 300-3000 Hz. The outpu~
filter half 48 of the same bandpass filter 44 is connected to the telephone handset speaker input ~9.of the two-wire to four-wire inter~ace 12 and to the .15 telephone handset speaker input 51 of the four-wire in~erEace 18.
The input filter 46 is connected to an analog-to-diyital converter half 52 of an analog-to-digital/
digital-to-analog converter 50 (~/D/A converter), the 20 output of which is serialized digital data at 64,000 bps, re~resentative of the analog input to the analog-to-digital half 52. This serialized data at 64,000 bps is passed to a serial~to-parallel converter 58 which provides an 8-bit word on output line 62 to an RMS
25 linear prediction analyzer portion o~ a linear predic-tion processor 41. The linear prediction analyzer portion of the processor 41 per~orms the compression of the 64,000 bps output o~ the serial-to-parallel con verter 58 to 2,400 bps for transmission and a linear 30 prediction synthesizer portion oE the processor ~1 perEorms an expandin~ conversion o~ 2,400 bps received data to eigllt-bit words at 64,000 bps, which is an input on line 64 to a parallel-to~serial converter 60. The 2,400 bits as compressed by the processor 41 is trans-35 mitted via, e.g., a modem (not sho-ln) to a remote l~z~'7;~
location, and th~ 2,400 bps as expanded by the synthe-sizer portio~ o the processor ~1 is that wl~ich has been .received ro~ a remote location, e~g.' through a modem, ,(not sho~n) and the expanded 64,000 bos is used locally 5 to drive, e.g., a tele~hone handset s~ea~er (not shown~.
The parallel-to-serial converter 60 is col~nected through a di~ital-to-analog conver~er 54 half o~ the A/D/~
converter 50 and a suitcase strap 56 to the out~ut Eilter half 4~.
The RMS analyzer ,oortion of the processor ~1 has a PDI section wllich provides an eight-bit control signal on line 42 to the A~C section 36, deQending upon the value of the root mean square (RMS) determined in the processor 41 during the compression ~unction, as 15 will be more fully ex21ained below.
Shown in ~igures 2 and 2A is a more detailed schematic view of the circuitry of ~igure 1. The ~wo-wire to four-~ire inter~ace contained with;n phantom lines 12 is shown to have an off-hook detector am~
20 ~ier 66, the negative in~ut 68 of which is connected to RING line 16 through a 160 Kohm resistor 72. The RING
line is connected to system ground, through a 47 ohm resistor 70. The negative input 68 of the am~lifier 6 is connected to system ground through a 1 microfarad 25 capacitor 74.
The positive input 76 of the amplifier 66 is connected to system supply voltge Vcc throu~h a 10 Kohm resistor 7~ and is connected to system ground through ~he parallel connection o a 1.6 Kohm resistor 80 and a .01 micro~arad capacitor 82. The output of ampliier 66 is connected to an OFF ~oo[~ line, whi~h gives an OFF
HOOK enabling sign~l to the analyzer 41 so~tware.
The two-wire to our-wire interface 12 i5 also shown to have a high voltage ringing circui~ connected 35 to 1~0V through a diode a4. The diode ~ is a lN4004 ... . , . ... . . _ _ , . , . _, . ..... _, .. , . ~ .. .
'7~
rectifier diode. The high volta~e ringing circuit includes transistors 86, B8 and 90O Transistor 86 is a PNP transistor, e.g., a 2N541S, having its base con-nected throu~h a 4.7 l~ohm resistor 92 to the diode 84 S and throu~h a 27 Kohm resistor 94 to the collector o~ an NPN transistor 90, e.g., a 2N3439 the elnitter of which is connected to ground. The emi~ter of the tran-sistor 8G is connected to the diode 84 through a 47 ohm resistor 98 and the collector o~ the transistor 86 is 10 connected through a 47 ohrn resistor 100 to the collector of an NPN transistor 88, e.g., a 2N3439, the emitter of which is connected to ground.
The bases o transistors 88 and 90 are connected to TTL level signals Ql~N~I and Q20NH through, 15 respectively, an 82 Kohm resistor 91 and a 360 ohm resistor 93.
A node 102 between the cbllector of the transistor 8~ and the resistor 100 is connected to a node 104 between the anode o~ a diode 106 and cathode of 20 a diode 108. The cathode o the diode 106 is connected to the cathode of the diode 84 and the anode of diode 108 is connected to ground, T'ne node 104 is connected to the TIP line and to the cathode o~ a diode 110, the anode of which is connected to a 25 node 112. Each of the diodes 106, 108 and llO are IN4004 diodes.
Node 112 is connected to a ~l2V bias supply through an 82 ohm resistor 11~ and an 82 ohm resis-tor 11~, a node 118 between which is connected to ground 30 through a .01 micro-farad capacitor 120. Node 112 is connected to the positive input 122 of an impedance matching hybrid o~erational amplifier 124 (hereina~ter n the hybrid operational ampliEier"). The negative input 125 o~ the hybrid operational ampli~ier 124 is 35 connected to node 112 through a 1.2 Kohm resistor 128 f~
and a 1.~ Kohm resis~or 126. The llybrid operational amplifier 124 has a negative feedback loop consisting o~
a Z7 ohm resistor 130, a 100 oh~ vari~ble resistor 132, a second lQ0 ohm variable resis~or 13~ and a second 5 27 ohm resistor 136, with a 55 millihenry inductor 138 connected between the varia~le resistors 132t 134 and the output o~ the hybrid operational amplifier 124. The output oE the hybrid o~erational amplifier 124 is con-nected to a node 144 through a 0.06~ microfarad capaci-10 tor 146 and a 9.1 Kohm resistor 148. ~ode 144 is theoutput 28 of two~wire-to-~our-wire inter~ace 12 and is connected to the output 30 of the four-wire interface 18, described in further detail below, through a 0.033 microEarad capacitor 140 and an 18 I'Co~-m resistor 142 Node 144 is connected to the negative input 150 of the spectrul~ shaping oper~tional ampli-ier 152 contained within section 32, the positive input 151 of which amplifier 152 is connected to ground.
The operational amplifier 152 has a negative ~eedback 20 loop to the negative input 150 through a 39.2 Kohm resistor 154. The output of the operational ampli-ier 152 is connected to switch 34, shown in Figure 2A, through a 0.068 microfarad capacitor 153.
One position of switch 34 directs the output 25 of operational amplifier 152 to the AGC circuit 36 and a 47 'Kohm ~GC input resistor 156 connected to ground. The AGC circuit 36 is, e.g., an AD7524 made by ~nalog Devices of Norwood, Massachusetts. The AGC circuI~ 36 has inputs D7-D0 from PDI pins PDI07-00 froln the 30 analyzer 41 (shown in Figure 1) and CS and WR inQutS
fro~ PDICS3 and PDI WRTL froM the analyzer 41, with the CS and ~R inputs also connected to Vcc through 1 Rohm resistors 155 and 157, respectively.
The output, OUT 1, of the AGC circuit 36 is connected to the VFXI input of an Intel 2912 filter 44, which V~XI- input is also connected to a second position o~ switch 3~ thro~gh the 47 Kohm ~GC bypass resis-tor 38. The output, OUT 1 of the AGC 36 is als? con-nected to ground through a zener diode 158 9 e.g., a lN57.11 diode made by Hewlett-Packard. The VFXI~ input to the filter 44 is groun~ed. The GSX pin oE the filter 44 is connected to RFB in the AGC circuit 36 through a 39 Kohm resistor 160. The Vcc pin oE the filter 44 is connected to YCC and also is connected to ground through a .01 Inicrofarad capacitor 162. The CLKO
pin o the filter 44 is connected to Vcc through a 1 Xohm resistor l66. The VFX output pin VFX0 of the 15 f ilter 44 is connected to the vFx in~ut of the analog-to-digital half 52 o~ the A/D/A converter S0 through a .3 micro~ara~ cap~citcr 164 and to th~ AUTO input pin o~
the A/~ converter through voltage dividing resis-tors 170, a 150 Kohm r~sistor, and 172, a 332 ohm resis-tor, and through a 475 ~ohm resistor 176, connected totne node 174 between the resistors 170 and 172. l'he A/D
converter 50 is an Intel 2911.
The V~RI input pin of the output hal~ 48 of the f ilter 4~ is connec~ed ~hrougll a switchcase strap or a switch 5O to either the VFX pin or the VFR pin o~ the A/D/A converter 50. The ClX and C2X pins of the A/D/A
converter are connected through a 2200 picofarad capaci-tor 178.
The CLKC pin of the filter 44 is connected to the IOCL~ line. The CLKC pin on the A/~ converter 50 is connected to Vcc through a l iCohm resistor 180. The TSX
pin on the A/D/A convert~r 50 i~ connected to the RE pin on the serial-to-parallel converter 58 and the CI pin on the parallel-to-serial converter 60, and also is con-35 nected to a +Sv source through a 1 l~ohm resistor lB6.
The C~x pin on the A/D/~ converter 50 is connecte~through an inverter lB2 to the CP pin on thc serial-to-parallel converter S8 and to the CLKR pin o~ the A/D/A
converter 50. The QH pLn of the parallel-to serial 5 converter 60 is connected to the DR pin of the A/D/A
converter 50. vcc o~ the A/D/A converter 50 is con-nected to Vcc across a .01 microfarad capacitor 184.
The Dx pin of the ~/D/A converter 50 is connected to the DA pin of the serial-to-parallel converte~r 580 The D~ pin o the serial-~o-parallel con-verter 53 is connected to the AD & NL line. The S/P, SE
and C~R pins of the serial-to-parallel converter 58 are connected to the PULLUP 2 line. A pair of flip-flops 188 and 190 serve to generate an interrupt signal 15 on the ADINT line and a reset signal on the ADRST line in response to a clock signal on the SRCLK line. This is a timing function to inform the analyzer 41 when data is ready to be sent from the serial-to-parallel con-verter 5~ and data is ready to be received by the 20 parallel-to-serial 60. Also the flip-flops 188 and 190 control the timing oE transfer of data from the A/D/A
converter 50 to or from the converters 58 and 60. The flip-flops 188 and 190 are connected to Vcc tl~rough a 1 Rohm resistor 191.
Negative voltage of -5v is supplied ~o VB~ of the filter 44 across a 1 microarad capacitor 192, and to VBB of the A/D/A converter 50, from an A79~105 volta~e regulator 194 (shown in Figure 2) made, ~or example, by Fairchild o~ Mountain View, California, which is sup-30 plied with -12v across a 2 microEarad capacitor 196.
As shown in ~igure Z the output VFR0 of filter 4~ ~or dri Ying the speaker in the telephone handset is connected throu~h a 10 Kohm variable resis-tor 198 and a 10 Xohm resis~or 200 to the ne~ative 35 input 202 of an operational amplifier 204, the positive ~$~
-12~
in~ut 206 o~ which is connected to ground through an 8.2 Xollm resistor 20~. The operational amplifier 204 has a feedback looo to the negative input 202 thereo throu~h a 27 Xohm resistor 210.
S ~he output of the operational amplifier 202 is connected to a node 212, which is connected to a node 214 bet~een the resistors 126 and 128, and forms the out2ut for the siynal to be passe~ throu~`n the t~o~
wire to four-~ire inter~ace to the TIP line 14 for 10 driving the tele~hone spea~er in the full duplex system on the tip line 14. Node 21~ is also connected to the four-wire interface 1~ through an 18 Rohm resistor 216.
The tele~hone speaker drive line 24 is connecte~ through a 619 ohm resis~or 230 to the output 15 Oe an operational amplifier 220, a negative in~ut 218 of which is connected to the resistor 216 and a positive in~ut 221 o~ which is connected to ground through a 13 Xohm resistor 2220 The operational amplifier 220 has a feedbacl~ loo~ connected to the negative in~ut 218, 20 including the parallel connection o~ ~ 9.1 Kohm resistor 228.
FIGURE 3 shows a block diagram of a synthe-si~er 249 contained in the processor 41 in the present invention. Durin~ each frame o~ 54 bits contained 25 within the 2,~00 bps received from the remote location via, e.g~, a modem (not shown), the synthesizer ~ortion o~ the processor 41 receives through a decoder 240 six bits of data re~resenting pitch, six bits of data`
representing gain, 1 sync bit, and 10 words of variable 30 bit length ~rom 5 to 2, totalling 40 bits of data erom which the synthesizer 249 contained in the processor 41 sotware, using the linear predictive algorithm, generates 180 ~oints defining the frequency spectrum envelope o~ the analog speech to he s~nthesize~. The 35 ~itch data is employed to drive an oscillator 250 at the -l3-~roper pitch. If pitch ~or that ~rame is 0, then an elec~ronic switch 252 in the synthesizer 249 is in the position to be supplied with random digital numbers, i.e., noise, Erom a random num~er generator 254. The 5 oscillator 250 is connected to the switch 252 through a filter 256 W)liC51 spreads the spectrum oE the oscil-lator 250 about its oscillating ~requency for better approximation of speech by tlle synthesizer 249. ~7hen the switch 252 is the ~osition si~own in ~GURE 3, the 10 voicing decision is a voiced decision and when it is in the pos ition to receiv~ noise, it is an unvoiced decision.
A filter 25~ is an adjustable digital Eilter, the outout of which is controlled ~y the 10 num~ers 15 de~ining the ~requency s~ectrum envelope for that frame, as generated by the synthesizer ~ortion of the processor 41. This results in an output of the filter 58 which corresponds quite closely to the analog speech signal in the time domain originally digitized 20 and compressed ~or transmission. This signal is amplified in a gain amplifier 260 accordin~ to the value of the gain (RMS) for tnat frame. Tilis value is equal to the measured RMS, which the analyzer 41 at a remote location com~uted in per~orlning the linear prediction 25 coding, ad~usted or the gain or attenuation, if any, introduce~ in the AGC section 32 at the remote location to ensure proper operation of the analyzer ~l at the remote location in compresslng the digitized voice at 64,000 bps to 2,400 bps by use o~ the linear prediction ~0 algorithm. There~ore it is the true gain necessary to duplicate the original analog speech in volu,~e.
The software implementation o~ automatic gain control at the speaker's end o~ the transmission link provided by the analyzer 41 at that end during voice 35 co,n~ression is shown in the ~low chart oE FIGUR~ 4.
,~odif ication of ~he yain in the AGC 3~ is dependent upon the RMS value in the analyzer 41. A programmed data processor or ilard wire~ large scale i,ntegrated circuit, e.g., a ~nicroprocessor controller in the analyzer 41 5 starting at start 300 (.~GAINC) f irst sets the valu2s for V~AX = 85, RANGE = .63096, IDE.~L = 512 and VINC = ~ in block 302. A decision is then made in block 3Q~ between whether the voicin~ decision in a given frame is a voiced decision or unvoiced decision, i.eO ~ is there a 10 pitch value or is pitch = 0. If it is unvoiced t'n~
count VCNT in an AGC accumul~tor within the micro-processor in the analyzer 41 is decremented by l in bl.ock 305. The count VCNT in the accumulator is then checked in bloc~ 306 to see if it is greater than or 15 equal to zero. If it is not greater than or equal to zero the count VCNT is set at zero in block 30~.
Returning to block 304, iE the decision is a voiced decision the AGCl loo~ is started at 310. The VCNT is incremented in block 312 by VINC which equals 4.
The present value of RMa i,n the analyzer 41, ARMS, is then compared in block 314 to see if it is ~reater than the most recent pe~k value ~VENG of ARMS. If it is greater, then AVENG is set to equal present AR~S in block 316 representiny now the most recent peak.
Regardless of whether AV~NG needs to be reset, the accu~ulated value oE the A~C accumulator VCNT is then compared in decision block 31a to see if it is less than the preselected value of VMAX, in this case 85~ it is, the no change T~OCHNG ins.ruction is initiated in block 320. The result oE the unvoiced instruction~ in blocks 305, 306 and 308 is also to ultima~ely initiate NOCHN~, as shown in ~IGURE 4.
Returning now to bloc~ 318, if VCNT is not less than VMAX~ VCNT is set to zero in block 320 and a decision is made whether ~o adjust the ~ain o~ the :~2~7~
AGC 36~ The most recent peak A~MS, AV~NG, is compared in block 322 to see if it is greater than or equal to ~enerally a midpoint selected value, IDEAL~ in this case 512, and also if the dif~erence between A~E~1G and IDEAL is less than or equal to some value, RANG~ If it is not > to ID~AL and the di~erence is not ~ RAtlGE then value GCNT in the gain accumulator is incremen~ed in block 32~ to GCN~ A~ter this, or if the decision in block 322 is a yes decision, then the DNTST instruc-tion is started in block 326~ In block 328 IDEAL iscompared to see if it is greater than or equal to AVENG
and if the difference between the AVENG and IDEAL is less than or equal to RANGE. If IDEAL is not less than or equal to AVENG, and tlle di'ference is not less than RANGE, the count GCNT is decremented by 1 in block 330.
Regardless of whether GCNT is decremented, the next instruction executed is to start NOCHNG at block 320.
If the count in the gain accumulator GcNr is less than 0 it is reset to 0 by the combin~tion of the steps in blocks 332 and 334. If GCNT is not less than 16 it is reset to 15 by the combination o the steps in blocks 336 and 338. The next instruction in block 339 provides for a look u~ in a memory table in the analyzer 41 of a gain control signal to be provided to the AGC 36 on lines PDI07-00 from the analyzer 41, based upon the value o~ GCNTo Thus the AGC controller in the analyzer 41 microprocessor assigns a value of -1 to unvoiced.deci- !
sions and +4 to voiced decisions. These are accumulated rom frame to frame during the processing by the ana-lyzer 41 for making gain adjustment decisions Eor use in the ~GC 36 and correspon~ to whether there was data in the respective ~rame indicating that pitch was present in the frame, as transmitted ~o the remote location in the Erame data. Only if VCNT e~ceeds V~AX is a gain ~'7 ~l~S~
change permitted. This ensures tnat a speech-li'~e si(~nal is present and that enough intervals have occurred on which to base a gain decision. Thus the AGC 36 in the apparatus oE the present invèntion i5 5 adjusted only in response to spe~ch signals and only to keep these signals within the range necessary for proper proc~ssing by the analyzer 41 in accordance with the linear predic~ive algorithm.
Once VCNT exceeds V~AX, an AGC 36 gain deci-10 sion is made and VCNT is then ~et to ~ero to preventrapid gain changes in the ~GC 36. The parameter used durin~ voiced intervals is the most recent ~eak ARMS in the analyzer 41 (AVENG) which is compared with the value representative of ~he desired RMS. The sign of the dif-15 ference, as determined in the software, determines thedirec~ion of the ~ain change~ No change is made if the magnitude of the difference is less than a preselected value, RANGE, since no change is needed if the magnitude of the difference is such that ~he measured ARMS energy 20 is close to the selected ID~AL. If the difference is yreater than the selected R~NGE then a one-step change of 2 db is made in the AGC 36, and AVENG is reset to zero so t~at the next measured ARMS will become AVENG.
The gain change is made by incrementing or 25 decrementing by one a four-bit counter GCNT within the micro~rocessor in the analyzer 41. The count GCNT in this counter is used witllin the so~tware in the ana-lyzer 41, used for controlling the AGC 36, to address a corresponding memory location and the new gain setting 30 contained therein is written to the AGC 36 on lines PDI07-00.
IDEAL is set at 512, which is half scale ~or the RMS parameter. RANGE is a multiplier ~63096 which corresponds to 4 db (~ = 20 lo~ ~1/o63096)~ V.YAX is 3s empirically set at 85.
, fY' 2~
The analyzer 41 receives data at 64,000 bps from the serial-to-parallel converter 58 and compresses this da~a according to the linear oredictive algorithm.
In the process it complltes RMS on a frame~by-~rame basis 5 and pereorms the decision-mal~ing process of ~rhether to adjust the ~ain of the AGC 36. The gain of the AGC 36 is thus a~ailable data ~or the anal~zer 41, whicn transmits, via, e.~, a modem (not shown~, the true yain (i.e~, the ARMS adjusted by whatever value the AGC 36 10 gain has been adjusted -to maintain the analyzer 41 in~
the proper range for accurately perforlning the linear prediction algorithl~) as par~ of the frame data, to an analyzer 41 a~ a remote location. Using the actual data or a rame, the analyzer 41 computes the best set of r 15 e.g~, 10 linear prediction algorithm factors, ~rom which the remote analyzer 41 can reconstruct the ~ull 1~0 poin~s o diqital data representing the frequency domain spectrum envelope or synthesis by a synthesizer 249 contained in the remote analyzer 41 to simulate a voice 20 si~nal which is an analog signal~
The analyzer 41 also receives compressed 2,400 bps data from a remote analyzer 41 via, eO~., a modem (not sho~n). Using this data, and the linear predictive algorithm, it generates a frequency domain 25 spectrum envelope for each frame. It also receives pitch and gain data for each frame and from the pitch, ~ain and envelope data it synthesizes in its synthesizer portion 24~ a 64,000 bps digital voice signal which is converted in the A/D/A convert~r 50 to drive the speaker 30 in the locaL telephone handset.
Echo suppression of the present inv~ntion is partially software implemented an~ includes also circuitry within the two-wire-to~our-wire interace 12 which unctions as an echo suppressor in the manner o~
35 balancing network couplers in the prior art. These employ transformers ~o accomL~lish echo suppression by balanciny impedances. The echo suppressor oE the present invention is particularly suited to the present system employing diyitized voice. In the inter~ace circuitry of the present invention the hybrid coupler of tlle prior art is replace~ with a hybrid coupling operational amplifier 124.
The source of echo in the interface circuitry of the present inven~ion is the two-wire to four-~ire load balancing circui~ including operational a~pli-fier 124. As the impedance of the two-wire load, i.e., the telephone, varies from the impe~ance ~ne balancing circuit expects to see, a larger amount of the synthe-sizer 249 output signal at node 21~ is re~lected into 13 the analog inQut to the analy~er ~1 through the soectrum shaping amplifier 32.
Because of the processing delay inherent in digital voice ~ransmission, especially employing data comQression and expansion, even small amounts of echo are annoying to the talker. The e~ho suppression em~loyed in the present invention effectively eli~inates this residual echo, and the flow chart for the software implementation is shown in ~IGURE 5 Echo suppression is carried out by a combina~
tion of the use of the balancing hybrid operational amplifier 124 and softwaee analysis of the near talker RMS in the analyzer 41, A~lS, and the far talker RMS in the synthesizer, 249, SR~S. Tllis d~termines whe~her the user at the respective end of the transmission link is tal'~ing or listening duriny each frame and accordingly attenuates ARMS or S~IS. This process begins in soEt-ware, e.g., in the analy~er 41, at STA~T 350. In deci-sion block 352 the ARMS is compared to see if it is greater tllan the most recent peak ARMS, iOe~ ~ ARMSP. If it is then the ARMSP value is set to the present ~R~S
~ 3 --1.9--value in block 3S4. Since decisions are made each Erame regarding which signal to suppress in order ko suppress echo effectively ~uring pauses and at the end o talk-ing, two delay functions are employed~ The first is to 5 hold ARMSP at its mos~ recent value ~or a selected timeO
This is done in block 354 hy setting the coun~ CACNT in an accumulator in the analy~er 41 to DCNT, equal to 16, and which CACNT is decremented by 1 each frame for a total of 16 frames, as long as ARMS is less than or 10 equal to ARMSP.
In decision block 356 SRMS is compared to SR~ISP, the most recent peak SRMS. If it is greater, then SRMSP is set to equal th~ present SRMS in ~_ ~ block 358. Also for the reasons explained above a delay 15 counter accumulator count CSCNT in an accumulator in the analyzer 41 is set to equal DCNT and is d~cremented by 1 once each frame for 16 frames as long as SRMS is less than or equal to SRMSP~
In decision block 360 CACNT is compared to 0 ~ and if less than or equal to 0 ARMSP is set at th~
present value o ARMS in block 362. This same function is performed in decision block 364 and block 366 with respect to CSCNT and SRMSP equal to the present SRMS.
A decision whether to at~enuate S~S is made 25 in decision block 368 by comparing ~RMSP to a value THRONE set at two-~iths scale, and also comparing to . _ .
see if ~RMSP is greater than or equal to SRMSP plus a raction of the hybrid loss HLOSS. The first condition makes certain that a reasonable volume of speech is 30 beiny transmitted/received and the second condition makes certain that the received energy is smaller, even when a correction is made for hybrid impedance mismatch.
I~ these conditions are met an attenua~ing counter for .
the synthesizer CNTA is set in block 370 at MAXCNT, 35 e.g., 16 and an attenuating counter ~or the analyzer ~ ~ 7 ~
CNTS is set to zero. This results in SRMS atten~ation at, e~g., 12 db each frame for as long as CNTA ls greater than 0.
Similarly if SRMSP is greater than THRONE and 5 S~1SP is greater than ARMSP ~ RLOSS a decision is made an decision block 372 which results in block 374 in the setting of an attenuating counter CNTS for the analyzer at MAXCNT and the attenuating counter C~TA for the synthesizer at 0, to attenuate ARMS for a selected 10 number of frames as C~lTS decrements each frame from ~ MAXCNT which may be, e.g., 16.
Moving on to FIGURE SA it is seen that ARMSP
and SRMSP are then com~ared in decision blocks 376 and 380, respectively, with a second threshold value THRTWO, 15 equal to four-fifths scale. If either is greater than this value then, respectively, the far talker or near talker is interrupting and attenuation must be accord-ingly removed. This is done in blocks 378 and 382 by setting, respectively, CNTS or CNTA equal to 0.
Decision blocks 384 and 386 control the actual attenuation so long as, respectively, CNTA is greater than 0 or CNTS is greater than 0. In the former event SRMS is set in block 386 to equal S~MS minus, e.g., 12 db and in the latter event ARMS is set in block 390 25 to equal ARMS minus, e.g., 12 db.
The decrementing ~unction is performed in block 392 by setting CNTA, CNTS, CACNT and CSCNT each equal to their respective values minus 1. The program then returns to ST~RT from RETURN 394, to begin process-3Q ing the data for the next frame.
Thus it can be seen that the software at eachend of the transmission link functions to attenuate the proper value, either SRMS or ARMS dependin~ on whether the near talker or far tal~er, as perceived by each 35 respective end of the transmission link, is the actual ~7,~
talker, the other signal~ either SR~S or ARMS, being thereby deter~ined to be echo and being attenuated to suppress the echo.
Echo suppression also occurs in the four-wire 5 interface section o~ the two-wire to four-wire con-verter. The voltage at node 112~ V112 is given by equation 1, ~T~126 ~ VSZT (1) V112 =
where: VT - telephone~MIC output voltaye ZT ~ telephone impedance VS = voltage at the output of operational amplifier 204 (the synthesizer output) Since ~he operational amplifier 124 is operat-ing with negative feedback, its negative input will track the positive input. A second node equation at the output of the ampliier 124 yieldsO-V112 - ~o + V112 ~ VS
Rf R128 -- (2) where. Vo is ~he voltage at the output o the operational amplifier 124 (the analyzer input) Rf is the equivalent resistance of the feed-back resistance inductance network o the operation amplifier 124~
, .. . . .
7~
Substitutin~ for Vllz from equation 1 yieldsO
= Vs [(~; ) ( f 128) R128 T (R 12 6 + Z T ) (Rf Rl 28) For proper operation there should be no Vs signal componen~ in Vo. For ~his ~co occur, the first 10 term on the right side o~ equa~ion 3 must equal zero.
That term equals zero when:
ZT Rf R126 + ~T R128 ~ Rf .15 In the design o the present invention, th.is requirement is sa'cisf ied u~ing Rf = ZT and R128 ~ R126 ~
Substituting these values into equation 3 yields V~ as a function of the microphone signal:
V~ - VT
In order to empirically match ZT~ measurements were taken of the telephone im~edance over the range oE
25 about 100 to 4000 Hz at a bias current of 16 ma. From tlliS data a matchin~ network according to the present invention was synthesized. Since telephone impedances vary from unit to unit, two adjustments are included in the network by way o the variable resistors 132 and 134 30 and 198 in order to improve the nominal matching.
The per~ormance o~ the two-wire to four-wire converter 12 is more critical in the present invention than in a normal telephone channel since the processing delay inherent in the use o~ digitized voice 1,rill produce suff icient delay in the ect~o path oE the con-verter 12 (synthesizer out to analyzer in) to ~isturb the normal cadence of the talker.
Once adjusted, the circuit yields approxi-mately 40 dB of loss in the echo pat~l across the 100 to 4000 ~z spectrum. To null ~he circuit a signal (1000 Hz, sinusoidal, .814 VRMS~ is inser,~ed at the center ~ost o~ suitcase strap 56 (with the strap 10 removed). V~riable resistor 198 is adjusted (Rx Gain~
Pot) to produce 1.1 * .2 VRMS at tlle output of ampli-fier 2Q4. This adjusts the receive gain and provides a re~erence signal ~or the two-wire to four-wire balance adjustment. The balance adjustment must be made with 15 the telephone connected to the RING and TIP lines an~
with OFF ~00~ activated. ~onitoring the output of the amplifier 152, varia~le resistor 132 and 134 are adjusted to null the signal at that point. The signal level at that point should be at least 35 dB lower than 20 at the output of amplifier 2040 The principal features of the operation oE the present invention will be no~ described with re~erence to FIGURES 2 and 2A. Bias current for the teleæhone is produced using a series resistor network 116 and 114 to 25 +12 volts with a decoupling capaeitor 120 to qround.
The ring driver 15 consists o~ a totem pole driver circuit which includes transistors 86, 88 and 90 and associ~ted discrete components. The circuit uses the TTL level signals QlONH and Q20NI{ to alternately 30 switch the TIP line between 180V and ground. The design of the TTL drive signals includes a "dead time" be~ween state chan~s in which both transistor 88 and transis-tor 86 are o~f.
Diodes 108 and 106 limit the spiking whic~
~ccurs when the current in the bell coil of the tele-phone (not shown~ tries to change ra~idly. Diode 110 isolates the ringing voltage from the two-wire to four 5 wire converter 12. When the rin~ driver 15 is active the voltage at node 112 will swing from 0 to ~12~, at which point diode 110 turns off, w~ile the cathode side of diode 110 continues toward 180V.
When the ring driver 15 is inactive both halves of the totem pole driver circuit are of, thereby presenting a very high i~pedance to the TIP line and having no e~ect on the two-wire ~o four-wire conver-ter 12 balance.
_~ The hookswitch status detection is accom-15 plished by the amplifier 6~ and its associated discrete components. Resistor 70 is a ~C current sense resistor.
The voltage across resistor 70 is low pass filtered at 1 Hz by resistor 72 and capacitor 74 and compared ~via amplifier 66) to a fixed threshold at the junction o~
resistors 78 and 80. In operation there are four combinations of ring state and hookswitch status which the status detection circuitry must recognize. Each combination is descri~ed below.
1. Ring Active, ON HOOK - for this state (which occurs when a call is received) the TIP and RING
leads are AC coupled through the telephone bell circuit, The voltage across the sense resistor 70 is therefore an AC slgnal ~f approximately 20 Hz). The 1 H~ LPF (resis-tor 72 and capacitor 74) prevents excursions of this signal from exceeding the threshold and the ONHOOK
status does not change.
2. Rinq Active, OFF HOOK - in this state (which occurs when a call is answered) the TIP and RING
lines are DC coupled throu~h the telephone. The LPF
3S capacitor ~ charges to the average value o the ring signal, which exceeds the preselected threshold and generates the OFF~OOK status, which should then be sensed by software to turn o~f the rifig signal.
3. Ring Inactive ON HOOK - in this state S (which occurs when the telephone is no longer being used) the TIP and RING lines are again AC c.oupled . No bias current can flow through the TI~ and RING lines and the vol~age across resistor 70 dro~s belo~ the threshold (to ~V) producing the ON HOOIC indic~tion.
- 10 4. R ng Inactive,_OFF HOO~ - in this state -tWhiCh occurs when a call-is initiated or in-progress) the TIP and RING lines are DC coupled. Bias current flows throuyh resistor 70 producing a voltage approxi-mately twice the thresllold voltage at the LP~ capaci-15 tor 82 output which ~roduces the OFF HOgK status.
The sp~ctru~ shaping ampliEier 32 provides anyanalog pre/de-emphasis which may be desirable for the transmit audio~ It also sums the transmit analog signals from both the two-wire and four-wire inQUts.
20 The circuit is AC coupled, via capacitors 1~6 and 140 to, respectively, the interfaces 12 and 1~ to remove the DC volta~e resulting ~rom the telephone bias currents.
The gains oE the two-wire and four-wire transmit paths can be set independently using resistor 148 and resis-25 tor 142 respectively. The nominal gain of the inteL-faces are 14.3 dB for the two-wire path in interface 12 and 3 dB for the four-wire path in interface 180 The gains are set so that the signal peaXs between capaci-tor 153 and swi~ch 34 reacil approximately 3 volts when 30 speaking at a normal level. The output oE the spectrum shaping amplifier 152 is AC couple~ through capaci-tor 153 to the AGC circuit 36 to prevent a DC offset voltage from causing unnecessary transitions in the AGC 36 output signal as the gain is changed.
'7~
The AGC circuit 36 and input filter 46 portion of the filter 44 are described together in f~rther detail here, as shown in FIGURE 6, because a ladder network contained in the AGC 36 circuit and an input 5 operat;onal amplifier 375 contained in the filter 44.are interconnected to ~orm a composite gàin block. The equi~alent circuit for the AGC 36 and a portion of the input filter 46 circuit within the filter 44 is shown in YIGURE 6.
Within the AGC circuit 36 is a eedback resistor 376 which, toget~ler wi~h feed~ack resistor 160 acts as a negative feedback loop for operational ampli-fier 375. The AGC circuit 36 and the operational am~
fier 375 also have an input resistor 378.
The gain of this AGC 36 and filter 44 circuit from EIN at switch 34 to Eo at V~x at the output of the operational ampli~ier 375 in the filter circuit 44 VFxOis Eo D /R160 ~ R376 G EIN 256 \ R378 where D is the digital code loaded into the AGC 36 (0 <
D < 255) on pins PDI07-00 and resistors 3~6 and 378 are 25 nominall~ 10 Kohms~ A digital-to-analog converter 380 in the AGC 36 circuit is connected to a precision refer-ence voltage Vref and provides a current output repre-sentative oE the value 256 ~ 1 where D is ~he digital input to the AGC 36 on PDI07-00 from the analyzer 41.
In operation the AGC 36 and input filter 46 circuits cover a gain range of 30 d~ ~14 dB to 16 d~)~
in 2 dB steps, although the hardware is capable o~
greater range and finer resolution. Table 1 lists the values of D stored in the memory in the analyze~ 41 ~27-corresponding to respective ~our-bit counts t0-15 decimal) from the AGC controller accumulator GCNT in the analyzer 41/ along with the-corresponding gains based on ~he component values used in the A~C 36 and the 5 input fal~er 46 circuits.
The remainder o~ the in~ut ilter 46 inte-grated circuit.actually per~orms the low pass filter function in filter 3B0 and introduces ~3 dB gain in the passband. The inout filter 46 output on pin 16 (VFxO) 10 of f ilter 44 is therefor~ 3 dB higher than the values shown in Table 1.
Table 1. ~GC/Filter Gain Set~ings . GCNT D Gain in dB
0 255. ~ 13.8 1 203. ~7 2 162. +9.8 3 12~. ~7.8
4 102. +S.B
81~ +3~1 6 64. +1.75 7 51 . -. 21 8 40. -~.3 9 32. -. 4.3 26. -6.1 11 20. -8.3 12 16 . -10 ~ 2 13 13. 12.0 14 10. 14.3 8 . -16 . 3 The AGC circuit 36 bypass strap 34 permits the AGC 36 to be bypassed Eor specific applications or ~or 35 test purposes. When th~ strap 34 is in the bypass ~28-position, the gain from the str~p to the inout (tr~ns-mitl f ilter 46 portion o~ filter 44 output VFxO is +3.36 dBf which is close to mid-range AGC 36 setting.
The A/D - D/P~ unction is per~ormed using the
81~ +3~1 6 64. +1.75 7 51 . -. 21 8 40. -~.3 9 32. -. 4.3 26. -6.1 11 20. -8.3 12 16 . -10 ~ 2 13 13. 12.0 14 10. 14.3 8 . -16 . 3 The AGC circuit 36 bypass strap 34 permits the AGC 36 to be bypassed Eor specific applications or ~or 35 test purposes. When th~ strap 34 is in the bypass ~28-position, the gain from the str~p to the inout (tr~ns-mitl f ilter 46 portion o~ filter 44 output VFxO is +3.36 dBf which is close to mid-range AGC 36 setting.
The A/D - D/P~ unction is per~ormed using the
5 INTEL 2911A A-Law CODEC 50. The CODEC 50 and an INTEL
2912 filter 44 form a func~ional block whici is intercon-nected as is well known in the art.
A suitcase strap is provided on the VFRI input of ~he output ( receiYe ) f ilter 48 portio~ of the 10 ilt2r 44 at 56 to allow ~he audio input to be looped back to the output ~or test purposes.
The serial output of the A/D converter 50 which is at 64,000 bps and represents the digitized voice is converted to 8 bit parallel word in serial-to-15 parallel converter 58. The TSX output of the CODEC 50is used for several functions in the AJD - D/A opera-tion. During its active time the TSX output enables the shi~t clocks on serial to-parallel converter 58 and parallel-to-serial converter ~0 so that the CODEC 50 can 20 output its AjD word. It also enables inputing a new D/A
word from the parallel-to-serial converter 60, which is the synthesized digital voice ~rom the synt~esizer 249 in the analyzer 41 at 64,0U0 bps. The trailing edge of TSX (data transfer is complete) is used to generate an 25 interrupt request for the AfD and D/A portions of the A/D/A converter 50 (ADINT) in flip-flop 88. The actual A/D and D/A conversions are started when ~he FS~X,R3 signal is generated for the CODEC ~/D/A converter 50.
FS signal is generated using retimed SRCI-K from flip-30 flop 190 on pin Q. The timinc3 sequence for the CODEC 50is shown in FIGURE 7. When an ADINT pulse is generated, .g., every eight bits in time the data ~eight bits) in the serial-to-parallel converter 58 is loaded to the 3l2~
processor 41 and the data (eiqht bits) in the parallel-to-serial converter 60 is loaded to the A/D/A
converter 50.
The Rx low pass f ilter output VFRO drives the 5 inverting amplifier 204~ The gain of this amplifier 204 is adjustable via variable resistor 198 to set the receive signal level. The output o~ amplif ier 204 drives both the two-wire and four-wire audio outpu~
circuits, which drive the speaker in the telephone 10 handset (not shown)O
SUMMARY OF THE SCOPE ANn ADVANTAGES OF THE INVENTION
It will be seen that the present invention 15 provides for echo suppression at both the talker end and the receiver end, in accordance with detectionr at each end of the transmission link, o which signal ~talk or listen) i5 stronger. This dual echo suppression is incorporated along with a hybrid operational amplifier 20 echo suppression circuit at each end, which particularly is suited for echo suppression in a transmission and receiver system employing digitized voice data and especially co~npressed digitized voice data.
The foregoing description oE the present 25 invention has been directed to a particular embodiment of the invention in accordance with the requirements o~
the patent statutes and for purposes o~ illustratin~ and explaining the invention. It will be apparent, however, to those s~illed in this art that many modifications and 30 changes in both the method and apparatus of the present invention may be made without departing ~rom the scope and spirit of the present invention. ~or example, the analyze~/synthesizer can be microprocessor implemented or implemented by, e.~., a minicomputer or by suitahle 35 har~-wired large-scale integrated circuitry dedicated to performance of the functions described herein. The particular values ~or the lo~ic decisions described herein may be varied as desire-3 ~rom the preferred embodiment described herein~ Further, the echo sup-5 pression technique described herein is not limited totranslnission and receipt of compressed diyital voice, and can be useul in ~ny system which transmits and receives digital voice data, especially wherein process-ing delays heighten the echo problem. It will be 10 further apparent th~t the invention may also be utilized, with suitable modifications within the state of the art which will be apparent to those skilled in the artO It is the applicantsl intention in the following claims to cover all such equivalent modiCi-15 cations and variations as fall within the true scope andspirit of the invention.
2912 filter 44 form a func~ional block whici is intercon-nected as is well known in the art.
A suitcase strap is provided on the VFRI input of ~he output ( receiYe ) f ilter 48 portio~ of the 10 ilt2r 44 at 56 to allow ~he audio input to be looped back to the output ~or test purposes.
The serial output of the A/D converter 50 which is at 64,000 bps and represents the digitized voice is converted to 8 bit parallel word in serial-to-15 parallel converter 58. The TSX output of the CODEC 50is used for several functions in the AJD - D/A opera-tion. During its active time the TSX output enables the shi~t clocks on serial to-parallel converter 58 and parallel-to-serial converter ~0 so that the CODEC 50 can 20 output its AjD word. It also enables inputing a new D/A
word from the parallel-to-serial converter 60, which is the synthesized digital voice ~rom the synt~esizer 249 in the analyzer 41 at 64,0U0 bps. The trailing edge of TSX (data transfer is complete) is used to generate an 25 interrupt request for the AfD and D/A portions of the A/D/A converter 50 (ADINT) in flip-flop 88. The actual A/D and D/A conversions are started when ~he FS~X,R3 signal is generated for the CODEC ~/D/A converter 50.
FS signal is generated using retimed SRCI-K from flip-30 flop 190 on pin Q. The timinc3 sequence for the CODEC 50is shown in FIGURE 7. When an ADINT pulse is generated, .g., every eight bits in time the data ~eight bits) in the serial-to-parallel converter 58 is loaded to the 3l2~
processor 41 and the data (eiqht bits) in the parallel-to-serial converter 60 is loaded to the A/D/A
converter 50.
The Rx low pass f ilter output VFRO drives the 5 inverting amplifier 204~ The gain of this amplifier 204 is adjustable via variable resistor 198 to set the receive signal level. The output o~ amplif ier 204 drives both the two-wire and four-wire audio outpu~
circuits, which drive the speaker in the telephone 10 handset (not shown)O
SUMMARY OF THE SCOPE ANn ADVANTAGES OF THE INVENTION
It will be seen that the present invention 15 provides for echo suppression at both the talker end and the receiver end, in accordance with detectionr at each end of the transmission link, o which signal ~talk or listen) i5 stronger. This dual echo suppression is incorporated along with a hybrid operational amplifier 20 echo suppression circuit at each end, which particularly is suited for echo suppression in a transmission and receiver system employing digitized voice data and especially co~npressed digitized voice data.
The foregoing description oE the present 25 invention has been directed to a particular embodiment of the invention in accordance with the requirements o~
the patent statutes and for purposes o~ illustratin~ and explaining the invention. It will be apparent, however, to those s~illed in this art that many modifications and 30 changes in both the method and apparatus of the present invention may be made without departing ~rom the scope and spirit of the present invention. ~or example, the analyze~/synthesizer can be microprocessor implemented or implemented by, e.~., a minicomputer or by suitahle 35 har~-wired large-scale integrated circuitry dedicated to performance of the functions described herein. The particular values ~or the lo~ic decisions described herein may be varied as desire-3 ~rom the preferred embodiment described herein~ Further, the echo sup-5 pression technique described herein is not limited totranslnission and receipt of compressed diyital voice, and can be useul in ~ny system which transmits and receives digital voice data, especially wherein process-ing delays heighten the echo problem. It will be 10 further apparent th~t the invention may also be utilized, with suitable modifications within the state of the art which will be apparent to those skilled in the artO It is the applicantsl intention in the following claims to cover all such equivalent modiCi-15 cations and variations as fall within the true scope andspirit of the invention.
Claims (3)
PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A digital communication apparatus for transmitting and receiving a compressed digital representation of speech produced by a near talker and a far talker respectively, said compressed digital speech representation including a coded gain parameter related to speech energy, said apparatus comprising:
transmission gain detection means for reading the gain parameter of said near talker's digital speech representation;
receiver gain detection means for reading the gain parameter of said far talker's digital speech representation;
means for reducing the gain parameter of said far talker's digital speech representation when a recent peak gain parameter in said near talker's speech representation is greater than both (1) a first selected threshold and (2) the gain parameter of said far talker's speech representation plus a selected nonzero compensation value; and means for reducing the gain parameter of said near talker's digital speech representation when a recent peak gain parameter in said far talker's digital speech representation is greater than both (1) said first selected threshold and (2) the gain parameter of said near talker's digital speech representation plus said selected nonzero compensation value.
transmission gain detection means for reading the gain parameter of said near talker's digital speech representation;
receiver gain detection means for reading the gain parameter of said far talker's digital speech representation;
means for reducing the gain parameter of said far talker's digital speech representation when a recent peak gain parameter in said near talker's speech representation is greater than both (1) a first selected threshold and (2) the gain parameter of said far talker's speech representation plus a selected nonzero compensation value; and means for reducing the gain parameter of said near talker's digital speech representation when a recent peak gain parameter in said far talker's digital speech representation is greater than both (1) said first selected threshold and (2) the gain parameter of said near talker's digital speech representation plus said selected nonzero compensation value.
2. The apparatus of Claim 1, further comprising:
a near talker interrupt detection means for removing the reduction of the gain parameter of the near talker digital speech representation responsive to detecting whether the gain parameter of the near talker's digital speech representation exceeds a second selected threshold; and, a far talker interrupt detection means for removing the reduction of the gain parameter of the far talker's digital speech representation responsive to detecting whether the gain parameter of the far talker's digital speech representation exceeds the second selected threshold.
a near talker interrupt detection means for removing the reduction of the gain parameter of the near talker digital speech representation responsive to detecting whether the gain parameter of the near talker's digital speech representation exceeds a second selected threshold; and, a far talker interrupt detection means for removing the reduction of the gain parameter of the far talker's digital speech representation responsive to detecting whether the gain parameter of the far talker's digital speech representation exceeds the second selected threshold.
3. A method of echo suppression in a digital communication link, said digital communication link communicating a compressed digital representation of speech produced by a near talker and a far talker, said compressed digital speech representation including a coded gain parameter related to speech energy, the method comprising the steps of:
reducing the gain parameters of said near talker or far talker digital speech representation of one end of the communication link in accordance with which of said gain parameters has the lesser magnitude;
reducing the gain parameter of said near talker or far talker digital speech representation at the other end of the communication link in accordance with which of said gain parameters has the lesser magnitude;
the reducing steps including the steps of:
reducing the gain parameter of said far talker's digital speech representation when a recent peak gain parameter in said near talker's digital speech representation is greater than both (1) a first selected threshold and (2) the gain parameter of said far talker's digital speech representation plus a selected nonzero compensation value; and reducing the gain parameter of said near talker's digital speech representation when a recent peak gain parameter in said far talker's digital speech representation is greater than both (1) said first selected threshold and (2) the gain parameter of said near talker's digital speech representation plus said selected nonzero compensation value.
reducing the gain parameters of said near talker or far talker digital speech representation of one end of the communication link in accordance with which of said gain parameters has the lesser magnitude;
reducing the gain parameter of said near talker or far talker digital speech representation at the other end of the communication link in accordance with which of said gain parameters has the lesser magnitude;
the reducing steps including the steps of:
reducing the gain parameter of said far talker's digital speech representation when a recent peak gain parameter in said near talker's digital speech representation is greater than both (1) a first selected threshold and (2) the gain parameter of said far talker's digital speech representation plus a selected nonzero compensation value; and reducing the gain parameter of said near talker's digital speech representation when a recent peak gain parameter in said far talker's digital speech representation is greater than both (1) said first selected threshold and (2) the gain parameter of said near talker's digital speech representation plus said selected nonzero compensation value.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/471,137 US4652703A (en) | 1983-03-01 | 1983-03-01 | Digital voice transmission having improved echo suppression |
| US471,137 | 1983-03-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1217288A true CA1217288A (en) | 1987-01-27 |
Family
ID=23870403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000448667A Expired CA1217288A (en) | 1983-03-01 | 1984-03-01 | Digital voice transmission having improved echo suppression |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4652703A (en) |
| CA (1) | CA1217288A (en) |
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-
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Also Published As
| Publication number | Publication date |
|---|---|
| US4652703A (en) | 1987-03-24 |
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