CA1217871A - Duplex central processing unit synchronization circuit - Google Patents
Duplex central processing unit synchronization circuitInfo
- Publication number
- CA1217871A CA1217871A CA000469814A CA469814A CA1217871A CA 1217871 A CA1217871 A CA 1217871A CA 000469814 A CA000469814 A CA 000469814A CA 469814 A CA469814 A CA 469814A CA 1217871 A CA1217871 A CA 1217871A
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- Prior art keywords
- cpu
- clock
- copy
- synchronization circuit
- periodic signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000012545 processing Methods 0.000 title abstract description 12
- 230000000737 periodic effect Effects 0.000 claims description 18
- 230000004044 response Effects 0.000 claims description 7
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 238000011022 operating instruction Methods 0.000 abstract 1
- 238000004886 process control Methods 0.000 abstract 1
- 238000004148 unit process Methods 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 description 11
- 239000000872 buffer Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
- G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2097—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements maintaining the standby controller/processing unit updated
Abstract
DUPLEX CENTRAL PROCESSING UNIT SYNCHRONIZATION CIRCUIT
ABSTRACT OF THE DISCLOSURE
This circuit provides for synchronizing the internal clocks of at least two central processing unit process controllers. In order to synchronize the internal clocks of these central processing units (CPUs), the CPUs periodically execute a predetermined set of operating instructions which cause their internal clocks to coincide. This synchronization function is dynamic in that it is continually performed in an on-line fashion while the processors are performing their telecommunication process control function.
ABSTRACT OF THE DISCLOSURE
This circuit provides for synchronizing the internal clocks of at least two central processing unit process controllers. In order to synchronize the internal clocks of these central processing units (CPUs), the CPUs periodically execute a predetermined set of operating instructions which cause their internal clocks to coincide. This synchronization function is dynamic in that it is continually performed in an on-line fashion while the processors are performing their telecommunication process control function.
Description
DUPLEX CENTRAL PROCES~ING UNIT SYNCHRONIZATION CIRCUIT
BACKGROUND OF THE INVENTION
The present invention pertains to controllers for operating a telecommunication process and more particularly to internal clock synchroni~ation of multiple central processing units.
Public policy requires that telecommunication systems provide virtually uninterrup-ted service to its subscribers over long periods of time. Providing redundant circuitry is an aid in meeting this public policy requirement.
However, simple duplication of circuitry creates a problem of simultaneous operation of the circuitry. In order to meet the objective of no loss o~ service for long periods oF time, it is undesirable for telecommunication system outages to occur during a change~o~er ~rom one copy of the duplicated circuitry to the redundant back-up copy of the circuitry~
Modern telecommunication systems employ multiprocessing arrangements of central processing units in order to accomplish their switching operations.
The central processing units (CPUs) of this multi-processing arrangement may be synchronized in order to avoid loss of service during change-over operations.
Typically, central processing unit synchronization has been performed by a vast amount of cLock circuitry, which provides the driving signals to the CPUs. With the advent of single chip microprocessor CPUs, this synchronization function is made difficult. Since much of the clocking function of these single chip microprocessor CPUs is internal to the chip package, synchronizing multiple CPU is more complex.
SUMMARY OF T'~E INVENTION
In a telecommunication system which has a system clock, a CPU synchronization circuit is connected between the system clock and at least two CPU copies. The system clock operates to produce two distinct periodic signals. The ~oal of the CPU
~7~
synchronization circuit is to ensure that all the CPUs are executing the same machine state of the same machine cycle at the same time. This is accomplished by synchronizing the internal cloks of the CPUs.
Fach of the CPUs of each copy includes a clock input lead which connects the system clock to each CPU copy; a status output lead which is capable of providing information as to the particular machine state and cycle of the CPU; and an address latch enable output lead, which provides proper timing for interrogation of the state of the status output lead.
At the appropriate CPU machine state, a production arrangement yields a predefined value via the status output lead of each CPU copyO
Each CPU copy also includes a generating apparatus which is connected to the corresponding CPU copy via the status output lead and via the address latch output lead. The generating apparatus operates in response to the production of the predefined value of the status output lead to produce an inhibit signal.
Lastly, each CPU copy includes a gating arrangement which is connected to the system clock, to the generating apparatus and -to the corresponding CPU of its copy. The gating arrangement operates in response to the inhibit signal and the second periodic signal to prevent one of the first periodic signals from being received by one corresponding CPU
copy. As a result, one CPU copy is slowed by one periodic signal and the other CPU copy is unchanged, resulting in synchronization of the two CPU copies~
BRIEF DESCRIPTION OF THE DRAWINGS
Fig~ 1 is a block diagram of the telecommu-nication system embodying the present invention.
Fig. 2 is a schematic diagram of the syn-chronization circuitry for synchronizing the internal clocks of at least two central processing units.
Fig. 3 is a timing diagram of various key signals for the synchronization process.
~2--~%~
DESCRIPTION OF THE PREFERRED E BODIMENT
Referring to Fig. 1, a time-space-time digital switching network along with the corxesponding common control is shown~ Telephone subscribers, such as subscribers 1 and 2, are shown connected to analog line unit 13. Analog line unit 13 is connected to both copies of the analog control unit 14 and 14'.
Originating time switches 20 and 20' are connected to a duplex pair oE space switch units 30 and 30' which are in turn connected to a duplex pair oE ter-minating time swikches 21 and 21'. Terminating time switches 21 and 21' are connected to analog control units 14 and 14' via digital pad devices and ultimately to the telephone subscribers 1 and 2 via analog line circuit 13. Digital control units 15, 15' and 16, 16' connect the digital spans to the switching network.
Digital span equipment may be implemented using a model 9004 Tl digital span, manufactured by GTE Lenkurt, Inc. Similarly, analog trunk unit 18 connects trunk circuits to the digital switching network via analog control units 17 and 17'.
A peripheral processor CPU 70 controls the digital switching network and digital and analog control units. Analog line unit 13 and a duplex pair of analog control units 14 and 14' interface to tele-phone subscribers directly. A duplicate pair of digital control units 15, 15' and 16, 16' control the incoming PCM data from the digital spans. Similarly, the analog trunk unit 18 and a duplex pair oE analog control units 17 and 17' interface to trunk circuits.
The analog and digital control units are each duplicated for reliability purposes.
The network of Fig. 1 also includes a REMOTE
DATA LINK CONTROLLER (RDLC) 100 which provides for-matting and control of data transmitted and receivedbetween the peripheral processors of two or more networks. The RDLC can provide up to 16, 64 kilobits per second data links arranged for full duplex operation ~3--and is configured so that it can provide one full duplex data link for each of the 16 Tl spans. RDLC
100 can operate together with one or two digital control units (DCUs), with each DCU being capable of providing up to eiyht T1 carrier facilities.
RDLC 100 includes a duplicated data link processor and control 80 and 80' and a duplicated peripheral processor I/O buffer 60 and 60'.
Each RDLC messaye consists of eight, 8-bit bytes of data Eor a total of 6~ bits. The peripheral processor I/O buffer provides four transmit message buffers and four receive message buffers for each of the 16 possible data links.
Normally, peripheral processor software writes a message into a transmit message buffer of peripheral processor I/O buffer 60 and 60' associated with a data link and then issues a transmit command to data link processor and control 80 and 80'. The data link processor and control 80 and 80' responds by taking the message out of the transmit message buffer and reformatting the data, so that it can be transmitted over a Tl carrier. Then data link pro-cessor and control 80 and 80' transmits the message to the distant end of the data link through the appro-priate DCU and digital span.
When a message is received, the data linkprocessor and control 80 and 80' reformats the re-ceived data and places the message into an appropriate receive message buffer in the peripheral I/O buffer 60 and 60' respectively. Data link processor and control 80 and 80' then causes an interrupt, alerting peripheral processor 70 and 70l to the fact that a message has been received. The RDLC will queue up to three received messages. It should be noted that under normal operating conditions, the RDLC operates in a duplex configuration, that is, each RDLC copy matches all outgoing signals performed in the DCUs.
7~
In order to synchronize the two RDLC copies, it ls necessary to ens~lre that both of thelr peripheral processors 70 and 701 are performing the same function at the same time. Each peripheral processor incl~1des an Intel 8085A or 8085A-2 8-~lt parallel central processing unit (CPU). Intel i.5 a reglstered traclemark of the Intel Corporation. In order to synchronize the two Intel 8085A processors, it is necessary that their respectLve internal clocks are synchronized to one another. The MCS-86 USER'S MANUAL, Copyrigl1t 1978 by the Intel Corporation, may be referenced by the reader for a clear understanding of the Intel processors.
Referring to Fig. 2, the Intel 8085A CPUs and associated synchroniæing circuitry comprising copy 0 and copy 1 of the RDLC is shown. CPUs 21 and 21' each include two inputs X1 and X2 which are connected to a clock source and which serve to drive the internal clock generator of the 8085A processor. The input frequency is divided by two on the integrated circuit package to give the processor its internal operating frequency.
Each CPU 21 and 21' also includes a trap input. The trap input is a non-maskable restart interrupt. It is unaffected by any mask or interrupt enable and has the highest priority of any interrupt.
The central processing units 21 and 21' each produce an output signal, referred to as an address latch enable (ALE). The ALE signal occurs during the first clock state of a machine cycle (see Fig. 3) and enables the address to be latched into an on-chip latch for peripheral devices. The falling edge of the ALE signal guarantees set-up and hold times for the address information. In addition, the falling edge of the ALE signal is used to strobe the status information. The ALE signal is not three-stated.
The status information of the 8085A
comprises three outputs S0, S1 and I0/M. The S0 and S1 output signals are not shown in Fig. 2. These ~l7~
status outputs become valid at the beginning of a machine cycle and remain stable throughout the cycle.
The falling edge of the ALE signal is used to latch the s-tatus of these three signals~ The values o the states of these three signals are indicated by the following table:
TABLE
Sl S0 Explanation 0 0 1 Memory Write 0 1 0 Memory Read 1 0 1 I/O Write 1 1 0 I/O Read 0 1 1 Opcode Fetch 1 1 1 Interrupt Acknowledge As can be seen from the above table for an I/O write or read, the IO/M is a logic 1.
A system clock (not shown) generates three clock signals for use by the CPUs 21 and 21' and the synchronizing circuitry. First, the system clock generates a 6 MHz signal ta range of 1 MHæ to 10 MHz may be employed) on the 6MCLK leadO Second, the clock generates a 12 MHz signal (a range of 10 MHz to 20 MHz may be employed corresponding to the 1 MHz to 10 MHz range of the 6MCLK lead) on the 12MCLK lead.
Lastly, the clock generates a pulse once every six milliseconds (a range of 1 Hz to lK H~ may be used) on the 6MSCLK lead.
The 6MCLK lead connects the system clock to NAND gates 4 and 4'. The other input to NAND gate 4 is connected to the Q output of flip-flop 23 via the -FRZ lead. Similarly, the other input to NAND
gate 4' is connected to the Q output of flip-flop 23' via a corresponding -FRZ lead.
The output of NAND gates 4 and 4' are con-nected respectively to the D-inputs of flip-flops 11 and 11'. The clock is connected to the CLK-input of flip-flops 11 and 11' via the 12MCLK lead. The Q outputs of flip-flops 11 and 11' are connected to ~7~
the Xl and X2 inputs of CPUs 21 and 21' respectively.
This connection to the Xl and X2 leads of the CPU
is in a push-pull configuration.
The ALE output of CPUs 21 and 21' is respec-tively connected to the clock inputs of flip~flops 23 and 23' via the corresponding ~LE lead. Similarly, the status lead IO/M of each CPU 21 and 21' is con-nected respectively to the J-input of flip-flops 23 and 23'. Flip-Elops 23 and 23' are J-K flip-flops and flip-flops 11 and 11' are D-type flip-flops of the 7400 logic family such as those manufactured b~
the Texas Instruments Corporation.
Every six milliseconds a signal is produced by the clock on the 6MSCLK lead and transmitted to CPUs 21 and 21' via the trap inputs. As a result~
a trap is generated by each CPU. This trap forces an internal branch to location 24 hexadecimal which contains an I/O instruction. As a result of the execution of this I/O instruction, status lead IO/M
is at logic 1. Flip-flops 23 and 23' will latch the IO/M lead value on the next falling edge of the ALE
signal. As a result, the -FRz lead will go active to logic 0 (see Fig. 3).
If one of the CPUs is operating faster than the other (i.e. not in synchronization), the -FRZ
lead at logic 0 will inhibit the operation of its corresponding NAND gate 4 or 4l. Thereby, flip-flop 11 or 11~ will be prevented from transmitting one clock pulse to the Xl and X2 leads of the CPU which is op~rating faster ~han the other CPU. That is, if the two RDLC microprocessor copies were operating out of synchronization, one will skip a clock pulse and the other will not. As a result of this clock pulse deletion, the internal clocks of CPUs 21 and 21' will be placed in synchronization.
Referring to Fig. 3, the timing of the 8085A or 8085A-2 microprocessor CPU is shown. The CLK signal i5 the internal clock of the 8085A micro-processor. Ml, M2 and M3 are three machine states _7_ which depict an instruction fetch, a memory read and an I/O write cycle respectively. ALE is the address latch enable signal which occurs during the first clock state of each machine cycleO The read control signal RD indicates whether a memory or I/O device is to be read and that the data bus is available Evr data transfer. The write control signal WR indicates that the contents of the data bus is ready to be written into the selected memory or I/O location.
The IO/M status signal indicates that an I/O read or write is occurring and i5 used to perform the synchronization of the CPUs as indicated above. The -FRZ lead is shown making its transition from logic 1 to logic 0 in response to the IO/M signal being logic 1 and a falling edge of the ALE signal.
Machine cycle Ml consists of four states, rrl through T4, since it is an opcode fetch. Machine cycles M2 and M3 each contain three states, Tl through T3, since they respectively constitute a memory read and an I/O write operation.
Although the preferred embodiment of the invention has been illustrated, and that form described in detail, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims.
BACKGROUND OF THE INVENTION
The present invention pertains to controllers for operating a telecommunication process and more particularly to internal clock synchroni~ation of multiple central processing units.
Public policy requires that telecommunication systems provide virtually uninterrup-ted service to its subscribers over long periods of time. Providing redundant circuitry is an aid in meeting this public policy requirement.
However, simple duplication of circuitry creates a problem of simultaneous operation of the circuitry. In order to meet the objective of no loss o~ service for long periods oF time, it is undesirable for telecommunication system outages to occur during a change~o~er ~rom one copy of the duplicated circuitry to the redundant back-up copy of the circuitry~
Modern telecommunication systems employ multiprocessing arrangements of central processing units in order to accomplish their switching operations.
The central processing units (CPUs) of this multi-processing arrangement may be synchronized in order to avoid loss of service during change-over operations.
Typically, central processing unit synchronization has been performed by a vast amount of cLock circuitry, which provides the driving signals to the CPUs. With the advent of single chip microprocessor CPUs, this synchronization function is made difficult. Since much of the clocking function of these single chip microprocessor CPUs is internal to the chip package, synchronizing multiple CPU is more complex.
SUMMARY OF T'~E INVENTION
In a telecommunication system which has a system clock, a CPU synchronization circuit is connected between the system clock and at least two CPU copies. The system clock operates to produce two distinct periodic signals. The ~oal of the CPU
~7~
synchronization circuit is to ensure that all the CPUs are executing the same machine state of the same machine cycle at the same time. This is accomplished by synchronizing the internal cloks of the CPUs.
Fach of the CPUs of each copy includes a clock input lead which connects the system clock to each CPU copy; a status output lead which is capable of providing information as to the particular machine state and cycle of the CPU; and an address latch enable output lead, which provides proper timing for interrogation of the state of the status output lead.
At the appropriate CPU machine state, a production arrangement yields a predefined value via the status output lead of each CPU copyO
Each CPU copy also includes a generating apparatus which is connected to the corresponding CPU copy via the status output lead and via the address latch output lead. The generating apparatus operates in response to the production of the predefined value of the status output lead to produce an inhibit signal.
Lastly, each CPU copy includes a gating arrangement which is connected to the system clock, to the generating apparatus and -to the corresponding CPU of its copy. The gating arrangement operates in response to the inhibit signal and the second periodic signal to prevent one of the first periodic signals from being received by one corresponding CPU
copy. As a result, one CPU copy is slowed by one periodic signal and the other CPU copy is unchanged, resulting in synchronization of the two CPU copies~
BRIEF DESCRIPTION OF THE DRAWINGS
Fig~ 1 is a block diagram of the telecommu-nication system embodying the present invention.
Fig. 2 is a schematic diagram of the syn-chronization circuitry for synchronizing the internal clocks of at least two central processing units.
Fig. 3 is a timing diagram of various key signals for the synchronization process.
~2--~%~
DESCRIPTION OF THE PREFERRED E BODIMENT
Referring to Fig. 1, a time-space-time digital switching network along with the corxesponding common control is shown~ Telephone subscribers, such as subscribers 1 and 2, are shown connected to analog line unit 13. Analog line unit 13 is connected to both copies of the analog control unit 14 and 14'.
Originating time switches 20 and 20' are connected to a duplex pair oE space switch units 30 and 30' which are in turn connected to a duplex pair oE ter-minating time swikches 21 and 21'. Terminating time switches 21 and 21' are connected to analog control units 14 and 14' via digital pad devices and ultimately to the telephone subscribers 1 and 2 via analog line circuit 13. Digital control units 15, 15' and 16, 16' connect the digital spans to the switching network.
Digital span equipment may be implemented using a model 9004 Tl digital span, manufactured by GTE Lenkurt, Inc. Similarly, analog trunk unit 18 connects trunk circuits to the digital switching network via analog control units 17 and 17'.
A peripheral processor CPU 70 controls the digital switching network and digital and analog control units. Analog line unit 13 and a duplex pair of analog control units 14 and 14' interface to tele-phone subscribers directly. A duplicate pair of digital control units 15, 15' and 16, 16' control the incoming PCM data from the digital spans. Similarly, the analog trunk unit 18 and a duplex pair oE analog control units 17 and 17' interface to trunk circuits.
The analog and digital control units are each duplicated for reliability purposes.
The network of Fig. 1 also includes a REMOTE
DATA LINK CONTROLLER (RDLC) 100 which provides for-matting and control of data transmitted and receivedbetween the peripheral processors of two or more networks. The RDLC can provide up to 16, 64 kilobits per second data links arranged for full duplex operation ~3--and is configured so that it can provide one full duplex data link for each of the 16 Tl spans. RDLC
100 can operate together with one or two digital control units (DCUs), with each DCU being capable of providing up to eiyht T1 carrier facilities.
RDLC 100 includes a duplicated data link processor and control 80 and 80' and a duplicated peripheral processor I/O buffer 60 and 60'.
Each RDLC messaye consists of eight, 8-bit bytes of data Eor a total of 6~ bits. The peripheral processor I/O buffer provides four transmit message buffers and four receive message buffers for each of the 16 possible data links.
Normally, peripheral processor software writes a message into a transmit message buffer of peripheral processor I/O buffer 60 and 60' associated with a data link and then issues a transmit command to data link processor and control 80 and 80'. The data link processor and control 80 and 80' responds by taking the message out of the transmit message buffer and reformatting the data, so that it can be transmitted over a Tl carrier. Then data link pro-cessor and control 80 and 80' transmits the message to the distant end of the data link through the appro-priate DCU and digital span.
When a message is received, the data linkprocessor and control 80 and 80' reformats the re-ceived data and places the message into an appropriate receive message buffer in the peripheral I/O buffer 60 and 60' respectively. Data link processor and control 80 and 80' then causes an interrupt, alerting peripheral processor 70 and 70l to the fact that a message has been received. The RDLC will queue up to three received messages. It should be noted that under normal operating conditions, the RDLC operates in a duplex configuration, that is, each RDLC copy matches all outgoing signals performed in the DCUs.
7~
In order to synchronize the two RDLC copies, it ls necessary to ens~lre that both of thelr peripheral processors 70 and 701 are performing the same function at the same time. Each peripheral processor incl~1des an Intel 8085A or 8085A-2 8-~lt parallel central processing unit (CPU). Intel i.5 a reglstered traclemark of the Intel Corporation. In order to synchronize the two Intel 8085A processors, it is necessary that their respectLve internal clocks are synchronized to one another. The MCS-86 USER'S MANUAL, Copyrigl1t 1978 by the Intel Corporation, may be referenced by the reader for a clear understanding of the Intel processors.
Referring to Fig. 2, the Intel 8085A CPUs and associated synchroniæing circuitry comprising copy 0 and copy 1 of the RDLC is shown. CPUs 21 and 21' each include two inputs X1 and X2 which are connected to a clock source and which serve to drive the internal clock generator of the 8085A processor. The input frequency is divided by two on the integrated circuit package to give the processor its internal operating frequency.
Each CPU 21 and 21' also includes a trap input. The trap input is a non-maskable restart interrupt. It is unaffected by any mask or interrupt enable and has the highest priority of any interrupt.
The central processing units 21 and 21' each produce an output signal, referred to as an address latch enable (ALE). The ALE signal occurs during the first clock state of a machine cycle (see Fig. 3) and enables the address to be latched into an on-chip latch for peripheral devices. The falling edge of the ALE signal guarantees set-up and hold times for the address information. In addition, the falling edge of the ALE signal is used to strobe the status information. The ALE signal is not three-stated.
The status information of the 8085A
comprises three outputs S0, S1 and I0/M. The S0 and S1 output signals are not shown in Fig. 2. These ~l7~
status outputs become valid at the beginning of a machine cycle and remain stable throughout the cycle.
The falling edge of the ALE signal is used to latch the s-tatus of these three signals~ The values o the states of these three signals are indicated by the following table:
TABLE
Sl S0 Explanation 0 0 1 Memory Write 0 1 0 Memory Read 1 0 1 I/O Write 1 1 0 I/O Read 0 1 1 Opcode Fetch 1 1 1 Interrupt Acknowledge As can be seen from the above table for an I/O write or read, the IO/M is a logic 1.
A system clock (not shown) generates three clock signals for use by the CPUs 21 and 21' and the synchronizing circuitry. First, the system clock generates a 6 MHz signal ta range of 1 MHæ to 10 MHz may be employed) on the 6MCLK leadO Second, the clock generates a 12 MHz signal (a range of 10 MHz to 20 MHz may be employed corresponding to the 1 MHz to 10 MHz range of the 6MCLK lead) on the 12MCLK lead.
Lastly, the clock generates a pulse once every six milliseconds (a range of 1 Hz to lK H~ may be used) on the 6MSCLK lead.
The 6MCLK lead connects the system clock to NAND gates 4 and 4'. The other input to NAND gate 4 is connected to the Q output of flip-flop 23 via the -FRZ lead. Similarly, the other input to NAND
gate 4' is connected to the Q output of flip-flop 23' via a corresponding -FRZ lead.
The output of NAND gates 4 and 4' are con-nected respectively to the D-inputs of flip-flops 11 and 11'. The clock is connected to the CLK-input of flip-flops 11 and 11' via the 12MCLK lead. The Q outputs of flip-flops 11 and 11' are connected to ~7~
the Xl and X2 inputs of CPUs 21 and 21' respectively.
This connection to the Xl and X2 leads of the CPU
is in a push-pull configuration.
The ALE output of CPUs 21 and 21' is respec-tively connected to the clock inputs of flip~flops 23 and 23' via the corresponding ~LE lead. Similarly, the status lead IO/M of each CPU 21 and 21' is con-nected respectively to the J-input of flip-flops 23 and 23'. Flip-Elops 23 and 23' are J-K flip-flops and flip-flops 11 and 11' are D-type flip-flops of the 7400 logic family such as those manufactured b~
the Texas Instruments Corporation.
Every six milliseconds a signal is produced by the clock on the 6MSCLK lead and transmitted to CPUs 21 and 21' via the trap inputs. As a result~
a trap is generated by each CPU. This trap forces an internal branch to location 24 hexadecimal which contains an I/O instruction. As a result of the execution of this I/O instruction, status lead IO/M
is at logic 1. Flip-flops 23 and 23' will latch the IO/M lead value on the next falling edge of the ALE
signal. As a result, the -FRz lead will go active to logic 0 (see Fig. 3).
If one of the CPUs is operating faster than the other (i.e. not in synchronization), the -FRZ
lead at logic 0 will inhibit the operation of its corresponding NAND gate 4 or 4l. Thereby, flip-flop 11 or 11~ will be prevented from transmitting one clock pulse to the Xl and X2 leads of the CPU which is op~rating faster ~han the other CPU. That is, if the two RDLC microprocessor copies were operating out of synchronization, one will skip a clock pulse and the other will not. As a result of this clock pulse deletion, the internal clocks of CPUs 21 and 21' will be placed in synchronization.
Referring to Fig. 3, the timing of the 8085A or 8085A-2 microprocessor CPU is shown. The CLK signal i5 the internal clock of the 8085A micro-processor. Ml, M2 and M3 are three machine states _7_ which depict an instruction fetch, a memory read and an I/O write cycle respectively. ALE is the address latch enable signal which occurs during the first clock state of each machine cycleO The read control signal RD indicates whether a memory or I/O device is to be read and that the data bus is available Evr data transfer. The write control signal WR indicates that the contents of the data bus is ready to be written into the selected memory or I/O location.
The IO/M status signal indicates that an I/O read or write is occurring and i5 used to perform the synchronization of the CPUs as indicated above. The -FRZ lead is shown making its transition from logic 1 to logic 0 in response to the IO/M signal being logic 1 and a falling edge of the ALE signal.
Machine cycle Ml consists of four states, rrl through T4, since it is an opcode fetch. Machine cycles M2 and M3 each contain three states, Tl through T3, since they respectively constitute a memory read and an I/O write operation.
Although the preferred embodiment of the invention has been illustrated, and that form described in detail, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims.
Claims (10)
1. In a telecommunication system, a CPU
synchronization circuit is connected to a clock of said telecommunication system, said CPU synchronization circuit comprising:
said clock being operated to produce at least first and second periodic signals;
CPU means including at least first and second non-synchronized CPU copies;
each of said CPU copies including:
a clock input lead connecting said clock to said CPU copy;
a status output lead;
an address latch output lead;
means for producing a predefined value of said status output lead;
means for generating an inhibit signal connected to said corresponding CPU copy via said status output lead and said address latch output lead and said means for gen-erating being operated in response to said operation of said means for producing to produce said inhibit signal; and gating means connected to said clock, to said means for generating and to said corresponding CPU copy, said gating means being operated in response to said inhibit signal of said means for generating to inhibit one of said first periodic signals from one said corresponding CPU copy, thereby synchronizing said first and second CPU
copies.
synchronization circuit is connected to a clock of said telecommunication system, said CPU synchronization circuit comprising:
said clock being operated to produce at least first and second periodic signals;
CPU means including at least first and second non-synchronized CPU copies;
each of said CPU copies including:
a clock input lead connecting said clock to said CPU copy;
a status output lead;
an address latch output lead;
means for producing a predefined value of said status output lead;
means for generating an inhibit signal connected to said corresponding CPU copy via said status output lead and said address latch output lead and said means for gen-erating being operated in response to said operation of said means for producing to produce said inhibit signal; and gating means connected to said clock, to said means for generating and to said corresponding CPU copy, said gating means being operated in response to said inhibit signal of said means for generating to inhibit one of said first periodic signals from one said corresponding CPU copy, thereby synchronizing said first and second CPU
copies.
2. A CPU synchronization circuit as claimed in claim 1, wherein there is included:
said clock being operated to produce a third periodic signal;
each said CPU copy further including:
a trap input lead connected between said clock and each said CPU copy, said trap input lead being operated to transmit said third periodic signal to each said CPU copy; and said CPU copy being periodically op-erated to initiate operation of said means for producing for cyclically resynchronizing said first and second CPU copies.
said clock being operated to produce a third periodic signal;
each said CPU copy further including:
a trap input lead connected between said clock and each said CPU copy, said trap input lead being operated to transmit said third periodic signal to each said CPU copy; and said CPU copy being periodically op-erated to initiate operation of said means for producing for cyclically resynchronizing said first and second CPU copies.
3. A CPU synchronization circuit as claimed in claim 1, wherein said means for generating includes a J-K flip-flop having a J-input connected to said status output lead, a clock-input connected to said address latch output lead, a K-input lead connected to electronic ground and a Q-output lead for providing said inhibit signal.
4. A CPU synchronization circuit as claimed in claim 3, said gating means of each said CPU copy including:
NAND gating means connected to said clock and to said Q-output lead of said J-K flip-flop and said NAND gating means being operated in response to said first periodic signal and to said inhibit signal to selectively transmit said first periodic signal; and latching means connected to said NAND gating means, to said corresponding CPU copy and to said clock, said latching means being operated in response to said second periodic signal of said clock to store values of said first periodic signal transmitted through said NAND gating means.
NAND gating means connected to said clock and to said Q-output lead of said J-K flip-flop and said NAND gating means being operated in response to said first periodic signal and to said inhibit signal to selectively transmit said first periodic signal; and latching means connected to said NAND gating means, to said corresponding CPU copy and to said clock, said latching means being operated in response to said second periodic signal of said clock to store values of said first periodic signal transmitted through said NAND gating means.
5. A CPU synchronization circuit as claimed in claim 4, wherein said latching means of each said CPU copy includes a D-type flip-flop having a D-input connected to said NAND gating means, a clock-input connected to said clock for receiving said second periodic signal and a Q-output connected to said corresponding CPU copy.
6. A CPU synchronization circuit as claimed in claim 5, wherein each said CPU copy includes a microprocessor CPU.
7. A CPU synchronization circuit as claimed in claim 6, wherein said connection of said corresponding microprocessor CPU to said corresponding D-type flip-flop includes first and second circuit connections to said microprocessor CPU for operating an internal clock of said microprocessor CPU in a push-pull con-figuration.
8. A CPU synchronization circuit as claimed in claim 1, wherein said second periodic signal is approximately twice in frequency of said first periodic signal.
9. A CPU synchronization circuit as claimed in claim 8, wherein said first periodic signal is in the frequency range of between 1 MHz and 10 MHz and said second periodic signal is in the frequency range of between 10 MHz and 20 MHz, correspondingly.
10. A CPU synchronization circuit as claimed in claim 2, wherein said third periodic signal is in the frequency range of between 1 Hz and 1K Hz.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US564,132 | 1983-12-22 | ||
| US06/564,132 US4569017A (en) | 1983-12-22 | 1983-12-22 | Duplex central processing unit synchronization circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1217871A true CA1217871A (en) | 1987-02-10 |
Family
ID=24253283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000469814A Expired CA1217871A (en) | 1983-12-22 | 1984-12-11 | Duplex central processing unit synchronization circuit |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4569017A (en) |
| CA (1) | CA1217871A (en) |
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| JPS6345670A (en) * | 1986-08-13 | 1988-02-26 | Hitachi Ltd | Inter-processor synchronizing device |
| EP0306211A3 (en) * | 1987-09-04 | 1990-09-26 | Digital Equipment Corporation | Synchronized twin computer system |
| US5185877A (en) * | 1987-09-04 | 1993-02-09 | Digital Equipment Corporation | Protocol for transfer of DMA data |
| US5050070A (en) * | 1988-02-29 | 1991-09-17 | Convex Computer Corporation | Multi-processor computer system having self-allocating processors |
| US5159686A (en) * | 1988-02-29 | 1992-10-27 | Convex Computer Corporation | Multi-processor computer system having process-independent communication register addressing |
| JPH0797328B2 (en) * | 1988-10-25 | 1995-10-18 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | False tolerant synchronization system |
| DE58908047D1 (en) * | 1989-04-25 | 1994-08-18 | Siemens Ag | Processes for the synchronization of data processing systems. |
| US5068780A (en) * | 1989-08-01 | 1991-11-26 | Digital Equipment Corporation | Method and apparatus for controlling initiation of bootstrap loading of an operating system in a computer system having first and second discrete computing zones |
| US5153881A (en) * | 1989-08-01 | 1992-10-06 | Digital Equipment Corporation | Method of handling errors in software |
| US5251227A (en) * | 1989-08-01 | 1993-10-05 | Digital Equipment Corporation | Targeted resets in a data processor including a trace memory to store transactions |
| US5163138A (en) * | 1989-08-01 | 1992-11-10 | Digital Equipment Corporation | Protocol for read write transfers via switching logic by transmitting and retransmitting an address |
| ATE127598T1 (en) * | 1990-06-01 | 1995-09-15 | Bell Telephone Mfg | METHOD FOR MODIFYING A FAULT-TOLERANT DATA PROCESSING SYSTEM. |
| US5319680A (en) * | 1991-09-03 | 1994-06-07 | The Whitaker Corporation | Phase locked loop synchronization system for use in data communications |
| US7013305B2 (en) | 2001-10-01 | 2006-03-14 | International Business Machines Corporation | Managing the state of coupling facility structures, detecting by one or more systems coupled to the coupling facility, the suspended state of the duplexed command, detecting being independent of message exchange |
| US6567376B1 (en) | 1999-02-25 | 2003-05-20 | Telefonaktiebolaget Lm Ericsson (Publ) | Using system frame number to implement timers in telecommunications system having redundancy |
| US6470462B1 (en) * | 1999-02-25 | 2002-10-22 | Telefonaktiebolaget Lm Ericsson (Publ) | Simultaneous resynchronization by command for state machines in redundant systems |
| US6859866B2 (en) | 2001-10-01 | 2005-02-22 | International Business Machines Corporation | Synchronizing processing of commands invoked against duplexed coupling facility structures |
| US6944787B2 (en) * | 2001-10-01 | 2005-09-13 | International Business Machines Corporation | System-managed duplexing of coupling facility structures |
| US6954817B2 (en) * | 2001-10-01 | 2005-10-11 | International Business Machines Corporation | Providing at least one peer connection between a plurality of coupling facilities to couple the plurality of coupling facilities |
| US7099935B2 (en) * | 2001-10-01 | 2006-08-29 | International Business Machines Corporation | Dynamically determining whether to process requests synchronously or asynchronously |
| US6910158B2 (en) * | 2001-10-01 | 2005-06-21 | International Business Machines Corporation | Test tool and methods for facilitating testing of duplexed computer functions |
| US6813726B2 (en) | 2001-10-01 | 2004-11-02 | International Business Machines Corporation | Restarting a coupling facility command using a token from another coupling facility command |
| US7158594B2 (en) * | 2002-08-21 | 2007-01-02 | Intel Corporation | Receivers for controlled frequency signals |
| US7224739B2 (en) * | 2002-08-21 | 2007-05-29 | Intel Corporation | Controlled frequency signals |
| US7305023B2 (en) * | 2003-07-23 | 2007-12-04 | Intel Corporation | Receivers for cycle encoded signals |
| US7308025B2 (en) | 2003-07-23 | 2007-12-11 | Intel Corporation | Transmitters providing cycle encoded signals |
| US9817433B2 (en) * | 2011-11-22 | 2017-11-14 | Arm Finance Overseas Limited | Apparatus and method for achieving glitch-free clock domain crossing signals |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1587572A (en) * | 1968-10-25 | 1970-03-20 | ||
| SE347826B (en) * | 1970-11-20 | 1972-08-14 | Ericsson Telefon Ab L M | |
| US3898621A (en) * | 1973-04-06 | 1975-08-05 | Gte Automatic Electric Lab Inc | Data processor system diagnostic arrangement |
| NL7309770A (en) * | 1973-07-13 | 1975-01-15 | Bell Telephone Mfg | CONTROL DEVICE. |
| US4099241A (en) * | 1973-10-30 | 1978-07-04 | Telefonaktiebolaget L M Ericsson | Apparatus for facilitating a cooperation between an executive computer and a reserve computer |
| IT1036311B (en) * | 1975-06-17 | 1979-10-30 | Cselt Centro Studi Lab Telecom | DUPLICATE SYSTEM FOR SUPERVISION AND CONTROL OF DUPLICATED TELECOMMUNICATION SYSTEMS |
| NL7510904A (en) * | 1975-09-17 | 1977-03-21 | Philips Nv | WORD GROUP PRIORITY DEVELOPMENT. |
| US4021784A (en) * | 1976-03-12 | 1977-05-03 | Sperry Rand Corporation | Clock synchronization system |
| US4270167A (en) * | 1978-06-30 | 1981-05-26 | Intel Corporation | Apparatus and method for cooperative and concurrent coprocessing of digital information |
| US4405898A (en) * | 1980-06-30 | 1983-09-20 | International Business Machines Corporation | Pseudo synchronous clocking |
-
1983
- 1983-12-22 US US06/564,132 patent/US4569017A/en not_active Expired - Fee Related
-
1984
- 1984-12-11 CA CA000469814A patent/CA1217871A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4569017A (en) | 1986-02-04 |
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