CA1218753A - Buffer-storage control system - Google Patents
Buffer-storage control systemInfo
- Publication number
- CA1218753A CA1218753A CA000453619A CA453619A CA1218753A CA 1218753 A CA1218753 A CA 1218753A CA 000453619 A CA000453619 A CA 000453619A CA 453619 A CA453619 A CA 453619A CA 1218753 A CA1218753 A CA 1218753A
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- CA
- Canada
- Prior art keywords
- address
- buffer
- way
- data
- control system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
Abstract
BUFFER-STORAGE CONTROL SYSTEM
ABSTRACT OF THE DISCLOSURE
A buffer-storage control system used in a pipeline data processor comprising a memory system having a two-level hierarchical structure composed of a main storage and a buffer storage. The buffer storage has a tag portion and a data portion, each portion being composed of a plurality of ways. In the buffer-storage control system, the tag portion and the data portion can be independently accessed and the data portion is so constituted for every way that it is possible to select one of a plurality of address passes and to select an address for a read access and an address for a write access for every way, thereby simultaneously effecting a read operation and write operation in the same machine cycle and executing the read access again only when the read access and the write access are effected for the same way.
ABSTRACT OF THE DISCLOSURE
A buffer-storage control system used in a pipeline data processor comprising a memory system having a two-level hierarchical structure composed of a main storage and a buffer storage. The buffer storage has a tag portion and a data portion, each portion being composed of a plurality of ways. In the buffer-storage control system, the tag portion and the data portion can be independently accessed and the data portion is so constituted for every way that it is possible to select one of a plurality of address passes and to select an address for a read access and an address for a write access for every way, thereby simultaneously effecting a read operation and write operation in the same machine cycle and executing the read access again only when the read access and the write access are effected for the same way.
Description
sUFFER-STORAGE CONTROL SYSTEM
BACKGROUND OF THE INVENTION
(1) Field of the Invention The present invention relates to a buffer-storage control system, more particularly a buffer-storage control system for storing access in a pipeline data processing system from a data processing unit and the like to a memory system having a two-level hierarchical structure composed of a main storage and a buffer storage.
BACKGROUND OF THE INVENTION
(1) Field of the Invention The present invention relates to a buffer-storage control system, more particularly a buffer-storage control system for storing access in a pipeline data processing system from a data processing unit and the like to a memory system having a two-level hierarchical structure composed of a main storage and a buffer storage.
(2) Description of the Prior Art A buffer storage generally comprises a tag portion (TAG) and a data portion (DATA), each of these portions comprising a plurali-ty of ways or way portions.
Each way of the tag portion and the data portion comprises a plurality of blocks, each block being a data unit of a storing or transferring operation. The tag portion has a plurality of valid bits corresponding to the blocks for indicating block validity, i.e., indi-cating that data is already transferred to the block from the main storage and a write operation is possible.
In a data processing system comprising a two-level hierarchical memory system composed of a main storage and a buffer storage, when the memory system is accessed, every way of the above-mentioned tag portion is read out simultaneously, i.e., the coincidence of addresses is checked, to determine whether or not the buffer storage stores data of a designated address. Noncoincidence of any of the addresses in the ways with the designated address means the target data is not stored in the buffer storage. Therefore, the data of the designated address is read from the main storage and transmitted to the buffer storage. Thereafter, the memory system is generally controlled so that the memory access is effected to the buffer storage.
In a buffer-storage control system of a "store-7S~
\
through" type, when store-accessing the main storage, if an address block memorizing the address corresponding to that for the store access is found in the buffer storage, the buffer storage is store accessed at the same time. If the address block is not found in the buffer storage, the memory system is controlled so that the buffer storage is not store-accessed but only the main storage.
If the data processor for performing pipeline processing is continuously storage-accessing the buffer storage, the storing operation and fetching operation caused by a succeeding instruction will overlap and the fetching operation and the subsequent storing operation of the succeeding instruction will be delayed. This wastes machine cycles and reduces the processing ability of the overall computer system.
SUMMARY OF THE INVE~TION
It is the main object of the present invention to realize high speed processing without delay, even when write operations occur in succession, where a write operation requires two cycles of a tag access and a data writing.
It is another object of the present invention to realize the processing of a read request without delay, even when read operations occur in succession after a write operation.
According to the present invention, there is provided a buffer-storage control system for a data processor having a main storage and a buffer storage which has a tag portion and a data portion, each of the tag and data portions having a plurality of ways; a read access to the buffer storage being carried out by ~ccessing simultaneously the tag portion and the data portion, and selecting the output of the data portion on the basis of the result of a comparison in the tag portion; a write access to the buffer storage being carried out by first accessing the tag in a first cycle to detect in which level the data block in question exists, and writing the data into the detected level in the second cycle; the tag portion and the data portion being capable of being independently accessed;
-2a~
the address which is the same as the address for the tag portion or other optional address being capable of being selected as an access address for the data portion;
thereby a tag access for a write access request and a writing of the other write request into the data portion can be treated in parallel.
According to a preferred embodiment of the present invention, in the above buffer-storage control system, each tag and data portion is composed of a plurality of ways, and the buffer-storage control system is so constituted that the tag portion and the data portion can be independently accessed and that the data portion is so constituted for every way that it is possible to select one of a plurality of address passes and to select an address ror a read access and an address for a write access for every way, thereby simultaneously effecting a read operation and a write operation in the same machine cycle and executing the read access again only when the read access and the write access are effected for the same way.
BRIEF DESCRIPTION OF THE DRAWINGS
75~^~
These and other ob~ects and advantages of the present invention will become clearer from the ensuring description of a preferred embodiments in reference to the attached drawings, in which:
Fig. 1 is a block circuit diagram of an example of a general data processing system comprising a memory system having a two-level hierarchical structure;
Fig. 2 is a block circuit diagram of the detailed structure of a central processing unit (CPU) used in the data processing system of Fig. l;
Fig. 3 is a block circuit diagram of a buffer storage used in a conventional buffer-storage control system;
Fig. 4 is a timing diagram of the storing operation in the circuit of Fig. 3;
Fig. 5A is a time chart of a pipeline proces-sing sequence in a data processing system using a conventional buffer-storage control system;
Fig. 5B is a time chart of a pipeline proces-sing sequence in a data processing system using abuffer-storage control system according to the present invention;
Fig. 6 is a block circuit diagram of a buffer storage used in a buffer-storage control system according to an embodiment of the present invention; and Fig. 7 is a block circuit diagram of a way-coincidence detecting circuit used for executing a re-read operation and connected to the circuit of Fig. 6.
DESCRIPTION OF THE PREFERRED EMPODIMENTS
Before describing the preferred embodiments, an explanation will be made of a conventional buffer-storage control system for reference.
As illustrated in Fig. 1, a general data processing system or a data processor comprises a CPU 1, a channel unit (CHU) 2, a main storage unit (MSU) 3, and a memory control unit tMCU~ 4 which couples all these units. The CHU 2 controls one or more channels which are connected thereto and to which one or more input/output apparatuses and the like are coupledO The MCU 4 effects memory-access control between the CPU 1, the CHU 2, and the MSU 3.
The CPU 1 comprises, as shown in Fig. 2, an instruction unit 5, an execution unit 6, a storage control unit 7, and a buffer storage or high speed buffer (HSB) 8.
In Fig. 2, the instruction unit 5 fetches and decodes instructions sequentially and controls the operation of the execution unit 6, and the storage control unit 7. The execution unit 6 effects operations in accordance with instructions decoded by the instruc-tion unit 5, thereby executing the instructions sequen-tially. The storage control unit 7 controls the access operation to the HSB 8 and the MSU 3 (Fig. 1) and is connected to the MCU 4 (Fig. 1). The HSB 8 and the MSU 3 compose a memory system having a two-level hierarchical structure.
In the above-mentioned system, the storing operation to the HSB 8 is per~ormed by the routine of detecting, first, whether or not the address to which data is stored is in the HSB 8 and of effecting the actual write operation when the address is found in the HSB 8.
Figure 3 is a block circuit diagram of circuit portions relating to the storing operation to the HSs 8 of a conventional system. Figure 4 is a time chart of the storing operation corresponding to the block circuit diagram of Fig. 3. In these drawings, 9 designates an effective address register (EAR) which is provided in the storage control unit 7 and which receives an address for an instruction-fetching operation or operand-access operation from the instruction unit 5 (Fig. 2) in the CPU. In the HSB 8, 21 designates a tag portion; 22 a data portion; 23-0, 23-1, ..., 23-F comparators; 24 an encoder; 25 a way number register (WNR); 10 and 11 a B2 register and an operand address register (OPAR), both provided in the storage control unit 7; and 30-0, 30-1, ..., 30-F gate circuits controlled by the outputs of the comparators 23-0, 23-1, ..., 23-F to pass the read data 5 from the ways 0 through F of the data portion 22, respectively.
The tag portion 21 comprises, for example, 16 ways (way 0, way 1, ..., way F) each having, for example, 64 entries. The data portion 22 also comprises, for example, 10 16 ways (way 0, way 1, ..., way F) each having, for example, 64 blocks. Each of the blocks of the ways in the data portion 22 has a length of 64 byte. Thus, the data portion has, for example, a memory capacity of 64 Kbyte. Each of the blocks of the ways in the tag 15 portion 21 memorizes a validity bit and upper address bits 8 through 19 of the data stored in the corrre-sponding block of the data portion 22.
In the storing operation, the HSB 8 is read by using a storing address, and it is checked whether or 2~ not the storing address is found in the HSB 8. In this case, the storing address is set into the EAR 9 shown in Fig. 3. By using bits 20 through 25 of the EAR 9 which correspond to a block address of the HSB 8, ~he content of the tag portion 21 of the HSB 8 is read. In the tag 25 portion 21 are stored validity bits (V bits) indicating whether the contents thereof are valid or not and upper address bits 8 through 19 of the data stored in the corresponding block. If any of the above-mentioned valid bits (V bits) is in the "on" state, the upper 30 address bits ~ through 19 and the bits 8 through 19 of the EAR 9 are compared by the comparators 23-0, 23-1, ..., 23-F, thereby detecting whether the storing address is memorized in the HSB 8 or not. If any comparator indicates coincidence, the number of the corresponding 35 way is encoded by the encoder 24 and set in the WNR 25, which is used for designating the way number to be written when the actual write operation is effected.
An explanation will now be made of the storing operation in reference to Fig. 3 using the time chart in Fig. 4. At first, in a pipeline data processing system, a priority flip-flop Popfch which is used for setting a storing address to the EAR 9 and which indicates the priority of using a pipeline is set, and a priority cycle (P-cycle) starts. Thereafter, the content of the tag portion 21 of the HSB 8 is read in two cycles B1 (buffer 1) and B2 (buffer 2~. At the end of the B2 cycle, the WNR 25 is subjected to a write operation.
The address data set in the EAR 9 is shifted into a B2 register 10 at the B2 cycle and memorized in the OPAR 11 at an R cycle. When the write operation to the HBS 8 is effected, a priority flip-flop Popst is set, the write address is loaded from the OPAR 11 to the EAR 9, and data is written into the block in a corresponding way of the data portion 22 of the HSB 8 designated by the content of the WNR 25.
Since there is one EAR 9, when such a storing operation is continuously effected and if the setting timings of setting the afore-mentioned priority flip-flops Popfch and Popst overlap, the setting of the Popfch of the succeeding instruction is delayed, as illustrated in the time chart of Fig. 5A. This wastes machine cycle~ and reduces the processing ability of the data processor.
According to the present invention, the priority flip-flops Popfch and Popst can be simultaneously processed as shown in Fig. 5B, thereby preventing delay of the processing by a priority flop-flop Popfch of a succeeding instruction due to a priority flip-flop Popst of a preceeding instruction.
An embodiment of the present invention is explained with reference to the drawings.
Figure 6 illustrates a buffer storage and the like used in a system as an embodiment of the present inven-tion. In Fig. 6, reference numerals 8, 9, 21, 22, 23-0, 7 L~ ~
23-1, ..., 23-F, 24, 25, 30-0, 30-1, ..., 30-F designate the same parts as those explained with reference to Fig. 3. Reference numerals 28-0, 28-1, ..., 28-F
designate selectors (SEL) which are necessary for 5 implementing the present invention and which have the ~unction of switching the address data for accessing a data portion 22 of an HSB 8.
In this embodiment, the tag portion 21 of,the HSR %
is accessed by using bits 20 through 25 of an EAR 9.
10 Regarding the data portion 22 of the HSB 8, it is possible to select either use of bits 20 through 25 of the EAR 9 as address data for each way or use of bits 20 through 25 of an OPAR 11 as address data.
The circuits for this selection are the SEL 28-0, 28-1, ..., 28-F which are controlled by the output signal of the WNR 25. That is, controlled so that only one way, in the data portion 22 of the HSB 8, designated by the content of the WNR 25, is accessed by using the bits 20 through 25 of the OPAR 11 explained with reference to Fig. 4. The simultaneously processed read operation is controlled so that the tag portion 21 of the HSB 8 and the data portion 22, except for the way designated by the content of the WNR 25, are accessed by using bits 20 through 25 of the EAR 9.
sy controlling the operation in this way, the read operation from ways other than the above-mentioned way to be written-in and the write operation are executed in the same machine cycle.
Another embodiment of the present invention will now explained. The embodiment is implemented by using circuits including an OR circuit 26, a way number register valid bit (WNRV) 27, and a gate circuit 29, shown in Fig. 6.
In the above-mentioned embodiment, when buffer-storage control of the "store-through" type is effected, if the storing address is not memorized in the tag ~ t~5 ~
portion 21 of the HSB 8, the WNRV 27 is set by using the OR signal of the coincidence signals C0, Cl, ..., CF
output from the comparators 23-0, 23-1, ..., 23-F
corresponding to the ways 0 through F, considering the fact that in this case it is not necessary to write in the data portion 22. If no coincidence signal is obtained from any comparator, the WNRV 27 is kept in an "off" condition. The gate circuit 29 is controlled by the thus obtained WNRV signal so that all the SEL 28-0, 28-1, ..., 2a-F select the bits 20 through 25 of the EAR 9.
In a write operation controlled in the above-mentioned manner, if no way in the tag portion 21 of the HSB 8 memorizes the storing address and it is not necessary to effect an actual write operation, the read access is allowed unconditionally in the same machine cycle. Even when an actual write operation is effected, it is possible to effect the write operation and a read operation in the same machine cycle if the ways in the tag portion 21 and the data portion do not coincide.
Thereby, the processing ability of the system is in-creased.
In the read operation, if the read address is memorized in the tag portion 21 of the HSB 8 and the way number thereof coincides with the way number for the write operation, the system is controlled so that the read operation is again executed by a way-coincidence detecting circuit shown in Fig. 7. In Fig. 7, reference numeral 12 designates a decoder for decoding the way number, reference numerals 13 AND circuits, and reference numeral 14 an OR circuit.
In the circuit of Fig. 7, when the read address and the write address use the same way numbers of HSB
TAG 21, each of the coincidence outputs C0, Cl, ..., CF
of the comparators 23-0, 23-1, ..., 23-F for every way of the HSB 8 relating to the read address, each of the outputs which relate to the write address and which are ~2~'7~
g obtained from the decoder 12 decoding the contents of the WNR 25 shown in Fig. 6, and the WNRV 27 corre-sponding to the content of the WNR 25 are logically operated by the AND circuit 13, so that the re-read 5 request signal REQ corresponding to the above-mentioned read address is generated.
As mentioned above in detail, in a data processing system which effects pipeline processing according to the present invention, it is possible to execute a read operation and write operation of a buffer storage in the same machine cycle. Especially in a buffer-storage control system of the "store-through" type, when the storing address is not memorized in the buffer storage, the read operation is executed unconditionally in the same machine cycle. Even when the write operation is effected, the read operation is executed again only when the way of the tag portion of the buffer storage coin-cides with the way of the read address. Therefore, the pipeline processing in the above-mentioned data processor can be efficiently executed, and the processing ability of the overall system can be increased.
Each way of the tag portion and the data portion comprises a plurality of blocks, each block being a data unit of a storing or transferring operation. The tag portion has a plurality of valid bits corresponding to the blocks for indicating block validity, i.e., indi-cating that data is already transferred to the block from the main storage and a write operation is possible.
In a data processing system comprising a two-level hierarchical memory system composed of a main storage and a buffer storage, when the memory system is accessed, every way of the above-mentioned tag portion is read out simultaneously, i.e., the coincidence of addresses is checked, to determine whether or not the buffer storage stores data of a designated address. Noncoincidence of any of the addresses in the ways with the designated address means the target data is not stored in the buffer storage. Therefore, the data of the designated address is read from the main storage and transmitted to the buffer storage. Thereafter, the memory system is generally controlled so that the memory access is effected to the buffer storage.
In a buffer-storage control system of a "store-7S~
\
through" type, when store-accessing the main storage, if an address block memorizing the address corresponding to that for the store access is found in the buffer storage, the buffer storage is store accessed at the same time. If the address block is not found in the buffer storage, the memory system is controlled so that the buffer storage is not store-accessed but only the main storage.
If the data processor for performing pipeline processing is continuously storage-accessing the buffer storage, the storing operation and fetching operation caused by a succeeding instruction will overlap and the fetching operation and the subsequent storing operation of the succeeding instruction will be delayed. This wastes machine cycles and reduces the processing ability of the overall computer system.
SUMMARY OF THE INVE~TION
It is the main object of the present invention to realize high speed processing without delay, even when write operations occur in succession, where a write operation requires two cycles of a tag access and a data writing.
It is another object of the present invention to realize the processing of a read request without delay, even when read operations occur in succession after a write operation.
According to the present invention, there is provided a buffer-storage control system for a data processor having a main storage and a buffer storage which has a tag portion and a data portion, each of the tag and data portions having a plurality of ways; a read access to the buffer storage being carried out by ~ccessing simultaneously the tag portion and the data portion, and selecting the output of the data portion on the basis of the result of a comparison in the tag portion; a write access to the buffer storage being carried out by first accessing the tag in a first cycle to detect in which level the data block in question exists, and writing the data into the detected level in the second cycle; the tag portion and the data portion being capable of being independently accessed;
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the address which is the same as the address for the tag portion or other optional address being capable of being selected as an access address for the data portion;
thereby a tag access for a write access request and a writing of the other write request into the data portion can be treated in parallel.
According to a preferred embodiment of the present invention, in the above buffer-storage control system, each tag and data portion is composed of a plurality of ways, and the buffer-storage control system is so constituted that the tag portion and the data portion can be independently accessed and that the data portion is so constituted for every way that it is possible to select one of a plurality of address passes and to select an address ror a read access and an address for a write access for every way, thereby simultaneously effecting a read operation and a write operation in the same machine cycle and executing the read access again only when the read access and the write access are effected for the same way.
BRIEF DESCRIPTION OF THE DRAWINGS
75~^~
These and other ob~ects and advantages of the present invention will become clearer from the ensuring description of a preferred embodiments in reference to the attached drawings, in which:
Fig. 1 is a block circuit diagram of an example of a general data processing system comprising a memory system having a two-level hierarchical structure;
Fig. 2 is a block circuit diagram of the detailed structure of a central processing unit (CPU) used in the data processing system of Fig. l;
Fig. 3 is a block circuit diagram of a buffer storage used in a conventional buffer-storage control system;
Fig. 4 is a timing diagram of the storing operation in the circuit of Fig. 3;
Fig. 5A is a time chart of a pipeline proces-sing sequence in a data processing system using a conventional buffer-storage control system;
Fig. 5B is a time chart of a pipeline proces-sing sequence in a data processing system using abuffer-storage control system according to the present invention;
Fig. 6 is a block circuit diagram of a buffer storage used in a buffer-storage control system according to an embodiment of the present invention; and Fig. 7 is a block circuit diagram of a way-coincidence detecting circuit used for executing a re-read operation and connected to the circuit of Fig. 6.
DESCRIPTION OF THE PREFERRED EMPODIMENTS
Before describing the preferred embodiments, an explanation will be made of a conventional buffer-storage control system for reference.
As illustrated in Fig. 1, a general data processing system or a data processor comprises a CPU 1, a channel unit (CHU) 2, a main storage unit (MSU) 3, and a memory control unit tMCU~ 4 which couples all these units. The CHU 2 controls one or more channels which are connected thereto and to which one or more input/output apparatuses and the like are coupledO The MCU 4 effects memory-access control between the CPU 1, the CHU 2, and the MSU 3.
The CPU 1 comprises, as shown in Fig. 2, an instruction unit 5, an execution unit 6, a storage control unit 7, and a buffer storage or high speed buffer (HSB) 8.
In Fig. 2, the instruction unit 5 fetches and decodes instructions sequentially and controls the operation of the execution unit 6, and the storage control unit 7. The execution unit 6 effects operations in accordance with instructions decoded by the instruc-tion unit 5, thereby executing the instructions sequen-tially. The storage control unit 7 controls the access operation to the HSB 8 and the MSU 3 (Fig. 1) and is connected to the MCU 4 (Fig. 1). The HSB 8 and the MSU 3 compose a memory system having a two-level hierarchical structure.
In the above-mentioned system, the storing operation to the HSB 8 is per~ormed by the routine of detecting, first, whether or not the address to which data is stored is in the HSB 8 and of effecting the actual write operation when the address is found in the HSB 8.
Figure 3 is a block circuit diagram of circuit portions relating to the storing operation to the HSs 8 of a conventional system. Figure 4 is a time chart of the storing operation corresponding to the block circuit diagram of Fig. 3. In these drawings, 9 designates an effective address register (EAR) which is provided in the storage control unit 7 and which receives an address for an instruction-fetching operation or operand-access operation from the instruction unit 5 (Fig. 2) in the CPU. In the HSB 8, 21 designates a tag portion; 22 a data portion; 23-0, 23-1, ..., 23-F comparators; 24 an encoder; 25 a way number register (WNR); 10 and 11 a B2 register and an operand address register (OPAR), both provided in the storage control unit 7; and 30-0, 30-1, ..., 30-F gate circuits controlled by the outputs of the comparators 23-0, 23-1, ..., 23-F to pass the read data 5 from the ways 0 through F of the data portion 22, respectively.
The tag portion 21 comprises, for example, 16 ways (way 0, way 1, ..., way F) each having, for example, 64 entries. The data portion 22 also comprises, for example, 10 16 ways (way 0, way 1, ..., way F) each having, for example, 64 blocks. Each of the blocks of the ways in the data portion 22 has a length of 64 byte. Thus, the data portion has, for example, a memory capacity of 64 Kbyte. Each of the blocks of the ways in the tag 15 portion 21 memorizes a validity bit and upper address bits 8 through 19 of the data stored in the corrre-sponding block of the data portion 22.
In the storing operation, the HSB 8 is read by using a storing address, and it is checked whether or 2~ not the storing address is found in the HSB 8. In this case, the storing address is set into the EAR 9 shown in Fig. 3. By using bits 20 through 25 of the EAR 9 which correspond to a block address of the HSB 8, ~he content of the tag portion 21 of the HSB 8 is read. In the tag 25 portion 21 are stored validity bits (V bits) indicating whether the contents thereof are valid or not and upper address bits 8 through 19 of the data stored in the corresponding block. If any of the above-mentioned valid bits (V bits) is in the "on" state, the upper 30 address bits ~ through 19 and the bits 8 through 19 of the EAR 9 are compared by the comparators 23-0, 23-1, ..., 23-F, thereby detecting whether the storing address is memorized in the HSB 8 or not. If any comparator indicates coincidence, the number of the corresponding 35 way is encoded by the encoder 24 and set in the WNR 25, which is used for designating the way number to be written when the actual write operation is effected.
An explanation will now be made of the storing operation in reference to Fig. 3 using the time chart in Fig. 4. At first, in a pipeline data processing system, a priority flip-flop Popfch which is used for setting a storing address to the EAR 9 and which indicates the priority of using a pipeline is set, and a priority cycle (P-cycle) starts. Thereafter, the content of the tag portion 21 of the HSB 8 is read in two cycles B1 (buffer 1) and B2 (buffer 2~. At the end of the B2 cycle, the WNR 25 is subjected to a write operation.
The address data set in the EAR 9 is shifted into a B2 register 10 at the B2 cycle and memorized in the OPAR 11 at an R cycle. When the write operation to the HBS 8 is effected, a priority flip-flop Popst is set, the write address is loaded from the OPAR 11 to the EAR 9, and data is written into the block in a corresponding way of the data portion 22 of the HSB 8 designated by the content of the WNR 25.
Since there is one EAR 9, when such a storing operation is continuously effected and if the setting timings of setting the afore-mentioned priority flip-flops Popfch and Popst overlap, the setting of the Popfch of the succeeding instruction is delayed, as illustrated in the time chart of Fig. 5A. This wastes machine cycle~ and reduces the processing ability of the data processor.
According to the present invention, the priority flip-flops Popfch and Popst can be simultaneously processed as shown in Fig. 5B, thereby preventing delay of the processing by a priority flop-flop Popfch of a succeeding instruction due to a priority flip-flop Popst of a preceeding instruction.
An embodiment of the present invention is explained with reference to the drawings.
Figure 6 illustrates a buffer storage and the like used in a system as an embodiment of the present inven-tion. In Fig. 6, reference numerals 8, 9, 21, 22, 23-0, 7 L~ ~
23-1, ..., 23-F, 24, 25, 30-0, 30-1, ..., 30-F designate the same parts as those explained with reference to Fig. 3. Reference numerals 28-0, 28-1, ..., 28-F
designate selectors (SEL) which are necessary for 5 implementing the present invention and which have the ~unction of switching the address data for accessing a data portion 22 of an HSB 8.
In this embodiment, the tag portion 21 of,the HSR %
is accessed by using bits 20 through 25 of an EAR 9.
10 Regarding the data portion 22 of the HSB 8, it is possible to select either use of bits 20 through 25 of the EAR 9 as address data for each way or use of bits 20 through 25 of an OPAR 11 as address data.
The circuits for this selection are the SEL 28-0, 28-1, ..., 28-F which are controlled by the output signal of the WNR 25. That is, controlled so that only one way, in the data portion 22 of the HSB 8, designated by the content of the WNR 25, is accessed by using the bits 20 through 25 of the OPAR 11 explained with reference to Fig. 4. The simultaneously processed read operation is controlled so that the tag portion 21 of the HSB 8 and the data portion 22, except for the way designated by the content of the WNR 25, are accessed by using bits 20 through 25 of the EAR 9.
sy controlling the operation in this way, the read operation from ways other than the above-mentioned way to be written-in and the write operation are executed in the same machine cycle.
Another embodiment of the present invention will now explained. The embodiment is implemented by using circuits including an OR circuit 26, a way number register valid bit (WNRV) 27, and a gate circuit 29, shown in Fig. 6.
In the above-mentioned embodiment, when buffer-storage control of the "store-through" type is effected, if the storing address is not memorized in the tag ~ t~5 ~
portion 21 of the HSB 8, the WNRV 27 is set by using the OR signal of the coincidence signals C0, Cl, ..., CF
output from the comparators 23-0, 23-1, ..., 23-F
corresponding to the ways 0 through F, considering the fact that in this case it is not necessary to write in the data portion 22. If no coincidence signal is obtained from any comparator, the WNRV 27 is kept in an "off" condition. The gate circuit 29 is controlled by the thus obtained WNRV signal so that all the SEL 28-0, 28-1, ..., 2a-F select the bits 20 through 25 of the EAR 9.
In a write operation controlled in the above-mentioned manner, if no way in the tag portion 21 of the HSB 8 memorizes the storing address and it is not necessary to effect an actual write operation, the read access is allowed unconditionally in the same machine cycle. Even when an actual write operation is effected, it is possible to effect the write operation and a read operation in the same machine cycle if the ways in the tag portion 21 and the data portion do not coincide.
Thereby, the processing ability of the system is in-creased.
In the read operation, if the read address is memorized in the tag portion 21 of the HSB 8 and the way number thereof coincides with the way number for the write operation, the system is controlled so that the read operation is again executed by a way-coincidence detecting circuit shown in Fig. 7. In Fig. 7, reference numeral 12 designates a decoder for decoding the way number, reference numerals 13 AND circuits, and reference numeral 14 an OR circuit.
In the circuit of Fig. 7, when the read address and the write address use the same way numbers of HSB
TAG 21, each of the coincidence outputs C0, Cl, ..., CF
of the comparators 23-0, 23-1, ..., 23-F for every way of the HSB 8 relating to the read address, each of the outputs which relate to the write address and which are ~2~'7~
g obtained from the decoder 12 decoding the contents of the WNR 25 shown in Fig. 6, and the WNRV 27 corre-sponding to the content of the WNR 25 are logically operated by the AND circuit 13, so that the re-read 5 request signal REQ corresponding to the above-mentioned read address is generated.
As mentioned above in detail, in a data processing system which effects pipeline processing according to the present invention, it is possible to execute a read operation and write operation of a buffer storage in the same machine cycle. Especially in a buffer-storage control system of the "store-through" type, when the storing address is not memorized in the buffer storage, the read operation is executed unconditionally in the same machine cycle. Even when the write operation is effected, the read operation is executed again only when the way of the tag portion of the buffer storage coin-cides with the way of the read address. Therefore, the pipeline processing in the above-mentioned data processor can be efficiently executed, and the processing ability of the overall system can be increased.
Claims (8)
1. A buffer-storage control system in a data processor comprising a main storage and a buffer storage which has a tag portion and a data portion, each of the tag and data portions having a plurality of ways;
a read access to the buffer storage being carried out by accessing simultaneously the tag portion and the data portion, and selecting the output of the data portion on the basis of the result of a comparison in the tag portion;
a write access to the buffer storage being carried out by first accessing the tag in a first cycle to detect in which level the data block in question exists, and writing the data into the detected level in the second cycle;
the tag portion and the data portion being capable of being independently accessed;
the address which is the same as the address for the tag portion or other optional address being capable of being selected as an access address for the data portion;
thereby a tag access for a write access request and a writing of the other write request into the data portion can be treated in parallel.
a read access to the buffer storage being carried out by accessing simultaneously the tag portion and the data portion, and selecting the output of the data portion on the basis of the result of a comparison in the tag portion;
a write access to the buffer storage being carried out by first accessing the tag in a first cycle to detect in which level the data block in question exists, and writing the data into the detected level in the second cycle;
the tag portion and the data portion being capable of being independently accessed;
the address which is the same as the address for the tag portion or other optional address being capable of being selected as an access address for the data portion;
thereby a tag access for a write access request and a writing of the other write request into the data portion can be treated in parallel.
2. A system according to claim 1, wherein the tag portion address in the preceding cycle is used for said other optional address.
3. A system according to claim 2, wherein said selection of said access address for the data portion is carried out in the manner that, when write requests occur in succession, the tag portion data for the preceding cycle is selected, and when there is no coincidence in the results of the tag portion accesses for the write request in the preceding cycle and a read request occurs in the present cycle, the address which is the same as the address for the tag portion is selected.
4. A buffer-storage control system according to claim 1 wherein each of said tag and data portions are composed of a plurality of ways, and wherein said buffer-storage control system is so constituted that said tag portion and said data portion can be independently accessed, and that said data portion is so constituted for every way that it is possible to select one of a plurality of address paths and to select an address for a read access and an address for a write access for every way, thereby simultaneously effecting a read operation and a write operation in the same machine cycle and executing the read access again only when the read access and the write access are effected for the same way.
5. A buffer-storage control system according to claim 4, wherein said buffer-storage control system comprises comparators for every way, each of which comparators compares an address for access operation and an address stored in the corresponding way, and a way number register for memorizing a number of a way corresponding to the comparator which outputs a coincidence signal, the output of said way number register being used for selecting the address in every way of said data portion.
6. A buffer-storage control system according to claim 5, wherein said buffer-storage control system further comprises selectors, each of which selectors corresponds to a way of said data portion and each of which selects one of addresses input thereto, said selectors being controlled on the basis of the output of said way number register.
7. A buffer-storage control system according to claim 5, wherein said buffer-storage control system further comprises an OR circuit which receives signals of valid bits from said ways of said tag portion, and a gate circuit which passes the output of said way number register in accordance with the output of said OR
circuit.
circuit.
8. A buffer-storage control system according to claim 5, wherein said buffer-storage control system comprises a way-coincidence detecting circuit which detects coincidence between the way number memorized in said way number register and the number of the way memorizing address which corresponds to an input address.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58085351A JPS59213084A (en) | 1983-05-16 | 1983-05-16 | Buffer store control system |
| JP58-085351 | 1983-05-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1218753A true CA1218753A (en) | 1987-03-03 |
Family
ID=13856259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000453619A Expired CA1218753A (en) | 1983-05-16 | 1984-05-04 | Buffer-storage control system |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US5097414A (en) |
| EP (1) | EP0125855B1 (en) |
| JP (1) | JPS59213084A (en) |
| KR (1) | KR890003688B1 (en) |
| AU (1) | AU551435B2 (en) |
| BR (1) | BR8402299A (en) |
| CA (1) | CA1218753A (en) |
| DE (1) | DE3485487D1 (en) |
| ES (1) | ES8503868A1 (en) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3687739T2 (en) * | 1985-12-02 | 1993-08-19 | Ibm | MEMORY ARRANGEMENT WITH MULTIPLE READ-WRITE ACCESS. |
| JPS63257853A (en) * | 1987-04-03 | 1988-10-25 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | Cash memory system |
| JPH0727492B2 (en) * | 1988-01-21 | 1995-03-29 | 三菱電機株式会社 | Buffer storage |
| JPH01280860A (en) * | 1988-05-06 | 1989-11-13 | Hitachi Ltd | Multiprocessor system with multiport cache memory |
| US5247649A (en) * | 1988-05-06 | 1993-09-21 | Hitachi, Ltd. | Multi-processor system having a multi-port cache memory |
| US5214777A (en) * | 1989-03-27 | 1993-05-25 | Ncr Corporation | High speed read/modify/write memory system and method |
| JPH077356B2 (en) * | 1989-05-19 | 1995-01-30 | 株式会社東芝 | Pipelined microprocessor |
| JPH0740247B2 (en) * | 1989-06-20 | 1995-05-01 | 松下電器産業株式会社 | Cache memory device |
| US5442769A (en) * | 1990-03-13 | 1995-08-15 | At&T Corp. | Processor having general registers with subdivisions addressable in instructions by register number and subdivision type |
| JP2636485B2 (en) * | 1990-09-21 | 1997-07-30 | 日本電気株式会社 | Cache storage |
| JPH04145552A (en) * | 1990-10-05 | 1992-05-19 | Nec Corp | Cache storage device |
| JPH04199242A (en) * | 1990-11-26 | 1992-07-20 | Nec Corp | Cache storage device |
| JPH04199243A (en) * | 1990-11-26 | 1992-07-20 | Nec Corp | Cache storage device |
| US5510973A (en) * | 1991-08-15 | 1996-04-23 | Fujitsu Limited | Buffer storage control system |
| JPH05143449A (en) * | 1991-11-22 | 1993-06-11 | Fujitsu Ltd | Main memory data write control method |
| JP2868141B2 (en) | 1992-03-16 | 1999-03-10 | 株式会社日立製作所 | Disk array device |
| US5678040A (en) * | 1993-10-29 | 1997-10-14 | Motorola, Inc. | Method for managing a hierarchical design transaction |
| US5860149A (en) * | 1995-06-07 | 1999-01-12 | Emulex Corporation | Memory buffer system using a single pointer to reference multiple associated data |
| US5915265A (en) * | 1995-12-22 | 1999-06-22 | Intel Corporation | Method and apparatus for dynamically allocating and resizing the dedicated memory in a shared memory buffer architecture system |
| JPH09237162A (en) * | 1996-02-23 | 1997-09-09 | Hewlett Packard Co <Hp> | Scanning data storage system, its stylus and medium abrasion managing methods and remaining life display device |
| US5924115A (en) * | 1996-03-29 | 1999-07-13 | Interval Research Corporation | Hierarchical memory architecture for a programmable integrated circuit having an interconnect structure connected in a tree configuration |
| US6029237A (en) * | 1997-10-08 | 2000-02-22 | Dell Usa, L.P. | Method for simulating the presence of a diskette drive in a NetPC computer that contains only a hard disk drive |
| JP2014006807A (en) * | 2012-06-26 | 2014-01-16 | Fujitsu Ltd | Processor, cache memory control apparatus, and cache memory control method |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4208716A (en) * | 1978-12-11 | 1980-06-17 | Honeywell Information Systems Inc. | Cache arrangement for performing simultaneous read/write operations |
| US4293910A (en) * | 1979-07-02 | 1981-10-06 | International Business Machines Corporation | Reconfigurable key-in-storage means for protecting interleaved main storage |
| JPS5619575A (en) * | 1979-07-25 | 1981-02-24 | Fujitsu Ltd | Data processing system having hierarchy memory |
| JPS5694567A (en) * | 1979-12-28 | 1981-07-31 | Fujitsu Ltd | Busy control system for buffer memory |
| US4407015A (en) * | 1980-11-26 | 1983-09-27 | Burroughs Corporation | Multiple event driven micro-sequencer |
| US4439829A (en) * | 1981-01-07 | 1984-03-27 | Wang Laboratories, Inc. | Data processing machine with improved cache memory management |
| CA1187198A (en) * | 1981-06-15 | 1985-05-14 | Takashi Chiba | System for controlling access to channel buffers |
| US4493026A (en) * | 1982-05-26 | 1985-01-08 | International Business Machines Corporation | Set associative sector cache |
-
1983
- 1983-05-16 JP JP58085351A patent/JPS59213084A/en active Granted
-
1984
- 1984-05-04 EP EP19840303047 patent/EP0125855B1/en not_active Expired - Lifetime
- 1984-05-04 DE DE8484303047T patent/DE3485487D1/en not_active Expired - Fee Related
- 1984-05-04 CA CA000453619A patent/CA1218753A/en not_active Expired
- 1984-05-09 KR KR8402493A patent/KR890003688B1/en not_active IP Right Cessation
- 1984-05-10 AU AU27887/84A patent/AU551435B2/en not_active Ceased
- 1984-05-14 ES ES532492A patent/ES8503868A1/en not_active Expired
- 1984-05-15 BR BR8402299A patent/BR8402299A/en not_active IP Right Cessation
-
1989
- 1989-10-17 US US07/423,588 patent/US5097414A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59213084A (en) | 1984-12-01 |
| KR840008849A (en) | 1984-12-19 |
| ES532492A0 (en) | 1985-03-01 |
| ES8503868A1 (en) | 1985-03-01 |
| EP0125855A2 (en) | 1984-11-21 |
| EP0125855B1 (en) | 1992-01-29 |
| KR890003688B1 (en) | 1989-09-30 |
| EP0125855A3 (en) | 1988-05-25 |
| AU551435B2 (en) | 1986-05-01 |
| US5097414A (en) | 1992-03-17 |
| DE3485487D1 (en) | 1992-03-12 |
| AU2788784A (en) | 1984-11-22 |
| JPS6215896B2 (en) | 1987-04-09 |
| BR8402299A (en) | 1984-12-26 |
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