CA1222652A - Dielectric optical waveguide and technique for fabricating same - Google Patents

Dielectric optical waveguide and technique for fabricating same

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Publication number
CA1222652A
CA1222652A CA000418683A CA418683A CA1222652A CA 1222652 A CA1222652 A CA 1222652A CA 000418683 A CA000418683 A CA 000418683A CA 418683 A CA418683 A CA 418683A CA 1222652 A CA1222652 A CA 1222652A
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Prior art keywords
layer
core
waveguide
overlying
cladding region
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CA000418683A
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French (fr)
Inventor
Kazuhito Furuya
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AT&T Corp
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Western Electric Co Inc
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    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13Integrated optical circuits characterised by the manufacturing method
    • G02B6/132Integrated optical circuits characterised by the manufacturing method by deposition of thin films

Abstract

ABSTRACT
DIELECTRIC OPTICAL WAVEGUIDE AND TECHNIQUE FOR FABRICATING SAME
A multilayer dielectric optical waveguide (30, 40) is formed on a III-V semiconductor substrate layer (6) comprised of either InGaAsP or AlGaAs. A lower cladding layer (30) of dielectric material such as SiOx, (x-2) having a lower index of refraction than the substrate layer is directionally deposited on an exposed surface (17) of the substrate layer by a controlled evaporation process.
A core layer (40) is fabricated on the lower cladding layer by coating an exposed surface (31) of the lower cladding layer with a dielectric material having an index of refraction greater than the index o-f the cladding layer.
One material useful as the core layer is polyimide Both one-dimensional and two-dimensional waveguides are capable of being made by appropriate addition of an upper cladding layer (50 or 60) about the core layer. The refractive index of the upper cladding layer is less than the refractive index of the core layer.

Description

`
~2;~5'~

K. FURUYA 2 DIELECTRIC OPTICAL WAVE DE AND TECilNIQUE
FOR FABRICA'rING SAME
._ _ The present invention relates to the ~ield of integrated optics, and preferably to monolithio integration of acti~ve and pas~i~e optical circuit components an a single substrate.
Integration of optical circuit components ha~
been established ~or a number o~ years. Two integration methodologies have been developed during thi~ time. A ~irst methodology involves the ~abrication of dielectric waveguide~ on a ~ilicon (Si) wa~er substrate. A second methodology utilizes ~emiconductor material ~or fabricating waveguide~
in a GaAs/AlGaAs optical crystal, Within the ~irst methodology, several techniques have been reportad ~or accomplishing fabrication of a dielectric wave~uide on the ~ilicon substrate. See, ~or example, W. Stutius et al.~ "Silicon nitride films on ~ilicon for optical waveguide~," Appl. Optics, Vol. 16, pp. 3218-3222, December 1977; G. Marx et al., "Integrated Optlcal Detector Array, Waveguide, and Modulator Based on Silicon Technology,~ IEEE J. of Solid-State Circuits, Vol. SC-12, pp. 10-13, February 1977; J. Boyd et al., "An Inteerated Optical Waveguide and Charge-Coupled Device Image Arrayp~ IEEE J. of Quantu~ Electronlcs, Vol. Q~-13, pp. 282-287, April 28 1977, and ~Integrated optioal 9ilicon photodiode array,~

:~2~6S~

Appl. Optics, Vol. 15, pp. 1389-1393, June 1976.
Stutius et al. show a silicon nitride ($13N~) thin ~ilm waveguide grown by low-pressure chemical vapor - deposltion on a silicon dioxide (SiO2) buffer layer.
The SiO2 buffer layer is a steam oxide layer grown ~t 1100 degrees Centigrade in a conventionnl horizontal reactor. In the Marx et al. reference, a hybrid, i.e., non-monolithic, integrated optical circuit is shown wherein a Corning 7059 glass waveguide film interconnects devices by taper coupling. The 7059 glass waveguide film i8 sputtered onto a SiO2 bu~fer layer which is thermally grown ut high temperature on a silicon ~ubstrate. Boyd et al. describe an integrated opt1cal component structure incorporating a taper-coupled, KPR photoresist waveguide spin-coated on a SiO2 buffer layer which is thermally grown at high temperature over a silicon substrate.
Although the techniques of Stutius et al., Marx et al., and Boyd et al. appear to offer approaches to integrating certain optical components with dielectric waveguides, their reliance on silicon teohnology and on high temperature thermal growth of the SiO2 buffer layer cause these techniques to be inapplicable for monolithic integration on optical cryst~ls suoh as AlGaAs/GaAs and InGaAsP/InP heterostructures. Silicon technology is a limitation on the applicability of the~e techniquss for monolithic integration besau~e thc bandgap str~eture o~
silicon is not conducive to fabrication of e~icient active optical circuit component~ such as light source6 on the silicon wafer substrate. Thermal growth is,also a limitation on applicability because the temperatures involved in the thermal growth process are considerably hiKher than the melting pcint temperatures of optical crystals in the AlGaA~/GaAs system or the InGaAsP/InP
9ystem.
As mentioned above, the second integration methodoloey provides an approach ~or fabrlcating 38 9~miconductor waveguldes in optical crystals of the - :~2 ~lGaAs/GaAs system. This methodology has resul-ted in the ~onolithic integration of active and passive optical circuit components such as light source~, modulators~ a~plifiers, detectors and couplers, as descrihed in the references cited below. .J L. Merz et al., "Integrated GaAs-AlxGal xAs injection lasers and detectors with etched reflector~," Appl. Phys. Lett., Vol. 30, pp.530-533, May 1977, disclose monolithic integration of a GaA~ double heterostructure laser with a passive waveguide and an external cavity detector ln a four layer GaAs-AlxGal_xAs device.
The integration of a detector or ~odulator with a large optical cavity, distributed Bragg reflector laser has been achieved by M. Shame et al. as disclosed in "Monolithic integration of GaAs~GaAl)As light modulator~
and distributed-Bragg-re~lector lasers~" Appl. Phys.
Lett., Vol. 32, pp. 314-316, March 1978. ~. Aiki et al.
in an article, "Frequency multiplexing light source with monoIithically integrated distributed-feedback dlode lasers," Appl. Phys. Lett., Vol. 29, pp. 506 50~, October 19767 have fabricated 3iX distributed ~eedback lasers on a ~ingle chip with the laser outputs t at dif~erent frequencies being multiplexed lnto a single waveguide Utilizlng an integrated twin guide structure, K.Ki~hino et al. have demon~trated the couplin~ of two devioes to a passive wavegulde in an ar~icle, "Monolithio integration of la~er and amplifier/detector by twin-guide ~tructure," Japan J. Appl. Phys., Vol. 17, pp.
589-590, M~rch 1978.
For the approaohes described above in relati'on to the second methodology, the passive waveguide is a layer of semiconductor material which i9 ~ubstantially transparent to the lightwave~ conducted therein.
Variation3 in the thickneas and the refractive index of the waveguide layer as well as the couplin~ length of the device affect proper operation of the resulting integrated optlcal cirou~t. In order to control these 38 variations, close monitoring is required for, and -~Z~65;~

increases the complexity oE, crystal growth processes employed in this integration methodology.
Although it is well known that dielectric waveguides of the Eirst methodology are more eEficient than semi-conductor waveguides of the second methodology, theproponents of the two methodologies described above have failed to address the problem of fabricating a mono-lithically integrated optical circuit which includes dielectric optical waveguides.
l~ In accordance with an aspect of the invention there is provided an integrated optical device, comprising a substrate which includes a first surface; a material region overlying said first surface, which region inc]udes direct bandgap semiconductor material and is capable of emitting light upon the application of energy, said region also including a second surface, from which light exits, inclined relative to said first surface, characterised in that said device further comprises a waveguide over-lying said first surface and including a core, said core
2~ including dielectric material essentially free of semi-conductor material and two surfaces substantially parallel to one another and to said first surface, and said core also abutting at least a portion of said second surface.
In accordance with another aspect of the invention there is provided a method for fabricating an optical device, comprising the step of ~orming a material region overlying a ~irst surface of a substrate, which region includes direct bandgap semiconductor material and is capable of emitting light upon the application of energy, 3a said material region including a second surface, from which light exits, inclined relative to said first surface, characterised in that said method further comprises the step of forming a waveguide overlying said first surface, said waveguide including a core, said core including dielectric material essentially free of semiconductor ~22265~
- 4a -material and two surfaces substantially parallel to one another and to said first surface, said core also abutting at least a portion of said second surface.
Monolithic integration on a IIT-V heterostructure optical crystal is accom~lished with dielectric optical waveguides in accordance with an embodiment of the invention. The dielectric waveguides are formed on either an AlzGal zAs waveguide substrate layer in a AlGaAs/GaAs system or an Inl yGayAsxPl_x waveguide substrate layer in an InGaAsP/InP system. Each :~3 9 ~ t- ~ >

waveguide includes at least a first layer of dielec-tric material such as SiO2 having a re~ractive index substantially lower than the re:~ractive index of the substrate layer. The ~irst layer is ormed by controlled, low temperature depositioll of evaporated SiO2 on the substrate layer. Generally, the first layar act~ as a lower cladding layer.
A second layer acting as a core layer of the dielectric optical waveguide is formed by coating the first layer with a dielectric material having a refractive index higher than the refractive index of first layer. One dielectric material suitable for spin coating as a core layer is polyimide. Wavegulde shape in the direction of light propagation is defined by selective removal o~ portions of the core layer through appropriate masking and etching techniques.
A -third layer acting as an upper cladding layer of the dielectric optical waveguide is deposited or spin-coated over the core layer. The upper cladding layer exhibits an index of refraction which is lower than the index o~ refraction for the core layer. Composition of the upper cladding layer can be substantially identical to the composition of the lower cladding layer to avoid asymmetry in the propagation characteri~tic~ of the optical waveguide. The upper cladding layer al~o passivates the surface of the entire integrated circuit. Where the waveguide shape is de~ined, the core layer is completely surrounded by both cladding layer~, which result~ in a two-dimensional dielectric optioal waveguide~ Where no waveguide shape i8 defined in the direction of light propagation, the core layer is bounded on only two parallel æides by the cladding layers, which results in a one-dimensional dielectric optical waveguide.
A more complete understanding of the invention may be obtained by readlng the ~ollowing description of a specific illustrative embodiment of the invention in 38 con~unction with the appended drawings in which:

6S~

FIG. 1 shows a portion of a multilayer semiconductor heterostructure body having a stripe mask deposited on the (100) surface with the str-ipe along the <01~> directlon;
FIGS. 2, 3, ~ and 5 show structural change~ of the semiconductor body of FIG. 1 after each of four sequential steps in an exemplary etching process for exposing smooth crystallographic surfaces;
FIG. 6 shows formation of a first dielectric waveguide layer on surface 17 of the semiconductor body of ~IG. 5;
FIG. 7 shows formation of a second dielectric waveguide layer on fiurface 31 of the semiconductor and dielectric body o~ FIG, 6;
FIG. 8 shows formation of a third dielectric waveguide layer on surface 41 of the semiconductor and dielectric body o~ FIG. 7;
FIG. 9 shows structural changes of the ~emiconductor body of FIG. 7 after removal oi~ selected portions of the seoond dielectric waveguide layer; and FIG. 10 ehow~ formation of the third dielectric w~veguide layer on the semiconductor and dielectric body of FIG. 9, In its most general terms, the invention is understood as~ and realized by, ~orming a multilayer dielectric optical waveguide on either a ternary or a quaternary III-V semiconductor compound substrate, Presence o~ additional semiconductor heterostructure or double heterostructure layer~, such as layers 2, 3~ 4, and 5 in the figUres~ provides insight only into ~he utility of the claimed invention as a means ~or monolithlcally integrating optical circuit components on a single substrate, Hence, the following description is intended not only to set ~orth the claimed invention in ~undamental detail, but also to e~plain the implementation o~ the claimed invention in a monolithic integration environment, 38 The detailed description is organized by section ~2~65~

-to describe basic features of a heterostructure sellliconductor body as shown in FIG. l, surface preparation of the heterostructure 6emiconductor body to expose a flat ternary or quaternary waveguide substrate layer (FIGS. 2 through 5), and formation of either a one-dimen~ional (FIGS. 6, 7 and 8) or two-dimensional (FIGS. 6, 7, 9 and 10) dielectric optical waveguide on the exposed waveguide substrate layer.
Optoelectronic and integrated optics devlces are grown in certain desirable crystallographic directions.
For III-V semiconductor heterostructure devices such as lasers and the like composed of either InGaAsP/InP or AlGaAs/GaA~ on a (100) substrate, a desired propagatlon direction is along the ~OlI> axis.
FIG. 1 show~ a multilayer semiconductor heterostructure crystalline body having mask 1 on the (100) crystallographic plane. The semiconductor body, as stated above, is in either the InGaAsP/InP system or the AlGaA~/GaAs sy~tem. Also included in FIG. 1, as well as all subsequent figure~, is a set of lattice ba3is vector~ indicating the three-dimensional orientation of the ssmiconductor body.
The ~emiconductor heterostructure of FIG. 1 comprises mask layer 1, p+--type cap layer 2, p-type upper cladding layer ~J n-type or undoped active layer 4, n-type lower cladding layer 5, n-type waveguide substrate layer 6 9 and n-type sub~trate 7, ~he conductivity type ~or each layer may be rever~ed so that each p-layer become~ an n-layer and each n-layer becomes a p-l~yer.
~urther, cap layer 2 is included only to show one exemplary embodiment of a heterostructure body.
Alternative embodiments can be realized by omitting the growth o~ cap layer 2 from fabrication of the ~emiconductor heterostructure body.
Semiconductor materials for the heterostructure are chosen from the group of III-V compounds. In the 38 InGaA9P/InP sy~tem, a binary III-V compound, InP, i~

~2~2tiS~

employed for cladding layers 3 and 5 and for substrate 7.
A quaternary III-V cosnpound, Inl yGayAsxYl x~ i9 utilized for cap layer 2, active layer l~, arld waveguide substrRte layer 6 wherein the alloy compoæition ratios x and y are chosen to produce a particular wavelength or energy bandgap and lattice constant for the heterostructure. For a description of techniqueæ for choosing x and y, see R. Moon et al, "Bandgap and Lattice Constant of GaInAsP as a Function o~ Alloy Composition"~ ~ , Vol. 3, p. 635 (1974).
In the description which follows, exemplary compositior ratio~, x _ 0.52 and y = 0.22, are selected to produce a wavelength of 1.3 ~m (0.95eV). It is important to note that the claimed invention is equally applicable when these ratios are varied to produce wavelengths in the range of 0.95 ~m to 1.8 ~m. For concentration ratios producing wavelengths above 1.5 ~m, it is necessary to grow a quaternary antimeltback layer between layers 3 and 4 during liquid phase epitaxial growth of the heterostructure. The presence of such an antimeltback layer requires the surface preparation described below to be modi~ied only slightly, in terms of etching exposure times, to provlde acceptable results.
For a heterost~ucture body as shown in FIG. 1 in the InGaAsP/InP sygtem, cap layer 2 is approximately 3000-5000 angstroms thick, claclding l~yer~ 3 and 5 are approximately 1.5-3~m thlck, active layer 4 and waveguide substrate layer 6 are approximately 1000-3000 angstroms thick, and substrate 7 is ~pproximately 75-100 ~m thick. Of course, for simplicity and clarity of` explanation, layer thicknesses in FIGS. l -throueh lO are not necessarily drawn to scale.
In the AlGaAs/GaAs ~ystem, a binary III-V
compound, GaAs, is employed for substrate 7. A ternary III-V compound, AlGaAs, i~ utilizèd for layers 2 through 6. Cap layer 2 utilize~ AlqGal ~As; cladding layers 3 and 5 utiliæe AlrGnl rA~ and AluGa~ As, respectively;
38 actlve layer 4 utillzes AlsGal ~As; and wave~uide ~z~s~

substrate layer 6 utilizes AlwGal wA~. Alloy composition ratios q, r, s, u and w are chosen to produce a particular wavelength or energy bandgap and lattice constant for the heterostructure semiconductor body.
In general, compositions ratios q, ~, and w are cho~en to be less than ratios r and u, and for symmetry purposes r and u are equal. A description of techniques for choosing the compositions ratios of the various AlGaAs layers is given by H. Kressel et al. in "Semiconductor Lasers and Heterojunction LEDs," pp. 357-363 (Academic Preqs: New York 1977).
Layer thicknesses for an AlGaAs/GaAs heterostructure body shown in FIG. 1 are substantially identical to those de~cribed above in relation to the InGaAsP/InP system, e~cept ~ubstrate layer 6 are in the range 0.2 to 1.8 ~m.
Surface Pre~ration for InGaA ~ Systems A mask layer ~s deposited on the (100) plane of the InGaAsP/InP semiconductor body by any suitable deposition process such as chemical vapor deposition or the like. An exemplary layer is chemically comprised of silicon-nitride. Mask 1 is formed by photolithography and dry etching of the silicon nitride to have edges bordering the striped region which are substantially smooth. Striped regions in mask 1 leave surface areas ~uch as surface 11 completely exposed, ag opposed to being covered by mask 1. 'rhe stripe in mask 1 is aligned with the <011~ direction o-f the semiconductor heterostructure body. Although this type of stripe mask produces a groove in the semiconductor ~ody, other masks such as the one including only the left or right half of mask 1 as shown in FIG. 1 can be utilized to produce a single wall, i.e., eOr effectively slicing away an unmasked portion of the semiconductor body.
FIGS. 2~ 3, 4, and 5 show structuraL changes which appear after the semiconductor heterostructure 38 body of FIG. 1 is sub~e¢-ted $o etchants in sequential 65~

etching process. The process illustrated by FIGS. 2 through 5 is called sequential etching because each - layer of the multilayer structure directly under exposed surface 11 (FIG. 1) i~ etched away individually in ~equence. That i8 ~ the portion of cap layer 2 directly under exposed surface 11 is etched away with a wet or dry chemical etchant to expose ~urface 12 on cladding layer 3. Since the etching proces~ stop~
at a heterojunction, it is apparent that ~t least the wet chemical etchant must e~hibit the property of material sele¢tivity.
Several wet chemical etchants have been shown to be e~fective for selectively etching quaternary layers such as layers 2 and 4 Examples of several selective etchant~ include: a solution of H2S04:H202:~I20 = (10:1:1) as de~cribed in R.J. Nelson et al., "High-Output Power in InGaAsP/InP (~ = 1.3~m) Strip-Buried Heterostructure Lasers," Applied Physics Lette_s, Vol. 36, p.358 (lg80~;
or AB etchant, wherein the A ~olution is (40.Oml. H20 + 0.3g.AgN03 ~ 40.Oml.l~) and the B
solution is (40.0g~ CrO3 + 40.0ml. H20) and A:B=(l:l) as described in G.H. Olsen et al., ~Universal Stain/
Etchant for Interfaces in III~V Compounds,~ Journal of A~plied Ph~sic~,Vol. 45, No. 11, p~ 5112 (197~);
or a solution of KOH:K3Fe(CN~6:H20. Etching time for the quaternary layers varie~ according to thickne~s of the quaterrlary layer, temperature, and alloy composition ratio~, x and y, for the quaternary layers.
For a 3000 angstroms thicknes~ of layer 2 (A = 1.3~m) and a temperature of 22 degrees Centigrade, the following approximate etching times produce the result~
shown in FIGS. 4 and 6: H2S04:H202:H20 etch for approximately 5 second~, AB etchant ~or approximately 15 seconds, and KOM:K3Fe(CN)6:H20 etch for approximately 8 seconds. This etching ~tep is halted by rinsing the etched ~emiconductor body in deionized water.
FIG. 3 ehows the structur~l change of the 38 8emicondwator body in FIG. 2 after etching in an InP

5;~

selective etch. For this etching step, HCL is a ~itable etchant to cut away the portion of layer 3 under surface 12 (FIG. 2), thereby exposing surface 13 on quaternary layer 4. Although this etchant 6top~
reacting automatically at surface 13, it must be carefully controlled to avoid causing a severe undercut in the remaining portions of layer 3 under mask 1. For an InP
layer thickness of approximately 1.5 ~m, an exemplary etching time period for concentrated HCl is approximately 1~5 second~ to produce the results shown both in FIG. 3 and FIG. 5. After this etching step9 as shown in FIG. 3, it is important to note that the etched, exposed walls o~ layer 3 exhibit crystallographic smoothness~
FIG. ~ illustrates the etructural change apparent in $he semiconductor hetero~tructure body, after the body shown in FIG. 3 is contacted with a wet chemical etchant to selectively etch quaternary layer 4 directly under ~urface 13 for a time period ~ufficient to expo~e sur~ace 14 on layer 5. Also, crystallographic surface 15 20 i9 expo~ed at a definite slope to the surface containing mask 1 and surface 11 (FIG. 1), that is~ the (100) plane.
The etching procedure and -the etchants employed at this ~tep have been de~cribed above in relation to FIG. 2.
FIG. 5 shows the completion of all structural changes caused by the sequential etching proces6. A~ain, an InP selective etchant, HCl, is contacted with exposed sur~aces of the ~emlconduotor body to create an optically flat mirror ~acet at sur~ace 15. In particular, ~urfaee l/t and crystallographic ~urface 15 are brought into contact) via immersion and agitation as described above, with a sv:lution of HCl ~or a time period sufficient to expose a preferred crystallographic plane a~ the optically flat polished mirror facet nnd to expo~e a ~mooth, flat ~urface, 6urface 17, on waveguide substrate layer 6. As shown in FIG. 5, a crystallographic plane preferentially expo~ed by the HCl etctlant is the (011) plane, denoted as ~ur~ace 16, which i~ perpendicular 38 to the (100) plane. Sur~ace 16 i9 an optically flat 2~

mirror facet hecause ~ICl preferentially exposes the ~011) cry~tallographic plane of only -the InP layers, i.e., layers 3 and 5, and does not etch the quaternary layers, layers 2, ~ and 6. Ilowever, the etching process is controlled to ~nake layers 2 through 5 substantially coplanar. For this example, the etching time period in a bath of concentrated ~Cl required to produce exposure of the (011) crystallographic plane a-t surface 16 and the flat surface 17 on waveguide substrate 6 is approximately 20 seconds.
Regardless of the semiconductor heterostructure system being employed, smoothness and flatness dimensions of ~urface 17 are important to subsequent fabrication of the dielectric optical waveguide thereon. As will become apparent below, the smoothness and flatness dimensions of surface l? affect the smoothness and flatness dimensions of the walls of the dielectric optical waveguide. Excessive scattering losses result for a waveguide having rough walls. It is generally regarded -tha-t the smoo-thness of the waveguide walls be controlled to a tolerance of a fraction of the desired optical wavelength over a dimension of about five wavelengths~ See, D. Marcuse, Bell System Technical Journal, Vol. 48, p. 3187 et seq. (1969), and also J.E.
_ Goell et al. 9 ~Ion bombardment fabrication of optlcal waveguides using electron re~ist masks,~ Aepl. ~
Lstt., Vol. 21, pp 72-73 (1972). Because the shape of the waveguide walls is directly determined by the shape of surface 17~ tolerance control of the smoothness of ~urface 17 and waveguide substrate layer 6 is required during the epitaxial growth of the semiconductor hetero~tructure body.
Surface Preparation for AlGaAs As described above, the semiconductor heterostruckure body o-f FIG. 1 is alternatively compri~ed of multiple layer~ of AlGaAs having different composition ratlos. Because the surface preparation techniques for an 38 AlGaAs/GaAs heterostructure are different from those ~2~2~i5~

~or an InGaA~P/InP heterostr-ucture, only FIGS. 1 and 5 are of importance to the following description.
Several etching techniques are known ~or structurally altering an AlGaAs ~emiconduotor body such as is shown in FIG. 1 by an amount sufficient to re~ult in the grooved semiconductor body shown in FIG. 5 having substantially smooth and flat surfaces 16 and 17. One technique reported by J.L. Merz et al. in their IEEE J.
of Quantum Electronics article entitled "GaAs Integrated Optical Circuits by Wet Chemical Etching, ~ Vol QE~15, pp. 72-82 (1979), involves the use of a two-step preferential etching process to produce flat surface6.
Another teehnique is disclosed by R. Logan et alO in U.S.
Patent 3,883,219 issued May 13, 1975. The Logan et al.
technique involves a slow etching process using Br2 ~ CH30H.
After surfaces 16 and 17 in either heterostructure system have been exposed, mask 1 is removed by a conventional dry etching technique. One 6uch dry etching technique is plasma etchin~ in an atmosphere of CF4. An op-tional step in surface preparation is to coat at least layer 16 with a reflective or anti-reflecti~e coating by evaporation, for example, to ensure sufficient reflection or coupling, raspectively, between layers 3, 4 and 5 and the dielectric optical waveguide to be formed on sur~ac~ 17.
Anti-re~lective coatings exhibit an index of refraction, nar, equal to the geometrical average of the indices of refraction, n~ and n40, for the co~e layers of the abutting active and passive waveguides, i.e., layers 4 and 40 (FIG. 7), re~pectively~ That is, nar = (n4n4 The thickness of the anti-reflective coating layer~
lar, is given by the expression, izzz~s~
_ 14 lar 4nar where A i~ the deslre wavelength o~ light Materials which are suitable for e~aporation onto surface 16 in an InGaAsP/InP system to form an anti-reflective coating layer are ~etal oxide~ ~uch as Ta205 and TiO5.
Reflective coatings possess an index of refra~tion, n~, lower than the index, n40, for the core layer of the passive dielectrio waveguide, layer 40 (FIG. 7). The thlckness of the reflective coating, 1~, formed by evaporation, for example, is given by the sxpres~ion, 1 _ A
R ~ 4nR
An exemplary reflective coating material i~ MgF2 which ha~ a refractive index nR equal to 1.35. ~ith this ooating material as a reflective layer on surface 16 in an InGaAsP/InP with a polyimide/SiOx waveguide, to be described below, the reflectivity increases by approximately 100 percent.
_ormation of One-Dimensional Waveguide FI~S. 6, 7 and 8 show successive illu~trative step~ for fabricating a one-dimensional dielectric optical waveguide on waveguide substrate layer 6 in the ~e~iconductor he~erostructure body shown in FI~. 5.
A typical dielectric optical waveguide comprises an elongated core of dielectric material ~urrounded by a medium having a lower index of refraction. When' a cros~-section of such a waveguide is viewed perpendicular to its optical axis (<Oli~ direction), it i~ apparent that the wavegulde confine~ light in two dimenslons, the <100> and <oii> directions. Hereinafter, thi~ type of structure is referred to as a two-di~ensional waveguide and will be discussed later in more detail. However, when the elongated core i~
3~ covered by the lower index of refraction medium on only 65~

two parallel sides, light i8 confined in only one dimension (<100> d:irection, for instanc0). This latter type of structure is referred to as a on~
dimensional waveguide whose formation i~ discus~ed .immediately below.

.3S

- 16 ~
Forrna-tion o-~ a dielectric optical waveguide on sur-facè 17 o~ waveguide substrate layer 6 begins in FIG. 6 wi-th controlled deposition o~ a dielectric material, such as silicon oxide (SiOx, x~2) to ~orm ~irst waveguide layer 30 only on suriace 17 The dielectric material chosen to ~orm ~irst waveguide layer 30 exhibits an index oi re~raction lower than that o-~ waveguide substrate layer 6. Deposition of the dielectric ma-terial is required to be highly controlled in order -to avoid having the first waveguide layer dielectric material attach to sur~ace 16 and, in particular, to surface 16 above an interiace between layers 4 and 5.
Two low temperature techniques have been developed ~or controlled, direGtional deposition o~ SiOx on layer 6. One technique involves thermal evaporation o~ a silicon monoxide, SiO, source in an oxygen atmosphere.
Another technique involves electron beam evaporation of a silicon dioxide, SiO2, source in a vacuum.
In the thermal evapora-tion technique, the semicond-uctor body oi FIG. 5 is placed in an oxygen (2) a-tmosphere oi approximately 2.0x10 4 mbar. Current is controllably supplied to a tantalum -filament for evaporating the SiO source. It is this current which controls the evaporation rate of the source SiO and also the deposition rate o:E SiO~ on sur-~ace 17 oi layer 6. As stated above, deposition o~ SiOx is directional in tha-t particles oi SiO and SiO2 are in a substan-tially collison-~ree environment and a-ttach only on a ~100 plane, i.e., suriace 17 and other sur~aces parallel thereto. An exemplary deposition rate which yields a controlled, directional deposition -~or ~irst ~aveguide layer 30 is approximately 5 angstroms per second or 0.03 ~m/min. The 2 atmosphere can be varied to change the proportion oi SiO -to SiO2 in layer 30. 0~ course, such variations o~ the 2 a-tmosphere al30 aifect the index o~
re~raction for layer 3n as SiO has a reiractive index o~
1.~0 and SiO2 has a re-~ractive index o~ 6 For the 38 exemplary 0~ atmosphere given above, the resul-ting - 17 ~
stoichiometry of layer 30 i~ SiOx (x-2~, a heterogeneous composition o~ SiO and SiO2 resembling SiO2 with an index o~ refrac-tion o~ 1.50.
The second deposition technique, as stated above, involves electron beam evaporation o~ a SiO2 source in a vacuum. An exemplary vacuum useful for this technique is approximately 10 6 torr. In this technique, the semiconductor body of FIG. 5 is placed in an evacuated chamber with a cruc:ible containing the SiO2 source. An electron beam oi' su:eficient power is focused on the source causing evaporation of SiO2. The power of the beam is carefully monitored to control the depo~ition rate, whereas the vacuum pressure is controlled to produce a directional flow of SiO2 only to those exposed surfaces parallel to surface 17 ((100) plane). Throughout this deposition process, the semiconductor body is at room temperature.
Hence, the bond which occurs at the interi'ace between layers 6 and 30 is an incomplete chemical bond.
First waveguide layer 30 is adjacent to layer 5 o~ the semiconductor heterostructure body, but does not completely abut the surface 16 of layer 5. Surface 31 is the exposed surface of first waveguide layer 30. Surface 31 exhibits essentially the same flatness of smoothness dimensions, that is, planarity as surface 17 except in a narrow region near surface 16 where layer 30 is tapered.
This narrow region of tapar extends no-t more than 0.3 ~m ~rom suri'ace 16.
Layer 30 acts as a lower cladding layer for the dielectric optical wavegllide. In general, layer 30,is approximately as thick as layer 5. In order to avoid radiation loss by evanescent coupling through the waveguide into layer 6, it is desirable for layer 30 to have an approximate thickness of at leæt1 ~m and, preferably, 2.0 ~m. The thickness of layer 30 also determi~es the position of a waveguide core layer, to be formed later, with respec-t to layer ~. Layer 30 should be su~ficiently thick in order to maximisethe transmission coef~icient ~rom semiconductor 38 core layer ~ to an abutting dielectric optical waveguide i2~2~S;~

core layer (FIG. 7, layer 40), that is, mode profile matching between layer 4 and the dielectric waveguide.
Mode profile matching is described below in more detail.
Layers 32 and 33 shown in FIG. 6 are also layers of SiOx (x~2). These layers are on layer 2 on the semiconductor body. Removal of layers 32 and 33 to allow contact attachment is accomplished with well known photoresist exposure and developing techniques. However, for the purposes of this description, removal of layers 32 and 33 is not undertaken.
FIG. 7 shows the formation of second waveguide layer ~0 on surface 31 of first waveguide layer 30 and abutting surface 16 of the semi-conductor heterostructure body. Layer 40 is comprised of a dielectric material having an index of refraction higher than the refractive index of layer 30. Waveguide layer 40 acts as a core layer of the waveguide. As such, it is desirable for the dielectric material chosen for layer 40 to exhibit optical transparency to the wavelength or wavelengths of light intended for propagation therein.
In one exemplary embodiment of this invention, an organic polyimide coating material such as PYRALIN (a trademark of E.I. DuPont de Nemours and Company) polyimide coating, PI2555, is employed for forming dielectric 25 waveguide layer 40. See, also, U.S. Patent 3,179,614 and 3,179,634 issued to W. Edwards on April 20, 1965. PYRALIN*
polyimide coating has a refractive index of approximately 1.70 and is transparent after 100 percent imidization to optical wavelengths in the range 0.85 to 1.8 ~m.
Second dielectric waveguide layer 40 with PYRALIN*
polyimide coating is formed by performing the following steps. 'rhe semiconductor and dielectric body of FIG. 6 is treated with a material to promote adhesion of layer 40 to surfaces 16 and 31. One exemplary adhesion promoter is sold under the product name VM-651 by ~.I. DuPont de Nemours and Company. Next, the polyimide coating film is applied to the semiconductor and dielectric body. Removal 3~ ol` air bubbles present in tlle polyimide coa~ing film is * trade mark 65~

_ 19 --accomplished by then placing -the semiconductor and dielectric hody in a vacuum chamber ~or a short period of time~ At this point the polyimide coa-ting eilm forming layer 40 is in complete contact with at least surfaces 16 and 31, as shown in FIG. 7. The body of FIG. 7 is then placed on a rotating table or spinner at room temperature, where it is held in place by a vacuum and rotated at a speed in the range 3000 to 7000 rpm. for approximately 2 minutes. Speed o~ rotation and viscosity of the polyimide coating film determine the thickness of layer 40 in the <100> direction. An exemplary range of thickness for polyimide coating ~ilm as layer 40 is approximately 0.3 to 1.2 ~m. Curing of the spun polyimide coating ~ilm is accomplished by baking the semiconductor and dielectric body o~ FIG. 7 ~or a time, and at a temperature, su~iicient to permit 100 percent imidization. In one example, curing was accomplished by baking at 200 degrees Centrigrade ~or about 2 hours, Surface 41 oi layer 40 is substantially ~lat and smooth throughout dielectric waveguide region 9.
Samiconductor regions 8 and 10 are identical ~or illustra-tive purposes to locate active optical circuit components interconnected by the dielectric waveguide.
As depicted by FIG. 7, the two-layer dielectric structure including layers 30 ancl 40 is a one-dimensional waveguide capable o~ lightwave propagation. The dielectric waveguide joins to semiconductor regions ~ and 10 with a butt-end inter~ace. The semiconductor and dielectric body o~ FIG. 7 is monoli-thically integrated optical circuit.
FIG. 8 shows an optional third dielectric 3a waveguide layer 50 covering sur~ace 41 and layer ~0.
Layer 50 is a dielectric ma-terial having an index o~
reiraction less than the index oi r~iraction for layer 40.
Thus, la~er 50 acts as a cladding layer ~or the dielectric core layer. Furthermore, layer 50 passivates suriace 41 and the entlre in-tegrated optical circuit. Deposition or spin-coating are suitable techn~ques ~or ~abricating layer 50.
38 In an example ~rom practice, thermal evaporation o~ silicon monoxide, SiO, in an oxygen atmosphere is used to deposit a ~ix (x~2) layer as layer 50, on surface ~1.
The -thermal evaporation techniq~eis described above in relation to fabrication of layex 30.
Formation of Two-Dimensional Waveguide FIGS. 6,7,9 and 10 show successive illustra-tive steps for fabrica-ting a two-dimensional dielectric optical waveguide on waveguide substrate layer 6 in the semiconductor body shown in FIG. 5.
Aiter layer 40 is spin-coated on surface 31 and prior to curing (see FIG. 7), the polyimide coating -film is partially cured by baking the film to effect less than 100 percent imidization, for example, at 130 degrees Centigrade for about 5 minutes. Partially cured polyimide is solvable in certain solu-tions.
Patterning o-f partially cured layer ~0 is performed using a standard phororesist such as AZ1350J -to produce an appropriate shape and transverse width (<011>
direction) -for the core layer of the dielectric waveguide.
The photoresist is developed. Then, selected portions of layer 40 are removed by etching with AZ303 developer. The remaining unetched portions of layer 40 are fully cured by baking at 200 degrees Centigrade for approximately 2 hours.
Cladding layer 60 is -then formed on exposed surfaces 31 and 41 to fully encapsulate the waveguide core layer, layer ~0. Formation of layer 60 is accomplished by means identical to those used ~or ~ormation of layer 50 in FIG. 8. Layer 60 has all of the same properties as those described above ~or layer 50.
Mode Profile ~atching.
For maximum transmission efficiency at the interface (surface 16) o:~ the active and the passive waveguide, field distribution profile of propagation modes in bo-th waveguides should be matched, i.e. mode profile matching. Theoretically ideal mode pro~ile matching is obtained under the following condition:
T ~ T and t - -t 38 where 12~6~

8 ~ . n~t~, T = ~ 40 2o?50,60l n40-t40' and 3,5 and n30,50,60 are the refractive indices of the respective cladding layers (subscripts) in regions 8 or 10, and 9. respectively.
For a more practical, non-ideal mode profile matching condition, the degree of matching is expressed by nmpm, the mode profile matching coefficient. nmpm is expressed as -follows:
~rG8(~ - ~)Gg(~)d(~2 nmpm rG2 ( ,B ) d B J~Gg ( ,6 ~ d ,B
where Gi~) is the -field distribution profile of a : propagation mode in region i, i = 8, 9, ~is a layer thickness coordinate in the <100> direction, and a is an offset distance measured in the <100> direction between the physical center axes of the waveguides in regions 8 and 9.
Field distribution profiles -for Gi(~) are found in the literature, for example, in D. Marcuse, "Light Transmission Optics", Van Nostrand 1972. A table has been included below to show variations of the mode profile matching coefficient as a function o~ center offset for sevelral di~ferent thicknesses of layer 40, t40.

12~265~

OFFSET MODE PROFILE MATCLIING COEFFICIEN'r, n m)t40 ~ 0.3~m t40 = 0.6~lm t40= 0.9~m .~ 0.88 0.96 0.93 0.1 0.85 0.91 o.c~o 50.2 0.78 0.83 0.82 0.3 0.68 0.71 0.71 0.4 0.57 0.57 0.57 0.5 0.~7 0.43 0.45 For the table above, it is assumed that a polyimide/SiO2 dielectric waveguide is in an InGaAsP/InP heterostructure system where the thickness o~ layer 4, t4, is 0.15~m and is 1.3~m.

Claims (16)

- 23 -
1. An integrated optical device, comprising: a substrate which includes a first surface; a material region overlying said first surface, which region includes direct bandgap semiconductor material and is capable of emitting light upon the application of energy, said region also including a second surface, from which light exits, inclined relative to said first surface, characterised in that said device further comprises a waveguide overlying said first surface and including a core, said core including dielectric material essentially free of semiconductor material and two surfaces substantially parallel to one another and to said first surface, and said core also abutting at least a portion of said second surface.
2. The device of claim 1, wherein said waveguide further includes a first cladding region overlying said first surface, said core overlying said first cladding region, the refractive index of said core being higher than that of said first cladding region.
3. The device of claim 1, wherein said dielectric material includes polyimide.
4. The device of claim 2, wherein said first cladding region includes silicon and oxygen.
5. The device of claim 2, wherein said waveguide further includes a second cladding region overlying said core, the refractive index of said core being higher than that of said second cladding region.
6. The device of claim 1, wherein said material region includes a heterostructure comprising first and second portions which include III-V semiconductor material, said first portion overlying said first surface, said second portion contacting at least a part of said first portion, a heterojunction existing at the interface between said first and second portions.
7. The device of claim 6, wherein said heterostructure further comprises a third portion which includes III-V semiconductor material and contacts at least a part of said second portion, a heterojunction existing at the interface between said second and third portions.
8. The device of claim 6, wherein said first portion includes InP and said second portion includes In1-yGayAsxP1-x where x and y are combination constants.
9. The device of claim 6, wherein said first portion includes AlrGa1-rAs and said second portion includes AlsGa1-sAs where r and s are combination constants.
10. A method for fabricating an optical device, com-prising the step of: forming a material region overlying a first surface of a substrate, which region includes direct bandgap semiconductor material and is capable of emitting light upon the application of energy, said material region including a second surface, from which light exits, inclined relative to said first surface, characterised in that said method further comprises the step of forming a waveguide overlying said first surface, said waveguide including a core, said core including dielectric material essentially free of semiconductor material and two surfaces substantially parallel to one another and to said first surface, said core also abutting at least a portion of said second surface.
11. The method of claim 10, wherein said waveguide further includes a cladding region overlying said first surface, said core overlying said cladding region, the refractive index of said core being higher than that of said cladding region.
12. The method of claim 10, wherein said core includes polyimide.
13. The method of claim 11, wherein said cladding region includes silicon and oxygen.
14. The method of claim 12, wherein the formation of said core includes the step of spin-depositing said polyimide.
15. The method of claim 13, wherein the formation of said cladding region includes the step of thermally evapo-rating said silicon and oxygen onto said first surface.
16. The method of claim 13, wherein the formation of said cladding region includes the step of electron-beam-evaporating said silicon and oxygen onto said first surface.
CA000418683A 1982-01-05 1982-12-29 Dielectric optical waveguide and technique for fabricating same Expired CA1222652A (en)

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Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2152694B (en) * 1984-01-05 1987-06-24 Standard Telephones Cables Ltd Wavelength selective optical waveguide coupler
EP0153169A3 (en) * 1984-02-17 1986-12-10 Stauffer Chemical Company Use of pnictide films for wave-guiding in opto-electronic devices
US5163118A (en) * 1986-11-10 1992-11-10 The United States Of America As Represented By The Secretary Of The Air Force Lattice mismatched hetrostructure optical waveguide
US5002352A (en) * 1989-12-07 1991-03-26 General Dynamics Corp., Electronics Divn. Monolithic array of fiber optic bandpass filters
FR2661253B1 (en) * 1990-04-24 1993-10-22 Instruments Sa OPTICAL ELEMENT COMPRISING AT LEAST ONE STACK OF DIELECTRIC LAYERS USED FOR THE REFLECTION AND / OR TRANSMISSION OF CERTAIN WAVELENGTHS, METHOD FOR THE PRODUCTION THEREOF AND MULTIPLEXER-DEMULTIPLEXER COMPRISING THE SAME.
US5054871A (en) * 1990-07-02 1991-10-08 Bell Communications Research, Inc. Semiconductor waveguide and impedance-matched detector
JPH04243216A (en) * 1991-01-17 1992-08-31 Nec Corp Production of optical waveguide and optical integrated element and production thereof
SE470147B (en) * 1992-04-16 1993-11-15 Ericsson Telefon Ab L M Enclosure for optical waveguide
EP0818693A1 (en) * 1992-07-08 1998-01-14 Matsushita Electric Industrial Co., Ltd. Optical waveguide device and manufacturing method of the same
JPH0653538A (en) * 1992-07-28 1994-02-25 Toshiba Corp Semiconductor light receiving element
KR0137125B1 (en) * 1992-11-16 1998-06-15 모리시타 요이찌 An optical wave guide device and a method for fabricating the same
EP0657900B1 (en) * 1993-12-06 1998-03-25 Matsushita Electric Industrial Co., Ltd. Hybrid magnetic structure and method for producing the same
US6132522A (en) * 1996-07-19 2000-10-17 Cfmt, Inc. Wet processing methods for the manufacture of electronic components using sequential chemical processing
JP2000347054A (en) * 1999-03-31 2000-12-15 Sharp Corp Optical device and its production as well as production of polyimide film
JP2001021744A (en) * 1999-07-07 2001-01-26 Shin Etsu Chem Co Ltd Manufacture of optical waveguide substrate
US6324204B1 (en) 1999-10-19 2001-11-27 Sparkolor Corporation Channel-switched tunable laser for DWDM communications
US6934313B1 (en) 1999-11-04 2005-08-23 Intel Corporation Method of making channel-aligned resonator devices
US6243517B1 (en) 1999-11-04 2001-06-05 Sparkolor Corporation Channel-switched cross-connect
US7068870B2 (en) * 2000-10-26 2006-06-27 Shipley Company, L.L.C. Variable width waveguide for mode-matching and method for making
US7023886B2 (en) 2001-11-08 2006-04-04 Intel Corporation Wavelength tunable optical components
US6690694B2 (en) 2001-11-08 2004-02-10 Intel Corporation Thermally wavelength tunable lasers
US20040188379A1 (en) * 2003-03-28 2004-09-30 Cabot Microelectronics Corporation Dielectric-in-dielectric damascene process for manufacturing planar waveguides
US7541058B2 (en) * 2007-10-09 2009-06-02 Endicott Interconnect Technologies, Inc. Method of making circuitized substrate with internal optical pathway
US20090162139A1 (en) * 2007-12-19 2009-06-25 General Electric Company Thermally Insulated Flange Bolts
DE102008050766B4 (en) * 2008-10-09 2017-11-30 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Waveguide arrangement and integrated optics with manufacturing process
KR101645256B1 (en) * 2009-12-03 2016-08-03 삼성전자주식회사 Optical waveguide device using bulk silicon wafer and fabrication method thereof
US8791405B2 (en) * 2009-12-03 2014-07-29 Samsung Electronics Co., Ltd. Optical waveguide and coupler apparatus and method of manufacturing the same
KR20110097240A (en) * 2010-02-25 2011-08-31 삼성전자주식회사 Optical serializer, optical deserializer, and data processing system having the same
US8885448B2 (en) * 2013-03-07 2014-11-11 Seagate Technology Llc Encapsulated laser diode for heat-assisted magnetic recording
FR3060772B1 (en) * 2016-12-20 2022-12-30 Thales Sa OPTIMIZED INTEGRATED PHOTONIC CIRCUIT

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3865646A (en) * 1972-09-25 1975-02-11 Bell Telephone Labor Inc Dielectric optical waveguides and technique for fabricating same
US3833435A (en) * 1972-09-25 1974-09-03 Bell Telephone Labor Inc Dielectric optical waveguides and technique for fabricating same
US3948583A (en) * 1974-12-09 1976-04-06 Bell Telephone Laboratories, Incorporated Isolation of passive devices and integration with active devices in optical waveguiding circuits
JPS53112081A (en) * 1977-03-10 1978-09-30 Matsushita Electric Ind Co Ltd Photo integrated semiconductor device
US4136928A (en) * 1977-05-06 1979-01-30 Bell Telephone Laboratories, Incorporated Optical integrated circuit including junction laser with oblique mirror
JPS5433748A (en) * 1977-08-22 1979-03-12 Nec Corp Optical integrated circuit of semiconductor

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GB2112956B (en) 1985-12-04
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FR2519432B1 (en) 1987-07-10
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JPH0548444B2 (en) 1993-07-21
DE3300131A1 (en) 1983-07-14

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