CA1227877A - Instruction prefetch operation for branch and branch- with-execute instructions - Google Patents
Instruction prefetch operation for branch and branch- with-execute instructionsInfo
- Publication number
- CA1227877A CA1227877A CA000481787A CA481787A CA1227877A CA 1227877 A CA1227877 A CA 1227877A CA 000481787 A CA000481787 A CA 000481787A CA 481787 A CA481787 A CA 481787A CA 1227877 A CA1227877 A CA 1227877A
- Authority
- CA
- Canada
- Prior art keywords
- instruction
- branch
- processor
- storage
- request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000872 buffer Substances 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000012545 processing Methods 0.000 claims description 4
- 238000013459 approach Methods 0.000 description 11
- 238000012163 sequencing technique Methods 0.000 description 8
- 241000282320 Panthera leo Species 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000003111 delayed effect Effects 0.000 description 2
- 201000002266 mite infestation Diseases 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
Abstract
INSTRUCTION PREFETCH OPERATION FOR BRANCH AND
BRANCH-WITH-EXECUTE INSTRUCTIONS
Abstract A method and apparatus are described for expand-ing the capability of an instruction prefetch buffer.
The method and apparatus enables the instruction prefetch buffer to distinguish between old prefetches that occurred before a branch in an instruction stream and new prefetches which occurred after the branch in the instruction stream. A control tag is generated each time a request for an instruction is sent to a storage. The returning instruction has appended thereto the original control tag which is then compared to the current value of control tag in the instruction prefetch buffer. If the two values match, then this is an indication that a branch has not occurred and the instruction is still required.
However, if the two values or the control tag are not equal, then this is an indication that a branch in the instruction stream has occurred and that the instruction being sent from storage to the buffer is no longer required. The method and apparatus are also applicable to the use of branch-with-execute instructions wherein a subject instruction is execut-ed immediately following the branch-with-execute instruction. The execution of this subject instruc-tion before the branch target instruction enables the system processor to continue operating while it is waiting for the branch target instruction.
BRANCH-WITH-EXECUTE INSTRUCTIONS
Abstract A method and apparatus are described for expand-ing the capability of an instruction prefetch buffer.
The method and apparatus enables the instruction prefetch buffer to distinguish between old prefetches that occurred before a branch in an instruction stream and new prefetches which occurred after the branch in the instruction stream. A control tag is generated each time a request for an instruction is sent to a storage. The returning instruction has appended thereto the original control tag which is then compared to the current value of control tag in the instruction prefetch buffer. If the two values match, then this is an indication that a branch has not occurred and the instruction is still required.
However, if the two values or the control tag are not equal, then this is an indication that a branch in the instruction stream has occurred and that the instruction being sent from storage to the buffer is no longer required. The method and apparatus are also applicable to the use of branch-with-execute instructions wherein a subject instruction is execut-ed immediately following the branch-with-execute instruction. The execution of this subject instruc-tion before the branch target instruction enables the system processor to continue operating while it is waiting for the branch target instruction.
Description
1~1 i ` Jo 't U 1 V
78~7 Description INSTRUCTION PREFETCH OPERATION FOR BRANCH
AND BRANCH-WITH-EXECUTE INSTRUCTIONS
Technical Field This invention relates to the operation of an instruction prefetch buffer in a pipeline processor and more particularly to the execution of branch and branch-with-execute instructions.
Background Art In a pipeline processor, multiple pieces of data, such as instructions, can move simultaneously through the channel connecting the processor with a storage means. A storage controller is used to direct such data between the storage means and the processor through the storage channel. The data moving through the channel is tagged so as to identi-fry its destination in the processor. Since the operation of the processor is much faster than that of the storage means, the use of such a pipeline storage channel together with appropriate buffers within the processor permits the processor to operate at its most effective rate and to conduct a plurality of simultaneous storage transactions. The concept of a pipeline storage channel is described in IBM
Technical Disclosure Bulletin article, "Synchronous LOSS Packet Switching Memory and I/O Channel", published March 1982, pages 4986-4987 by Jeremiah et at, and in IBM Technical Disclosure Bulletin article, "Exact Interrupt Capability for Processors Using a Packet-Switching Storage Channel", published August 1982, pages 1771-1772 by Hester et at.
t7~3t7~7 Instructions in such a pipeline processor are usually fetched several cycles in advance of their execution. This increases processor performance by allowing instruction accessing to be overlapped with instruction execution. A problem arises, however, whenever a successful branch instruction is encoun-toned. A successful branch invalidates all in-structions which have been prefetched since they are part of an old instruction stream. During the time lug that the processor is waiting to access the new instruction stream for the branch, it is essentially idle. This idle time decreases the overall perform mange of the processor.
A further problem that arises as a result of a branch is that the instruction prefetch buffer in the processor has no advance knowledge of a successful branch, so there may be several pending requests from previous prophecies when the successful branch occurs. The problem then is how to distinguish between old prophecies, i.e., ones that occurred before the successful branch and which are no longer necessary, and the new prophecies which are needed as a result of the successful branch.
One approach to solve this branching problem is to divine the instruction prefetch buffer into two halves, and to alternate between the two halves every time a successful branch occurs. Since the storage channel utilizes a tag to identify each request source, a set of tags could be associated with each half of the instruction prefetch buffer. Thus, whenever a successful branch occurs, the instruction prefetch buffer would change to the alternate set of tags. In this manner, the instruction prefetch buffer could determine whether or not a reply from a prefetch request should go into the active half of Allah 010 t the buffer by comparing the returned tag with the currently active tag set. If the tag were a member of the active set, then the prefetch would be assess-axed with the current execution stream and cons-quaintly should be placed in the active half of the buffer. Conversely, if the tag were not a member of the active set, then it would no longer be required and could be placed in the inactive half of the buffer. Although this approach is workable it only utilizes one-half of the storage area in the instruct lion prefetch buffer at any given time.
One technique for overcoming the branching problem is disclosed in U. S. Patent 4,430,706, wherein a branch prediction approach is employed. In this approach, an auxiliary implementation is added to a pipeline data processor for monitoring both the instruction flow and the recent conditional branches and their outcome. Whenever a branch instruction is encountered more than once, its prior behavior is used to predict the particular branch to be taken.
The processor then provisionally executes the in-structions in such predicted branch. However, when a predicted branch turns out to be incorrect, such processing ceases and the processor then attempts to take a correct branch. Two problems with this approach are that, first, extra hardware is required, end second, processing time is wasted whenever a wrong branch is predicted and subsequently processed.
Another approach to the branching problem is disclosed in U. S. Patents 4,155,120 and 4,179,737, wherein it is assumed that no branching possibilities are present. In accordance with this approach, microinstruction sequencing is assumed to be unweakened-tonal even though a plurality of branching possibly-flies may indeed exist in the microinstruction OX
sequencing flow. In this manner, microinstruction sequencing may proceed rapidly as long as no branch-in occurs. However, when a branch does in fact occur, it must be detected and then a correction cycle must be initiated. A problem with this apt preach is that as the number of branching operations increases, sequencing must be altered and corrected for incorrect sequencing because of lack of recogni-lion of branching possibilities. Further this approach requires means for monitoring the correct-news of the sequencing of microinstruction concur-gently with the execution of microinstruction during each cycle for which a branching decision is required.
Still another approach to reducing performance degradation due to branching is to introduce a set of branch-with-execute, also known as delayed branch, instructions. These instructions are defined such that the next sequential instruction following the branch instruction is executed prior to the execution of the branch target instruction. This next sequent trial instruction is known as the subject instruction.
The subject instruction usually has already teen fetched at the completion of the branch-with-execute instruction, and consequently, the processor executes it instead of remaining idle while waiting for the branch target fetch to be completed.
The branch-with-execute approach is relatively easy to implement on a processor which has a single instruction prefetch buffer. The processor executes the subject instruction which is being fetched and decoded while the branch-with-execute instruction is executing. In a normal branch, the processor would ignore the subject instruction. However, the branch-with-execute approach becomes much more A u i u Z~7~7 difficult to implement as the size of the instruction prefetch buffer increases.
Disclosure of the Invention Accordingly, it is an object of this invention to provide improved execution sequencing in a pipeline processor system.
It is another object of this invention to provide improved instruction prefetch buffer Utah-ligation and efficiency.
It is still a further object or this invention to provide improved branch and branch-with-execute instruction sequencing in an instruction prefetch buffer in a pipeline processor.
In accordance with these and other objects, there is disclosed a technique which allows an instruction prefetch buffer to appear to contain twice as many logical locations as physical lo-cations. This technique reduces the amount of storage required in the instruction prefetch buffer (IPB) by a factor of two without reducing IPB perform mange. The technique is especially useful for handling branching operations. When a branch occurs, the IPB begins fetching instructions starting at the branch target address. However, since the IPB has no advance knowledge of the branch, there may be several pending requests from the previous prefetched in-structions when the branch occurs. The technique disclosed herein enables the IPB to distinguish between old prophecies, that is, those that occurred before the branch, and the new prophecies which are needed as a result of the branch.
The IPB contains a plurality of registers which are used to hold instructions prior to their eye-caution. Each of these registers has a number Aureole aye associated with it which uniquely identifies that register. Additionally, a control bit is associated with each register to indicate if there is a can-celled fetch outstanding (COO) for that particular register. A canceled fetch outstanding occurs after a branch when a previous fetch has not yet been returned to the IPB from storage over the storage channel. Recall that these previous prophecies are no longer required after the branch occurs. In addition to the register identifier and the COO
control bit, there is also a control bit in the processor which is complemented every time a branch occurs. This latter control bit is known as the branch target bit (BOB).
When a prefetch is returned to the IPB, the BOB
value associated with the returning prefetch is compared to the current BOB value in the IPB. If the two are equal, then this is an indication that a branch his not occurred and that the prefetch request which was sent to storage is still needed. In this situation, the returning prefetch is written into the register in the IPB specified by control bits of the returning prefetch. The returned instruction is then used when needed for execution. However, if the BOB
value associated with the returning prefetch is not equal to the current BOB value in the IPB, then this is an indication that a branch has occurred and that the returning prefetch is no longer needed. As a result, the returning prefetch is not written into one of the registers of the IPB.
Whenever a branch occurs, the COO bits assess-axed with each register of the IPB are examined. If any of such bits are set, then the branch must wait until all COO bits are reset. As previously noted, the BOB is also complemented when the branch occurs.
'J 1 I.' I I
Finally, COO bits in the IPB are set for locations for which a yrefetch has been sent to storage but has not yet returned.
The preferred embodiment disclosed herein is also applicable to the operation of a pipeline processor using branch-with-execute instructions.
The next sequential instruction following a branch instruction, which is known as the subject instruct lion, is executed before the branch target instruct lion is executed. The subject instruction useless already been fetched at the completion of the branch-with-execute instruction, and consequently, the processor executes it instead of going idle while waiting for the branch target fetch to be completed.
ennui the branch-with-execute instruction is executed, the IPB decides which IPB location is to be used as the destination of the ranch target fetch.
The IPB allocates that particular location and determines whether or not the fetch of the subject instruction has begun. If such fetch has not begun, then the branch-with-execute instruction must be held off because it must modify the instruction address register which must be used in order to initiate the fetch of the subject instruction. At this time, the IPB frees all locations in the IPB not associated with the subject instruction and it also retains the IPB pointer to the subject instruction as well as the subject instruction itself. After the subject instruction has begun execution, the IPB frees the IPB location or locations associated with the subject instruction so that these locations may be used for prefetching. Finally, the IPB updates its pointer to point to the target instruction required.
AWAIT
I 7~7 Brief Description of the Drawing Fig. 1 is a block diagram of a pipeline process son system according to the present invention.
Fig. 2 is a flow chart depicting the branching operation according to the present invention.
Fig. 3 is a flow chart depicting instruction execution according to the present invention.
Fig. 4 is a flow chart depicting the prefetching operation of the present invention.
Fig. 5 is a flow chart depicting the returning tag operation of the present invention.
Fig. 6 is a time diagram showing the instruction fetching and decoding as well as the instruction execution for a normal branching operation.
Fig. 7 is a more detailed time diagram of instruction execution according to the present invention.
Fig. 8 is a diagram showing eight possible states of the instruction prefetch buffer at the beginning of a branch-with-execute.
Fig. 9 is a block diagram depicting the opera-lion of an instruction prefetch buffer according to the present invention.
Best Mode for Carrying Out the Invention Referring now to Fig. 1, there is shown a pipeline processor with particular emphasis on instruction prefetch buffer 11. Information in the form of instructions is communicated over storage channel 12 through storage controller 13 between instruction prefetch buffer (IPB) 11 and storage 14.
IPB 11 comprises four registers, IPB0, 15, IPB1, 16, IPB2, 17, and IPB3, 18. Mach of registers 15 through 18 has logic means, COO, associated with it for indicating whether each of these registers has a Audi
78~7 Description INSTRUCTION PREFETCH OPERATION FOR BRANCH
AND BRANCH-WITH-EXECUTE INSTRUCTIONS
Technical Field This invention relates to the operation of an instruction prefetch buffer in a pipeline processor and more particularly to the execution of branch and branch-with-execute instructions.
Background Art In a pipeline processor, multiple pieces of data, such as instructions, can move simultaneously through the channel connecting the processor with a storage means. A storage controller is used to direct such data between the storage means and the processor through the storage channel. The data moving through the channel is tagged so as to identi-fry its destination in the processor. Since the operation of the processor is much faster than that of the storage means, the use of such a pipeline storage channel together with appropriate buffers within the processor permits the processor to operate at its most effective rate and to conduct a plurality of simultaneous storage transactions. The concept of a pipeline storage channel is described in IBM
Technical Disclosure Bulletin article, "Synchronous LOSS Packet Switching Memory and I/O Channel", published March 1982, pages 4986-4987 by Jeremiah et at, and in IBM Technical Disclosure Bulletin article, "Exact Interrupt Capability for Processors Using a Packet-Switching Storage Channel", published August 1982, pages 1771-1772 by Hester et at.
t7~3t7~7 Instructions in such a pipeline processor are usually fetched several cycles in advance of their execution. This increases processor performance by allowing instruction accessing to be overlapped with instruction execution. A problem arises, however, whenever a successful branch instruction is encoun-toned. A successful branch invalidates all in-structions which have been prefetched since they are part of an old instruction stream. During the time lug that the processor is waiting to access the new instruction stream for the branch, it is essentially idle. This idle time decreases the overall perform mange of the processor.
A further problem that arises as a result of a branch is that the instruction prefetch buffer in the processor has no advance knowledge of a successful branch, so there may be several pending requests from previous prophecies when the successful branch occurs. The problem then is how to distinguish between old prophecies, i.e., ones that occurred before the successful branch and which are no longer necessary, and the new prophecies which are needed as a result of the successful branch.
One approach to solve this branching problem is to divine the instruction prefetch buffer into two halves, and to alternate between the two halves every time a successful branch occurs. Since the storage channel utilizes a tag to identify each request source, a set of tags could be associated with each half of the instruction prefetch buffer. Thus, whenever a successful branch occurs, the instruction prefetch buffer would change to the alternate set of tags. In this manner, the instruction prefetch buffer could determine whether or not a reply from a prefetch request should go into the active half of Allah 010 t the buffer by comparing the returned tag with the currently active tag set. If the tag were a member of the active set, then the prefetch would be assess-axed with the current execution stream and cons-quaintly should be placed in the active half of the buffer. Conversely, if the tag were not a member of the active set, then it would no longer be required and could be placed in the inactive half of the buffer. Although this approach is workable it only utilizes one-half of the storage area in the instruct lion prefetch buffer at any given time.
One technique for overcoming the branching problem is disclosed in U. S. Patent 4,430,706, wherein a branch prediction approach is employed. In this approach, an auxiliary implementation is added to a pipeline data processor for monitoring both the instruction flow and the recent conditional branches and their outcome. Whenever a branch instruction is encountered more than once, its prior behavior is used to predict the particular branch to be taken.
The processor then provisionally executes the in-structions in such predicted branch. However, when a predicted branch turns out to be incorrect, such processing ceases and the processor then attempts to take a correct branch. Two problems with this approach are that, first, extra hardware is required, end second, processing time is wasted whenever a wrong branch is predicted and subsequently processed.
Another approach to the branching problem is disclosed in U. S. Patents 4,155,120 and 4,179,737, wherein it is assumed that no branching possibilities are present. In accordance with this approach, microinstruction sequencing is assumed to be unweakened-tonal even though a plurality of branching possibly-flies may indeed exist in the microinstruction OX
sequencing flow. In this manner, microinstruction sequencing may proceed rapidly as long as no branch-in occurs. However, when a branch does in fact occur, it must be detected and then a correction cycle must be initiated. A problem with this apt preach is that as the number of branching operations increases, sequencing must be altered and corrected for incorrect sequencing because of lack of recogni-lion of branching possibilities. Further this approach requires means for monitoring the correct-news of the sequencing of microinstruction concur-gently with the execution of microinstruction during each cycle for which a branching decision is required.
Still another approach to reducing performance degradation due to branching is to introduce a set of branch-with-execute, also known as delayed branch, instructions. These instructions are defined such that the next sequential instruction following the branch instruction is executed prior to the execution of the branch target instruction. This next sequent trial instruction is known as the subject instruction.
The subject instruction usually has already teen fetched at the completion of the branch-with-execute instruction, and consequently, the processor executes it instead of remaining idle while waiting for the branch target fetch to be completed.
The branch-with-execute approach is relatively easy to implement on a processor which has a single instruction prefetch buffer. The processor executes the subject instruction which is being fetched and decoded while the branch-with-execute instruction is executing. In a normal branch, the processor would ignore the subject instruction. However, the branch-with-execute approach becomes much more A u i u Z~7~7 difficult to implement as the size of the instruction prefetch buffer increases.
Disclosure of the Invention Accordingly, it is an object of this invention to provide improved execution sequencing in a pipeline processor system.
It is another object of this invention to provide improved instruction prefetch buffer Utah-ligation and efficiency.
It is still a further object or this invention to provide improved branch and branch-with-execute instruction sequencing in an instruction prefetch buffer in a pipeline processor.
In accordance with these and other objects, there is disclosed a technique which allows an instruction prefetch buffer to appear to contain twice as many logical locations as physical lo-cations. This technique reduces the amount of storage required in the instruction prefetch buffer (IPB) by a factor of two without reducing IPB perform mange. The technique is especially useful for handling branching operations. When a branch occurs, the IPB begins fetching instructions starting at the branch target address. However, since the IPB has no advance knowledge of the branch, there may be several pending requests from the previous prefetched in-structions when the branch occurs. The technique disclosed herein enables the IPB to distinguish between old prophecies, that is, those that occurred before the branch, and the new prophecies which are needed as a result of the branch.
The IPB contains a plurality of registers which are used to hold instructions prior to their eye-caution. Each of these registers has a number Aureole aye associated with it which uniquely identifies that register. Additionally, a control bit is associated with each register to indicate if there is a can-celled fetch outstanding (COO) for that particular register. A canceled fetch outstanding occurs after a branch when a previous fetch has not yet been returned to the IPB from storage over the storage channel. Recall that these previous prophecies are no longer required after the branch occurs. In addition to the register identifier and the COO
control bit, there is also a control bit in the processor which is complemented every time a branch occurs. This latter control bit is known as the branch target bit (BOB).
When a prefetch is returned to the IPB, the BOB
value associated with the returning prefetch is compared to the current BOB value in the IPB. If the two are equal, then this is an indication that a branch his not occurred and that the prefetch request which was sent to storage is still needed. In this situation, the returning prefetch is written into the register in the IPB specified by control bits of the returning prefetch. The returned instruction is then used when needed for execution. However, if the BOB
value associated with the returning prefetch is not equal to the current BOB value in the IPB, then this is an indication that a branch has occurred and that the returning prefetch is no longer needed. As a result, the returning prefetch is not written into one of the registers of the IPB.
Whenever a branch occurs, the COO bits assess-axed with each register of the IPB are examined. If any of such bits are set, then the branch must wait until all COO bits are reset. As previously noted, the BOB is also complemented when the branch occurs.
'J 1 I.' I I
Finally, COO bits in the IPB are set for locations for which a yrefetch has been sent to storage but has not yet returned.
The preferred embodiment disclosed herein is also applicable to the operation of a pipeline processor using branch-with-execute instructions.
The next sequential instruction following a branch instruction, which is known as the subject instruct lion, is executed before the branch target instruct lion is executed. The subject instruction useless already been fetched at the completion of the branch-with-execute instruction, and consequently, the processor executes it instead of going idle while waiting for the branch target fetch to be completed.
ennui the branch-with-execute instruction is executed, the IPB decides which IPB location is to be used as the destination of the ranch target fetch.
The IPB allocates that particular location and determines whether or not the fetch of the subject instruction has begun. If such fetch has not begun, then the branch-with-execute instruction must be held off because it must modify the instruction address register which must be used in order to initiate the fetch of the subject instruction. At this time, the IPB frees all locations in the IPB not associated with the subject instruction and it also retains the IPB pointer to the subject instruction as well as the subject instruction itself. After the subject instruction has begun execution, the IPB frees the IPB location or locations associated with the subject instruction so that these locations may be used for prefetching. Finally, the IPB updates its pointer to point to the target instruction required.
AWAIT
I 7~7 Brief Description of the Drawing Fig. 1 is a block diagram of a pipeline process son system according to the present invention.
Fig. 2 is a flow chart depicting the branching operation according to the present invention.
Fig. 3 is a flow chart depicting instruction execution according to the present invention.
Fig. 4 is a flow chart depicting the prefetching operation of the present invention.
Fig. 5 is a flow chart depicting the returning tag operation of the present invention.
Fig. 6 is a time diagram showing the instruction fetching and decoding as well as the instruction execution for a normal branching operation.
Fig. 7 is a more detailed time diagram of instruction execution according to the present invention.
Fig. 8 is a diagram showing eight possible states of the instruction prefetch buffer at the beginning of a branch-with-execute.
Fig. 9 is a block diagram depicting the opera-lion of an instruction prefetch buffer according to the present invention.
Best Mode for Carrying Out the Invention Referring now to Fig. 1, there is shown a pipeline processor with particular emphasis on instruction prefetch buffer 11. Information in the form of instructions is communicated over storage channel 12 through storage controller 13 between instruction prefetch buffer (IPB) 11 and storage 14.
IPB 11 comprises four registers, IPB0, 15, IPB1, 16, IPB2, 17, and IPB3, 18. Mach of registers 15 through 18 has logic means, COO, associated with it for indicating whether each of these registers has a Audi
2~:78~7 canceled fetch outstanding (COO). IPB 11 also includes a branch tag register (BAR) lo which con-twins a control bit for indicating whenever an instruction branch occurs. IPB 11 also contains control logic 21 for directing the fetching of instructions to and from IPB 11.
Each of registers 15 through 18 has a number associated with it, O through 3, which uniquely identifies such register. Additionally, there is a control bit associated with each of registers 15 through 18 to indicate if there is a canceled fetch outstanding (COO) for that associated register.
There is also a control bit in BAR 19 called the branch target bit (BOB) which is complemented every time a branch occurs in the instruction stream.
In operation, whenever the next instruction is 'o be fetched, IPB 11 determines which of registers 15 through 18 should be used for the fetch. A tag is then generated for the prefetch so as to indicate the I source of the instruction request. Control logic 21 generates this tag for the instruction fetch by appending the current BOB value to the register number selectee for such request. The prefetch request is then sent to storage 14 over storage channel 12 in order to obtain the next instruction.
After the prefetch request has been processed by storage 14, it will be returned over channel 12 to Its if. The returned prefetch request will contain the next instruction along with its identifying tag.
A determination will then be made if the returned prefetch instruction is still needed. This is done by comparing the BOB value in the returning instruct lion to the current BOB value in BAR 19. If the two values are equal, then this is an indication that a branch has not occurred since the time that the prefetch request was sent to storage 14. Consequent-lye the prefetch instruction is still required. At this time, the prefetch instruction returned is then written into the register specified by the returning tag identifier, and the instruction is then used when it is needed for an execution.
If the BOB value in the returning prefetch instruction and the current BOB value in BAR 19 are different, then this is an indication that a branch in the instruction stream has occurred. Consequent-lye the prefetch instruction is no longer needed and therefore, is not written in one of registers 15 through 18. The COO bit associated with the return-in prefetch instruction is then reset. At the time a branch in the instruction stream occurs, the COO
bits associated with each of registers 15 through 18 are examined. If any of these COO bits are set, then the execution of the branch in the instruction stream must wait until all of these COO bits are reset.
Also at this time, the BOB in sty 19 is complemented.
Finally, control logic 21 examines each of registers 15 through 18 to determine if any prefetch has been sent to storage 14 but has not yet returned. If this is the case, then the COO bit associated with that register is set thus indicating that there is a canceled fetch outstanding.
The flow chart in Fig. 2 details the operation of IPB 11 at the time a branch in the instruction stream occurs. As indicated in box 22, a determine-lion is made as to whether or not there are anycancelled fetches outstanding. If there are, then box 23 indicates that no further operation occurs until the canceled tag identifying a returned prefetch instruction is sent from storage 14 to IP8 11. If there are no current fetches outstanding, Aureole ~L~2~8'~7 then box 24 provides that control logic 21 sets a CF0 bit for all registers 15 through 18 for which a prefetch has been allocated. Also at this time, the Bomb value in BAR lo is complemented as indicated in box 25 and all tags are set to their available state for enabling instructions to be fetched from storage as indicated in box 26. Finally in box 27, an identifying tag is selected in order to fetch the branch target instruction from storage 14. This prefetching process continues until all target fetches are completed.
The flow chart in Fig. 3 indicates the operation of IPB 11 when instruction execution unit 37 asks for the next instruction. As indicated in box 31, the next instruction address is calculated within IPB 11.
Then in box 32, a decision is made as to whether or not the location in IPB 11 of the next instruction has been freed. If the answer is affirmative, then the freed IPB tag is set to its available state.
However, if the answer is negative, then a further decision is made in block 34 as to whether or not the next instruction tag is in a valid state. If the next instruction tag is not in a valid state, then IPB 11 must wait for the selected tag to return from storage 14 over channel 12. However, if the next instruction tag is in a valid state, then the next instruction is provided to execution unit 37 for execution.
The process for selecting the next identifying tag for a prefetch is detailed in the flow chart shown in Fig. 4. After the next prefetch tag has been selected, a determination is made as to whether or not the tag is available. If such tag is not available, then IPB 11 must wait for such tag to become available as indicated in blocks 42 and 43.
Await ~2'~78~7~7 However, if the tag is available, then it is allocate Ed to the next prefetch as shown in block I
Finally the next prefetch along with identifying tag is sent to storage 14 so as to obtain the next instruction.
As shown in Fig. 5, when an instruction is returned from storage 14 with its associated identi-lying tag, a determination is made as to whether or not the BOB returning with the instruction is equal to the current BOB value in IPB 11. If the two values are not equal, then this is an indication that a branch has occurred in the instruction stream and consequently the prefetched instruction is no longer needed. The COO bit for each returning tag is then reset. However, if the returning BOB value is equal to the current BOB value in Its 11, then as stated previously this is an indication that a branch in the instruction stream has not occurred. A determination is then made as shown in block 53, as to whether or not a reply to an exception state exists. If the answer is affirmative then the tag identifier is set to the exception state, while if the answer is negative then the tag is set to the valid state and the instruction awaits execution.
One technique for decreasing performance Debra-ration in IPB 11 due to branches is to introduce a set of branch-with-execute, also known as delayed branch, instructions. The branch-with-execute instructions are defined such that the next sequent trial instruction following the branch instruction, which is known as the subject instruction, is execute Ed before the branch target instruction is executed.
The subject instruction usually has already been fetched at the completion of the branch-with-execute instruction and consequently the processor 10 Alr5-oL~-olo ~2~787~7 executes it. A branch-with-execute instruction sequence is shown in Fig. 6. In cycle 61, the instruction immediately preceding the branch-with-execute is being fetched and decoded, while in cycle 62 this instruction is being executed.
Simultaneously in cycle 62, the branch-with-execute instruction is being fetched and decoded. In cycle 63 the subject instruction is being fetched and decoded while the branch-with-execute instruction is being executed. Likewise in cycle 64, the target instruction is being fetched and decoded while the subject instruction is executed. This simultaneous fetching and execution operation continues in cycles 65 and 66 as the target instruction and the instruction immediately following the target instruction are decoded and executed. In Fig. 6, the instruction fetch and decode time is assumed to be equal to the execution time. In many instances, it is more economical to use slower interleaved storage, and to use prefetch instructions further in advance.
Such an operation is shown in Fig. 7.
The prefetching technique shown in Fig. 7 requires that IPB 11 contains at least four in-structions since this is the number of prophecies required to support the execution ox one instruction every cycle. Since processor 10 may not be able to execute an instruction immediately after the prefetch has been completed, one buffer location is required to hold each prefetchO In the preferred embodiment disclosed herein, IPB if contains four 32 bit aegis-lens 15 through 18 which may contain up to eight instructions each.
Fig. 8 depicts the eight possible branch-with-execute cases which can exist based on the branch-with-execute instruction length, the Aye Pull ~2;2~78t7t7 subject instruction length, and address alignment.
In each of these eight cases, there is located a branch-with-execute instruction and a subject in-struction in one or more of registers 15 through 18.
It is to be noted that registers 15 through 18 are organized as a circular queue so that these eight cases could exist with the branch-with-execute instruction (BRA) and could begin in any one of registers 15 through 18. Each arrow shown in Fig. 8 represents a pointer which can have one of eight binary values, 0 through 7. These pointers indicate the beginning of the next instruction to be executed.
The pointers in Fig. 8 are set as they would be on the first cycle of the branch-with-execute instruct lion, i.e., immediately after the branch-with-execute instruction and immediately before the execution of the subject instruction.
When the branch-with-execute instruction is executed, IPB 11 determines the location within IPB
11 which is to be the destination of the branch target fetch. IPB if also allocates that location and determines whether or not the fetch of the subject instruction has begun. If such fetch has not begun, then the branch-with-execute instruction is held off. Finally, IPB 11 frees all locations therein not associated with the subject instruction and retains the pointer to the subject instruction.
after the subject instruction has begun execution, IPB 11 frees those locations associated with the subject instruction so that they may be used for prefetching and also updates the IPB pointer to point to the target instruction.
The operation of IPB 11 with respect to the execution of a branch-with-execute instruction is explained with reference to Fig. 9. A
Aureole statute branch-with-execute instruction may encounter any hold off condition encountered by a normal branch instruction. Thus, a branch-with-execute instruction may be held off because a canceled fetch outstanding S (COO) bit is set for any location in IPB 11 indicate in that a prefetch, canceled because of a branch, has still not been received from storage 14. Add-tonally, a hold off may occur in a branch-with-execute instruction whenever the prefetch for all or part of the subject instruction has not yet been initiated when the branch-with-execute begins execution. To detect this condition, IPB 11 inspects the state of the locations in IPB if assess-axed with the IPB pointer and with the Its pointer incremented by a value of one. If either of these locations is free, i.e., available for prefetching, then the branch-with-execute is held off.
Assuming that the branch-with-execute is not held off, then the value of the IPB pointer is incremented by a value of three. This is done using logic blocks 96 and 98. The location in IPB 11 associated with this value is guaranteed not to contain any part of the subject instruction due to the incrementation of such value by three. The low order bit of this calculated value is then replaced by the next to low order bit of the branch target address. The resulting value is the IPB pointer used to decode the target instruction. If the complete subject instruction has not yet been received from storage 14 when the branch-with-execute instruction executes, then the new IPB pointer value for the target instruction is stored in BAR 19. At this time, the IPB location indicated by incrementing the IPB pointer by three is then allocated in IPB 11 for the branch target fetch. This is shown in block 101.
1, - (I 4-- I, L I, I
As indicated in block 102, all locations in IPB 11 except the location previously allocated and the locations associated with the current IPB pointer and the current Its pointer plus one are freed. The location allocated previously cannot be freed because it is needed for the branch target fetch. The locations associated with the current IPB pointer and the current IPB pointer plus one may hold the subject instruction and thus they cannot be freed. The COO
bit for the location in IPB 11 previously allocated and the locations previously freed are then set.
This indication is set for each location that is already allocated when it is either allocated or freed so as to mark the outstanding prefetch to that location as invalid. Note that the subject instruct lion locations are not effected here because any outstanding subject instruction prophecies are still valid.
The logic in block 95 performs the function of decoding the subject instruction. This decoding operation is complete when all parts of the subject instruction have been properly received from aegis-lens 15 through 18. At this time, IPB pointer 96 is loaded with the contents of BAR 19. This latter step prepared IPB 11 to decode the target instruction when it is received from storage 14. Finally, the lo-cation in IPB 11 associated with the BY 19 value decrement Ed by two is then freed by the logic in block 102. This procedure frees a location which may not have already been freed either due to the branch or to the decoding of the subject instruction. By following the above procedure, a branch-with-execute is implemented without canceling all of the fetches of previous instructions prior to a branch. By canceling all but one of these instructions and 7~7 executing this one instruction, regardless of the branch, processor 10 is kept busy during any comma-nications with storage 14 which are required as a result of the branch. The execution of this one instruction can significantly increase the efficiency of operation of pipeline processor 10 with respect to IPB 11.
Although the description of the invention provided herein has been primarily directed to a preferred embodiment and to a variation in that preferred embodiment in order to clearly demonstrate the basic principles of the invention, it is to be understood that many modifications and variations in the structure and operation of the invention are possible without departing from the spirit and the scope of the invention.
I
Each of registers 15 through 18 has a number associated with it, O through 3, which uniquely identifies such register. Additionally, there is a control bit associated with each of registers 15 through 18 to indicate if there is a canceled fetch outstanding (COO) for that associated register.
There is also a control bit in BAR 19 called the branch target bit (BOB) which is complemented every time a branch occurs in the instruction stream.
In operation, whenever the next instruction is 'o be fetched, IPB 11 determines which of registers 15 through 18 should be used for the fetch. A tag is then generated for the prefetch so as to indicate the I source of the instruction request. Control logic 21 generates this tag for the instruction fetch by appending the current BOB value to the register number selectee for such request. The prefetch request is then sent to storage 14 over storage channel 12 in order to obtain the next instruction.
After the prefetch request has been processed by storage 14, it will be returned over channel 12 to Its if. The returned prefetch request will contain the next instruction along with its identifying tag.
A determination will then be made if the returned prefetch instruction is still needed. This is done by comparing the BOB value in the returning instruct lion to the current BOB value in BAR 19. If the two values are equal, then this is an indication that a branch has not occurred since the time that the prefetch request was sent to storage 14. Consequent-lye the prefetch instruction is still required. At this time, the prefetch instruction returned is then written into the register specified by the returning tag identifier, and the instruction is then used when it is needed for an execution.
If the BOB value in the returning prefetch instruction and the current BOB value in BAR 19 are different, then this is an indication that a branch in the instruction stream has occurred. Consequent-lye the prefetch instruction is no longer needed and therefore, is not written in one of registers 15 through 18. The COO bit associated with the return-in prefetch instruction is then reset. At the time a branch in the instruction stream occurs, the COO
bits associated with each of registers 15 through 18 are examined. If any of these COO bits are set, then the execution of the branch in the instruction stream must wait until all of these COO bits are reset.
Also at this time, the BOB in sty 19 is complemented.
Finally, control logic 21 examines each of registers 15 through 18 to determine if any prefetch has been sent to storage 14 but has not yet returned. If this is the case, then the COO bit associated with that register is set thus indicating that there is a canceled fetch outstanding.
The flow chart in Fig. 2 details the operation of IPB 11 at the time a branch in the instruction stream occurs. As indicated in box 22, a determine-lion is made as to whether or not there are anycancelled fetches outstanding. If there are, then box 23 indicates that no further operation occurs until the canceled tag identifying a returned prefetch instruction is sent from storage 14 to IP8 11. If there are no current fetches outstanding, Aureole ~L~2~8'~7 then box 24 provides that control logic 21 sets a CF0 bit for all registers 15 through 18 for which a prefetch has been allocated. Also at this time, the Bomb value in BAR lo is complemented as indicated in box 25 and all tags are set to their available state for enabling instructions to be fetched from storage as indicated in box 26. Finally in box 27, an identifying tag is selected in order to fetch the branch target instruction from storage 14. This prefetching process continues until all target fetches are completed.
The flow chart in Fig. 3 indicates the operation of IPB 11 when instruction execution unit 37 asks for the next instruction. As indicated in box 31, the next instruction address is calculated within IPB 11.
Then in box 32, a decision is made as to whether or not the location in IPB 11 of the next instruction has been freed. If the answer is affirmative, then the freed IPB tag is set to its available state.
However, if the answer is negative, then a further decision is made in block 34 as to whether or not the next instruction tag is in a valid state. If the next instruction tag is not in a valid state, then IPB 11 must wait for the selected tag to return from storage 14 over channel 12. However, if the next instruction tag is in a valid state, then the next instruction is provided to execution unit 37 for execution.
The process for selecting the next identifying tag for a prefetch is detailed in the flow chart shown in Fig. 4. After the next prefetch tag has been selected, a determination is made as to whether or not the tag is available. If such tag is not available, then IPB 11 must wait for such tag to become available as indicated in blocks 42 and 43.
Await ~2'~78~7~7 However, if the tag is available, then it is allocate Ed to the next prefetch as shown in block I
Finally the next prefetch along with identifying tag is sent to storage 14 so as to obtain the next instruction.
As shown in Fig. 5, when an instruction is returned from storage 14 with its associated identi-lying tag, a determination is made as to whether or not the BOB returning with the instruction is equal to the current BOB value in IPB 11. If the two values are not equal, then this is an indication that a branch has occurred in the instruction stream and consequently the prefetched instruction is no longer needed. The COO bit for each returning tag is then reset. However, if the returning BOB value is equal to the current BOB value in Its 11, then as stated previously this is an indication that a branch in the instruction stream has not occurred. A determination is then made as shown in block 53, as to whether or not a reply to an exception state exists. If the answer is affirmative then the tag identifier is set to the exception state, while if the answer is negative then the tag is set to the valid state and the instruction awaits execution.
One technique for decreasing performance Debra-ration in IPB 11 due to branches is to introduce a set of branch-with-execute, also known as delayed branch, instructions. The branch-with-execute instructions are defined such that the next sequent trial instruction following the branch instruction, which is known as the subject instruction, is execute Ed before the branch target instruction is executed.
The subject instruction usually has already been fetched at the completion of the branch-with-execute instruction and consequently the processor 10 Alr5-oL~-olo ~2~787~7 executes it. A branch-with-execute instruction sequence is shown in Fig. 6. In cycle 61, the instruction immediately preceding the branch-with-execute is being fetched and decoded, while in cycle 62 this instruction is being executed.
Simultaneously in cycle 62, the branch-with-execute instruction is being fetched and decoded. In cycle 63 the subject instruction is being fetched and decoded while the branch-with-execute instruction is being executed. Likewise in cycle 64, the target instruction is being fetched and decoded while the subject instruction is executed. This simultaneous fetching and execution operation continues in cycles 65 and 66 as the target instruction and the instruction immediately following the target instruction are decoded and executed. In Fig. 6, the instruction fetch and decode time is assumed to be equal to the execution time. In many instances, it is more economical to use slower interleaved storage, and to use prefetch instructions further in advance.
Such an operation is shown in Fig. 7.
The prefetching technique shown in Fig. 7 requires that IPB 11 contains at least four in-structions since this is the number of prophecies required to support the execution ox one instruction every cycle. Since processor 10 may not be able to execute an instruction immediately after the prefetch has been completed, one buffer location is required to hold each prefetchO In the preferred embodiment disclosed herein, IPB if contains four 32 bit aegis-lens 15 through 18 which may contain up to eight instructions each.
Fig. 8 depicts the eight possible branch-with-execute cases which can exist based on the branch-with-execute instruction length, the Aye Pull ~2;2~78t7t7 subject instruction length, and address alignment.
In each of these eight cases, there is located a branch-with-execute instruction and a subject in-struction in one or more of registers 15 through 18.
It is to be noted that registers 15 through 18 are organized as a circular queue so that these eight cases could exist with the branch-with-execute instruction (BRA) and could begin in any one of registers 15 through 18. Each arrow shown in Fig. 8 represents a pointer which can have one of eight binary values, 0 through 7. These pointers indicate the beginning of the next instruction to be executed.
The pointers in Fig. 8 are set as they would be on the first cycle of the branch-with-execute instruct lion, i.e., immediately after the branch-with-execute instruction and immediately before the execution of the subject instruction.
When the branch-with-execute instruction is executed, IPB 11 determines the location within IPB
11 which is to be the destination of the branch target fetch. IPB if also allocates that location and determines whether or not the fetch of the subject instruction has begun. If such fetch has not begun, then the branch-with-execute instruction is held off. Finally, IPB 11 frees all locations therein not associated with the subject instruction and retains the pointer to the subject instruction.
after the subject instruction has begun execution, IPB 11 frees those locations associated with the subject instruction so that they may be used for prefetching and also updates the IPB pointer to point to the target instruction.
The operation of IPB 11 with respect to the execution of a branch-with-execute instruction is explained with reference to Fig. 9. A
Aureole statute branch-with-execute instruction may encounter any hold off condition encountered by a normal branch instruction. Thus, a branch-with-execute instruction may be held off because a canceled fetch outstanding S (COO) bit is set for any location in IPB 11 indicate in that a prefetch, canceled because of a branch, has still not been received from storage 14. Add-tonally, a hold off may occur in a branch-with-execute instruction whenever the prefetch for all or part of the subject instruction has not yet been initiated when the branch-with-execute begins execution. To detect this condition, IPB 11 inspects the state of the locations in IPB if assess-axed with the IPB pointer and with the Its pointer incremented by a value of one. If either of these locations is free, i.e., available for prefetching, then the branch-with-execute is held off.
Assuming that the branch-with-execute is not held off, then the value of the IPB pointer is incremented by a value of three. This is done using logic blocks 96 and 98. The location in IPB 11 associated with this value is guaranteed not to contain any part of the subject instruction due to the incrementation of such value by three. The low order bit of this calculated value is then replaced by the next to low order bit of the branch target address. The resulting value is the IPB pointer used to decode the target instruction. If the complete subject instruction has not yet been received from storage 14 when the branch-with-execute instruction executes, then the new IPB pointer value for the target instruction is stored in BAR 19. At this time, the IPB location indicated by incrementing the IPB pointer by three is then allocated in IPB 11 for the branch target fetch. This is shown in block 101.
1, - (I 4-- I, L I, I
As indicated in block 102, all locations in IPB 11 except the location previously allocated and the locations associated with the current IPB pointer and the current Its pointer plus one are freed. The location allocated previously cannot be freed because it is needed for the branch target fetch. The locations associated with the current IPB pointer and the current IPB pointer plus one may hold the subject instruction and thus they cannot be freed. The COO
bit for the location in IPB 11 previously allocated and the locations previously freed are then set.
This indication is set for each location that is already allocated when it is either allocated or freed so as to mark the outstanding prefetch to that location as invalid. Note that the subject instruct lion locations are not effected here because any outstanding subject instruction prophecies are still valid.
The logic in block 95 performs the function of decoding the subject instruction. This decoding operation is complete when all parts of the subject instruction have been properly received from aegis-lens 15 through 18. At this time, IPB pointer 96 is loaded with the contents of BAR 19. This latter step prepared IPB 11 to decode the target instruction when it is received from storage 14. Finally, the lo-cation in IPB 11 associated with the BY 19 value decrement Ed by two is then freed by the logic in block 102. This procedure frees a location which may not have already been freed either due to the branch or to the decoding of the subject instruction. By following the above procedure, a branch-with-execute is implemented without canceling all of the fetches of previous instructions prior to a branch. By canceling all but one of these instructions and 7~7 executing this one instruction, regardless of the branch, processor 10 is kept busy during any comma-nications with storage 14 which are required as a result of the branch. The execution of this one instruction can significantly increase the efficiency of operation of pipeline processor 10 with respect to IPB 11.
Although the description of the invention provided herein has been primarily directed to a preferred embodiment and to a variation in that preferred embodiment in order to clearly demonstrate the basic principles of the invention, it is to be understood that many modifications and variations in the structure and operation of the invention are possible without departing from the spirit and the scope of the invention.
I
Claims (10)
1. In a processing system including a processor for executing a plurality of instructions having at least one branch instruction, and a storage from which said processor prophecies instructions, said processor comprising:
means for generating a control tag whose current value is changed each time a branch instruction is reached;
means for sending a request for instructions to said storage;
means for appending said control tag to each request sent to said storage; and, means for retaining each instruction sent from said storage to said processor, in response to said request, until execution by said processor, subsequent to said processor determining that the value of control tag accompanying each said instruction is equal to the current value of the control tag in said generating means.
means for generating a control tag whose current value is changed each time a branch instruction is reached;
means for sending a request for instructions to said storage;
means for appending said control tag to each request sent to said storage; and, means for retaining each instruction sent from said storage to said processor, in response to said request, until execution by said processor, subsequent to said processor determining that the value of control tag accompanying each said instruction is equal to the current value of the control tag in said generating means.
2. A processor according to Claim 1 wherein said means for retaining comprises an instruction prefetch buffer having a plurality of separately identifiable registers.
3. A processor according to Claim 2 further comprising means connected to said instruction prefetch buffer for appending a number to each request for instruction identifying to which one of said plurality of registers each instruction returned is to be sent.
4. A processor according to Claim 2 further comprising means connected to each of said plurality of separately identifiable registers for setting a control signal each time a request for instruction is sent to said storage.
5. A processor according to Claim 4 wherein said means further comprises means for resetting said control signal subsequent to the value of control tag accompa-nying each returned instruction being unequal to the current value of the control tag in said generating means, thereby indicating that a branch instruction has been reached.
6. A processor according to Claim 5 further comprising means connected to said instruction prefetch buffer for delaying execution of said branch instruction until said control signal has been reset.
7. In a processing system including a processor and a storage from which said processor prefetches instructions, a method for executing a plurality of instructions having at least one branch instruction, said method comprising:
generating a control tag whose current value is changed each time a branch instruction is reached;
sending a request for instructions to said storage;
appending said control tag to each request sent to said storage; and, retaining each instruction sent from said storage to said processor, in response to said request, until execution by said processor, subsequent to said processor determining that the value of control tag accompanying each said returned instruction is equal to the current value` of the control tag.
generating a control tag whose current value is changed each time a branch instruction is reached;
sending a request for instructions to said storage;
appending said control tag to each request sent to said storage; and, retaining each instruction sent from said storage to said processor, in response to said request, until execution by said processor, subsequent to said processor determining that the value of control tag accompanying each said returned instruction is equal to the current value` of the control tag.
8. A method according to Claim 7 further comprising the step of appending a number to each request for instruc-tion identifying a location to which each returned instruction is to be sent.
9. A method according to Claim 7 further comprising the step of setting a control signal each time a request for instruction is sent to said storage.
10. A method according to Claim 9 further comprising the step of resetting said control signal subsequent to the value of control tag accompanying each returned in-struction being unequal to the current value of said control tag.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US666,790 | 1984-10-31 | ||
| US06/666,790 US4775927A (en) | 1984-10-31 | 1984-10-31 | Processor including fetch operation for branch instruction with control tag |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1227877A true CA1227877A (en) | 1987-10-06 |
Family
ID=24675490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000481787A Expired CA1227877A (en) | 1984-10-31 | 1985-05-17 | Instruction prefetch operation for branch and branch- with-execute instructions |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4775927A (en) |
| EP (2) | EP0448499B1 (en) |
| JP (2) | JPS61109147A (en) |
| CA (1) | CA1227877A (en) |
| DE (2) | DE3588182T2 (en) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0239081B1 (en) * | 1986-03-26 | 1995-09-06 | Hitachi, Ltd. | Pipelined data processor capable of decoding and executing plural instructions in parallel |
| JPH0731615B2 (en) * | 1986-04-18 | 1995-04-10 | 日本電気株式会社 | Information processing equipment |
| JPS6393038A (en) * | 1986-10-07 | 1988-04-23 | Mitsubishi Electric Corp | Computer |
| US5117489A (en) * | 1987-04-22 | 1992-05-26 | Mitsubishi Denki Kabushiki Kaisha | Data-driven processor having an internal tag-generating system for generating a distinct tagged information and assembling with un-tagged information of an input/output data packet |
| US4942520A (en) * | 1987-07-31 | 1990-07-17 | Prime Computer, Inc. | Method and apparatus for indexing, accessing and updating a memory |
| JPS6488844A (en) * | 1987-09-30 | 1989-04-03 | Takeshi Sakamura | Data processor |
| JPH0769812B2 (en) * | 1987-12-29 | 1995-07-31 | 富士通株式会社 | Data processing device |
| US5155818A (en) * | 1988-09-28 | 1992-10-13 | Data General Corporation | Unconditional wide branch instruction acceleration |
| US5226126A (en) * | 1989-02-24 | 1993-07-06 | Nexgen Microsystems | Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags |
| US5768575A (en) * | 1989-02-24 | 1998-06-16 | Advanced Micro Devices, Inc. | Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions |
| US5781753A (en) | 1989-02-24 | 1998-07-14 | Advanced Micro Devices, Inc. | Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions |
| JPH03139726A (en) * | 1989-10-26 | 1991-06-13 | Hitachi Ltd | Instruction readout control system |
| US5028186A (en) * | 1990-01-29 | 1991-07-02 | Mechanical Plastics Corp. | Hollow wall anchor with enhanced holding strength |
| US5255371A (en) * | 1990-04-02 | 1993-10-19 | Unisys Corporation | Apparatus for interfacing a real-time communication link to an asynchronous digital computer system by utilizing grouped data transfer commands |
| JP2544027B2 (en) * | 1990-05-24 | 1996-10-16 | 株式会社東芝 | Low power consumption programmable logic array and information processing apparatus using the same |
| CA2045735A1 (en) * | 1990-06-29 | 1991-12-30 | Richard Lee Sites | Computer performance by eliminating branches |
| US5493687A (en) | 1991-07-08 | 1996-02-20 | Seiko Epson Corporation | RISC microprocessor architecture implementing multiple typed register sets |
| US5539911A (en) | 1991-07-08 | 1996-07-23 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
| JP2761688B2 (en) * | 1992-02-07 | 1998-06-04 | 三菱電機株式会社 | Data processing device |
| JP3730252B2 (en) | 1992-03-31 | 2005-12-21 | トランスメタ コーポレイション | Register name changing method and name changing system |
| WO1993022722A1 (en) | 1992-05-01 | 1993-11-11 | Seiko Epson Corporation | A system and method for retiring instructions in a superscalar microprocessor |
| US5628021A (en) | 1992-12-31 | 1997-05-06 | Seiko Epson Corporation | System and method for assigning tags to control instruction processing in a superscalar processor |
| EP1107111A3 (en) | 1992-12-31 | 2002-02-06 | Seiko Epson Corporation | System and method for register renaming |
| JP2596712B2 (en) * | 1993-07-01 | 1997-04-02 | インターナショナル・ビジネス・マシーンズ・コーポレイション | System and method for managing execution of instructions, including adjacent branch instructions |
| US6065108A (en) * | 1996-01-24 | 2000-05-16 | Sun Microsystems Inc | Non-quick instruction accelerator including instruction identifier and data set storage and method of implementing same |
| US5796998A (en) * | 1996-11-21 | 1998-08-18 | International Business Machines Corporation | Apparatus and method for performing branch target address calculation and branch prediciton in parallel in an information handling system |
| EP0855645A3 (en) * | 1996-12-31 | 2000-05-24 | Texas Instruments Incorporated | System and method for speculative execution of instructions with data prefetch |
| US6157998A (en) | 1998-04-03 | 2000-12-05 | Motorola Inc. | Method for performing branch prediction and resolution of two or more branch instructions within two or more branch prediction buffers |
| EP1050811A1 (en) * | 1999-05-03 | 2000-11-08 | STMicroelectronics SA | Branching in a computer system |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5021821B1 (en) * | 1968-10-31 | 1975-07-25 | ||
| JPS52120735A (en) * | 1976-04-05 | 1977-10-11 | Agency Of Ind Science & Technol | Microporogram control unit |
| US4155120A (en) * | 1977-12-01 | 1979-05-15 | Burroughs Corporation | Apparatus and method for controlling microinstruction sequencing by selectively inhibiting microinstruction execution |
| AU529675B2 (en) * | 1977-12-07 | 1983-06-16 | Honeywell Information Systems Incorp. | Cache memory unit |
| US4179737A (en) * | 1977-12-23 | 1979-12-18 | Burroughs Corporation | Means and methods for providing greater speed and flexibility of microinstruction sequencing |
| US4360868A (en) * | 1978-12-06 | 1982-11-23 | Data General Corporation | Instruction prefetch means having first and second register for storing and providing a current PC while generating a next PC |
| JPS5582357A (en) * | 1978-12-15 | 1980-06-21 | Nec Corp | Information processing unit |
| JPS56129950A (en) * | 1980-03-07 | 1981-10-12 | Hitachi Ltd | Information processor |
| US4348724A (en) * | 1980-04-15 | 1982-09-07 | Honeywell Information Systems Inc. | Address pairing apparatus for a control store of a data processing system |
| JPS56149646A (en) * | 1980-04-21 | 1981-11-19 | Toshiba Corp | Operation controller |
| US4430706A (en) * | 1980-10-27 | 1984-02-07 | Burroughs Corporation | Branch prediction apparatus and method for a data processing system |
| JPS57193843A (en) * | 1981-05-22 | 1982-11-29 | Mitsubishi Electric Corp | Pipeline computer |
| JPS581247A (en) * | 1981-06-26 | 1983-01-06 | Mitsubishi Electric Corp | Cntrolling method for instruction advance-fetch |
| US4435756A (en) * | 1981-12-03 | 1984-03-06 | Burroughs Corporation | Branch predicting computer |
-
1984
- 1984-10-31 US US06/666,790 patent/US4775927A/en not_active Expired - Lifetime
-
1985
- 1985-05-17 CA CA000481787A patent/CA1227877A/en not_active Expired
- 1985-08-16 JP JP60179565A patent/JPS61109147A/en active Pending
- 1985-08-20 EP EP91480085A patent/EP0448499B1/en not_active Expired - Lifetime
- 1985-08-20 EP EP85110391A patent/EP0180725B1/en not_active Expired
- 1985-08-20 DE DE3588182T patent/DE3588182T2/en not_active Expired - Fee Related
- 1985-08-20 DE DE8585110391T patent/DE3586235T2/en not_active Expired - Fee Related
-
1988
- 1988-04-28 JP JP1988056781U patent/JP2504830Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE3588182T2 (en) | 1998-10-29 |
| EP0180725B1 (en) | 1992-06-17 |
| EP0448499A2 (en) | 1991-09-25 |
| JPS63199341U (en) | 1988-12-22 |
| DE3586235T2 (en) | 1993-02-11 |
| EP0448499B1 (en) | 1998-04-08 |
| DE3586235D1 (en) | 1992-07-23 |
| JP2504830Y2 (en) | 1996-07-24 |
| DE3588182D1 (en) | 1998-05-14 |
| EP0448499A3 (en) | 1992-05-06 |
| US4775927A (en) | 1988-10-04 |
| EP0180725A3 (en) | 1988-10-05 |
| EP0180725A2 (en) | 1986-05-14 |
| JPS61109147A (en) | 1986-05-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1227877A (en) | Instruction prefetch operation for branch and branch- with-execute instructions | |
| US5127091A (en) | System for reducing delay in instruction execution by executing branch instructions in separate processor while dispatching subsequent instructions to primary processor | |
| US5941981A (en) | System for using a data history table to select among multiple data prefetch algorithms | |
| CA1268555A (en) | Branch stream coprocessor | |
| EP0162778B1 (en) | Instruction prefetch system for conditional branch instruction for central processor unit | |
| JP2531495B2 (en) | Method and system for improving branch history prediction accuracy in a superscalar processor system | |
| US4942525A (en) | Data processor for concurrent executing of instructions by plural execution units | |
| EP0423906B1 (en) | Method of and apparatus for nullifying an instruction | |
| CA1282181C (en) | Method and apparatus for facilitating instruction processing of a digital computer | |
| US5297281A (en) | Multiple sequence processor system | |
| US20050198480A1 (en) | Apparatus and method of controlling instruction fetch | |
| US5146570A (en) | System executing branch-with-execute instruction resulting in next successive instruction being execute while specified target instruction is prefetched for following execution | |
| US4719570A (en) | Apparatus for prefetching instructions | |
| US5784711A (en) | Data cache prefetching under control of instruction cache | |
| US4541047A (en) | Pipelined data processing system | |
| KR100267101B1 (en) | Instruction fetch unit and processor processing method | |
| EP0297943B1 (en) | Microcode reading control system | |
| US4763253A (en) | Microcomputer with change of flow | |
| EP0240606B1 (en) | Pipe-line processing system and microprocessor using the system | |
| US5897654A (en) | Method and system for efficiently fetching from cache during a cache fill operation | |
| US6292866B1 (en) | Processor | |
| US9507600B2 (en) | Processor loop buffer | |
| US5276853A (en) | Cache system | |
| US6961844B1 (en) | System and method for extracting instruction boundaries in a fetched cacheline, given an arbitrary offset within the cacheline | |
| US20040098564A1 (en) | Status register update logic optimization |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |