CA1229428A - Integrated circuit chip structure wiring and circuitry for driving highly capacitive on chip wiring nets - Google Patents
Integrated circuit chip structure wiring and circuitry for driving highly capacitive on chip wiring netsInfo
- Publication number
- CA1229428A CA1229428A CA000490346A CA490346A CA1229428A CA 1229428 A CA1229428 A CA 1229428A CA 000490346 A CA000490346 A CA 000490346A CA 490346 A CA490346 A CA 490346A CA 1229428 A CA1229428 A CA 1229428A
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- CA
- Canada
- Prior art keywords
- integrated circuit
- transistor
- level metal
- chip
- spaced apart
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11801—Masterslice integrated circuits using bipolar technology
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00376—Modifications for compensating variations of temperature, supply voltage or other physical parameters in bipolar transistor circuits
Abstract
ABSTRACT OF THE DISCLOSURE
The disclosure is directed to integrated circuit chips and particularly to "gate array", or "master slices" whereon one or more circuits drive a highly capacitive on chip wiring net. The driving circuits are modified and a compensation circuit coupled to the highly capacitive on chip wiring net to mitigate the burden caused by the high capacitance. The integrated circuit structure also contains efficiently positioned on each chip a number of compensation circuits which are readily connectable during the fabrication of the chip. The employment of one, or a number of, on chip compensation circuits does not materially increase the chip power consumption.
The disclosure is directed to integrated circuit chips and particularly to "gate array", or "master slices" whereon one or more circuits drive a highly capacitive on chip wiring net. The driving circuits are modified and a compensation circuit coupled to the highly capacitive on chip wiring net to mitigate the burden caused by the high capacitance. The integrated circuit structure also contains efficiently positioned on each chip a number of compensation circuits which are readily connectable during the fabrication of the chip. The employment of one, or a number of, on chip compensation circuits does not materially increase the chip power consumption.
Description
~I9-83-063 r -1-lob IMPROVED INTEGRATED CIRCUIT CHIP STRUCTURE
WIRING AND CIRCUITRY FOR DRIVING HIG~TY
CAPACITIVE ON CHIP WIRING NETS
Field of the Invention The invention concerns an integrated circuit chip structure containing a plurality of integrated circuits and a plurality of wiring nets interconnecting said integrated circuit chips. At least one of said wiring nets subjected to unduly high capacitive loading. A compensations circuit is connected to the unduly high capacitively loaded wiring net to obviate, or at least reduce, the detrimental effects on electrical performance resulting from the unduly high capacitance.
Related Material US. Patent No. 4,521,700 issued June 4, 1985 by R.J. Blumberg, S. Browner and R. Robortaccio and of common assignee herewith Background of the Invention and Prior Art The prior art has addressed the problem of highly capacitive wiring nets by employing push-pull outputs and/or higher power circuits. The push-pull circuit requires more components and more silicon area on the chip.
The prior art includes numerous patents and publications directed to integrated circuit structure, wiring and circuitry for improving the operation of I
Z~2~3 integrated circuitry contained on a semiconductor chip.
Summary of the Invention The invention is directed to integrated circuit chips and particularly to "gate array", or "master slices" where one or more circuits drive a highly capacitive on chip wiring net. As is well known in the art the driving of a highly capacitive on chip wiring net is a burden which results in pulse delay and shrinkage. In accordance with the invention the driving circuits are modified and a compensation circuit coupled to the highly capacitive on chip wiring net to mitigate the burden. Further, the FOE
, ~2~28 invention includes integrated circuit structure to efficiently position on the chip a number of companies-lion circuits which are easily connected, as needed, during the fabrication of the chip. Also the employ-mint of one, or a number of, on chip compensation circuits does not materially increase the chip power consumption.
In VSLI, high capacitive loading of a wiring net must be addressed. As chips become larger and circuit density increases this problem intensifies. When an automatic wiring system wires the chip, it is frequently the situation that in the order of approximately I of the time a high capacitive wiring net will occur. A high capacitive wiring net causes the internal circuit to have a significant increase in signal delay, or pulse transmission. Thy disclosed technique, in accordance with the invention, will speed up these "problem" nets after the automatic wiring has been accomplished and without increasing the internal cell size.
The benefits of the invention may preferably be obtained by placing components of a "speed up" or compensation circuit in the silicon chip under a second level power bus. This integrated circuit chip location is particularly desirable in that frequently the silicon under the second level power buss is otherwise unused or blink. In general, a chip layout includes second level power buses which run the length of the chip. These power buses may be separated by a number, such as six to eight, of internal cells for power distribution.
Numerous "gate array" (or maser slice layouts containing a sizable number of warble cells are known to he art. A large number of US. Patents and ~22~42~
publications are directed Jo "gate array" (or Easter-slice) layouts, cells containing components, wiring interconnecting components contained in a cell, first level metal conductors and second level metal conductors. US. Patent No. 4,249,193 fully identified swooper is directed to an improved master slice design technique including structure, wiring and method of fabricating very large scale integrated circuit devices.
The primary object of the invention is to provide an improved integrated circuit chip.
A further object of the invention is to provide circuitry which compensates for the impaired electrical performance in integrated circuitry employing heavily capacitive wiring nets.
A further object of the invention is to provide in an integrated circuit chip fabricated as a part number from a gate array, circuitry and structure for off-setting the impaired, or diminished, performance of the integrated circuitry due to heavily capacitive wiring nets.
A further object of the invention is to provide compensating circuitry for TTL circuits called upon to drive a wiring net subjected to high capacitive loading.
the forgoing and other objects, features and advantages of the invention will be more apparent from the following more particular description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.
Brief Description of the Drawings Figure lo discloses a TTL circuit which may be employed in the practice of the invention. The TTL
circuit of Fly. lo is fully disclosed and claimed in , , .
FUGUE -5- ( ~Z~8 US. Patent 4,521,700 issued June 4, 1985 entitled -`"TTL logic Circuits".
Figure lo discloses a well known TTL circuit which may be employed in the practice of the invention.
Figure lo discloses a DTL circuit which may be employed in the practice of the invention.
Figure lo discloses a DTL circuit which may be employed in the practice of the invention.
Figure PA discloses the TTL circuit of Figure lo modified in accordance with the invention.
Figure 2B discloses the TTL circuit ox Figure lo modified in accordance with the invention.
Figure 2C discloses the DTL circuit of Figure lo modified in accordance with the invention Figure ED discloses the DTL circuit of Figure lo modified in accordance with the invention.
Figures PA through ED respectively further disclose a compensating or speed-up) circuit employed in accordance with the practice of applicants' invention.
Figure 3 depicts an integrated circuit (master-slice, or gate array) chip having an array of cells of m columns and n rows whereby the chip has m x n cells.
As further depicted in Figure 3, each row of cells has insulated therefrom and superimposed there over a first level metal wiring channel. Each wiring channel comprises a plurality of first level metal conductors.
Also represented in Figure 3 are a plurality of spaced apart second metal power busses. The second level metal power busses are superimposed over and insulated from the first level metal wiring channels.
Figure 4 discloses illustrative waveforms A, B, C
referred to hereinafter in the detailed explanation of the invention. Waveforms A depicts an ideal condition wherein an input pulse and an output pulse are of equal duration and the delay between the input and output pulse is relatively short. In waveforms B the pulse shrinkage reduction in duration) and time delay between the input pulse and output pulse are very troublesome and pronounced if not totally unaccept-able. Waveforms B illustrate the burden incurred, in the absence of the practice of applicants invention, where a relatively highly capacitive on chip wiring net must be driven. Waveforms C illustrate the benefits resulting from the practice of applicants' invention, where a highly capacitive on-chip wiring net must be driven. In waveforms C, it is seen that the "ideal" condition depicted by waveforms A is approached. Alternatively stated, the excessive delay and pulse shrinkage depicted by waveforms B is obviated or at least materially mitigated.
Figure 5 is a circuit schematic, in accordance with the invention, and corresponding to the structure and circuitry of Figure 6 concentrating on the particular net of interest.
Figure 6 is a planar vow of a portion of an integrated circuit chip, such as depicted in Figure 3 and in accordance with the invention. Figure 5 illustrates an embodiment of the invention wherein the driving TTL circuit(s) and the driven TTL circuit are depicted as well as the interconnecting highly kapok-itive wiring net (first level metal) and a compel-station circuit. Also illustrated is the placement Of the compensation circuit beneath a second level metal power bus.
Figure 7 is a further view of a portion of an integrated circuit chip, such as depicted in Figure 2 and in accordance with the in notion.
Figure 8 is a cross-sectional view taken along the lines 8-8 of Figure 7.
Figure g is a cross-sectional view taken along the lines 9~9 of Figure 7.
FOE I
9~Z8 Figure 10 is a cross-sectional view taken along the lines Lowe of Figure 7.
Figure 11 is a cross-sectional view taken along the lines 11-11 of Figure 7.
Figure 12 is a circuit block diagram referred to in the explanation of the waveforms of Figure 13.
Figure 13 discloses waveforms illustrative of the operation of the invention, as contrasted to waveforms of the prior art. In the explanation of the waveforms -set-forth hereinafter reference is made to the circuit block diagram of Figure 12.
Detailed Description of the Invention and Preferred Embodiment As chips become larger and the interconnections between gates become more complex, the occurrence of high capacitive wiring nets increases. The TTL
circuit family has a weakness at high capacitive loading which is intensified as circuit power is lowered. The problem is seen in the rising transition of the output. The delay (when heavily loader) is greatly determined by an ARC time constant. The circuitry in accordance with the invention will provide a much lower ARC time constant for the high capacitive nets. This "limitedly use of circuit modification including a speed-up circuit solves the loading problem while adding minimal power to the overall chip requirement. For example, a TTL circuit operating with a power of 180 micro watts may have a 19 NATO second TAO (rising output delay. This compares with a 6.6 NATO second delay for the circuit as modified in accordance with the invention. Figure lo is in accordance with the prior art. Figure PA is in accordance with the invention.
Another critical aspect of circuit performance is pulse shrinkage. The ideal case is when both edges (Ton, Tiff) have the same delay. The waveforms of FOE r I
I
Figure 4 illustrate pulse delay and pulse shrinkage for ideal circuitry, for circuitry in accordance with the prior art, and for circuitry in accordance with the invention. Waveforms A show the ideal case where a 20 no input pulse yields a 20 no output pulse.
Waveforms B Shea the case of a TTL circuit loaded with a highly capacitive output wiring net. Since the delay of the leading edge is much longer than the trailing edge, very significant pulse shrinkage occurs. In the illustrative example, a 20 no input pulse is transformed into a 4.8 no output pulse.
Waveforms C show the case of a TTL circuit loaded with a highly capacitive output net and modified in accordance with the invention. From waveforms C it is seen that an input pulse of 20 nanosecond results in an output pulse of l6.9 nanoseconds. It is apparent that the circuitry in accordance with the invention is very effective in minimizing the skew between the input and output pulses.
To be an effective solution the circuitry added and modified in accordance with the practice of the invention must be easily implemented and have minimal impact on chip size. The additional circuitry does not make a demand on chip silicon space since the circuit components thereof may be placed in chip silicon under a second metal power bus. tin many, if not most, gate array chips the silicon area under a suckered level metal bus is not utilized for cells or in any manner.) When the automatic wiring system goner-ales a highly capacitive wiring net, for example Spy, the additional circuitry may be implemented by omitting a contact and placing a via; no rewiring is necessary As will be fully apparent from the further description hereinafter with detailed reference to us the drawings) to generate a large capacitance a considerable amount of first level metal is required.
For a brief overall understanding of the invention at I
this point the explanation will by limited to Figure 7. Fig. 7 shows four internal cells two by two separated by a vertically extending second level metal power Russ. There are two speed-up, or compensation, circuits shown in the drawing. Figure 7 also illustrates the physical placement and components (To, Al) of each of the speed circuits.
The components for the speed-up circuits (To &
Al) are located under the second metal level power buss tax, which minimizes the space required to use the compensation circuit. The resistor end of the compensation circuit (B) is automatically connected to the power supply on first metal level conductor (C).
The emitter end of the circuit (D) is connected to a second metal level wiring tab (Go which runs parallel to the second metal level power buss (A) crossing over all wiring channels (El or Eye in that row of internal cells. The circuit is connected by placing a via (F) between the second metal level wiring tab (G) and a high capacitive first metal level conductor line (H) crossing under it. Figure 7 shows two rows of internal cells and their corresponding speed-up circuits. Figure 7 discloses a small portion of Figure 3. Figure 3 illustrates second level metal pudgier bussing on a gate array (or master slice) chip.
Figure 3, for purposes of illustration, shows an internal matrix of 48X52 cells with six second level metal vertical power busses. This would allow 312 (6~52) speed-up circuits.
With the tendency to increase chip size and lower circuit power the problem of high capacitive nets has become a major concern. The practice of the disclosed invention provides an effective solution (with minimal impact on the automatic wiring system, chip size, and chip power) to the problem and burden of driving highly capacitive on chip wiring nets.
.
, . . . , I, , ,, . . . , . .
FOE owe_ - ~Z9~ 8 Figures lulled show various types (TTL and DTL) of logic circuits. These circuits have a problem as circuit power is reduced because the falling and rising output transitions have different sensitivities to capacitive loading. During the falling transition the output transistor (A) is turned on yielding a logy impedance path to ground. During the rising transition the ARC time constant of the collector resistor (B) determines the speed. This ARC time constant is increased more and more as the need for lower power circuits arise. Because of this transition speed "skew" problem a major concern is pulse shrinkage. Figure 4 illustrates this problem by means of some timing diagrams. Waveforms A represent the ideal case where the rising and falling delay are equal. If this were true the pulse output would always equal the input pulse. Waveforms B illustrate what happens with a real circuit loaded with 5 picofarads. The rising output delay is 19.1 no while the falling output delay is 3.9 no yielding a pulse shrinkage of 15.2 no. The compensating circuit reduces the effect of the load capacitance on the rising output in order to alleviate this "skew"
problem. Figures PA through ED respectively show a compensating circuit used in conjunction with the circuits shown in Fig. I through lo. The compensating circuit components I offer the rising transition a much lower impudence path to the power supply. The improvement in capacitive sensitivity can be seen in Figures 12 and 13. Figure 12 shows how the waveforms were generated across 2 stages each being loaded to 5 picofarads. Waveform A in Fig. 13 represents the input and waveforms B and C represent the TTL output and the compensated TTL circuit output, respectively This illustration clearly shows that the effect of the large capacitance has been significantly reduced with the compensating circuit.
~29~2~
Fig. 4 waveforms C illustrate ho the delay improvement has alleviated the pulse shrinkage problem. Although the rising output delay (6.6ns) is still slower than the falling output delay (3.5ns) the pulse shrinkage has been reduced to 3.1 no as opposed to the previous 15.2 no. This significant improvement is primarily achieved because the compensating circuit speeds up the slower transition (rising output a great deal and effects the other transition minimally.
Figure 3 depicts a generalized chip structure which contains 52 vertical and 48 horizontal cells. For power distribution power busses are placed at some fixed increment which is 8 cells for this example. There is one compensating circuit for each power bus in each cell height. This results in 52x6 compensating circuits. It can be clearly seen that any wire having a large capacitance would have a high probability of passing under one of the power busses shown in Fig. 3. Figure 7 shows where a compensating circuit is placed and how it is connected. The components are placed under the second level metal power bus (A). A
piece of first level metal ID) is used to connect the emitter to the via (a first metal level to second metal level connection (E). piece of second metal (G) makes a connection to the via (En and crosses over all the first level metal wiring channels (WOW). If one of the first level wiring channels has a large capacitive net, a via F
can be placed connecting the compensating circuit to the desired line. Figures ill are cross-sectional views, respectively taken along the lines I 9-9, 10-10 and lull of Figure 7 to clarify the illustration.
Figure 5 is an example of TTL logic circuit connections (no particular function) and how a compensating circuit is employed. In conjunction with the logic diagram of Figure 5 a chip layout is shown in Figure 6. In Figure 5, the driving and driven integrated TAO, logic circuits are labeled Ill through ICY and the compensation circuit is represented my a labeled box. Solid black squares depict first to i `:
second level connections (vies). This illustration, Figure 6, shows the interconnection of a compensating circuit on an actual chip layout.
Although the invention has been described with a certain degree of particularity it is understood that the present disclosure has been made only by way of example and that numerous changes may be made without departing from the spirit and scope of the invention.
FOE
WIRING AND CIRCUITRY FOR DRIVING HIG~TY
CAPACITIVE ON CHIP WIRING NETS
Field of the Invention The invention concerns an integrated circuit chip structure containing a plurality of integrated circuits and a plurality of wiring nets interconnecting said integrated circuit chips. At least one of said wiring nets subjected to unduly high capacitive loading. A compensations circuit is connected to the unduly high capacitively loaded wiring net to obviate, or at least reduce, the detrimental effects on electrical performance resulting from the unduly high capacitance.
Related Material US. Patent No. 4,521,700 issued June 4, 1985 by R.J. Blumberg, S. Browner and R. Robortaccio and of common assignee herewith Background of the Invention and Prior Art The prior art has addressed the problem of highly capacitive wiring nets by employing push-pull outputs and/or higher power circuits. The push-pull circuit requires more components and more silicon area on the chip.
The prior art includes numerous patents and publications directed to integrated circuit structure, wiring and circuitry for improving the operation of I
Z~2~3 integrated circuitry contained on a semiconductor chip.
Summary of the Invention The invention is directed to integrated circuit chips and particularly to "gate array", or "master slices" where one or more circuits drive a highly capacitive on chip wiring net. As is well known in the art the driving of a highly capacitive on chip wiring net is a burden which results in pulse delay and shrinkage. In accordance with the invention the driving circuits are modified and a compensation circuit coupled to the highly capacitive on chip wiring net to mitigate the burden. Further, the FOE
, ~2~28 invention includes integrated circuit structure to efficiently position on the chip a number of companies-lion circuits which are easily connected, as needed, during the fabrication of the chip. Also the employ-mint of one, or a number of, on chip compensation circuits does not materially increase the chip power consumption.
In VSLI, high capacitive loading of a wiring net must be addressed. As chips become larger and circuit density increases this problem intensifies. When an automatic wiring system wires the chip, it is frequently the situation that in the order of approximately I of the time a high capacitive wiring net will occur. A high capacitive wiring net causes the internal circuit to have a significant increase in signal delay, or pulse transmission. Thy disclosed technique, in accordance with the invention, will speed up these "problem" nets after the automatic wiring has been accomplished and without increasing the internal cell size.
The benefits of the invention may preferably be obtained by placing components of a "speed up" or compensation circuit in the silicon chip under a second level power bus. This integrated circuit chip location is particularly desirable in that frequently the silicon under the second level power buss is otherwise unused or blink. In general, a chip layout includes second level power buses which run the length of the chip. These power buses may be separated by a number, such as six to eight, of internal cells for power distribution.
Numerous "gate array" (or maser slice layouts containing a sizable number of warble cells are known to he art. A large number of US. Patents and ~22~42~
publications are directed Jo "gate array" (or Easter-slice) layouts, cells containing components, wiring interconnecting components contained in a cell, first level metal conductors and second level metal conductors. US. Patent No. 4,249,193 fully identified swooper is directed to an improved master slice design technique including structure, wiring and method of fabricating very large scale integrated circuit devices.
The primary object of the invention is to provide an improved integrated circuit chip.
A further object of the invention is to provide circuitry which compensates for the impaired electrical performance in integrated circuitry employing heavily capacitive wiring nets.
A further object of the invention is to provide in an integrated circuit chip fabricated as a part number from a gate array, circuitry and structure for off-setting the impaired, or diminished, performance of the integrated circuitry due to heavily capacitive wiring nets.
A further object of the invention is to provide compensating circuitry for TTL circuits called upon to drive a wiring net subjected to high capacitive loading.
the forgoing and other objects, features and advantages of the invention will be more apparent from the following more particular description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.
Brief Description of the Drawings Figure lo discloses a TTL circuit which may be employed in the practice of the invention. The TTL
circuit of Fly. lo is fully disclosed and claimed in , , .
FUGUE -5- ( ~Z~8 US. Patent 4,521,700 issued June 4, 1985 entitled -`"TTL logic Circuits".
Figure lo discloses a well known TTL circuit which may be employed in the practice of the invention.
Figure lo discloses a DTL circuit which may be employed in the practice of the invention.
Figure lo discloses a DTL circuit which may be employed in the practice of the invention.
Figure PA discloses the TTL circuit of Figure lo modified in accordance with the invention.
Figure 2B discloses the TTL circuit ox Figure lo modified in accordance with the invention.
Figure 2C discloses the DTL circuit of Figure lo modified in accordance with the invention Figure ED discloses the DTL circuit of Figure lo modified in accordance with the invention.
Figures PA through ED respectively further disclose a compensating or speed-up) circuit employed in accordance with the practice of applicants' invention.
Figure 3 depicts an integrated circuit (master-slice, or gate array) chip having an array of cells of m columns and n rows whereby the chip has m x n cells.
As further depicted in Figure 3, each row of cells has insulated therefrom and superimposed there over a first level metal wiring channel. Each wiring channel comprises a plurality of first level metal conductors.
Also represented in Figure 3 are a plurality of spaced apart second metal power busses. The second level metal power busses are superimposed over and insulated from the first level metal wiring channels.
Figure 4 discloses illustrative waveforms A, B, C
referred to hereinafter in the detailed explanation of the invention. Waveforms A depicts an ideal condition wherein an input pulse and an output pulse are of equal duration and the delay between the input and output pulse is relatively short. In waveforms B the pulse shrinkage reduction in duration) and time delay between the input pulse and output pulse are very troublesome and pronounced if not totally unaccept-able. Waveforms B illustrate the burden incurred, in the absence of the practice of applicants invention, where a relatively highly capacitive on chip wiring net must be driven. Waveforms C illustrate the benefits resulting from the practice of applicants' invention, where a highly capacitive on-chip wiring net must be driven. In waveforms C, it is seen that the "ideal" condition depicted by waveforms A is approached. Alternatively stated, the excessive delay and pulse shrinkage depicted by waveforms B is obviated or at least materially mitigated.
Figure 5 is a circuit schematic, in accordance with the invention, and corresponding to the structure and circuitry of Figure 6 concentrating on the particular net of interest.
Figure 6 is a planar vow of a portion of an integrated circuit chip, such as depicted in Figure 3 and in accordance with the invention. Figure 5 illustrates an embodiment of the invention wherein the driving TTL circuit(s) and the driven TTL circuit are depicted as well as the interconnecting highly kapok-itive wiring net (first level metal) and a compel-station circuit. Also illustrated is the placement Of the compensation circuit beneath a second level metal power bus.
Figure 7 is a further view of a portion of an integrated circuit chip, such as depicted in Figure 2 and in accordance with the in notion.
Figure 8 is a cross-sectional view taken along the lines 8-8 of Figure 7.
Figure g is a cross-sectional view taken along the lines 9~9 of Figure 7.
FOE I
9~Z8 Figure 10 is a cross-sectional view taken along the lines Lowe of Figure 7.
Figure 11 is a cross-sectional view taken along the lines 11-11 of Figure 7.
Figure 12 is a circuit block diagram referred to in the explanation of the waveforms of Figure 13.
Figure 13 discloses waveforms illustrative of the operation of the invention, as contrasted to waveforms of the prior art. In the explanation of the waveforms -set-forth hereinafter reference is made to the circuit block diagram of Figure 12.
Detailed Description of the Invention and Preferred Embodiment As chips become larger and the interconnections between gates become more complex, the occurrence of high capacitive wiring nets increases. The TTL
circuit family has a weakness at high capacitive loading which is intensified as circuit power is lowered. The problem is seen in the rising transition of the output. The delay (when heavily loader) is greatly determined by an ARC time constant. The circuitry in accordance with the invention will provide a much lower ARC time constant for the high capacitive nets. This "limitedly use of circuit modification including a speed-up circuit solves the loading problem while adding minimal power to the overall chip requirement. For example, a TTL circuit operating with a power of 180 micro watts may have a 19 NATO second TAO (rising output delay. This compares with a 6.6 NATO second delay for the circuit as modified in accordance with the invention. Figure lo is in accordance with the prior art. Figure PA is in accordance with the invention.
Another critical aspect of circuit performance is pulse shrinkage. The ideal case is when both edges (Ton, Tiff) have the same delay. The waveforms of FOE r I
I
Figure 4 illustrate pulse delay and pulse shrinkage for ideal circuitry, for circuitry in accordance with the prior art, and for circuitry in accordance with the invention. Waveforms A show the ideal case where a 20 no input pulse yields a 20 no output pulse.
Waveforms B Shea the case of a TTL circuit loaded with a highly capacitive output wiring net. Since the delay of the leading edge is much longer than the trailing edge, very significant pulse shrinkage occurs. In the illustrative example, a 20 no input pulse is transformed into a 4.8 no output pulse.
Waveforms C show the case of a TTL circuit loaded with a highly capacitive output net and modified in accordance with the invention. From waveforms C it is seen that an input pulse of 20 nanosecond results in an output pulse of l6.9 nanoseconds. It is apparent that the circuitry in accordance with the invention is very effective in minimizing the skew between the input and output pulses.
To be an effective solution the circuitry added and modified in accordance with the practice of the invention must be easily implemented and have minimal impact on chip size. The additional circuitry does not make a demand on chip silicon space since the circuit components thereof may be placed in chip silicon under a second metal power bus. tin many, if not most, gate array chips the silicon area under a suckered level metal bus is not utilized for cells or in any manner.) When the automatic wiring system goner-ales a highly capacitive wiring net, for example Spy, the additional circuitry may be implemented by omitting a contact and placing a via; no rewiring is necessary As will be fully apparent from the further description hereinafter with detailed reference to us the drawings) to generate a large capacitance a considerable amount of first level metal is required.
For a brief overall understanding of the invention at I
this point the explanation will by limited to Figure 7. Fig. 7 shows four internal cells two by two separated by a vertically extending second level metal power Russ. There are two speed-up, or compensation, circuits shown in the drawing. Figure 7 also illustrates the physical placement and components (To, Al) of each of the speed circuits.
The components for the speed-up circuits (To &
Al) are located under the second metal level power buss tax, which minimizes the space required to use the compensation circuit. The resistor end of the compensation circuit (B) is automatically connected to the power supply on first metal level conductor (C).
The emitter end of the circuit (D) is connected to a second metal level wiring tab (Go which runs parallel to the second metal level power buss (A) crossing over all wiring channels (El or Eye in that row of internal cells. The circuit is connected by placing a via (F) between the second metal level wiring tab (G) and a high capacitive first metal level conductor line (H) crossing under it. Figure 7 shows two rows of internal cells and their corresponding speed-up circuits. Figure 7 discloses a small portion of Figure 3. Figure 3 illustrates second level metal pudgier bussing on a gate array (or master slice) chip.
Figure 3, for purposes of illustration, shows an internal matrix of 48X52 cells with six second level metal vertical power busses. This would allow 312 (6~52) speed-up circuits.
With the tendency to increase chip size and lower circuit power the problem of high capacitive nets has become a major concern. The practice of the disclosed invention provides an effective solution (with minimal impact on the automatic wiring system, chip size, and chip power) to the problem and burden of driving highly capacitive on chip wiring nets.
.
, . . . , I, , ,, . . . , . .
FOE owe_ - ~Z9~ 8 Figures lulled show various types (TTL and DTL) of logic circuits. These circuits have a problem as circuit power is reduced because the falling and rising output transitions have different sensitivities to capacitive loading. During the falling transition the output transistor (A) is turned on yielding a logy impedance path to ground. During the rising transition the ARC time constant of the collector resistor (B) determines the speed. This ARC time constant is increased more and more as the need for lower power circuits arise. Because of this transition speed "skew" problem a major concern is pulse shrinkage. Figure 4 illustrates this problem by means of some timing diagrams. Waveforms A represent the ideal case where the rising and falling delay are equal. If this were true the pulse output would always equal the input pulse. Waveforms B illustrate what happens with a real circuit loaded with 5 picofarads. The rising output delay is 19.1 no while the falling output delay is 3.9 no yielding a pulse shrinkage of 15.2 no. The compensating circuit reduces the effect of the load capacitance on the rising output in order to alleviate this "skew"
problem. Figures PA through ED respectively show a compensating circuit used in conjunction with the circuits shown in Fig. I through lo. The compensating circuit components I offer the rising transition a much lower impudence path to the power supply. The improvement in capacitive sensitivity can be seen in Figures 12 and 13. Figure 12 shows how the waveforms were generated across 2 stages each being loaded to 5 picofarads. Waveform A in Fig. 13 represents the input and waveforms B and C represent the TTL output and the compensated TTL circuit output, respectively This illustration clearly shows that the effect of the large capacitance has been significantly reduced with the compensating circuit.
~29~2~
Fig. 4 waveforms C illustrate ho the delay improvement has alleviated the pulse shrinkage problem. Although the rising output delay (6.6ns) is still slower than the falling output delay (3.5ns) the pulse shrinkage has been reduced to 3.1 no as opposed to the previous 15.2 no. This significant improvement is primarily achieved because the compensating circuit speeds up the slower transition (rising output a great deal and effects the other transition minimally.
Figure 3 depicts a generalized chip structure which contains 52 vertical and 48 horizontal cells. For power distribution power busses are placed at some fixed increment which is 8 cells for this example. There is one compensating circuit for each power bus in each cell height. This results in 52x6 compensating circuits. It can be clearly seen that any wire having a large capacitance would have a high probability of passing under one of the power busses shown in Fig. 3. Figure 7 shows where a compensating circuit is placed and how it is connected. The components are placed under the second level metal power bus (A). A
piece of first level metal ID) is used to connect the emitter to the via (a first metal level to second metal level connection (E). piece of second metal (G) makes a connection to the via (En and crosses over all the first level metal wiring channels (WOW). If one of the first level wiring channels has a large capacitive net, a via F
can be placed connecting the compensating circuit to the desired line. Figures ill are cross-sectional views, respectively taken along the lines I 9-9, 10-10 and lull of Figure 7 to clarify the illustration.
Figure 5 is an example of TTL logic circuit connections (no particular function) and how a compensating circuit is employed. In conjunction with the logic diagram of Figure 5 a chip layout is shown in Figure 6. In Figure 5, the driving and driven integrated TAO, logic circuits are labeled Ill through ICY and the compensation circuit is represented my a labeled box. Solid black squares depict first to i `:
second level connections (vies). This illustration, Figure 6, shows the interconnection of a compensating circuit on an actual chip layout.
Although the invention has been described with a certain degree of particularity it is understood that the present disclosure has been made only by way of example and that numerous changes may be made without departing from the spirit and scope of the invention.
FOE
Claims (11)
1. In an integrated circuit semiconductor chip, said integrated circuit semiconductor chip comprising:
at least n integrated circuits formed in said semicon-ductor chip, where n is a positive integer having a range of 2 through 6, each of said n integrated circuits having at least one input and an output;
at least one additional integrated circuit, said one additional integrated circuit having at least one input and an output, said at least one input of said at least one additional integrated circuit being spaced from said outputs of said n integrated circuits;
a plurality of spaced apart first level metal conductors contained on said integrated circuit chip, said plurality of spaced apart first level metal conductors being insulated from and superimposed over said integrated circuits contained on said integrated circuit chip, said plurality of spaced apart first level metal conductors each extending in a first direction;
a plurality of spaced apart second level metal conductors contained on said integrated circuit chip, said plurality of spaced apart second level metal conductors being insulated from and superimposed over said plurality of spaced apart first level metal conductors, said plurality of spaced apart second level metal conductors each extending in a direction orthogonal to said first direction of said plurality of spaced apart first level metal conductors;
a wiring net contained on said chip and interconnecting said n outputs of said n integrated circuits and said at least one input of said additional integrated circuit, said wiring net including one of said first level metal conductors, said wiring net possessing an unduly large magnitude of capacitance, said unduly large magnitude of the capacitance of said wiring net having a detrimental effect on the electrical characteristics of a pulse transmitted from the output of one or more of said n integrated circuits to said at least one input of said additional integrated circuit;
and a compensation circuit for materially mitigating the detrimental effect of the unduly large magnitude of the capacitance of said wiring net, said compensation circuit connected between said wiring net and a predetermined one of said spaced apart second level metal connectors, said compensation circuit consisting essentially of a serially connected resistor and a diode.
at least n integrated circuits formed in said semicon-ductor chip, where n is a positive integer having a range of 2 through 6, each of said n integrated circuits having at least one input and an output;
at least one additional integrated circuit, said one additional integrated circuit having at least one input and an output, said at least one input of said at least one additional integrated circuit being spaced from said outputs of said n integrated circuits;
a plurality of spaced apart first level metal conductors contained on said integrated circuit chip, said plurality of spaced apart first level metal conductors being insulated from and superimposed over said integrated circuits contained on said integrated circuit chip, said plurality of spaced apart first level metal conductors each extending in a first direction;
a plurality of spaced apart second level metal conductors contained on said integrated circuit chip, said plurality of spaced apart second level metal conductors being insulated from and superimposed over said plurality of spaced apart first level metal conductors, said plurality of spaced apart second level metal conductors each extending in a direction orthogonal to said first direction of said plurality of spaced apart first level metal conductors;
a wiring net contained on said chip and interconnecting said n outputs of said n integrated circuits and said at least one input of said additional integrated circuit, said wiring net including one of said first level metal conductors, said wiring net possessing an unduly large magnitude of capacitance, said unduly large magnitude of the capacitance of said wiring net having a detrimental effect on the electrical characteristics of a pulse transmitted from the output of one or more of said n integrated circuits to said at least one input of said additional integrated circuit;
and a compensation circuit for materially mitigating the detrimental effect of the unduly large magnitude of the capacitance of said wiring net, said compensation circuit connected between said wiring net and a predetermined one of said spaced apart second level metal connectors, said compensation circuit consisting essentially of a serially connected resistor and a diode.
2. In an integrated circuit semiconductor chip, said integrated circuit semiconductor chip comprising:
at least n integrated circuits formed in said semicon-ductor chip, where n is a positive integer having a range of 2 through 6, each of said n integrated circuits having at least one input and an output;
at least one additional integrated circuit, said one additional integrated circuit having at least one input and an output said at least one input of said at least one additional integrated circuit being spaced from said outputs of said n integrated circuits;
a plurality of spaced apart first level metal conductors contained on said integrated circuit chip, said plurality of spaced apart first level metal conductors being insulated from and superimposed over said integrated circuits contained on said integrated circuit chip, said plurality of spaced apart first level metal conductors each extending in a first direction;
a plurality of spaced apart second level metal conduc-tors contained on said integrated circuit chip, said plurality of spaced apart second level metal conductors being insulated from and superimposed over said plurality of spaced apart first level metal conductors, said plurality of spaced apart second level metal conductors each extending in a direction orthogonal to said first direction of said plurality of spaced apart first level metal conductors;
a wiring net contained on said chip and interconnecting said n outputs of said n integrated circuits and said at least one input of said additional integrated circuit, said wiring net including one of said first level metal conductors, said wiring net possessing an unduly large magnitude of capacitance, said unduly large magnitude of the capacitance of said wiring net having a detrimental effect on the electrical characteristics of a pulse transmitted from the output of one or more of said n integrated circuits to said at least one input of said additional integrated circuit; and a compensation circuit for materially mitigating the detrimental effect of the unduly large magnitude of the capacitance of said wiring net, said compensation circuit connected between said wiring net and a predetermined one of said spaced apart second level metal connectors.
at least n integrated circuits formed in said semicon-ductor chip, where n is a positive integer having a range of 2 through 6, each of said n integrated circuits having at least one input and an output;
at least one additional integrated circuit, said one additional integrated circuit having at least one input and an output said at least one input of said at least one additional integrated circuit being spaced from said outputs of said n integrated circuits;
a plurality of spaced apart first level metal conductors contained on said integrated circuit chip, said plurality of spaced apart first level metal conductors being insulated from and superimposed over said integrated circuits contained on said integrated circuit chip, said plurality of spaced apart first level metal conductors each extending in a first direction;
a plurality of spaced apart second level metal conduc-tors contained on said integrated circuit chip, said plurality of spaced apart second level metal conductors being insulated from and superimposed over said plurality of spaced apart first level metal conductors, said plurality of spaced apart second level metal conductors each extending in a direction orthogonal to said first direction of said plurality of spaced apart first level metal conductors;
a wiring net contained on said chip and interconnecting said n outputs of said n integrated circuits and said at least one input of said additional integrated circuit, said wiring net including one of said first level metal conductors, said wiring net possessing an unduly large magnitude of capacitance, said unduly large magnitude of the capacitance of said wiring net having a detrimental effect on the electrical characteristics of a pulse transmitted from the output of one or more of said n integrated circuits to said at least one input of said additional integrated circuit; and a compensation circuit for materially mitigating the detrimental effect of the unduly large magnitude of the capacitance of said wiring net, said compensation circuit connected between said wiring net and a predetermined one of said spaced apart second level metal connectors.
3. In an integrated circuit semiconductor chip, as recited in claim 2, wherein each of n integrated circuits and said one additional integrated circuit are respectively TTL type circuits or respectively DTL type circuits.
4. In an integrated circuit semiconductor chip, as recited in claim 3, wherein said unduly large magnitude capacitance of said wiring net results in said wiring net having an unduly large RC time constant and said compensation circuit materially reduces the RC time constant of said wiring net whereby said detrimental effect on the electrical characteristics of said transmitted pulse is materially mitigated.
5. In an integrated circuit semiconductor chip, as recited in claim 4, wherein said compensation circuit comprises the serial interconnection of a resistor and a diode between said wiring net and said predetermined one of said spaced apart second level metal connectors.
6. In an integrated circuit semiconductor chip, as recited in claim 5, wherein said serially connected resistor and diode of said compensation circuit are respectively formed in said semiconductor material beneath said prede-termined one of said second level metal conductors.
7. In an integrated circuit semiconductor chip, as recited in claim 6, wherein said diode of said compensation circuit is provided by a diode connected transistor.
8. In an integrated circuit, as recited in claim 7, wherein each of said n integrated circuits of TTL type comprises, a first transistor having one or more emitters, a base, and a collector, one or more inputs respectively connected to said one or more emitters of said first transistor, a second transistor having an emitter, a base, and a collector, said emitter of said second transistor connected to a first potential, said base of said second transistor connected to said collector of said first transistor, said collector of said second transistor connected to said wiring net, a first resistor connected between said base of said first transistor and a second potential, and a second resistor connected between said base of said second transistor and said second potential.
9. In an integrated circuit, as recited in claim 7, wherein said at least one additional integrated circuit of TTL type comprises, a first transistor having one or more emitters, a base, and a collector, one or more inputs respectively connected to said one or more emitters of said first transistor, at least one of said inputs connected to said wiring net, a second transistor having an emitter, a base, and a collector, said emitter of said second transistor connected to a said first potential, said base of said second transistor connected to said collector of said first transistor, a first resistor connected between said base of said first transistor and a second potential, a second resistor and a third resistor, said second resistor and said third resistor serially connected between said base of said second transistor and said second potential, a fourth resistor connected between said juncture of said second and third resistors and said collector of said second transistor, and an output terminal connected to said collector of said second transistor.
10. In an integrated circuit, as recited in claim 7, wherein each of said n integrated circuits of TTL type and said at least integrated circuit of TTL type respectively comprise, a first transistor having one or more emitters, a base, and a collector, one or more inputs respectively connected to said one or more emitters of said first transistor, a second transistor having an emitter, a base, and a collector, said emitter of said second transistor connected to a first potential, said base of said second transistor connected to said collector of said first transistor, said collector of said second transistor connected to a wiring net, a first resistor connected between said base of said first transistor and a second potential, and a second resistor connected between said base of said second transistor and said second potential.
11. In an integrated circuit, as recited in claim 8, 9 or 10, wherein said second potential is also impressed on said predetermined one of said spaced apart second level metal conductors.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/677,618 US4774559A (en) | 1984-12-03 | 1984-12-03 | Integrated circuit chip structure wiring and circuitry for driving highly capacitive on chip wiring nets |
| US677,618 | 1984-12-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1229428A true CA1229428A (en) | 1987-11-17 |
Family
ID=24719455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000490346A Expired CA1229428A (en) | 1984-12-03 | 1985-09-10 | Integrated circuit chip structure wiring and circuitry for driving highly capacitive on chip wiring nets |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4774559A (en) |
| EP (1) | EP0186769B1 (en) |
| JP (1) | JPS61135225A (en) |
| CA (1) | CA1229428A (en) |
| DE (1) | DE3577022D1 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5111276A (en) * | 1985-03-19 | 1992-05-05 | National Semiconductor Corp. | Thick bus metallization interconnect structure to reduce bus area |
| JP2606845B2 (en) * | 1987-06-19 | 1997-05-07 | 富士通株式会社 | Semiconductor integrated circuit |
| US5223733A (en) * | 1988-10-31 | 1993-06-29 | Hitachi, Ltd. | Semiconductor integrated circuit apparatus and method for designing the same |
| US5136357A (en) * | 1989-06-26 | 1992-08-04 | Micron Technology, Inc. | Low-noise, area-efficient, high-frequency clock signal distribution line structure |
| US5206529A (en) * | 1989-09-25 | 1993-04-27 | Nec Corporation | Semiconductor integrated circuit device |
| US5068715A (en) * | 1990-06-29 | 1991-11-26 | Digital Equipment Corporation | High-power, high-performance integrated circuit chip package |
| JP3027990B2 (en) * | 1991-03-18 | 2000-04-04 | 富士通株式会社 | Method for manufacturing semiconductor device |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3379584A (en) * | 1964-09-04 | 1968-04-23 | Texas Instruments Inc | Semiconductor wafer with at least one epitaxial layer and methods of making same |
| US3555294A (en) * | 1967-02-28 | 1971-01-12 | Motorola Inc | Transistor-transistor logic circuits having improved voltage transfer characteristic |
| US3562547A (en) * | 1967-04-17 | 1971-02-09 | Ibm | Protection diode for integrated circuit |
| US3488564A (en) * | 1968-04-01 | 1970-01-06 | Fairchild Camera Instr Co | Planar epitaxial resistors |
| US3513365A (en) * | 1968-06-24 | 1970-05-19 | Mark W Levi | Field-effect integrated circuit and method of fabrication |
| US3610951A (en) * | 1969-04-03 | 1971-10-05 | Sprague Electric Co | Dynamic shift register |
| US3631309A (en) * | 1970-07-23 | 1971-12-28 | Semiconductor Elect Memories | Integrated circuit bipolar memory cell |
| US3656004A (en) * | 1970-09-28 | 1972-04-11 | Ibm | Bipolar capacitor driver |
| JPS5435474B2 (en) * | 1973-03-26 | 1979-11-02 | ||
| JPS50142128A (en) * | 1974-05-07 | 1975-11-15 | ||
| JPS60953B2 (en) * | 1977-12-30 | 1985-01-11 | 富士通株式会社 | Semiconductor integrated circuit device |
| US4200811A (en) * | 1978-05-11 | 1980-04-29 | Rca Corporation | Frequency divider circuit |
| US4249193A (en) * | 1978-05-25 | 1981-02-03 | International Business Machines Corporation | LSI Semiconductor device and fabrication thereof |
| US4278897A (en) * | 1978-12-28 | 1981-07-14 | Fujitsu Limited | Large scale semiconductor integrated circuit device |
| US4295149A (en) * | 1978-12-29 | 1981-10-13 | International Business Machines Corporation | Master image chip organization technique or method |
| US4346343A (en) * | 1980-05-16 | 1982-08-24 | International Business Machines Corporation | Power control means for eliminating circuit to circuit delay differences and providing a desired circuit delay |
| JPS57160143A (en) * | 1981-03-27 | 1982-10-02 | Fujitsu Ltd | Semiconductor device |
| US4417159A (en) * | 1981-08-18 | 1983-11-22 | International Business Machines Corporation | Diode-transistor active pull up driver |
| JPS5844743A (en) * | 1981-09-10 | 1983-03-15 | Fujitsu Ltd | Semiconductor integrated circuit |
| US4489417A (en) * | 1982-11-24 | 1984-12-18 | International Business Machines Corporation | Multi-level communication circuitry for communicating digital signals between integrated circuits |
| US4584653A (en) * | 1983-03-22 | 1986-04-22 | Fujitsu Limited | Method for manufacturing a gate array integrated circuit device |
-
1984
- 1984-12-03 US US06/677,618 patent/US4774559A/en not_active Expired - Fee Related
-
1985
- 1985-09-04 JP JP60194028A patent/JPS61135225A/en active Granted
- 1985-09-10 CA CA000490346A patent/CA1229428A/en not_active Expired
- 1985-11-19 EP EP85114667A patent/EP0186769B1/en not_active Expired
- 1985-11-19 DE DE8585114667T patent/DE3577022D1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP0186769B1 (en) | 1990-04-04 |
| EP0186769A2 (en) | 1986-07-09 |
| JPS61135225A (en) | 1986-06-23 |
| US4774559A (en) | 1988-09-27 |
| EP0186769A3 (en) | 1988-09-07 |
| DE3577022D1 (en) | 1990-05-10 |
| JPH0518462B2 (en) | 1993-03-12 |
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