CA1232380A - Correlation detectors for use in direct sequence spread spectrum signal receiver - Google Patents

Abstract

CORRELATION DETECTORS FOR USE IN DIRECT
SEQUENCE SPREAD SPECTRUM SIGNAL RECEIVER
Abstract A plurality of transmitters synchronized to a common clock each transmit a data signal spread by a common bipolar pseudo-random code having a different assigned code sequence shift. A receiver, synchronized to the clock, discriminates the signal transmitted by a predetermined transmitter from signals transmitted by the others by generating a first bipolar pseudo-random code that is a replica of the common bipolar pseudo-random code and has a code sequence shift corresponding to that of the predetermined transmitter, and a second bipolar pseudo-random code that is a replica of the common bipolar pseudo-random code and has an unassigned code sequence shift. The difference between the first and second bipolar pseudo-random code sequences which is a trinary code sequence, is cross-correlated with the incoming signals. The cross-correlation despreads only the signal spread by the sequence having the predetermined code sequence shift. Each receiver includes a number of correlation detectors offset from each other by a fraction of a code chip together with decision circuitry to identify cross-correlation peaks for optimum synchronization. Analog and digital implementations of the correlation detectors are disclosed.

Description

~3~38~) OORRELATION DETECT~RS FQR U5E IN DIRECT

Technical Field The invention relates generally to code division multiplexing usinq direct sequence spread spectrum signal processing, and more particularly, toward signal processing to increase the number of transmitters multiplexed for a given code length.

Backqround Art In a spread spectrum system, a transmitted signal is spread over a frequer.cy band that is much wider than the minimum bandwidth required to t~ansmit particular information. Whereas in other forms of modulation, such as amplitude modulation or frequen~y ~dulation, the transmission bandwidth is comparable to the bandwidth of the information itself, a spread spectrum system spreads an information bandwidth of, for example, only a few kiLohertz oYer a band that is many mRgahertz wide, by mcdulating the information with a wideband encoding signal. Thus, an important characteristic distinguishing spread spectrum systems from other types of broadband transmission systems is that in spread spectrum signal processing, a signal other than the information being sent spreads the transmitted signal.
Spreading of the transmitted sign 1 in typical spread spectrum systems is provided by (1) direct sequence modulation,

(2) frequency 'nopping or (3) pulsed-FM or "chirp" modulation. In direct sequence modulation, a carrier is modulated by a digital code se~ence whose bit rate is much higher ~han the information signal bandwidth~ ~requency hopping involves shif~ing the carrier frequency in discrete increment~ in a pattern dictated by a code sequencet and in chirp modulation, the carrier is swept over a wide band during a given pulse interval. Other, less frequently used, carrier spreading techniques include time hopping, wherein transmission time, usually of a low duty cycle and short duration, is governed by a code sequence and time-frequency hopping wherein a code sequence determines both the transmitted frequency and the time of transmission5 AppLications of spread spectrum systems are various, depending upon characteristics of the codes being employed for band spreading and other factors. In direct sequence spread spectrum systems, for example, where the code is a pseudo~random sequence, the composite signal acquires the characteristics of noise, making the transmission undiscernable to an eavesdropper who is not capable of decoding the transmission. ~dditionaL
applications include navigation and ranging with a resolution depending upon the particular code rates and sequence lengths used. Reference is made to the textbook of R.C. Dixon, S~read Spectrum ~ , John Wiley and Sons, New York, 1976, especially Chapter 9, or application details.
Direct sequence modulation involves modulation of a carrier by a code se~uence of any one of several different formats, such ~3~3~

as AM or FM, although biphase phase~shift keying is the most common. In biphase phase shift keying (~S~), a balanced mixer whose inputs are a code sequence and an ~F carrier, controls the carrier to be transmitted with a first phase shift of X9 when the code sequence is a "1" and with a second phase shift of (180 + X) when the code sequence is a "0". Biphase phas2-shift keyed modulation is advantageous over other forms because the carrier is suppressed in the transmission making the transmission more difficult to receive by conventional equipment and preserving more power to ~e applied to information, as oFposed to the carrier, in the transmission. Ch æ acteristics of biphase phase-shift keying are given in Chapter 4 of the aforementioned DLxon text.
The type of code used for spreading the band~idth of the lS tran~mission is preferably a linear code, particularly if message security is not required, and is a maximal code for best cross correlation characteristics. Maximal codes are, by definition, the longest codes that could be generated by a given shift register or other delay element of a given length. In binary shift cegister sequence generators, the maximum length (~C) seque~ce that is capable of being generated by a shift register having n stages is 2n _ 1 bits. A shift register seq~tence generator is formEd from a shift register with certain of the shift register stages fed back to other stages. The output bit stream has a length depending upon the number of stases of the register and fe~dback employ~d, before the sequence repeats. A
shift register having five stages, for exa~ple, is capable of generating a 31 bit binary sequence (i.e. 25 - 1), as its maximal length (ML) sequence. Shift register ML seqtence generators having a large number of stages generate ML sequences that repeat so infrequently that the sequences appear to be random, acquiring the attributes of noise, and are dif~icult detect. Direct sequence systems are thus sometimes called "pseudo-noise" SySteltts.

~3~3~3~

Properties of maximal sequences are summarized in Section 3.1 of Dixon and feedback connections for maximal code generators from

3 to 100 stages are listed in Table 3.6 of the Dixon text. For a 1023 bit code, corresponding to a shift register having 10 stages with maximal length feedbac~, there are 512 "lns and 511 "O~s; the difference is 1. Whereas the reLative positions of "lns and "O"s vary among M~ code sequences, the number of ~l~s and the numker of ~O"s in each maximal length sequence are constant for identical ML
length sequences.
Because the difference between the numker of "l"s a~d the num~er of ~O~s in any maximal length sequence is unity, autocorrelation of a maxi~al linear code, which is a bit ~y bit ccmparison of the sequence with a phase shifted replica of itself, has a value of -1, except at the 0 i 1 bit phase shift area, in which correlation varies linearly from -1 to ~2n _ 1). A 1023 bit maximal c~de (2 - 1) therefore has a peak-to-aYerage autocorr21ation value of 1024, a ranse of 30.1 db.
It is this characteristic which makes direct sequence spread spe~trum transmission useful in code division multiplexing.
Receivers set to different shi~ts of a co~mon ML code are s~nchronized only to transmitters having that shift of the common code. Thus, more than one signal can be unambiguously tr~nsmitted at the same frequency and at the same tims. In an autocorrelation type multiplexed system, there is a common cloc~ or timing source to wnich several transmitters and at least one receiver are synchronized. The transmitters generate a co~mon maximal length sequencs with the code of each transmitter phase shifted by at least one bit relative to the other codes. The receiver generates a local replica of the common transmitted maxim21 length sequence having a code sequence shift that corresponds to the shift of the particular transmitter to which the receiver is tuned. The locally generated sequence is autocorrelated with the lncoming signal by a correlation detector adjusted so as to recognize the level associated with only i l-bit synchronization to despread and ~3~3~3~

-- s --extract information from only the signal generated by the predetermined transmitter.
Becausa the autocorrelation characteristic of a maximal length code sequence has an offset corresponding to the inverse of the coda length, or V/ (2n - 1) where V is the magnitude of voltage corresponding to "1"
and n is the number of shift register stages, overlap occurs between neighboring channels Thus, there is imperfect rejection of unwanted incoming signals. Unambiguous signal discrimination thus reg~tires a guard band between channels reducing the number of potential transmitters for a given code length. A long maximal length sequence compensates for the guard band to increase the number o~ potential transmitters, but this slows synchronization and creakes power imbalance of the multiplexing transmitters.
Canadian application Serial No. 477,~17, filed on March 22, 1985 and assigned to the assignee of this invention, describes a code division multiplex method and system, wherein a plurality of transmitters synchronized to a common clock each transmit data spread by a common bipolar psuedo-random code having a different assigned code sequence shift. A receiver, synchronized to the clock, discriminates khe signal transmitted by a predetermined transmitter from signals transmittPd by the others ~y cross-coxrelating the incoming si~nal with a trinary sequence that is developed at the receiver. The receiver develops the trinary sequence by generating (1) a first pseudo-random code that i5 a replica of the common bipolar pseudo-random code transmitted by the transmitters and has a code sequence shift corresponding to that of the predetermined transmitter to which tha receiver is tuned, and (2) a second bipolar pseudo-random code that is a replica of the common bipolar pseudo-random code and has an unasssinged code seq~tance shift, and substracting the second code from the first~

~3~3~3~

-- 6 ~
Correlation consists of multiplication of a locally devsloped trinary sequence. Integration of thP
product averages out random noise to enhance the signal-to-noise ratio. ~hen the transmitted signal i9 biphase, the transmitted wav~forms for a "one" and a "zero" differ from each other by a 180 phase shift. With the predetermined transmitter and the receiver synchronized to each other, th~
multiplier output is at a maximum at a positive polarity for a "one" and at a negative polarity for a "zero". The multiplier output is integrated for the duration of a l-bit period. If the initial integrator output is "zero" then the polarity of the integrator output at the end of a bit period corresponds to the transmitted binary information.
In the a~orementioned copending application Serial No. 477,217, filed March 22, 1985 the degree of correlation betwe~n the predetermined transmitter and the receiver is determined by comparing the output o~ several correlation detectors having re~erence signals that are displaced in time from each other. An error signal is generated and applied to control receiver timing to perfectly align the code sequence shift of the receiver reference sequence to the code sequence shift of the predetermined transmitter.
A large number of adjustments of the correlation detector components, however, are required. For N correl-ation detectors, there are required 2N analog multipliers,requiring three adjustments each, N subtractors, each requiring adjustments, an integrate and dump integrator circuit (requiring two adjustments each~ and N sample and hold circuits, each requiring one adjustment. An eight channel detector (consisting of eight correlation detectors) thus requires eighty adjustments. This creates a significant problem, both during initial calibration and during maintenance~
Disclosure of Invention It is, accordingly, a primary object o~ the invention to provide an improved correlation detector to be used for signal detection.

Another object is to provide an improved correlation detector to be used in detection of signals in a code divislon multiplex system.
~nother object is to provide an improved correlation detector to be used in direct sequence spread spectrum code division ~ultiplex system.
A further object is to provide correlation detector circuitry having a minimum number of required calibration adjustment.
A further object is to provide an improved correlation detector hav mg a minimum num~er of re~uired calibration adjusbments for application in a multiple channel detector to determine degree of correlation between a receiver and a predetermined transmitter within a code division multiplex cammunication systemO
la The a~ove and other objects are satisfied in accordar.ce with the invention which involves,a number of differen~ em~odiments of - a correlation detector~wherein first and second reference sisnals in the form of bipolar digital sequences aLe multiplied by an inccming data modulated, bipolar se~uence, and the products are subtsacted form each other~ The differences are integrated to avera~e out random noise and are further demodulated ~o recover oinary information. The transfer function developed by each channel o~ the correlation de~ector is T s(t)[r(t)-e(t)]dt where r(t) is the bipolar sequence having a code shift corresponding to that of the predetermined transmitter, e(t) is the bipolar code sequence having an unassigned code shift, stt) is the incoming signal, and T is a bit period.
In accordance with one emk~diment, thë multiplier for each channel or sub-receiver ccmprises an analog multiplexer having two inputs ccntrolled respectively by the corresponding two reference sequences r(t) and e(t). The multiplexer selectively applies the input sequence and an inversion of the input sequence s(t) to a subtractor to develop a sequence equivalent to the expression s(t)[r(t)-e(t)] to be integrated over a bit period to develop the correlation.
In a second em~odiment, the N-channel correlation detector comprises N three-input analog multiplexers that, in response to the polarities o~ the ~o reference sequences, supply either the input signal s(t), an inversion of the input signal s(t), or zero, to the integrate and dump circuits for integration over successive bit periods. The two reference signals r(t~ and e(t) control the three-input multiplexer through digital logic circuitry.
In accordance with a third en~odiment, all signal processing is perfor~ed digitally. The received signal s(t) is digitized and gebraically sLmmed in an accumulator over a period of time equal to a bit pe~iod. The differenc~ between the intial and final values in the accumulator represents the value of s(t) integrated over a bit period. The value of the accumulator is maintained constant when the values of the two reference signals are equal.
When the two referen~e signals are not equal, the contents of the accumulator are m~dified in accordance with the value o s(t);
when r(t) is a "one" the digitized value of s(t) i5 added to the acc~mulator; ~hen r(t) is a "zero" the digitized value of s(t) is subtracted from th~ accu~ulator.
In accordance with a variation of the third ~mbodiment, a voltage-to-frequency converter digitizes the input signal and accumulates the sum with a frequency counter. 'i~hen the two reference signals are equal, a clock driving the counter is disabled. ~hen r(t) is a "one", the binary counter is controlled to accumulate pulses at a rate proportional to s(t) from the voltage-to-frequency converter. ~hen r(t) is a "zero", the accumulation is subtractive and the count direction is reversed.
In this disclosure, there is shown and described only the preferred emkcdiments of the invention, but as aforementioned, it is to be understood that the invention is capable of use in various o~her combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.

3~

Brief Description of the Drawin~s Figure l is a simplified block diagram showi~g a DSSS code division multiplex receiver;
Figure 2 is a representation of a bipolar pseudo-random pulse sequence;
Figure 3 is a diagram ~howing an autocorr21ation pattern for a bipolar pseudo-random pulse sequence of the type shown in Figure 2;
Figure 4 is a superposition of several auto-correlation patterns corresponding to neighboring trans-mitters in a code division multiplex system;
Figure 5 is a diagram corresponding to Figure 4, wi~h signals of neighboring ~ransmitters separated by guard bands;
Figures 6(a) ~(d) are wave forms showing trinary code generation;
Figure 7 is a simplified block diagram showing a receiver operated in accordance with the principles of the invention;
Figure 8, on the second sheet of drawings, is a diagram showing an idealized cross-correlation pattern be-tween a locally developed trinary code sequence and an in-coming binary code sequence in accordance with the lnventlon;
Figures 9(a)-9(c) are diagrams showing correlation patterns developed by multiple channel correlation detectors in accordance with various embodiments of the invention;
Figure lO, on the fourth sheet of drawings illus-trates an actual correlation pattern obtained in the re-ceiver o~ the present invention when operated in the pres-ence of various degrading factors:
Figure ll illustrates an analog embodiment of multiple correlation detectors for determining the degree of correlation in accordance with the invention;
Figure 12 is a circuit simplication of the analog embodiment of Figure ll using binary reference signals;
Figure 13 is a further circuit simplification of ~l~3~3~3~D

the analog circuit of Figure 11, using digital logic toraduce the number of analog multiplexers;
Figures 14(a) and 14(b) illustrate two methods of implementing the circuit of Figure 13;
Figure 15 i5 a digital implementation of one channel of the circuit shown in Figure 11;
Figure 16 is an N-channel generalization of the circuit implementation in Figure 15;
Figure 17, on the tenth sheet of drawings, shows another digital implementation of a single channel correlator of a type shown in Figure 11;
Figure 18 is an N-channel generalization of the circuit shown in Figure 17;
Figure 19 illustrates an in-phase and quadrature-phase correlation pattern, together with the locations of sub-receiver channels for correlation detection;
Figure 20(a) and 20~b) are flow charts showing two alternative methods for performing fine tuning of the r ~ iver;
Figure 21, on the seventh sheet of drawings, illus-trates a microprocessor based circuit for performing fine tuning of the receiver and signal presence detection;
~igures 22(a) and 22(b) are flow charts respec-tively showing methods for correcting receiver timing and for performing signal presence detection and appear on the fifteenth and ~ourteenth sheets of drawings, respectively;
Figure 23 is a flow chart showing one technique fox performing coarse tuning of the receiver;
Figure 24(a) - 24(e) are timing diagrams showing the relationship of timing pulses between a kransmitter and a recsiver;
Figure 25, on the ninth sheet of drawings, illus-trates a circuit for locking a transmitter and receiver to the same timing pulses; and Figure 26 illustrates a microprocessor based cir-cuit for performing data recovery in the receiver.
Best Mode for Practicin~ the Invention General In spread spectrum communications, spreadmg of si ~ 1 bandwidth beyond the bandwidth n~rmally reqlk~d for data being ~3~3~

transmitted i5 accGmplished by first phase shift keyed (PSX) modulating a carrier waveform by data to be transmitted, and then modulating the resultant signal by a reference pseudo-random code of length L running at a repetition rate which is normally at least twice the data rate. Forms of modulation other than PSR can be applied to modulate the carrier as well as to spread the composite signal, although PSK is preferred or reasons set forth earlier.
To demodulate the signal transmission, the received signal is hetero~yned or multiplied by the same reference code as the one used to spread the ccmposite transmission, and assuming that the transmitted and locally generated receiver codes are synchronous, the carrier inversions caused by the code PSK modulation at the transmitter are removed and the original base-band modulated carrier is restored in the receiver.
Figure 1 illustrates the fundamental elements of a basic spread sFectrum receiver incorporating one aspect of the invention~ Receiver 100 receives a direct sequence spread spectrum (DSSS~ signal transmitted by a particular transmitter among a plurality of such transmitters~ and processes the received signal to discriminate the signal transmitted by the particular transmitter frcm among the signals transmitted by all the transmitters. Bearing in mind that the received signal is essentially modulated twice, that isl the carrier is modulated with data and then the composite is modulated by a pseudo-random code sequence to spread the c~nposite over a bandwidth that is camparable to the bandwidth of the pseudo-random sequence, receiver 100 provides two stages of demodulation of the received signal to extract the transmission data. The received DSSS signal is first heterodyned or multiplied by the code of the particuLar transmitter whose signal is being discriminated from among the others. ~hus, assuming that the codes generated at the transmitter and receiver are synchronous, the carrier inversions caused by the code PSK modulation at the transmitter are removed ~3~3~

at multiplier 102, and the original base-band modulated carrier is restored. The narrow-band restored carrier is appLied to a band pass filter (not shown) designed to pass only the base-band modulated carrier. Base-~and data are then extracted by heterodyning or multiplying the restored carrier by a locally generated carrier at multiplier 104~ The output of multiplier 104 is applied to a conventional correlation filter L06, sucn as an integrate and dumy circuit, follcwed by a sample and hold circuit whicn develops signals corresponding to the transmitted data.
m e receiver lO0 is controlled by a standard microprocessor 108, synchronized to a system clock 110, to which the transmitters are also synchronized. Because noise and undesired transmissions are treated in the same prosess of multiplication in multiplier 102 by the locally generated reerence code that compresses the received direct sequence signal into the original carrier bandwidth, any incoming signal not synchronous with the locally generate~ reference code is spread into a ban~width equal to the sum of the bandwidth of the incoming signal and the bandwidth of the reference code. Since this uNsynchronized input signal is mapped into a bandwidth that is a~ least as wide as the reference code, a band pass filter can reject a significant amount of the pcwer of an undesired signal. This is the significance of a DSSS
systen: synchronous input signals at the reference code mcdulated bandwidth are transformed to the base-band modulated bandwidth, whereas non-syncbronous input signals remain spread over the code-modulated bandwidth.
Synchronization processing makes use of a property inherent in the particular code that is employed at the transmitter. The autocorrelation of a maximal length (ML) sequence, that is, multiplication of the sequence by a time shifted replica of itself, is at a peak when synchronization is achieved and has an absolute value that drops to P2/L, where P is the magnitude cf the code sequence and L is the code length, as synchronization becomes lost (i.e., the time difference betweQn the code and its 3~

replica approaches a code chip or greater)O The sign of the autocorrelation pattern is dependent upon the data bit ~eing used to moduLate the transmitter. It is thus possible to recover the transmitted data at the receiver by monitoring the sign of the autocorrelation output when the receiver and transmit~er are properly synchronized.
Reerring to Figure 2, a pseudo random code sequence of a type to which receiver 100 is tuned is bipolar, that is, it is assumed to switch polarities of a constant voltage pcwer supply.
In the invention, bipolar, rather than unipolar, sequences are used to improve power transmission efficiency, since ~he carrier is suppressed in bipolar transmission. Bipolar tran$mission also avoids high concentrations of energy in any freauency band to help avoid interference between ~ransmissions by different transmitters in the system. Each bipolar sequence has a magnitude P and a chip duration Tc. The length of the ML sequence depends upon the number of different transmitters whose signals are to oe code-division multiplexed within the system. Each transmitter is assigned the same transmission code having a different specified chip of the cG~non M~ sequence. The maximum number of transmitters that are capable of being multiplexed within this system thus corresponds to the length of the ML sequence.
The number of transmitters that may be multiplexed without interference within a code-division multiplex system of this ~y~e is equal, theoretically, to the bit length of the se~uence. For an ML code having a length of 63 bits, for example, ~he transmission channel is theoretically capable of multiple~ing 63 different transmitters. This assumes that synchronization is deemed to be achieved between the receiver and a preseLected transmitter when the autocorrelation between the code received fr~n the transmitter and the locaLly generated code, both synchronized to a common timing source, is at a peak. In practice, ho~ever, the number of transmitters that can be code division multiple~ed in the system is much lower than the ~%3~

theoretical maximum, because there is overlap between neighboring correlation curves due to the -P /L term in the autocorrelation of the ML sequence. ~his can be better appreciated with reference to ~igure 3 which shows a correlation curve for a single transmission and Figure 4 which shows a number of correlation curves ror neighboring transmlssions, that is, for transmissions that are time offset from each other by a single code chip.
In Figure 3, the correlation curve has a magnitude -P2/L
when the transmitted and locally generated code sequences are time offset frcm each other by greater than a code chip Tc, where P
is the absolute magnitude of the sequence and L is the sequence length in bits. When the transmitted and locally generated codes are near synchronization, that is, are within a time offset of one code chip of each other, the correlation increases Ln magnitude to a peak of P at perfect synchronization. Thus, ~ynchronization between the receiver and a single tIansmitter can be detected by monitoring the correlation output and deeming synchronization to exist when the correlation signal is above a predetermined positive value.
Referring now, however, to Figure 4, assume that there are three ~ransmitted code sequences k, k-l and k~l, time shifted from each other by a single code chip. Each correlation has a positive peak value of p2 and a negative peak value of -P2/L, as Ln Figure 3. The correlation curves of neighboring code sequences overlap, within the regions shown by cross-hatching in ~igure 4.
In those regions, neigh~oring code sequences have common correlations, making it Lmpossible to distinguish between transmissions. As a practical matter, to avoid interference between transmissions, it is necessary to insert a guard band between sequences, as sho~n in Figure 5. This is provided by assigning transmissions to sequence shifts corresponding only to alternate code chip delays, rather than to every code cnip delay as in Figure 4. The result is that, at best, only one-half the number of transmissions, ccmDared to the theoretical maximum .

~3~

number, can be multiplexed. In practice, even fe~er than one-half the theoretical maximum tran~mitters are ca~able of being multiplexed in a code divisio~ multiplex systen using bipolar sequences because a guard band that is greater than that provided using only alternate code shift delays is required to avoid synchronization ambiguities.
In accordan oe with one asFect of the invention, the number of transmitters that are capable of being multiplexed is increased to one less than the theoretical limit by cross-correlating the input signal with a trinary code developed by obtaining the difference between the code sequence assigned to tho particular transmitter to which the receiver is tuned and a code sequence that is unassigned. In other ~ords, two bipolar code sequences are developed at the receiver. One of the codes is the replica of the common co~e sequence transmitted by all the transmitters and has a sequence shift that corresponds to the sequence shift of a predetermined one of the transmitters. The second code is a replica of the co~non bipolar sequence and has a code sequence shift that is not assigned to any of ~he transmitters. One of the locally generated codes i5 subtracted from the other, and the resultant, which is a trinary code sequence, is correlated with the inco~in~ signals. The sequence shift of the trinary code sequence is brought to within one code chip of the secuence generated by the preselected transmitter, using a static synchronization technique to be described ~elow. Perfest synchronization between the receiver and preselected transmitter is obtained using dynamic synchronization, also to be described in detail below, obtaine~ generally by successively shif'ing the timing of the receiver by a fraction of a code chip and monitoring the output of ~he correlatorO When the correlation out~ut is at a peak, the receiver and preselected transmitter are ccnsidered to ~e synchronized to each other. Assuming now that the receiver and transmitter are also synchronized to corres,oonding clock pulses (i.e., ~he transmitt2r is not synchronized to one clock pulse and the receiver synchronized to another), the polarity of the correlation output is nitored to extract the transmitted data.

~3~3~3 Development of the trinary pulse sequence to be cross-correlated with the transmitted sequences is ~etter understood with reference to Figures 6(a)-6(d). In Figure 6(a), a transmitted bipolar sequence s(t) havins an absolute magnitude P
and chip period Tc is shown. ~his sequence is a simpliflcation of an actual sequence which, in practice, would be substantially longer, e.g., 63 bits. Within the receiver is developed a first reference pulse sequence r(t) shown in Figure 6(b). Ihe s~quence r(t) is identical to the sequence s(t) transmitted by the predetermined transmitter sho~n in Figure 6(a~, because the transmitter and receiver sequences have the same delay and are presumed sync~ronized to each other.
The receiver senerates a second reference pulse sequence e~), shown in Figure 6(c), which is the same sequence as the one transmitted by the preselected transmitter as well as by all the other transmitters but has a sequence delay that i5 not assigned to any of the transmitters.
The difference [r(t) - e(t)] ~etween ~he two locally generated reference pulse sequences is obtained, to provide the trinary pulse sequence shcwn in Fiyure 6(d). The trinary sequence has a value ~2, 0, -2], depending upon the relative binaIy values of the two reference pulse sequences r(t) and e(t).
It is to ~e understoGd ~hat the sequence length in the example shown in ~igure 6 is 7 bits~ altnough in practice, much longer sequences wollld ~e applied to accommodate a relatively large number of transmitters to be code division multiplexed.
Referring to Figure 7, development of the trinary reference sequence to be cross-correlated with incoming bipolar pulse sequences for signal demultiplexing is provided in a receiver 200~ m e receiver 200 receives the transmitted pulse sequences s(t) and applies the inc~ming sequences to the inputs of a first correlation multiplier 202 and a second correlation mul~iplier 204. m e first correlation multiplier 202 multiplies the incoming sequences s(t) by the locally generated reference pulse sequence 3~

r~t) having a se~uence shift correspond mg to the sequence shift of the preselected transmitter. The multiplier 204 multiplies the in~omlng sequences s(t) by the pulse sequence e(t) having an unassigned pulse sequence shift. The resultant multiplication products are applied to a differen oe circuit 206, and the difference is integrated and sampled in a standard correlation filter 208 to develop an output signal Yout.
It is po m ted out that in Figure 7, the input sequences s(t) are first multiplied respectively by the two reference pulse sequences r(t) and e(t), and then the product difference is obtained in difference circuit 206. This is equivalent to obtaining the difference between the two reference pulse sequences r(t) and e(t) and then multiplying the difference by the incoming sequences s(t).
The resultant cros~-correlation is shown in Figure 8. ~ote that each correlation curve has a value 0 when the preselected transmission and locally generated reference sequence r(t)-e(t) are displaced from each other by more than one cGde chip. This contrasts with the cross-correlation curve of Figure 3, wherein there is a negative residual correlation having a magnitude P2/L. ~he magnitude of the correlation curve increases linearly to a peak value of P~L+l)~L when the preselected transmitted and locally generated reference pulse sequences are synchronized.
The advantage of this correlation stra~egy is appreciated by ccnparing Figure 9a showing the correlations of a nu~er of neighboring trans~issions in accordance with the invention and Figure 4. In particular, Fig. 9a shows codes with a separation of 2 code chips. Hcwever, it will be appreciated that the Figure 9a transmissions can be displaced from each other by a single code shift and that there is no overlap between the correlations of adjacent transmissions, whereas in Figure 4, overlap occurs in the cross-hatched portions. The invention thus enables the number of transmissions capable of being multiplexed to be equal to one less than the length of the pulse s~quence ln bits, a result that is not possible using prior art systems. Even if a guard band is placed between transmissions in the strategy shown in Figure 9a, the number of transmissio~s that can be reliably multiplex~d is substantially greater than the numker that can be reliably s multiplexed using the correlation strate~y shown in FLgure 4.
Assume that the code-division multiplexed PSK signal Y(t) incaming at the receiver is expressed as follows:
Y(t) = ~ PjdjXj(t)cos(Wct + 0) ~ N(t) (1) where for J incoming transmissions:
O C t C T, where T is a code chip period;
Pj is the power within each incoming bipolar pulse sequence;
dj is the polarity or sign of each corresponding incoming sequence;
Xj(t) is the transmitted data;
Wc is the frequency o the carrier in radians;
O is the carrier phase; and N(t) is noise~
m e output VA(T) of the conventionaL receiver, using a single reference code sequence, is defined by the following:

V~(T) = Prdr + L ~ Pjdj + NA (2) j~
where:
Pr is the pcwer of the desired incoming sequence;
dr is the da~a sign of the desired sequence, L is the pulse sequence length in bits;
Pj is the power of each of the undesired sequences;
dj is the corres~onding data sign of the undesired sequence; and NA is noise.
The output VB(T) of the receiver operating in accordance with the principles of the invention is deflned as ollows:
~ (T) = Prdr (1 ~ (3) ~3'~3~

Because the correlation method of the lnvention involves a subtraction of a code se~uence having an unassigned code sequence shift, all undesired transmission components (identified by the subscript "rn) in the output VB(T) are perfectly rejected, whereas in the prior art receiver, the output VA(T) involves contributions of the undesired transmissions (having tne subscript "j") as well as the desired transmissions (subscript "r").
~ultiplexer trinary signal correlation induces an additional three decibels of degrada~ion in data sign21-to-noise demodulation with respect to white noise appearing at the receiver input, compared to conventional correlation using only the particular transmission binary pulse sequence. Thus, __ .

(4) l; N2 = 2(1+1/~

~he multiplexing strategy discussed above results in perfect unwanted access rejestion capability using r~L codes of any length in a code-division multiplex systen. In the past, only ML codes of suf~iciently long length were potentially usable with the number of allowa~le multiplexers being much less than the code length. Even there, power imbalances of the multiplexing transmitters occurred.
Additionally, the ideal cross correlation patter~ in Fig. 9a lends itself to multiplexing schemes usi~g more tnan the theoretical limit of code, each time-offset by less than a code chip, and assuming a more complex receiver configuration. For example, it has been discovered that the number of transmitters which could be multiplexed can be increased to 2 x (L-2) channels by adding a code between each of the code sequences shown in Fig.
4, with only a slight trade off in overall receiver signal-to-noise performance. As shown in Fig. 9b an additional code c~n be inserted between each of the codes shown in Fi~. 4.
~he codes are detected at a plurality of taps provided at the receiver. The outputs of the various receiver taps shown in Fig.
9b are as follow5:

3i~1 TABLE I
1. ex~ra code 2. 1/2 extra code 3. null 4. 1/2 code 1

5. code 1 + 1/2 code 1'

6. 1/2 c~de 1 ~ code 1' + 1/2 code 2

7- V 2 code 1' + code 2 1 1/2 code 2' The sequence of equations may then be solved for each channel:
channel 1 ~ 2 x tap 4 channel 1' = 2 x (tap 5 - channel 1) channel 2 = 2 x (tap 7 - channel 1' - tap 4) channel 2' ~ 2 x (tap 7 - channel 2 - tap 5) .. .. ..
channel L' - 2 x tap(2L ~ 3) In practice, the above arrangem~nt would be somewhat difficult to implement due to both noise and synchronization proble~s. An alternative implemen~a~ion would require tha~ a null of ~he carriers occurred at the point where the correlation envelope is equal to 1/2 the maximum. In such an arrangement, the equations for the outputs of the taps beccme:

T~BLE II
1. extra code 2. null 3. null 4. nuLl 5. code 1 6. code 1' 7. code 2 This arrangement allows for full data recovery wi~hout interference. However, it may still be somewhat susceptible to noise.

~3;~

In order to overcome the above problems, there is shown in Fig. 9c an arrangement in which two or more code sequences are grouped together and separated by guard-bands. ~he exact - separation of the groups or the patterns comprising the groups is independent of this arrangement. This approach also allows the grouping of transmitters with similar characteristics and simplifies synchronization problems.
Any additional modulation by data bearing signals and that necessary for improved ccmmunication between transmitters and receivers can be incorporated in the above describ~d strategies.
The only condition required is that any additional modulaticn must not destrcy the necessary timing of the shifted pulse sequences thereby maintaining receiver multiplexing sensitivity.

Synchronization - General The receiver and preselected transmitter must be time synchronized to each other before data can be extracted. Assuming that the receiver and transmltter are synchroni2ed to a common timing source (if the commercial power line is the transmission 2~ medium, common tlming can be obtained from the 60 ~ertz power source), ynchronization is a matter of adapting receiver timing to different propagation delays of the transmitted signal as well as to the tining signal and to delays inherent in the transmitter and receiver. Scme of these delays are fixed, and can be comFensated using a ~Istatic~ delay, to synchronize the receiver and predetermined transmitter to within one code chip of each other, wherein a chip is defined as the bit period of the pseudo-random code generator.
In general, static delay can be comDensated during initial calibration of the receiver, since most static delays are fixed.
A difficulty occurs, hcwever, when the transmission medium ls a transmission line with the transmitter and receiver synchronized to a common timing source, and wherein co~munication ~etween the two units is bidirectional. Static delay must thus be examined 3~

- 2~ -frcm two reference points, one where the transmitter is at the timing source and the other where the receiver is at the timing source.
With the transmitter located at the tLming source and the receiver located elsewhere, the timing signal and transmitted siqnal will propagate at aFproximately the same speed from the transmitter to the receiver. Other timing variatlons between the transmitter and receiver are due to delays induced within the transmitter and receiver circuitry, and can be preset to synchronize the transmitter and receiver to within one code chip of each other. All receivers remote from the timing source can thus have identical static delays.
If the receiver is located at the tlming source and the transmi~ter is located elsewhere, however, each receiver may lS require a static delay that is unique or each remote transmitter to account for different signal propagation distances. Thus, to enable a receiver to receive signals from a multiplicity of transmitters, the static delay oE the receiver must be variable~
In practice, the static delay between each transmitter and the receiver is measured u~on installation of tne transmitter; that static delay value for all future co~munications with a particular transmitter is ~reset with m the receiver. ~ne~ever a transmission is received from that transmitter, to obtain united synchronization of the transmitter, receiver tLming is automatically adjusted to accammodate the delay associated ~ith the particular transmitter.
In one embodiment of the invention, there are a plurality of transmitter/receiver units disposed in a so-called "master/slave"
arransement. In this arrangement, one transmitter/receiver ur.it;
called the master station, acts as the source of thming signals for the other stations (slave units). The amount of delay associated with the timing signals between the master station and each of the slave stations includes such things as the filter delay for the timing signal source at ~he master station, the 38~

received filter delay at the master ~tation, t~e signal propagation delay between the master and a particular slave, the coupling delay at the master station and the transmit filter delay at the master station. Knowledge of ~hese various delays will give an esti~ate of the amount of static delay associated between the master station and a particular slave station ~owever, some variation in each dela~ will occur with changes in the transmission line associated with temperature changes, transmission frequency, etc.
~hile dynamic delay adjustments can tdke care of most of these changes in the static delay characteristics between the master and slave units, the multiplexing capabilities of the system may be some~hat reduced because the receiver at a partlcular master or slave unit must be capable of tracking delay variations over a range of several code chips. This requires a guard band that is wide enough to allow the signals of two adjacent receivers to vary in time over their as55ciated bands without interference.
Howevert it has ~een discovered that the amount of required guard band may be reduced by ~eriodically measuring, at the ~aster station, the static delays associated with signal transmission between the master station and each of the slave stations and then periodically adjusting the transmitter signal timing at the slave in order to bring the static delay back into a desired range.
This allows more slave stations to transmit at one time since the guard band required for delay variations can be greatly reduced thus allowing more usable code delays for multiplexing.
Variations from synchronization established by the static delay are compensated by a dynamic delay mechanism within each receiver. The dynamic delay consists of two stages: fine tuning and coarse tuning. Whereas static delay timing causes the receiver and predetermined transmitter to be synchronized to each other to within one code chip, fine tuning uses correlation detection to make fine adjustments in receiver timing as a 9L~3~3~3~

function of received transmission, rather than as a function of an expected transmission (static delay).
After fine tuning has established that receiver timinq is at a local correlation peak, it ~ecomes necessary to det_rmine if the local peak to which the receiver is timed is the "correct" local peak for best correlation. ~his is necessary because, depending upon the correlation properties of the code selected, as well as other factors, there are likely to be multiple correlation ~eaks, with the primary local peaks having the greatest peak magnitude.
These multiple peaks arise fram carrier correlation within the +lTC code correlation peak. Finally, it must be determined which of the system timing pulses present in each data bit is the proper one for synchroni~ation. Without such a determination, a condition can exist wherein the transmitter is locked to one timing pulse while the receiver is locked to another timing pulse. This is because these are two timing pulses in a data period and incorrect timing causes a quadrature condition between transmitter and receiver data ~eriods. Thu5, the net energy for such quadra~ure data periods is zero, Even with the receiver and transmitter properly synchronized to each other, data cannot be extracted from the received seguence ~ecause it is not ~ossible to detect and decode the data transmission unless the receiver and transmitter are locked to the same timing pulses~ Fine tuning and coarse tuning as well as synchronization to the proper timing oulse within each data bit shall now be described in more detail.
Figure 10 illustrates the correlation pattern obtained by cross-correlating an incoming, bi-polar pulse sequence together with its carrier and the locally generated trinary reference sequence. The correlation pattern has a major peak at receiver timing Vl and has minor correlation peaks at receiver timings V2, V3, V6 and V7, referred to hereinafter as "channelsn. The correlation peak at prLmary channel Vl depends upon the correlation properties of the code selected as a Eunction of code chip time delay difference between the inc~ming code sequence and 3~38~

the reference code sequence. The correlation is at a peak wnen synchronizatlon bet~een the receiver and transmitter is achieved, with the absolute value of the correlation dropping to zero as the synchronization difference ap,oroaGhes a code chip or greater. It should ~e noted that, due to imperfect correlation properties of the code and due to the influe~ce on correlation by the sinusoidal carrier, the correlation shown in Figure 10 i5 approximately sinusoidal as compared to the piece-wise linear, ideal correlation profile shown in Figure 9a which does not include a carrier. This is the reason that coarse tuning is requirel; fine tuning adjusts receiver timing until a correl2tion peak is determined; coarse tuning then determines whether the correlation peak is the major correlation peak associated with channel Vl or is a minor correlation peak associated with channels V2, ~3, V6 or V7, or others.
In accordan oe with one aspect of the invention, synchronization of the receiver is achieved by providing a plurality of separate sub-receivers or correlation de~ectors that are tuned to each receiver channeL. Aasuming that each of the channels Vl, V2, V3, V6 and V7 are spaced apart from each other in time by one third of a code chip, ine tuning adjusts the receiver timing such ~hat the channels are all located at local peaks.
Further~ore, assuming that channel Vl is within a code chip of being synchronized, the channel Vl is within one sixth of a code chip of a local peak. The outputs of the correlation detectors are ap~lied to a microprocessor 314, described oelowr to develop a receiver timing signal for synchronization to the transmi~tQr and to extract transmission data. Various embcdiments of the multiple correlation detec~ors are illustrated in Figures 11-13.
Correlation Detection One emkcdiment of the multiple channel correlation detector shown in Figure 11 is generalized for ~ correlation channels. The multiple channel correlation circuit identified generally by 300 ~L~3~3~

comprises for each channel a correlator 302 each ccmDrising a first multiplier 304, a second multiplier 306 and a difference circuit 308. The first multiplier 304 has one input that receives the inconing sequences s(t) and a second input that receives the fir~t locally generated reference sequence r(t) having a sequence shift that corresponds to the sequence shift of a predetermined transmitter. The multiplier 306 has one input that receives inccming sequences s(t) and a second input that receives the second reference sequence e(t) having an unassigned sequence shift. m e outputs of the two multipliers 304 and 306 representing, respectively, the products of the incoming sequences and the two locally generated reference sequences are applied to the inputs of difference circuit 308. The difference output is applied to an integrate and dump type filter 310, matched to the period of a bit at the chip rate, to develop a signal VN for each channel as follows:
VN = S s(~) k (tN) - e(tN)]dt (S) o wherein VN and s(t) are analog signals while r( ~) and e( ~) are binary signals. The output of the integrate and dump circuit 310 is aFplied to a sample and hold circuit 312 which monitors and stores the magnitude and polarity of the integrator output V~.
This value if applied to a conventional microprocessor 314 that in response to outputs from all N of the detectors 302 extracts the binary data frcm the predetermined transmission and develops a timing error signal to retain the receiver locked in synchronism with the predetermined transmitter, as discussed in more detail below.
The analcg multiple channel correlation detector shown in Figure 11 requires a substantial num~er of calibration adjustments associated with the multipliers 304, 306, the difference circuits 308, the integrate and dump circuits 310 and the sample and ho~d circuits 312. In practice, an 8-channel detector of this t~pe requires approxi~ately 80 calibration adjust~ents.

If only the polarity of the reference sequences r(t) and e(t) is used, considerable simplification of the system results, with only a slight degradation in performance. Because the two reference sequences are binary (bi-polar) signals, multiplication can be achieved in an N cha~nel correlator using 2N two-input analog multiplexers and one inverter, shown in Figure 12. In this implementation, the binary reference signal determines whether the input signal s(t) or an inverted input signal s~t) is selected to ~e applied to subtraction circuit 308. Bearing m mind that the desired output of each of the N difference circuits 308 is s(tN)[r(tN) - e(tN)], each channel in the correlation detector 400 shown in Figure 12 comprises a first two-input multiplexer 402 and a second two-input multiplexer 404 controlled, respectively, by the instantaneous polarities of the first and second bi-polar reference sequences r( ~) and e(tN). One input of each of ~he t~o multiplexers ~02, 404 is connected to a first line 406 that receives the incoming sequences s(t) and a second input connected to a line 408. The line 408 receives the incoming sequences s(t) inverted in polarity by an inverter 4100 The multiplexers 402 and 404 are driven by the reference sequences r(~) and e(tN) through drivers 412 and 414.
Assuming that the polarities of r(t~) and e(tN) are identical, both of the multiplexers 402 and 404 are connected to the line 406. The input sequence s(t) is thus applied to both the positive and negative input terminals of the differen oe circuit 308 whereby a zero signal is applied to integrate and dump circuit 310 (Fig. 11). If r( ~) is positive and e(t~) is negative, multiplexer 402 is connected to line 406 and multiplexer 404 is connected to line 408. The sequence s(t) is thus applied to the positive input of difference circuit 308 and the inverted sequence s(t) is applied to the negative input terminal of circuit 308; the sequence 2s(t) is thus applied to integrate and dump circuit 310.
If, on the other hand, the relative polarities of the two reference sequences are reversed, the sequence s(t) is applied to 3~

the negative input of difference circuit 308 and the inverted input se~uence s(t) is aeplied to the positive input of dif~erence circuit 308. Ine signal -2s(t) is thus applied to integrate and dum~ circuit 31Q, thereby satisfying the equa~ion VN(t) = s(tN3[r( ~) - e(tN)3.
The circuit o Figure 12 is advantageous over the circuit o Figure 11 beca~-se analog multiplier calibration adjustments are not required in Figure 12, although the inverter 410 requires t~o (balance and offset) calibration adjust~ents. The num3er of adjustments requi~ed for an eight-channel detector is thus reduced from approximately 80 to 34.
Referring to Figure 13, a urther simplification of the circuit shown in Figure 11 can be achieved by recognizing that the input to each integrate and dump circuit 310 is the difference between two signals, each of which is the input sequence s(t) multiplied by a ~l or a l, with the output being zero when the t-~o reference se~uences are equal to each other~ In accordance with Figure 13, the 2N multipliers and the N subtractors are replaced, in circuit 500, by N three-i~put analog multiplexers 502. One input of each of the multiplexers 502 is connected to a line 504 which receives the input se~uence s(t). A second input of multiplexer 502 is connected to a line 506 which receives an inversion s(t) of the input sequence, inverted by 508. The third input of multiplexer 502 is connected to a line 510 that in turn is connected to ground.
The first reference sequence r(tn) is connected directly to the control input of multiplexer 502 through an inverter/driver 512. Also connected to the control input of multiplexer 502 is an exclusive-oR circuit 514 having inputs connected respectively to the two reference sequences r(tn) and e(tn).
When the t~o reference sequences are equal to each other, the out2ut of the exclusive-OR circuit 514 drives the multiplexer to line 510, causing the output of multiplexer 502 ~o generate a zero signal to integrate/dump circuit 310 (Fig. 11). If ~.he first reference r(tn) equals 1, the output Y(t) of multiplexer S02 equals s(t). If r(t) equals 0, on the other hand, the multiplexer output v(t) equals -s~t). ~he output of the difference circuit thus generates the signal s(tn)[r(tn) - e(tn)] and the integrate and dump output for each channel is S s(t)[r(tn) - e(tn)ldt, as required. (6) ~o circuits for implementing the three-inpu~ analog multiplexer 502 of Figure 13 are shown respectively in Figures 14a and 14b. In Figure 14a, each of the two t~o-input multiplexers 600, 602 have the following chaxacteristics:
x = x0, when A = 0;
x = xl, when A = 1.
~he first reference sequence r(t) is connected to control terminal A of multiplexer 600 and to one input of an exclusive-O~ circuit 604. The second reference sequence e(t) is connected to a second input of exclusive-CR circuit ~04. The output of the exclusive-OR
604 is c~nnected to the control terminal A of multiplexer 602.
The incoming sequ2nces s(t) are connected to one input terminal xl of multiplexer 600, and, through an inverter 606, to the second input x0 of the same multiplexerO The output x of multiplexer 600 is applied to one input xi of ~ultiplexer 602;
the second input x0 of multiplexer 602 is connected to ground.
2S The output v(t) of the multiplexer shown in Figure 14a is defined by the following truth table, which corresponds to the required equation v(t) = s(t)[r(tn) - e(tn)].
I~BLE III
r(t) e(t) r ~3 e v(t) 0 1 1 -s(t) 1 0 1 s(t) ~3~

In the embodiment of the three-input multiplexer 606 shown in Figure 14b, the output x is connected selectively to any one of the four inputs xO, xl, x2, x3, depend m g upon the binary values of control inputs A, B. The input se~uences s(t) are S connected directly to input x2 and through an inverter 608 to input xl. Inputs xO and X3 are connected to ground. The two reference sequences e(t) and r(t) are connected respectively to control inputs A and B of multiplexer 606.
Ihe operation of multiplexer 606 is described by the truth table ~et forth a~ove with respect to Figure 14a and also provides the desired output v(t).
The correlation detector embodiments of Figures 11-14 are based upon the analog techni~ue of integrating a continuous signal. The number of calibration adjustments required can be l; reduced further by replacing analog integration in the correlation de~ector by discrete signal s~mmation. Referring to Figure 15, correlation detector 700, provided in each channel of the receiver, digitizes the incoming sequences s(t) and algebraically sums the digitized signal in an accumulator over a period of time equal to a bit period. The dif~erence between the initial and final values in the accumulator represents the value of s(t) integrated over a bit period. Accumulation is controlled by the values of the reference sequences r(t) and e(t). ~hen the two eeference sequences are equal, the accumulated value is unchanged. ~hen r(t) and e(t) are unequal, the accumulation is incremented or decr2mented by the value of s(t) depending upon the value of r(t).
Correlation detector 700 comprises an analog-to-digital converter 70~ that receives the analog sequence s(t) and in response generates a corresponding digital signal at output terminal D. The output of analog-to~digital converter 702 is applied to one input A of an adder/subtracter circuit 704 having an output applied to the input of an accumulator register 706.
The output of the accumulator 706 is a~plied to output register 708 and also to the second input B of adder/subtracter 704.

~3~3~

Operation of the units 702-708 as well as of a ~equencer 710 are syn~hronized to a bit periad T. Sequencer 710 in turn controls the conversion times of A~D converter 702 and the accumulation times of accumulator register 706 at outputs 712 and 714, respectively. ~he accumulator register 706 is also controlled by the values of the t~o refrence sequences r(t) and e(t) through exclusive-CR gate 116 and AND gate 718.
The adder/subtracter 704 develsps an output signal which is the sum of the digitized input sequence s(t) and the contents of accumulator register 706 when reference seauence r(~) is 1 and generates the difference between the accumulator register contents and ~he digi~ized value of input sequence s(t) when reference ~equence r(t) is zero. Selective addition and subtraction of the t~o signals applied at adder/subtracter inputs A, B are controlled by the signal applied at input ~, developed by reference sequence r(t) through an inverter 720.
If r(t) equals e(t), the exclusive-O~ gate 716 develops a logic 0 signal that is applied to one input of AND gate 718. To the output input of ~ND gate 718 is a write-accumulation signal developed by s~querncer 7100 Sequencer 710 alternatel~ develops a ~convert input" signal applied to A~D converter 702 ~o provide an analog-to-digital conversion of input sequence s(t) and a "write accumulator" signal ~hich adds or subtracts the instantaneous value of s(t) to the current accumulated value, to be applied to output register 708 and then to microprocessor 314 (Figure 11) which develops binary out,out and timing error signals.
Thu9, the content of the accumulator register 706 re~ains unchanged when r(t) equals e(t) under control of an exclusive-OR
gate 7160 When r(t) equals a logic 1, the content of accumulator register 706 i5 incremented by the value of the inccmlng sequen~e s(t); when r(t) equals a logic 0, on the other hand, the content of the accumulator register is decremented by the value of the input seoNence stt). This nas the effect of multiplying s(t) by +l or -1 and integrating.

3~

The correlation detector 700 of ~igure 15 is generalized into I an N-channel correlation detector 800 in Figure 160 The reference sequences r(tn) and e(tn) are applied to an input latch 802 hav~ng r(tn) and e(tn) outputs that are applied respectively to a pair of N to 1 multiplexers 804, 806. The outputs of the t~o multiplexers 804, 806 in turn are a~plied to the inputs of e~clusive-CR gate 808 that controls accumulator memory 810 through AND gate 812.
Accumulator memory 810 in Figure 16 corresponds to accumulator register 706 in Figure 15. Memory 810, hoh-ever, contains a plurality of memory regions corresponding to each channel and addressed by a chann~l sequencer 814 controlled by the output of sequencer 816. Similarly, the output of accumulator me~ory 810 is applied to an output memory 818 that corresponds to output registRr 708 in Figure 15~ Memory 818, hcwe~er, contains a plurality of memory regions corresponding to the correlation channels and addressed by the output of sequencer 816.
m e incoming sequence s(t) is s Q led by a s Q le and hold circuit B20 and applied to analog-to-digital converter 822 wherein the incaming analcg sequence s(t) is digitized and applied to adder/sub~racter 824 in a manner described with respec~ to Figure 15.
In operation, s Q le and hold circuit 820 samples the incoming analog sequence s(t) and converts the samples to corresDonding digital values in synchronism ~ith the bit period T
develope~ by microprocessor 314 (Figure 11) and applied to sequencer 816. The content of the accumulator memory 810, within each memory region addressed by sequencer 816 is incremented 0 decremented by the current value of s(t), deFending upon the value of the reference sequence r(t) at the corresponding channel. The circuit 800 thus successively s Q les tne input sequence, multiplies the sequence by ~1 or -1 and integrates or each channel N, under control of channel sequencer 314 and sequencer 816, as well as of the microprocessor 314. The accumulator memory ~3~3 810 and output me~ory 818 thus monitor N accumulation channels, with time sync~ronism of signals during channel sequencing ~eing preserved by the sam~le and hold circuit 820 and the input latch 802.
Referring now to Figure 17, another digital implementation of a single channel correlation detector 900 comprises a conventional voltage-to-frequency converter 902 that receives the absolute value of input sequence s(t) through an absolute value circuit 904. Absolute value circuit 904 is required ~ecause the voltage-to-frequency converter 902 responds, as is conventional, to a unipolar input signal. Voltage-to frequency converter 902 converts the instantaneous magnitude of the incaming sequence s(t) to a single corresponding ~re~uency signal to be a~plied to an up/down counter 906 through one input of an AND gate ~08.
Ihe input sequence s(t~ is also applied to an analog ccmparator 908 which keeps track of the polarity of the in~ut sequence s(t). In other words, the out~ut of the analog c~parator 908 is representative of the sign of the input sequence s(t). The reference sequences r(t) and e(t) are applied to the remaining mput Of sate 908 through e~clusive-CR gate 910.
The up/down counter 906 is controlled by a secand exclusive-CR gate 91~ that receives the output of the analog comparator 908 and the first reference sequence r(t). Thus, the up/down counter is controlled to increment when the signs of the input sequence s(t) and reference sequence r(t) are the same;
otherwise the counter is caused to decrement. The outDut of counter 906 is applied to a latch 914 synchronized to bit period T.
The clock CLg of up/down counter 906 is disabled by exclusive oR gate 910 when the two reference sequences r(t) and e(t) are equal to each other. Otherwise, the counter clock is enabled and the counter 906 tracks the incoming s2auence s(t). In other words, when r(t) is 1, the counter counts up for a positive polarity sequence bit s(t) and counts d~wn for a negative polarity sequence bit s(t). ~hen the referen oe sequence r(t) is a logic ~ 3 zero, on the other har.d, accumulation i5 subtracted and the count direc~ion is reversed.
m e circuit 900 of Figure 17 is generalized to N channels of correlation detection by circuit 1000 in Figure 18. In circuit 1000, voltage-to-frequency converter 1002, absolute YalUe circuit 1004 a~d analog comparator 1006 correspond to corresponding components in Figure 17 and are co~mon to all channels. Up/down counter 1008 as well as AND gate 1010 and exclusive-OR gates 1012 and 1014, hcwever, are duplicated for each cnannel. The output of each binary up/down counter 1008 is applied to a latch 1016, ccmmonly synchronized to a bit period T. The outputs of the ~
latches are aFplied to microprocessor 314 (such as shown in Fig.
11) which processes the individual channel correlation signals and in reseonse develops binary data recovered ~ram the predetermined transmitter and timing signals to shit receiver tLming into synchronism with the predetermin æ transmitter.

~ynamic Synchronization As discussed above, s~atic synchronization involves establishing predetermined delays in the receiver that correspond to diferent prop2gation tLmes asscciated with different transmitters. Static delays, preset in the receiver during initial set-up, synchronize the transmitter and receiver to within one code chip of each other. Perfect correlation is then established by microprocessor 314 in response to the correlation signals develo~ed by the correlation detectors described above.
~icroprocessor 314 more speciEically processes the channel correlation signals to control receiver timing to synchronize to the predetermined transmitter in two stages; namely, fine and coarse tuning, ollowed by synchronization correction, if necessary, to the proper pulses of the system clock.
Referring again to Figure 10, it is recalled that code correlation is a function of code chip time delay diferences be~ween a received code and a reference code and, depending uFon ~3~3~3 the particular correlation properties of the code employed, has a peak when synchronization is achieved and has an absolute value that drops to zero as the synchronization difference approaches a code chip or greater. Data are recovered from ~he correlation pattern, based upon the recognition that the sign of the pattern depends upon the data bit used to modulate the transmitter. Thus, wnen the receiver and a predetermined transmitter are properly synchronized to each other, transmitted data are recovered by monitoring the sign of the voltage Vl at the primary correlation channel.

Fine Tuning Referring to Figure 19, a correlation pattern corresponding to the correlation pattern shown in Figure 10 is identified by 1100. This is an "in-phase" correlation pattern, with coarse correction channels Vl, V2, V3, V6 and V7 that are used to determine which of the correlation peaks corresponds to the primary channel, with maximum correlation at synchronization. An additional pair of channels V4, V5 are fine, or vernier, c~rrection channels, which maintain receiver synchroni~ation by maximizing the correlation output of the primary channel Vl. In the forea,oing discussion, it should be recognized that all referenoes to fraction of a code chip are related to the ratio be~een the carrier requency and code generation frequencies. ~s one example/ the carrier frequency is 5670 Hz, and the code generation frequency is at 3870 bits/second, so that references to fractions of a code chip are related by a ratio of 3/2, allo~ing three peaks per co~e chip. The additional correlation curve 1200 in Figure 19 is a quadrature-phase correlation curve that is displaced from the in-~hase correlation curve by 90 degrees. The significance of the quadrature-phase correlation curve is that the value of the quadrature-phase curve is at zero when the value of the in-phase quadrature curve is at a maximum. As shall ~e discussed below, signal processing, and particularly correlation peak detection, is simplified using quadrature-phase correlation.

~3~3~3~

Because there are three correlation peaks per code chip, assuming that the primary correlation cnannel Vl is ~ithin a code chip of being proFerly synchronized, the primary channel Vl is within one-sixth of a code chip of a "local" peak. ~ine tuning causes the receiver to adjust its timing, under control of microprocessor 314, such that the correlation channels Vl, V2, V3, V6 and V7, spaced apart fron each other by one-third of a code chip, are all located at local peaks. One methcd of adjusting receiver timing to locate the five correlation channels to local peaks i5 by serial hunting shown in the flow chart given in Figure 20ta). This involves U52 of a preamble of a length 2(p ~ s), where s is the number of smoothings on each bit and p is equal to one-sixth (in this example~ of a code chip period divided by the receiver correlation resolution, or the number of correlations of minimum resolution required to adjust the receiver from a synchronization null to a ~eak.
For each data bit in the preamble, the receiver primary correlation channel Vl timing is adjusted by a mlnimlm fraction 1/6(p) of a code chip (step 1320) and the magnitude of the correlation voltage Vl is stored (1330). Ihis process is repeated until the receiver has changed its timing over a maximum of a fu~l one~third of a code chip (1340). Thereafter, the point at which the magnitude of the primary correlation Vl is at a maximum is selected as being the local peak (1350), and the timing of the receiver is adjusted to position channel Vl at that point (1360).
An alternative fine tuning method controlled by microprocessor 314 is the use o fine tuning channels V4 and VS
shown in Figure 19. ~ne fine tuning channels V4 and V5, provided by an additional pair of correlation detectors (not shown), are offset in time from the prinary correlation channel Vl by an equal fraction of a code chip that is less than one-sixth of a code chipo O~tionally, a preamble may be included in the method, having a worst case length of p s with a mini~um receiver correction (resolution) being l/6(p) of a code chip. Referring to 3~30 Figure 20(b), the correlation voltages V4 and V~ are applied to mlcroprocessor 314 (step 1950) along with the correlation voltage of the pr~mary channel Vl. By ccmparing the relative magnitudes of V4 and V5 (steps 1960, 1970), the microprocessor determines the direction toward ~ich receiver tim mg is to be shifted (steps 1980, 1990) to position the primary channel V1 at the major Local correlation peak. A system of this type is shown schematically in Figure 21. Programming of microprocessor 314 is omitted for brevity, but i5 considered routine to implement based upon the simplified flow chart of Figure 20(b) and the discussion herein.
Another alternative fine tuning method involves the use of a channel whose timing is generated with a quadrature-phase carrier~ ~ecognizing from Figure 19 that the nulls of the quadrature-phase correlation pattern 1200 occur at the peaks of in-phase correlation pattern llO0, an error voltage may be develoFed by microprocessor 314 based upon the sign of the product of the in~phase and quadrature-phase patterns. The sign of the error voltaga ~us indicates a direction to which receiver tLming must be shited to cause the receiver correlation channels to synchronize to local correlation peaks. It is also possible t.o aFply the ~agnitudes of the in-phase and ~uadrature-phase correlation voltages llO0 and 1200 to determine not only the direction of shift of receiver timing to achieve synchronization but also the amount of shift required to obtain a local peak.
Thust in accordance with another aspect of the invention and as sum~ari2ed in the flow chart of Figure 22(a), the in-phase vl and ~uadrature-phase Vlq correlation voltages are measured (step 2050). The ratio of the in-phase V1 and quadrature-phase Vlq correlation voltages is calculated (2060), and if the ratio is positive (2080), the two correlations are presumed to have the same polarity and receiver timing delay is increased (2095);
otherwise, the two correlations are presumed to have opposite polarities and receiver timing delay is decreased (2090). To prevent receiver timing from being changed if the receiver is ~ 3 perfectly synchronized to the ~redetermined transmitter, and to avoid cGmplications caused by delay in the ceceiver whereby a correction decision is made using information that is more than one data bit old, the absolute value of the ratio Vl~Vlq, WhiGh is essentially a cotangent function, is monitored. A table stored in a memory associated with microprocessor 312 relates the ratio Vl~Vlq to the number of fine tuning corrections, e.g., 1~48th of a code chip for each correction, to reach optimal synchronization.
The table is set forth below.
~IE IV
Number of Corrections (Equal fractions of a C~

l 5.02 2 2.~1 3 1.49 4 l.00 0.668 6 0.~149 7 0.1999

8 0 Thus, the r.umber of corrections aFplied to receiver timing is determined directly from ~l~Vlq, and there is a correction dead band when the ratio is greater than 5.02, eliminating receiver hunting about optimum synchronization. ~Irthermore, the number of data bits needed to move the receiver from a correction null to a correlation peak is reduced from 8 (in this example) to as low as 1, minimizing the length of any required preamble and providing accelerated serial hunting. Finally, it is ~ossible to inhibit tracking corrections on consecutive data bits without decreasing the tracking rate of the receiver, thereby eliminating overshoot.

~3~

Signal Presence Detection Ihe provision of quadrature-phase Vlq as well as in-phase Vl correlation voltages furthermore makes it posslble to determine a signal present within a background of noise. As summarized in the progratn flow chart of Figure 22(b), when only noise is present at the receiver input, bo~h the in-phase Vl and quadrature-phase Vlq voltages will have approximately the same value K, such that the ratio Vl/Vl~ will be c10s2 to unity. With both signal and nois~
present, hcwever, fine tuning maximizes Vl and minimizes Vlq to obtain a ratio much greater than unity~ The ratio VlJVlq is thus used as an indlcation o signal present. In practice, the ratio may be mcnitored over a nu~ber of data bits, with smoothing techniques or majority voting being applied to ensure accuracy.
Circuitry for det~cting presence of a signal in a background of noise is shown in Figure 21~ with microprocessor 314 developing signals Vl and Vlq in response to the outputs of the correlation detectors discussed above. The signals Vl, Vlq are process~d with the microprocessor 314 to develop the ratio Vl/Vl~ and the absolute 0 value Vl/Vlq of the resultant is magnitude compared with a predetermined threshold magnitude to determane whether an incoming signal re~resents a data transmussion or whether it is merely noise.
Followin~ determanation that the receiver is tuned to a local peak using fine tuning as described above, it becomes necessary to determine through coarse tuning, whether the current local peak is the "correct" local peak such that the receiver has best correlation.

Coarse Tuning In accordance with one embodiment, coarse tuning of the receiver to a predetermined transmitter to ensure that the receiver is tuned to the maximum, and other than a secondary, correlation peak involves serial hunting wherein, having once fixed a point as a local peak, the receiver is adjusted in ~3~

multiples of one-third of a code cnip to measure the magnitude o~
the receive signal at each adjacent local peak. ~nce the magnitudes of the peaks are determined, a decision as to tne proper peak is made. Because the magnitudes of ad]acent peaks near the center of the correlation pattern are difficult to distinguish from one another due to channel filter distortion, a conventional ~center-of-m~ass" a~proach may be used to identify tne maximum local peak by basing the decision on the relative values of a11 channels rather than on only a selection of the channel having tne greatest correlation magnitude.
The microprocessor 314 is programmed in a coarse tuning, serial hunt mode to cause the receiver, following identification of a local peak, to shift in timi~g by multioles of one-third of a code chip, measure and store correlation magnitudes and make comparisons using the center of mass approach or other app~oach to identify the correct correlation peak. Serial h~nting r~quires a transmission preamble of length W s where W is the width of the peak search range (in thirds of a code chip) and s is the number of bits of smootning in the voltage readings.
In Figure 23, a simplified flow char~ of programming of microprocessor 314 to provide coarse tuning by serial hunting includes a test at step 1200 to determine, using fine tuning as discussed above, whetner the receiver is at a local peak~ If the receiver is not at a local peak, the receiver is ~ine tuned until the receiver is determined to b~ at a local peak. The receiver, once at a local peak, is incren~ented (step 1202) until its timing is at R ~ N, wherein K is the timiny of the local peak obtained durin~ ine tuning and N is a predetermined number of thirds of a code chip. The correlation value of K + N is measured and stored (step 1204), and the receiver timing is decremented by one-t~ird of a code chip (step 120~). The correlation of the receiver and predetermined transmitter is now measured and stored (step 1208), and receiver timing is tested to determine whether it is at (K N), that is, at the opposite side of the initially ~etect~d ~3~3~

local peak K (step 1210). If not, the receiver timing is again decremented and the correlation is measured and stored~
Othe~wise, all the stored correlations are tested (step 121~) to identify a peak correlation.
In accordance with another embodimentl to reduce the prea~ble lengtn, multiple secondary receiver channels, offset from each other by multiples of one-third of a code chip on both sides of the primary channel Vl develop primary and secondary correlation signa~ls to be aFplied to microprocessor 314. The microprocessor 314 is programmed, using center of mass analysis or other analysis, to identify the primary channel Vl which has the greatest m~ximum correlation and the secondary channels. By using a multiple number of receiver channels or correlation detectors, rather than serial hunting circ~itry or programming, the length of the preamble required for coarse corrections may ~e reduced to the number of bits of smcothing, s. This assumes of course tnat for the desired width of search, a channel exists witn common ofEsets of multiples of one-third o~ a code chip on both sides of the pr~mary correlation channel Vl~
Wit`n multiple receivers it i5 not necessary to program ~he microprocessor to serially hunt. ~he microprocessor 314 is instead programmed to simply compare the outputs of the correlation detectors, all tuned to a Local peak, to identiiy tne peak having tne greatest magnitude.
Timing Signal Correction If the data bit rate of the transmission is less than one-half the pulse re2etition rate of the timing source, the transmitter and receiver may oecome locked to different timing pulses even though they appear to be perfectly synchronized to each other. For example, for a data bit rate of 30 bits ~er second, a timing pulse source of 60 Hz and a carrier fr~quency located between 60 Hz harmonics, the transmitter may become locked to a first 60 Hz timing pulse with the receiver locked to the next successive 60 HZ timing pulse. .~n alternatmg data trans~ission will not ~e detected due to ~mproper receiver data timing recovery with otherwise perfect synchronization between the receiver and transmitter.
To illustrate this condition more clearly, Figure 2g(a) is a diagram representing the timing pulses to which the receiver and a predetermined transmitter are synchronized. ~he transmitter carrier is shown in Figure 24~b) and transmitted data representing alternate ones and zeros are shcwn in Figure 24tb). ~ssuming that the receiver and transmitter are synchronized to the same timing pulses, the integrate and dump circuits 310 of the receiver will be synchronized to the transmitted data inversions so as to dump at the trailing edge of each datum, as shown in Figure 24(d), where "dots'9 designate integration dump points. The sampled integrator output is thus a replica of the data embedded within the transmission.
If t`ne transmitter and receiver are not synchronized to the same timing pulses, however, the integrate and dump circuits 310 will not be properly synchronized to the data being transmitted.
m is condition is shown is Figure 24(c), where the integration du~,o points occur between transmission data inversions, and the sampled output of the integrator 310 is at zero.
In other words, with the receiver and transmitter respectively synchronized to successive, rather than the same, timing pulses, it i5 impossible to recover any of the transmission data. It is therefore necessary to test the receiver and transmitter to ensure that the t~o units are synchronized to the sam~, rather than successive, timing pulses.
In accordance with one aspect of the invention, associated with the primary receiver channel Vl is a secondary receiver channel Vl' having a built-in additional delay of one-half a data bit. Cne of the two channels Vl and Vl' will always therefore detect the transmitted signal. ~ determination is made by a~plying an alternating data prea~ble associa~ed with the 3~q~

transmission to the primary and secondary receiver channels. By comparing the magnitudes o the correlation outputs of the ~wo receiver channels, the correct channel (having the larger correlation magnitude) is the one synchronized to the same timing pulse as the transmitter is. Data are monitored at the "correct"
channel only.
~ simplified circuit for synchronizing receiver timing to cause the receiver and transmitter to be locked to the sa~,e timing pulses as sho~n in Figure 25~ Microprocessor 314 develops a secondary channel Vl' of~set from channel Vl by one-half of a data bit. In response ts an inccming sequence having an alternating preamble, the microprocessor con~oares the magnitudes of the data outputs from the channel Vl and its half bit delayed cha M el Vl', and identifies the one channel having the larger magnitude. miS
channel is thus presum~d to be the one which is locked to the same timing pulses as the transmitter is, and is reapplied to the micro~rocessor for data recovery.
In an alternative embodiment of the invention, the need or the secondary receiver channel Vl' may be eliminated. The transmitter and receiver can be synchronized wnen the ~iming referen oe frequency is less than or equal to the data sampling rate and the ratio of the data sampling rate to the timing reference frequency is an integer by ccmbining more than one of the consecutive data sam~les together to yield one data point or bit. By combining these da~a samples, an optLnum data sample point may be determined while receiving an alternating sign preamble by comparing the magnitudes of all possible summations and selecting the sample which give a max~mum output. If each sample is assigned to its own synchronization point, then synchronization may be acco~plished by locking to the time that gives the maximum output.
For example, if the timing signal has a frequency of 60 Hertz and a data sampling rate of 30 samDles ~er second, for a data rate of 30 bits per second each data sample is used to yield one data 3~

~ 4~ -point or bit. For data rates of 15, 7.5 or 3.15 bits per second two, four and eight consecutive data sam~les are used to yield one data bit. In addition to eliminating the need for a redundant data channel, the above techni~ue eliminates the need for the data sampling rate to be the same as the data rate. In fact, sampling may occur at a rate higher than the data rate. This allows the data samples to be ccmbined digitally, for example in a microprocessor, and allows the data rate to be independent of the actual har~ware timing.
Data Recovery Data recovery in spread spectrum systems is well '~nown. As backgro~nd, reference is made to section 5~3 of the ~ixon text mentioned earlier, and particularly to the discussion of Costas loop demodulators beginning on page 155.
- Because the spread spectrum system as provided herein includes multiple correlation channels, data recovery is im~roved in accordance with one asFect of the inven~ion by extracting data at each channel rather than at only a single correlation channel.
It is thereby ~ossible to Lower system message error rate and possibly to also reduce the len~th of or eli~inate any re~uired preambles for receiver synchronization.
With reference again to Figure l9, it is noted that the correlation pattern LOGO is centered about the pr~mary correlation Ghannel Yl. The sign of the primary correlation Ghannel Vl is dependent upon the sign of the data being transmitted. ~ positive value of Vl thus corresponds to a logic l being transmitted whereas a negative value of the correlation Vl corresponds to a logic O being transmitted.
The correlations at V2, V3, V6 and V1 also have values that correspond to the sign of the data being transmitted.
Specifically, the relationship of the voltage outputs at channels Vl, V2, V3, V6 and V7, in the absence of noise and distortion, are described as ollo~s:

~3~38~

V~ = V3 = Rl Vl V6 = V7 - ~2 Vl ~here ~7) Rl = -2/3 R2 = 1/3 In accordance with tne invention, the data sign at the output of each correlation detector, follow mg pro~er receiver synchronization, is m~nitored. Depending upon the characteristics of noise and distortion, data may be extIacted usin~ only the outputs at channels Vl, V2 and V3, with an effective sign~l-to-noise ratio gain of (l+l/L)-t ~ uj Kj)2 (8) (1~ uj 2 ~ 2~(Rl+l/L) ul (u2+u3) + 2 (R2~ ) u2-u3 ]=l where K. = relative noise free amplitude of V with respect to Vll j = 2, 3 (Kj = Rl in the distortion free case), L a the length of the pseudo-random code and u; = weighting factor or Vj, j = 1, 2, 3. ~ne weighting factors are selected according to the par~icular distortion present~
Figure 26 is a simplified circuit diagram showing microprocessor 314 responsive to channels Vl, V2 and V3 and programmed to combine all three correlation channel outputs to extract transmission data, with weighting .actors selected according to particular distortion '~nown to be present on the transmission medium. Table V illustrates the signal-to-noise enhancements under a fe~ possible distortion and weighting factor scenarios.

~2d ~3Z ~ ~

~, I,E V

S~
WEIGFIING F~CTCRS FoR Vj DISTCRTICN F~CTORS EQR Vj IMPRfVEMENT
S uI U2 u3kl k2 k3 FACTOR
_ _. j.~ 1 - _ ; ~
-1 _1j 1 _1 _1 1~44 1 -1 -1 1 -0.9 -0.9 1.254 _._ I - _ __ _._ _ _ .. __ 1 -1 -1 1 -0.8 -0.8 1.082 _ ~ ~ j _ _ _ _ _ _ . _ 1 1 -1 1 -0.7 0.7 0.922 1 _0.34 _0.34 1 -0.67 -0.67 0.971 _ ; ~ _ _ ~ _ _ l _ _ _ ~
1 -0.67 -0.67 1 -0.67 -0.67 0.918 __ _. _ ; - _... . . _ 1 1 -0.9 -0.~ 1 -0.9 -0.6 1.055 _ ~ ________ _ 1 -0.~ -0.8 1 0.8 -0.3 1.09 _ I _ _ _ ~ . _ _.
1 -o.g L~ 1 o 9 ! -09 _ 1.252 An additional advantage of providing a recovery on all channels of the receiver is that random and burst errors, which tend to affect all channels, can be identified and ignored. This is similar to signal pres~nce detection using in phase and quadrature-phase correlation cutputs, as discussed a~ove, but employs all channels rather than orthogonal outputs associated with a single channel.
Furthermore, as an additional advantage of obtaining data recover~ at all correlation channels or at least several correlation channels, it is possible to monitor synchronization during message re~eption. Although synchronization adjustments are not feasible during message reception, the message content may be recovered, without repeats, using the additional receiver channels.
In this disclosure, there is shown and described only the ~referred embodiments of the invention; however, it is to be ~3~3~

~ ~7 -understosd that the invention is capable o~ use in various other ccmbir~ations and enviroTIments and is caFable of changes or modifications within the scope oE the inventive concept as ex~ressed herein.

Claims (7)

WHAT IS CLAIMED IS:

1. A direct sequence spread spectrum code division multiplex system, including a plurality of transmitters synchronized to a common timing signal and each transmitting a data signal s(t) spread by a bipolar pseudo-random code which is a different assigned shift of a common bipolar sequence; characterized by:
a receiver synchronized to said timing signal for receiving said data signals and discriminating the signal transmitted by a predetermined transmitter spread by a bipolar psuedo-random code having a predetermined assigned code sequence shift from the signals transmitted by the other transmitter, said receiver includes a plurality of correlation detectors and means for developing (1) a first reference bipolar sequence r(t) that is a replica of the common bipolar sequence and has a code shift that is within one code chip of the assigned shift of the predetermined transmitter and is displaced from the common bipolar code sequence applied to the other correlation detectors by a common fraction of a code chip less than unity, and (2) a second reference bipolar sequence e(t) that is a replica of the common bipolar sequence and has an unassigned code sequence shift, each of said correlation detectors including first means for obtaining the product of the transmitted sequences s(t) and the first reference bipolar sequence r(t); second means for obtaining the product of the transmitted sequences s(t) and the second reference bipolar sequence e(t) and third means for obtaining a difference between the products obtained by the first and second means; synchronous integrator means for integrating the difference; means for synchronously sampling an output of the integrator means and signal processor means responsive to outputs of said correlation detectors to synchronize said receiver to said predetermined transmitter.

2. The receiver of Claim 1, characterized in that each of said first and second means includes first and second analog multiplexers, each of said multiplexers having two input terminals and an output terminal; means for controlling said first and second multiplexers in response, respectively, to the first and second reference bipolar sequence r(t) and e(t); and a difference circuit connected to the outputs of the two multiplexers; said transmitted sequences s(t) being applied to one of thed input terminals of the multiplexers and being applied, through an inverter, to the second input terminals of the multiplexers; each of said multiplexers being connected to its first input terminal when its respective reference sequence has one value applied thereto and to its second input terminal when its respective reference sequence has a second value, the output v(t) of the difference circuit having the following values:
r(t) - e(t); v(t) = O
r(t) = l, e(t) = 0; v(t) = +2s(t) r(t) = O, e(t) = l; v(t) = -2s(t)

3. The receiver of Claim 1, characterized in that each of said first and second means comprises an analog multiplexer having three input terminals and an output terminal, said transmitted sequences s(t) being applied to the first input terminal of said multiplexer and being applied through an inverter to the second input terminal of said multiplexer and the third input terminal receiving a ground; and digital logic means for connecting the multiplexer to its third input when r(t) = e(t) and to one of its first and second inputs, selectively, when r(t) ? e(t).

4. me receiver of Claim 1, characterized in that each of said first and second means comprises a pair of two-input analog multiplexers connected in tandem, the first multiplexer having its two inputs connected, respectively, to receive said transmitted sequences s(t) and to an inversion s(t) of said transmitted sequences; said second multiplexer having its two inputs connected respectively to a ground and to an output of said first analog multiplexer, and digital logic means for controlling said first and second multiplexers in response to said two reference sequences r(t), e(t) to generate an output v(t):
r(t) = e(t); v(t) = O
r(t) = O, e(t) = l; v(t) = -s(t) r(t) = l, e(t) = O; v(t) = +s(t).

5. The receiver of Claim 1 characterized in that each of said product detectors includes an analog multiplexer having four inputs and an output; two of said inputs being connected to a ground and the remaining two inputs being connected respectively to receive said input sequences s(t) and to an inversion s(t) of said input sequences, and means for controlling said multiplexer to develop the following output signal v(t):
r(t) = e(t); v(t) = O
r(t) = O, e(t) - l; v(t) = -s(t) r(t) = l, e(t) = O; v(t) = +s(t).

6. The receiver of Claim 1 characterized in that each of said first and second means includes an analog-to-digital converter for digitizing the transmitted sequences s(t); an accumulator responsive to the output of the converter and logic means responsive to the reference sequences r(t), e(t) to maintain constant count in the accumulator when r(t) = e(t) and to increment or decrement the count in accumulator when r(t) ? e(t);
an output register; means for periodically transferring the contents of the accumulator to the output register; and means for processing the contents of the output register to develop a receiver timing error signal to synchronize the receiver to the predetermined transmitter.

7. The receiver of any of Claims 1, 2, or 3 characterized in that each of said first and second means comprises:
a voltage-to-frequency converter;
means for obtaining the absolute value of the transmitted sequences s(t);
a reversible counter responsive to the output of the voltaye-to-frequency converter means; and digital logic means for controlling said reversible counter means whereby the counter (a) is disabled when r(t) = e(t) (b) upcounts when s(t) is positive and downcounts when s(t) is negative, when r(t) = O, e(t) = 1 downcounts when s(t) is positive and upcounts when s(t) is negative, when r(t) = 1, e(t) = O