CA1234638A - Dynamic event selection network - Google Patents
Dynamic event selection networkInfo
- Publication number
- CA1234638A CA1234638A CA000479495A CA479495A CA1234638A CA 1234638 A CA1234638 A CA 1234638A CA 000479495 A CA000479495 A CA 000479495A CA 479495 A CA479495 A CA 479495A CA 1234638 A CA1234638 A CA 1234638A
- Authority
- CA
- Canada
- Prior art keywords
- random access
- access memory
- selection network
- dynamic event
- event selection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
Abstract
DYNAMIC EVENT SELECTION NETWORK
ABSTRACT OF THE DISCLOSURE
This invention describes a method for mapping one or more of a number of input events to one or more of a number of output functions. This method involves the use of a memory device to perform the mapping between the input events and the output func-tions. This invention performs the mapping function with a minimum of hardware devices.
ABSTRACT OF THE DISCLOSURE
This invention describes a method for mapping one or more of a number of input events to one or more of a number of output functions. This method involves the use of a memory device to perform the mapping between the input events and the output func-tions. This invention performs the mapping function with a minimum of hardware devices.
Description
34ti3~
DYNAMIC EVE~T SELECTION NETWORR
BACKGROUND OF THE INVENTION
The present invention pertains to processor systems and more particularly to the use of memory devices to dynamically map one or more of a number of input events to one or more of a number oE output functions automatically.
In processor systems, it is required of the processor that it interact with external stimuli such as sensors, indicators, timers, etc. Each o these stimuli may initiate or may be initiated by the processor to perform some particular function.
Some typical triggering events might include hardware matchers providing an output, counter or timer outputs or interrupt or other logic signals transmitted from or to the processor.
An assignment scheme is required to associate a particular triggering event with a desired func-tional output. This scheme is accomplished with an event routing scheme. Typically, event routing schemes are accomplished with dedicated connections or with multiplexers. Hard-wired connections allow no flex-ibility in altering the results for given input patternO
Such a configuration is very limiting for processor application. Implementing an event selection scheme with multiplexers requires full availability of input events at each multiplexer to select the particular output. This scheme needs many hard-wired connections.
In addition, this scheme requires a dedicated multi-plexer for each output function to be programmed.Having such a large amount of hardware to implement a selection scheme is costly and requires a considerable amount of physical space.
3~
SUMMARY OF_THE_INVENTION
A dynamic event selection network is con-nected between a plurality of input sources, each of which provides triggering signals and a plurality of control devices, each which is operated in response to a control signal. A processor is connected to the selection network and initiates the operation of the network. A dynamic mapping arrangement is connected to the processor, to the input sources and to the control devices. The dynamic mapping arrange-ment operates in response to a set of changeable values of the triggering signals of the input sources to produce a particular set of changeable values of the control signals for transmission to the control devices.
The dynamic mapping arrangement is operated in response to a sele~t signal of the processor to alter each of the many sets oE values of control signals which it contains.
BRIEF DESCRIPTION_OF THE DRAWING
Fig. 1 is a schematic diagram of a dynamic event selection network embodying the principles of operation of the present invention.
FigO 2 is a schematic diagram of an extended ~5 dynamic event selection network.
Fig. 3 is a schematic cliagram of an extended dynamic event selection network~
Fig. 4 is a schematic diagram of a multi-level dynamic event selection network.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to Fig. 1, a trigger routing network which uses a static ~AM device is shown.
The trigger routing network employs a minimum amount of devices and provides complete flexibility to route any of a number of input events to one or more of 3~L6.~3 any output functions. Furthermore, two or more input events may be logically combined to produce two or more output unctions, This scheme provides for a complete mapping of any input event or events to any one or more output function.
Random access memory (RAM) device 20 is a 256 x 4-bit static RAM device~ One such RAM device is capable of providing up to eight input events and mapping them to any or all of four output functions.
Each of the eight input events is termed a triggering event. These triggering events may be output signals from devices such as hardware matchers.
These hardware matchers are devices which are manually or automatically settable to a predetermined value.
This predetermined value is compared with a dynamically changing value presented on an address or a data bus for example. Further examples of these triggering events may be a system interrupt signal, generated by a processor. Processors may generate interrupt signals asynchronously to permit signaling between peripheral devices and the associated processor.
Another type of triggering event is one which is generated by a ~imer signal from a clock.
The clock periodically transmits signals to the trigger routing network in order to enable a certain output function to occur after a particular number of signals have been counted.
Examples of output functions may include, but are not limited to: transmitting a signal to halt a central processing unit; arming a particular flip-flop device 30; incrementing an event counter 40; activating a timer 50 or any ccmbination of the above functions.
A processor, which may take the form of a central processing unit, hard-wired logic or a process ~3~63~3 controller, is connected to 2:1 multiplexer 10. The processor is also connected to multiplexer 10 via a lead called the load signal to select the input to the multiplexer 10. The load signal provides for determining which of the two inputs is gated through multiplexer 10. The address bus connects the pro-cessor to multiplexer 10 and provides for accessing each of the 256 x 4-bit words of RAM memory 20. When the processor wishes to write or change the mapping of the triggering events to the output unctions, it selects an address via the address bus and trans-mits the load signal to multiplexer 10. Multiplexer 10 gates the address bus through to the address inputs (A0 through A7) of RAM memory 20. The processor also signals on the write enable lead to ellect a write access to the ~AM memory 20. RAM memory 20 is then written with a 4-bit data word at the appropriate address contained on the address bus via the DATA
IN bus (D:tO through DI3) connected between the pro-cessor and RA~1 memory 20.
Multiplexer 10 is connected to RAM memory20 via an 8-bit bus connected to the address inputs (A0 through A7~ of RAM memory 20. The second input to multiplexer 10 is another 8-bit bus comprising the triggering events such as address matchers, inter rupt generators or timers, as mentioned above.
When the processor is not writing the RAM
memory 20, the load signal will be such that the triggering event will be gated through multiplexer 10 via the 8-bit bus to the address inputs o RAM
memory 20.
Since multiplexer 10 enables the leads repre-senting the triggering events to be connected to RAM
memory 20 via the address inputs A0 through A7, the occurrence of any triggering event will cause a par-ticular 4-bit word in RAM memory 20 to be accessed.
If the word accessed by the particular address has been pre-set by the processor with a logic 1 in a particular data bit position, the function associated with that data bl~ will be triggered or enabled.
As a result of a particular address being accessed, a 4-bit data word is read from memory and transmitted via the D0 through D3 output leads of RAM memory 20. The processor via the HALT lead, flip-flop 30, event counter 40 and timer 50 are respec-tively connected to the D0 through D3 output leads of RAM memory device 20. In response to the memory access of RAM device 20, an appropriate 4-bit data word will be read and transmitted via the D0 through D3 lead. Devices which are connected to these output leads will have their respective function enabled if the corresponding lead has a value of logic 1.
If, for example, a logic 1 is present on the D0 output lead, a signal will be transmitted via the HALT lead to the processor. This HALT signal will instruct the processor to stop its current op-eration. If the Dl lead presented at logic 1 value, flip-flop 30 will be set. Flip-flop 30 is connected to AND gate 60 and matcher A is also connected to AND gate 60. AND gate 60 is connected via the EVENT
4 lead as an input to multiplexer 10. Therefore, as a result, the output function of the Dl lead via flip-flop 30 causes another triggering event to access RAM memory 20 as input event 4. When the matcher A signal is true and flip-flop 30 is set, the EVENT
4 signal will be yenerated and transmitted to RAM
memory device 20 to generate one or more other output functions in the same manner as indicated above.
1,2;~i3~
Hardware matchers ~, C and D are respectively con-nected to multiplexer 10 via the EVENT 3, EVENT 2 and EVENT 1 leads.
Event counter 40 is connected as a triggering event via the EVENT 5 lead to multiplexer 10. As a result, the activation of event counter 40 by RAM
memory 20 can trigger the access of another RAM memory word, which may result in another combination of output functions being enabled. Similarly, timer 50 is con-nected to multiplexer 10 as a triggering event via the EVENT 6 lead. Other triggering events such as a system interrupt or an external timer are connected via EVENT leads 7 and 8 respectively to multiplexer 10 and operate to select particular data words o RAM memory 20.
For configuration in which more than four input events or output functions are desired, a plu-rality As shown in Fig. 2, as many as eight input events and the address bus from the processor con-taining eight address leads are connected to 2:1 multi-plexer 21. When the controller load signal indicates that one of the R~M memories 22 or 23 is to be written, address bus A0 through A7 is gated through multiplexer 21 and either RAM 22 or 23 is written. The writing of R~MS 22 and 23 is controlled by the WRITE SEL 1 or WRITE SEL 2 signals from the processor~ That is, the particular WRITE SEL signal which is enabled will determine which particular RAM 22 or 23 is written with the data word to be output via the D0 through D3 leads when that particular address is later selected~
When the controller load signal is in the opposite logic value, the input events are enabled through multiplexer 21. One or both of the ~AMS 22 and 23 may be enabled by the ~ITE SEL signal 1 or
DYNAMIC EVE~T SELECTION NETWORR
BACKGROUND OF THE INVENTION
The present invention pertains to processor systems and more particularly to the use of memory devices to dynamically map one or more of a number of input events to one or more of a number oE output functions automatically.
In processor systems, it is required of the processor that it interact with external stimuli such as sensors, indicators, timers, etc. Each o these stimuli may initiate or may be initiated by the processor to perform some particular function.
Some typical triggering events might include hardware matchers providing an output, counter or timer outputs or interrupt or other logic signals transmitted from or to the processor.
An assignment scheme is required to associate a particular triggering event with a desired func-tional output. This scheme is accomplished with an event routing scheme. Typically, event routing schemes are accomplished with dedicated connections or with multiplexers. Hard-wired connections allow no flex-ibility in altering the results for given input patternO
Such a configuration is very limiting for processor application. Implementing an event selection scheme with multiplexers requires full availability of input events at each multiplexer to select the particular output. This scheme needs many hard-wired connections.
In addition, this scheme requires a dedicated multi-plexer for each output function to be programmed.Having such a large amount of hardware to implement a selection scheme is costly and requires a considerable amount of physical space.
3~
SUMMARY OF_THE_INVENTION
A dynamic event selection network is con-nected between a plurality of input sources, each of which provides triggering signals and a plurality of control devices, each which is operated in response to a control signal. A processor is connected to the selection network and initiates the operation of the network. A dynamic mapping arrangement is connected to the processor, to the input sources and to the control devices. The dynamic mapping arrange-ment operates in response to a set of changeable values of the triggering signals of the input sources to produce a particular set of changeable values of the control signals for transmission to the control devices.
The dynamic mapping arrangement is operated in response to a sele~t signal of the processor to alter each of the many sets oE values of control signals which it contains.
BRIEF DESCRIPTION_OF THE DRAWING
Fig. 1 is a schematic diagram of a dynamic event selection network embodying the principles of operation of the present invention.
FigO 2 is a schematic diagram of an extended ~5 dynamic event selection network.
Fig. 3 is a schematic cliagram of an extended dynamic event selection network~
Fig. 4 is a schematic diagram of a multi-level dynamic event selection network.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to Fig. 1, a trigger routing network which uses a static ~AM device is shown.
The trigger routing network employs a minimum amount of devices and provides complete flexibility to route any of a number of input events to one or more of 3~L6.~3 any output functions. Furthermore, two or more input events may be logically combined to produce two or more output unctions, This scheme provides for a complete mapping of any input event or events to any one or more output function.
Random access memory (RAM) device 20 is a 256 x 4-bit static RAM device~ One such RAM device is capable of providing up to eight input events and mapping them to any or all of four output functions.
Each of the eight input events is termed a triggering event. These triggering events may be output signals from devices such as hardware matchers.
These hardware matchers are devices which are manually or automatically settable to a predetermined value.
This predetermined value is compared with a dynamically changing value presented on an address or a data bus for example. Further examples of these triggering events may be a system interrupt signal, generated by a processor. Processors may generate interrupt signals asynchronously to permit signaling between peripheral devices and the associated processor.
Another type of triggering event is one which is generated by a ~imer signal from a clock.
The clock periodically transmits signals to the trigger routing network in order to enable a certain output function to occur after a particular number of signals have been counted.
Examples of output functions may include, but are not limited to: transmitting a signal to halt a central processing unit; arming a particular flip-flop device 30; incrementing an event counter 40; activating a timer 50 or any ccmbination of the above functions.
A processor, which may take the form of a central processing unit, hard-wired logic or a process ~3~63~3 controller, is connected to 2:1 multiplexer 10. The processor is also connected to multiplexer 10 via a lead called the load signal to select the input to the multiplexer 10. The load signal provides for determining which of the two inputs is gated through multiplexer 10. The address bus connects the pro-cessor to multiplexer 10 and provides for accessing each of the 256 x 4-bit words of RAM memory 20. When the processor wishes to write or change the mapping of the triggering events to the output unctions, it selects an address via the address bus and trans-mits the load signal to multiplexer 10. Multiplexer 10 gates the address bus through to the address inputs (A0 through A7) of RAM memory 20. The processor also signals on the write enable lead to ellect a write access to the ~AM memory 20. RAM memory 20 is then written with a 4-bit data word at the appropriate address contained on the address bus via the DATA
IN bus (D:tO through DI3) connected between the pro-cessor and RA~1 memory 20.
Multiplexer 10 is connected to RAM memory20 via an 8-bit bus connected to the address inputs (A0 through A7~ of RAM memory 20. The second input to multiplexer 10 is another 8-bit bus comprising the triggering events such as address matchers, inter rupt generators or timers, as mentioned above.
When the processor is not writing the RAM
memory 20, the load signal will be such that the triggering event will be gated through multiplexer 10 via the 8-bit bus to the address inputs o RAM
memory 20.
Since multiplexer 10 enables the leads repre-senting the triggering events to be connected to RAM
memory 20 via the address inputs A0 through A7, the occurrence of any triggering event will cause a par-ticular 4-bit word in RAM memory 20 to be accessed.
If the word accessed by the particular address has been pre-set by the processor with a logic 1 in a particular data bit position, the function associated with that data bl~ will be triggered or enabled.
As a result of a particular address being accessed, a 4-bit data word is read from memory and transmitted via the D0 through D3 output leads of RAM memory 20. The processor via the HALT lead, flip-flop 30, event counter 40 and timer 50 are respec-tively connected to the D0 through D3 output leads of RAM memory device 20. In response to the memory access of RAM device 20, an appropriate 4-bit data word will be read and transmitted via the D0 through D3 lead. Devices which are connected to these output leads will have their respective function enabled if the corresponding lead has a value of logic 1.
If, for example, a logic 1 is present on the D0 output lead, a signal will be transmitted via the HALT lead to the processor. This HALT signal will instruct the processor to stop its current op-eration. If the Dl lead presented at logic 1 value, flip-flop 30 will be set. Flip-flop 30 is connected to AND gate 60 and matcher A is also connected to AND gate 60. AND gate 60 is connected via the EVENT
4 lead as an input to multiplexer 10. Therefore, as a result, the output function of the Dl lead via flip-flop 30 causes another triggering event to access RAM memory 20 as input event 4. When the matcher A signal is true and flip-flop 30 is set, the EVENT
4 signal will be yenerated and transmitted to RAM
memory device 20 to generate one or more other output functions in the same manner as indicated above.
1,2;~i3~
Hardware matchers ~, C and D are respectively con-nected to multiplexer 10 via the EVENT 3, EVENT 2 and EVENT 1 leads.
Event counter 40 is connected as a triggering event via the EVENT 5 lead to multiplexer 10. As a result, the activation of event counter 40 by RAM
memory 20 can trigger the access of another RAM memory word, which may result in another combination of output functions being enabled. Similarly, timer 50 is con-nected to multiplexer 10 as a triggering event via the EVENT 6 lead. Other triggering events such as a system interrupt or an external timer are connected via EVENT leads 7 and 8 respectively to multiplexer 10 and operate to select particular data words o RAM memory 20.
For configuration in which more than four input events or output functions are desired, a plu-rality As shown in Fig. 2, as many as eight input events and the address bus from the processor con-taining eight address leads are connected to 2:1 multi-plexer 21. When the controller load signal indicates that one of the R~M memories 22 or 23 is to be written, address bus A0 through A7 is gated through multiplexer 21 and either RAM 22 or 23 is written. The writing of R~MS 22 and 23 is controlled by the WRITE SEL 1 or WRITE SEL 2 signals from the processor~ That is, the particular WRITE SEL signal which is enabled will determine which particular RAM 22 or 23 is written with the data word to be output via the D0 through D3 leads when that particular address is later selected~
When the controller load signal is in the opposite logic value, the input events are enabled through multiplexer 21. One or both of the ~AMS 22 and 23 may be enabled by the ~ITE SEL signal 1 or
2 respectively. The RAM which is enabled will have ~3~
the contents at the address selected by the input events 1 through 8 read out and displayed on th~ D0 through D3 leads. Therefore, for controlling as many as eight output functions, such as output functions A through H shown in Fig. 2, both RAM memories 22 and 23 will be enabled simultaneously and a complete 8-bit data word will be displayed across output function leads A through H.
These output functions may be employed similar to that discussed in supra. to control as many as eight events or to be connected back to the selection network as other input events to trigger the further reading oE other data words within RAMS
22 and 23. In such an arrangement, a total of eight input events and eight output functions may be implemented.
For mapping up to sixteen input events to four output functions, we now turn to Fig. 3. When the controller load signal is at a first logic value, multiplexers 301 and 302 enable writing RAM memories 311 and 312 respectively, via the DATA IN bus as dis-cussed supra. When the controller load signal is in the opposite logic state, multiplexers 301 and 302 enable input events 1 through 8 and 9 through 16, respectively, to be gated through multiplexers 301 and 30~ to RAM memories 311 and 312. The 4-bit data words from each of R~M memory 311 and 312 as addressed by the address presented on ~he input event leads 1 through 16, are read out and transmitted via the D0 through D3 leads of RAM memories 311 and 312.
The D0 through D3 leads of each RAM memory 311 and 312 are respectively connec~ed to OR gates 321 through 324. The output of each OR gate 321 through 324 pro-vides one output function A through D, respectively.
That is~ if the contents of the address read from RAM memory 311 or RAM memory 312 has a 1 in the ~3~63~
corresponding bit position, the related output Eunc-tion will be enabled~ For example, if the D0 lead of RAM memory 311 is at logic 1 and the D0 lead of RAM memory 312 is at logic 0, output function A will be enabled. Similarly, if the logic values of the D0 output leads are reversed from the previous logic values, output function A will be enabled. If however, D0 leads of both RAM memories 311 and 312 are at logic 0, output function A will not be enabled.
Re~erring to Fig. 4, the same figure is shown as in Fig. 3 except that ~R gates 321 through 324 have been replaced by multiplexer 331 and ~AM
memory 332. The operation of this circui~ is similar to that as described in Fig. 3, except for the multi-plexer 331 and RAM 332 replacing OR gates 321-324.
RAM memory 332 is connected to multiplexer 331 and to the processor via the WRITE SEL 3 lead. Multi-plexer 331 is connected to the address bus oE the processor A0 through A7 and the controller load signal of the processor via the controller load signal lead.
Multiplexer 331 is connected via the D0 through D3 outputs to RAM memories 311 and 312. In order for the processor to write RAM memory 332, the WRITE SEL
the contents at the address selected by the input events 1 through 8 read out and displayed on th~ D0 through D3 leads. Therefore, for controlling as many as eight output functions, such as output functions A through H shown in Fig. 2, both RAM memories 22 and 23 will be enabled simultaneously and a complete 8-bit data word will be displayed across output function leads A through H.
These output functions may be employed similar to that discussed in supra. to control as many as eight events or to be connected back to the selection network as other input events to trigger the further reading oE other data words within RAMS
22 and 23. In such an arrangement, a total of eight input events and eight output functions may be implemented.
For mapping up to sixteen input events to four output functions, we now turn to Fig. 3. When the controller load signal is at a first logic value, multiplexers 301 and 302 enable writing RAM memories 311 and 312 respectively, via the DATA IN bus as dis-cussed supra. When the controller load signal is in the opposite logic state, multiplexers 301 and 302 enable input events 1 through 8 and 9 through 16, respectively, to be gated through multiplexers 301 and 30~ to RAM memories 311 and 312. The 4-bit data words from each of R~M memory 311 and 312 as addressed by the address presented on ~he input event leads 1 through 16, are read out and transmitted via the D0 through D3 leads of RAM memories 311 and 312.
The D0 through D3 leads of each RAM memory 311 and 312 are respectively connec~ed to OR gates 321 through 324. The output of each OR gate 321 through 324 pro-vides one output function A through D, respectively.
That is~ if the contents of the address read from RAM memory 311 or RAM memory 312 has a 1 in the ~3~63~
corresponding bit position, the related output Eunc-tion will be enabled~ For example, if the D0 lead of RAM memory 311 is at logic 1 and the D0 lead of RAM memory 312 is at logic 0, output function A will be enabled. Similarly, if the logic values of the D0 output leads are reversed from the previous logic values, output function A will be enabled. If however, D0 leads of both RAM memories 311 and 312 are at logic 0, output function A will not be enabled.
Re~erring to Fig. 4, the same figure is shown as in Fig. 3 except that ~R gates 321 through 324 have been replaced by multiplexer 331 and ~AM
memory 332. The operation of this circui~ is similar to that as described in Fig. 3, except for the multi-plexer 331 and RAM 332 replacing OR gates 321-324.
RAM memory 332 is connected to multiplexer 331 and to the processor via the WRITE SEL 3 lead. Multi-plexer 331 is connected to the address bus oE the processor A0 through A7 and the controller load signal of the processor via the controller load signal lead.
Multiplexer 331 is connected via the D0 through D3 outputs to RAM memories 311 and 312. In order for the processor to write RAM memory 332, the WRITE SEL
3 lead will be set and the controller load signal will in~icate that multiplexer 331 is to enable the address A0 through A7 from the processor to be trans-mitted to R~M memory 332. In addition, the data to be written at that address will be transmitted to ~AM memory 332 via the DATA IN bus. As a result, that particular address within RAM memory 332 will con~ain ~he identity of which output functions A
through ~ are to be enabled for a particular address selection of the A0 through A7 leads of RAM memory 332.
When the controller load signal lead in-dicates that multiplexer 331 is to select as inputs ~ 3 to RAM 33~ the result of input events 1 through 16, the ~0 through D3 leads of RAM memories 311 and 312 now comprise an 8-bit bus which is gated through multiplexer 331 to the A0 through A7 address inputs of RAM memory 332. The functional operation of RAM
332 will be similar to that for ~he RAM devices dis-cussed supra. Therefore, the 8-bit pattern which is represented by the data output leads D0 through D3 of RAM memory 311 and the D0 through D3 output leads of RAM memory 312 will be used subsequently as an address to RAM memory 332 in order to select one or more of output functions A through D. The advantage of this over the Fig. 3 configuration is that full availability of the four output functions A through D is obtained from any or all of the input events 1 through 16. In the Fig. 3 configuration, the outputs of RAM memories 311 and 312 are necessarily ORed in order to provide the four outputs. In Fig.
through ~ are to be enabled for a particular address selection of the A0 through A7 leads of RAM memory 332.
When the controller load signal lead in-dicates that multiplexer 331 is to select as inputs ~ 3 to RAM 33~ the result of input events 1 through 16, the ~0 through D3 leads of RAM memories 311 and 312 now comprise an 8-bit bus which is gated through multiplexer 331 to the A0 through A7 address inputs of RAM memory 332. The functional operation of RAM
332 will be similar to that for ~he RAM devices dis-cussed supra. Therefore, the 8-bit pattern which is represented by the data output leads D0 through D3 of RAM memory 311 and the D0 through D3 output leads of RAM memory 312 will be used subsequently as an address to RAM memory 332 in order to select one or more of output functions A through D. The advantage of this over the Fig. 3 configuration is that full availability of the four output functions A through D is obtained from any or all of the input events 1 through 16. In the Fig. 3 configuration, the outputs of RAM memories 311 and 312 are necessarily ORed in order to provide the four outputs. In Fig.
4, any combination of the D0 through D3 leads of RAM
memories 311 and 312 may provide the output functions A through D. This greatly enhances the flexibility of this dyna~ic event selection network.
Although the preferred embodiment of the invention has been illustrated, and that form described in detail, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims.
memories 311 and 312 may provide the output functions A through D. This greatly enhances the flexibility of this dyna~ic event selection network.
Although the preferred embodiment of the invention has been illustrated, and that form described in detail, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims.
Claims (20)
1. A dynamic event selection network comprising:
a plurality of sources of input events each connected to said selection network providing a triggering signal;
a plurality of control devices each connected to said selection network and operated in response to a control signal;
processor means connected to said selection network;
means for dynamically mapping connected to said processor means, to said sources of input events and to said control devices, said means for dynamically mapping being operated in response to a set of changeable values of said triggering signals of said sources of input events to produce one particu-lar set of a plurality of sets of changeable values of said control signals for transmission to said control devices; and said means for dynamically mapping being operated in response to a select signal of said pro-cessor means to alter each of said plurality of sets of said values of said control signals.
a plurality of sources of input events each connected to said selection network providing a triggering signal;
a plurality of control devices each connected to said selection network and operated in response to a control signal;
processor means connected to said selection network;
means for dynamically mapping connected to said processor means, to said sources of input events and to said control devices, said means for dynamically mapping being operated in response to a set of changeable values of said triggering signals of said sources of input events to produce one particu-lar set of a plurality of sets of changeable values of said control signals for transmission to said control devices; and said means for dynamically mapping being operated in response to a select signal of said pro-cessor means to alter each of said plurality of sets of said values of said control signals.
2. A dynamic event selection network as claimed in claim 1, wherein said means for dynamically mapping includes:
multiplexing means connected to said pro-cessor means and to said sources of input events, said multiplexing means being operated to transmit said triggering signals and being operated to transmit an address of said processor means; and memory means connected to said multiplexing means, to said processor means and to said control devices, said memory means being operated to store each of said plurality of sets of values of said control signals for transmission to said control devices and said memory means being operated to write new sets of values of said control signals to replace each existing set of control signals.
multiplexing means connected to said pro-cessor means and to said sources of input events, said multiplexing means being operated to transmit said triggering signals and being operated to transmit an address of said processor means; and memory means connected to said multiplexing means, to said processor means and to said control devices, said memory means being operated to store each of said plurality of sets of values of said control signals for transmission to said control devices and said memory means being operated to write new sets of values of said control signals to replace each existing set of control signals.
3. A dynamic event selection network as claimed in claim 2, wherein said multiplexing means includes an 8-bit wide 2:1 multiplexer arrangement.
4. A dynamic event selection network as claimed in claim 2, wherein said memory means includes random access memory means providing for the operation of up to four control devices by as many as eight sources of input events.
5. A dynamic event selection network as claimed in claim 2, wherein said multiplexing means includes first multiplexer means connected to said processor means and to said sources of input events.
6. A dynamic event selection network as claimed in claim 5, wherein said memory means includes:
first random access memory means connected to said processor means and to said first multiplexer means; and second random access memory means connected to said processor means and to said first multiplexer means.
first random access memory means connected to said processor means and to said first multiplexer means; and second random access memory means connected to said processor means and to said first multiplexer means.
7. A dynamic event selection network as claimed in claim 6, wherein said first and second random access memory means are each connected to a plurality of control devices and said first and second random access memory means being operated in response to as many as eight sources of input events to control as many as eight control devices.
8. A dynamic event selection network as claimed in claim 2, wherein said multiplexing means includes:
first multiplexer means connected to said processor means and to a first plurality of said sources of input events; and second multiplexer means connected to said processor means and to a second plurality of said sources of input events.
first multiplexer means connected to said processor means and to a first plurality of said sources of input events; and second multiplexer means connected to said processor means and to a second plurality of said sources of input events.
9. A dynamic event selection network as claimed in claim 8, wherein said memory means includes:
first random access memory means connected to said processor means and to said first multiplexer means; and second random access memory means connected to said processor means and to said second multiplexer means.
first random access memory means connected to said processor means and to said first multiplexer means; and second random access memory means connected to said processor means and to said second multiplexer means.
10. A dynamic event selection network as claimed in claim 9, wherein said first and second random access memory means are each connected to a plurality of said control devices and said first and second random access memory means being operated in response to as many as sixteen sources of input events to control as many as four control devices.
11. A dynamic event selection network as claimed in claim 10, wherein there is further included gating means connected to said first and second random access memory means and to said plurality of control devices. -12-
12. A dynamic event selection network as claimed in claim 11, wherein said gating means in-cludes a plurality of OR gating means.
13. A dynamic event selection network as claimed in claim 9, wherein there is further included third multiplexer means connected to said first and second random access memory means and to said pro-cessor means, said third multiplexer means being operated in response to said processor means to trans-mit said control signals of said first and second random access memory means and being operated to transmit an address from said processor means.
14. A dynamic event selection network as claimed in claim 13, wherein there is further included third random access memory means connected to said third multiplexer means and to said processor means, said third random access memory means being operated in response to said control signals of said first and second random access memory means to produce a second set of control signals for transmission to said control devices.
15. A dynamic event selection network as claimed in claim 14, wherein said third random access memory means is connected to said plurality of control devices and said third random access memory means is operated in response to as many as sixteen sources of input events to transmit said second set of control signals to as many as four control devices.
16. A dynamic event selection network as claimed in claim 4, wherein said random access memory means includes a 256 word by 4-bit random access memory device.
17. A dynamic event selection network as claimed in claim 6, wherein said first and second random access memory means each includes a 256 word by 4-bit random access memory device.
18. A dynamic event selection network as claimed in claim 9, wherein said first and second random access memory means each include a 256 word by 4-bit random access memory device.
19. A dynamic event selection network as claimed in claim 15, wherein said third random access memory means includes a 256 word by 4-bit random access memory device.
20. A dynamic event selection network as claimed in claim 13, wherein said third multiplexer means includes an 8-bit wide 2:1 multiplexer arrangement.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US612,535 | 1984-05-21 | ||
| US06/612,535 US4603235A (en) | 1984-05-21 | 1984-05-21 | Dynamic event selection network |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1234638A true CA1234638A (en) | 1988-03-29 |
Family
ID=24453580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000479495A Expired CA1234638A (en) | 1984-05-21 | 1985-04-18 | Dynamic event selection network |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4603235A (en) |
| JP (1) | JPS60258602A (en) |
| BE (1) | BE902455A (en) |
| CA (1) | CA1234638A (en) |
| IT (1) | IT1183625B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4984235A (en) * | 1987-04-27 | 1991-01-08 | Thinking Machines Corporation | Method and apparatus for routing message packets and recording the roofing sequence |
| US4916444A (en) * | 1988-03-25 | 1990-04-10 | King Fred N | Method and apparatus for mapping communications media |
| US7657384B1 (en) * | 2007-03-28 | 2010-02-02 | Environmental Analytics, Inc. | Management of response to triggering events in connection with monitoring fugitive emissions |
| US8751173B1 (en) | 2007-03-28 | 2014-06-10 | LDARtools, Inc. | Management of response to triggering events in connection with monitoring fugitive emissions |
| US8274402B1 (en) | 2008-01-24 | 2012-09-25 | LDARtools, Inc. | Data collection process for optical leak detection |
| US8587319B1 (en) | 2010-10-08 | 2013-11-19 | LDARtools, Inc. | Battery operated flame ionization detector |
| US10488854B1 (en) | 2014-05-20 | 2019-11-26 | InspectionLogic Corporation | Method and determination for fugitive emissions monitoring time |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50982A (en) * | 1973-05-09 | 1975-01-08 | ||
| US4156798A (en) * | 1977-08-29 | 1979-05-29 | Doelz Melvin L | Small packet communication network |
| US4412285A (en) * | 1981-04-01 | 1983-10-25 | Teradata Corporation | Multiprocessor intercommunication system and method |
| US4456954A (en) * | 1981-06-15 | 1984-06-26 | International Business Machines Corporation | Virtual machine system with guest architecture emulation using hardware TLB's for plural level address translations |
| US4475156A (en) * | 1982-09-21 | 1984-10-02 | Xerox Corporation | Virtual machine control |
-
1984
- 1984-05-21 US US06/612,535 patent/US4603235A/en not_active Expired - Fee Related
-
1985
- 1985-04-18 CA CA000479495A patent/CA1234638A/en not_active Expired
- 1985-05-14 IT IT20691/85A patent/IT1183625B/en active
- 1985-05-20 JP JP60106224A patent/JPS60258602A/en active Pending
- 1985-05-20 BE BE2/60689A patent/BE902455A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| IT1183625B (en) | 1987-10-22 |
| BE902455A (en) | 1985-09-16 |
| JPS60258602A (en) | 1985-12-20 |
| IT8520691A0 (en) | 1985-05-14 |
| US4603235A (en) | 1986-07-29 |
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