CA1235228A - Polling method for data processing system - Google Patents
Polling method for data processing systemInfo
- Publication number
- CA1235228A CA1235228A CA000482438A CA482438A CA1235228A CA 1235228 A CA1235228 A CA 1235228A CA 000482438 A CA000482438 A CA 000482438A CA 482438 A CA482438 A CA 482438A CA 1235228 A CA1235228 A CA 1235228A
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- CA
- Canada
- Prior art keywords
- processing unit
- active
- inactive
- polling
- byte
- Prior art date
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- Expired
Links
- 238000012545 processing Methods 0.000 title claims abstract description 82
- 238000000034 method Methods 0.000 title claims abstract description 13
- 230000004044 response Effects 0.000 claims abstract description 19
- 238000004891 communication Methods 0.000 claims description 15
- 230000005540 biological transmission Effects 0.000 claims description 8
- 230000008859 change Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 10
- 239000000872 buffer Substances 0.000 description 9
- 239000010451 perlite Substances 0.000 description 6
- 230000006870 function Effects 0.000 description 4
- 238000012546 transfer Methods 0.000 description 2
- 229910016459 AlB2 Inorganic materials 0.000 description 1
- 102220625993 HMG box transcription factor BBX_D20A_mutation Human genes 0.000 description 1
- 101000693961 Trachemys scripta 68 kDa serum albumin Proteins 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 102220344020 rs114142266 Human genes 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
Abstract
POLLING METHOD FOR DATA PROCESSING SYSTEM
Abstract of the Disclosure A method for polling a plurality of remote processing units includes establishing a table of active and inactive remote processing units, sequen-tially polling each of the active processing units, at the conclusion of polling the active processing units, pollinq an inactive processing unit after which all of the active processing units are again polled. This sequence is repeated until all the active and inactive processing units have been polled. If in polling a processing unit, a response to the poll message indi-cates a change of status of the polled processing unit has occurred, the table is accordingly updated to reflect the current status of the processing unit.
Abstract of the Disclosure A method for polling a plurality of remote processing units includes establishing a table of active and inactive remote processing units, sequen-tially polling each of the active processing units, at the conclusion of polling the active processing units, pollinq an inactive processing unit after which all of the active processing units are again polled. This sequence is repeated until all the active and inactive processing units have been polled. If in polling a processing unit, a response to the poll message indi-cates a change of status of the polled processing unit has occurred, the table is accordingly updated to reflect the current status of the processing unit.
Description
~;~3~X;;~
POLLING MET~OP FQR DATA PRQC~ SY~TE~
~ackground of t~ Invention The present invention is directed to a data processing system which includes a central or master controlled processor and a number of remote processors and, more particularly, it relates to a method and apparatus for polling both active and inactive remote processors as part of the data processing system.
With the cost of microprocessor chips dropping, their use in relatively low-cost data pro-cessing system are increasing. In modern data termi-nal devices, microprocessors are incorporated in keyboards, displays, printers, etc. These devices are associated with the functional operation of the termi-nal device. Terminals are used in some businessenvironments which require that certain of the oper-ating devices such as a printer, keyboard and display may be added to the terminal or removed from the terminal at various times during the day in accordance with business conditions. Prior polling systems such as taught by United States Patent ~o. 3,766,530, No.
3,866,175 and No. 4rO71~908 set up groups of active remote devices which are then polled by the master processor. But if other remote devices are added to the communication network or removed, the polling system is unable to pick up the change in the polling sequence. It is therefore a principal object of this invention to provide a polling sequence which detects the removal or the addition of a remote processing device from the communication network. It i8 a fur-ther object of this invention to provide a high-speed polling sequence of both active and inactive remote processing devices associated with a communication network.
SummarY of the Invention These and other o~jects of the invention are fulfilled by providing a polling sequence in which a table of all the remote processing devices associated with a central processing device is set up for identi-fying each of the remote processing devices as being an active or inactive device. The central processing device will initiate a polling sequence by polling each of the active devices listed in the table. At the conclusion of polling all the active devices, the first inactive device listed on the table is polled after which all the active devices are again polled. At the conclusion of the polling of the active devices, the next inactive device in the table is polled. This sequence is repeated enabling the central processing device to poll all of the active/inactive devices in a very short time. If during the polling sequence, an active device becomes inactive or an inactive device becomes active, the polling of the devices using this polling system allows the central processor to make changes in the poll table at the time that such changes are found so that the polling of the devices will con-tinue in the above-cited se~uence. There is further provided a method for polling during a processing oper-ation a plurality of active and inactive remote proc-essing units interconnected in a communication network with a master processing unit having a memory compris-ing the steps of: a) sequentially transmitting a status message from the master processing unit to each of the remote processing units prior to the start of the proc-essing operation; b) transmitting a response message to the master processing unit from a remote processing unit that is active in response to receiving the status message; c) establishing in the memory a table of first and second bytes of binary signals in accordance with the response received to the status message in which ~Z3S2;~8 - 2a -each first byte of binary signals represents an active remote processing unit that h.as transmitted a response message to the master processing unit and each second byte of binary signals represents an inactive remote processing unit in the communication network that has not transmitted a response message to the master proc-essing unit; d) sequentially transmitting a polling message to each active remote processing unit in the order listed in the table; e~ at the conclusion of transmitting a polling message to the last active re-mote processing unit listed in the table, transmitting a polling message to the first inactive remote process-ing unit listed in the table; f) after transmitting a polling message to the first inactive remote processing unit, repeating step (d); g) at the conclusion of transmitting a polling message to the last active re-mote processing unit listed in the table, transmitting a polling message to the next inactive remote process-ing unit listed in the table; h) repeating steps td), (e), (f) and (g) until all of the active and inactive remote processing units listed in the table have been polled; i) generating first and second time-out periods by the master processing unit at the start of transmit-ting a polling word to an inactive processing unit;
j) storing a third byte of binary signals in the poll table representing the inactive processing unit polled if the inactive unit does not respond within the first time-out period; and k) changing the third byte of binary signals representing the inactive processing unit polled to said first byte of binary signals upon receiving a response message from the inactive processing unit polled to the transmission of the polling word within said second time-out period.
.,, v.
~. , v ~Z35X28 - 2b -Brief Description of the Drawin~
Additional advantages and features of the present invention will become apparent and fully understood from reading the following description, taken in conjunction with the annexed drawings, in which;
Fig. 1 is a schematic diagram of a multi-point data processing system including a central pro-cessor device connected to a plurality of data terminal devices in which the present invention may be used;
.
, 1~35~X~3 Fig. 2 is a schematic diagram of a communication bus of each of the data terminals of Fig. 1 showing the microprocessor device arrangement of the communication controller located therein;
Fig. 3 is a functional block diagram of each of the microprocessor devices found in the data pro-cessing system;
Figs. 4A and 4B taken together disclose a detailed block diagram of the microprocessor device of Fig. 3.
Fig. 5 is a flow chart of the overall polling sequence between the microprocessor device in the controller and the microprocessor devices in the various operating devices of the terminal device;
lS Fig. 6 is a detailed flow chart for the polling sequence step of Fig. 5 in which the active/inactive microprocessor devices are polled;
Fig. 7 is a detailed flow chart for the polling sequence of the last active/inactive micropro-cessor device;
Fig. 8 is a schematic diagram cf thepoll/select message:
Fig. 9 is a schematic diagram of the poll table stored in the RAM memory unit of the controller microprocessor device; and Fig. 10 is a schematic diagram of an address message transmitted between the microprocessor device of the controller and the microprocessor devices of the operating devices of the terminal device.
Detailed ~escription of the Invention Referring to Fig. 1, there is shown a schematic diagram of a typical multi-point data pro-cessing system forming a local area communication network which may include a central processor 20 and a 35 plurality of data terminal devices 22 connected to the processor 20 by a serial communication bus 24 and ~Z35X;~8 a serial sub-system transfer bus 26 on which data is transmitted between the processor 20 and the terminal devices 22 in a manner that is well known in the art. As shown in Fig. 2, the data appearing on the serial buses 24 and 26 are inputted into a communication interface unit or controller 28 in each of the terminal devices 22. Included in the controller 28 are a pair of microproces-sor devices 30, 32 interconnected by a serial communication bus 34. For a com-plete description of the communication network of the controller 28, reference should be made to the copending Canadian patent application "High Speed Data Transmission System" by Houser et al., Serial No. 482,435, filed on May 27~
1985 and assigned to the NCR Corporation. As is well known in the art, the controller 28 functions to control the transmission of data between the central processor 20 and the various remote operating devices associated with the ter-minal device 22 such as a printer 36, a keyboard 38, a CRT display 40, and a UPC scanner 42. Associated with each of the operating devices is a micropro-cessor device 44 which functions in the same manner as microprocessors 30 and 32. The microprocessor device 30 controls the transmission of data between the controller 28 and the central processor 20 (Fig. 1), while the microproces-sor device 32 controls the transmission of data over the serial bus 46 between the controller 28 and the microprocessor devices 44 associated with each of the operating devices 36-42 inclusive. The microprocessor devices 30, 32 and 44 referred to herein may comprise an Intel 8n51 microprocessor chlp which is commercially available from the Intel Corporation of Santa Clara, California.
A description of the Intel 8051 microprocessor chip may be found in the publi-cation "MCS-51 Family of Single Chip Microcomputer User's Manual" published by the Intel Corporation in July, 1981. "Intel" is a trademark owned by the lntel Corporation.
l.Z35228 t Referring now to Fig. 3, there is disclosed a functional block diagram of the microprocessor devic-es 30~ 32 and 44. Included in each of the micropro-cessor devices is a central processing unit (CPU) 50 which is operated by clock signals from an oscillator and timing circuit 52 which in turn receives a refer-ence frequency signal from an external clock (not shown). The processing unit 50 has access over data ~us 54 to a 4,096 byte program memory block 56, a 128 byte RAM memory block 58, a two 16 bit timer/event counter block 60, a 64R byte bus expansion control block 62, a programmable I/O control block 64 and a programmable serial port block 66 for either micropro-cessor communications or I/O expansion.
Referring now to Figs. 4A and 4B taken together, there is shown a detailed block diagram of the microprocessor devices 30, 32 and 44. Included in each of the microprocessor devices is a 4R x 8 ROM
memory unit 70 (Fig. 4B) for program storage, which may be internal or external to the microprocessor devices 30, 32 or 44, a 128 byte internal RAM memory unit generally indicated by the numeral 58 (Fig. 4A) which includes a general purpose register 73, four banks of eight 8-bit registers 74 and a plurality of special function registers 76. Included in the spe-cial function registers 76 (Fig. 4A) is an accumulator (ACC) 78, an 8-bit stack pointer register (SP) 80, a high-order data pointer (DPH) 82, a low-order data pointer ~DPL) 84, a timer/counter mode register (TMOD) 86 in which are stored the data bits that select which operation each timer/counter will perform, four timer/counter registers (THI) 88, (THO) 90, (TLI) 92 and (TLO) 94, and a timer/control register (TCON) 96 for controlling the operation of the timer/counter registers 88-94 inclusive. Further included in the microprocessor device is a program control section 98 (Fig. 4B) which controls the sequence in which the ~Z 3S Zz 8 t instructions of the program stored in the ROM 70 are executed and an arithmetic/logic unit 102 (Fig. 4A) for performing arithmetic operation in a manner that is well known in the art. The microprocessor device includes four ports in which port zero 104 (Fig. 4A) is used for data transfer and port three 100 contains the transmit/receive lines connected between the microprocessor device 32 in the controller 28 and the remote microprocessor devices 44 associated with the operating devices of the terminal device 22.
Referring now to Fig. 5, there is disclosed a flow chart of a polling sequence between the micro-processor device 32 (Fig. 2) and the microprocessor devices 44 each associated with one of the remote operating devices 36-42 inclusive. Prior to the start of a polling sequence, the microprocessor device 32 will have transmitted a status or configuration mes-sage to each of the microprocessor devices 44 associ-ated with the devices 36-42 inclusive (Fig. 2). This occurs at power-up or when the system is reset. If a microprocessor device 44 is active, that is, is pre-sent and in an operating mode, the microprocessor device 32 will establish a poll table 106 (Fig. 9) in the RAM general purpose register 73 (Fig. 4A) in which the binary bits FE are stored at an address of a microprocessor device 44 which is present and active.
If a device is inactive, the binary bits 00 are stored.
If the microprocessor device 32 attempts to poll but fails to communicate with a microprocessor device 44, the binary bits FF are stored in the table.
The microprocessor device 32 will again try to poll the device. If after two failures in a row to reach the device, the binary bits 00 are stored in the table 106. lf a polled microprocessor device 44 responds after the first re-try operation, the binary bits FE
are stored in the table. After establishing the i ~ 235;~Z8 table 106, the microprocessor device 32 will check (block 108) (Fig. 5) for a select buffer (not shown3 to see if any data has been received from the central processor 20 which is to be transmitted to an active microprocessor device 44 listed in the table 106. The select buffer is located in an external RAM memory unit connected to the microprocessor device 32. If the buffer contains data, the program stored in the ROM memory unit 70 (Fig. 4B) will send (block 110) a select message 115 ~Fig. 8) to see if the microproces-sor device 44 is available to receive a message. The construction of the message 115 ~Fig. 8) is the same for either a poll or select message with the code 02 representing a poll message and 04 representing a select message. The program will check (block 116) if the device is busy in accordance with the response message received from the polled device. If the polled microprocessor device 44 is busy, the program will again check the select buffers to see if there is any data to be transmitted to a listed active device.
If the device is not busy, the microprocessor device 32 will send a data message 112 (Fig. 10) to the microprocessor device 44 (block 118) which includes a four byte message identification field 114 and at least one byte data field 117, free the select buffer to receive further data from the remote processor 20 and check to see if further data has been received and stored in the select buffer.
If no further data has been received from the control processor 20, the program will start polling the microprocessor devices 44 by going to the poll table 106 (Fig. 9) and retrieve (block 120) (Figs. 5 and 6) the poll address of the first microprocessor device 44 listed in the table. The program will check (block 122) (Fig. 6) to see if the device is an active device. If it is, the program will exit (block 124) (Fig. 6) this sequence and send (block 126) (Fig. 5~
~L2352Z8 the poll message 115 (Fig. 8) to the active device asking if the device has any data to be sent to the remote processor 20. If at the time of polling, the polled device has no data to send to the remote pro-cessor 20 (Fig. 1) indicated by transmitting an idlemessage (block 128) to the microprocessor device 32 (Fig. 5), the program will loop back and again start the polling sequence by checking (block 108) to see if there is a select buffer containing data to be trans-mitted to one of the active devices.
If the microprocessor device 32 receives amessage for the central processor 20 in response to its poll message, the program will transmit (block 130) (Fig. 5~ the received message from the active device to the central processor 20 and again check (block 108) to see if there is a select buffer pre-sent. The program will continue polling the active devices (block 122) (Fig. 6) until the pointer in one of the registers 74 in the RAM memory unit 58 (Fig.
4A) points to a device address in the general purpose register 73 which is not active. The program will check (block 136) (Fig. 6) to see if it is the last active device listed in the poll table 106 (Fig. 9).
If it is not, the program will get the next active device address (block 120) in the poll table. If the device is the last active device in the poll table 106, the program will poll (block 138) the address of the next inactive device after polling the last active device.
In polling an inactive microprocessor device, the program will start (block 140) (Fig. 7) by sending the poll message 115 (Fig. 8) (block 142) and start (block 144) a 256 msec timer (not shown). The program will then check for a response (block 146) to the poll message. If it fails to get a response before the 256 msec timer times out, it will check (block 148) if the time out is the first time out. If it is the first time out, it will repeat sending the poll message (block 142). If no response is received before the second time out, the program will check (block 150) to see if the polled device is an active device. If it is not, it will exit (block 152) back into ~he polling sequence. If the device is an active device, the program will update the poll table 106 (Fig. 9) by replacing the code designation FE with ~0. If the polled device responds (block 146) within the first or second time out, the program will check the identity of the device (block 156). If it is an active device, it will exit (block 152) back into the polling se-quence. If it is an inactive device, it will update the poll table 106 by replacing the code designation 00 with FE. Upon returning to the polling sequence, the program will check (block 158) (Fig. 6) to see if it is at the end of the poll table. If it is not, it will repeat the polling sequence of the active devices (Figs. 5 and 6).
When the program reaches the end of the poll table 106 after polling the last inactive microproces-sor device 44, it will start a timing sequence in sounters 88 through 92 (Fig. 4A) inclusive to produce a 15 millisecond time-out. This time period allows the active operating devices of the terminal device 22 such as a keyboard to complete its operating cycle which may produce data required for transmission to the remote processor 20. After checking (block 160) (Fig. 6) for the presence of a time-out, and finding that a time-out has occurred, the program will restart the timer (block 162) and start again polling the table 106 of active devices and the next inactive device. This process will continue until all of the active and inactive microprocessor devices 44 have been polled.
The following comprises a detailed program listing for the polling sequence shown in Figs. 5, 6 ~235Z28 and 7. The actual machine codes and instructions shown relate to the Intel 8051 microprocessor chip in the embodiment described, however the techniques employed herein may be extended to other processors.
Definition ~f the various machine codes and instruc-tions may be obtained from, for example, the publica-tion entitled "8051 User Manual," which was published by Intel Corporation in 1982.
LOCA-~IQ~ OB~ECT 11~ SOURCE
300 POLL_LOOP:
0082 758DC5 301 MOV THl,~0C5H
0085 758B68 302 MOV TLl,~Q68H
0088 D20A 303 SETB POLL_TIME
306 WAIT_NR:
659 CT6:
02D7 201405 660 JB POLL_TOG,CT7 02DA D214 661 SETB POLL_TOG
02DC 02048C 662 JMP SEL_CHECR
663 CT7:
02DF 020584 664 JMP POL_CHECR
1106 ; POLL 10E FOR INPUT
1108 POL_CHECR:
0584 753205 1109 MOV STAT_TYPE, ~POL_STAT
0587 12081A 1110 CALL STAT_CR
058C 12082A ~112 CALL GET_BUFF
058F 7005 1113 JNZ PCO_5 0591 D215 1114 SETB POLL_ZERO
0593 0205A5 1115 JMP PCO_l 1116 PCO_5:
0596 7605 1117 MOV ~RO,~POL_STAT
0598 F537 1118 MOVI POL_~T,A
1119 PCO:
059A 300F08 1120 JNB DIAG_REQ_FLG, PCO_l 059D D20D 1121 SETB DIAG_IN_PRG
059F 85302E 1122 MOV UA,DIAG_tA
05A2 0205AE 1123 JMP PC_l 1124 PCO_l:
05A5 12086Bt 1125 CALL GET_POLL_ID
05A8 7004 1126 JNZ PC_l 05AA D214 1127 SETB POLL_TOG
05AC 41A2 1128 JMP START_CK
1129 PC_l:
005AE C207 1130 CLR IDL_FLAG
05B0 C200 1131 CLR SECOND_TRY
1132 SEND_POLL:
05B2 D206 1133 SETB POL_IN_PRG
05B4 C207 1134 CLR IDL_F1AG
C5B6 C201 1135 CLR IDL_LINE
05B8 C204 1136 CLR NO_RESP
05BA C202 1137 CLR BCC_ERR
05BC C209 1138 CLR MSG_IN
05BE 1205C5 1139 CALL POLL_SETUP
05C1 41A2 1140 JMP START_CX
1142 WAIT_NR_JMPl:
C5C3 018B 1143 JMP WAIT_NR
1145 POLL_SETUP:
05C9 75D018 1148 MOV PSW,~18H
05CC C582 1149 XCH A,DPL
05CE C8 1150 XCH A,R3 ~LZ3~Z8 05CF C583 1151 XCH A,DPH
05Dl CC 1152 XCH A,R4 05D2 7452 1153 MOV A,$STACK2 05D4 C581 1154 XCH A,SP
05D6 CD 1155 XCH A,R5 05DC 10150A 1159 JBC POLL_ZERO, PS_O
05E1 853783 1161 MOV DPH,POL_PT
05E4 758200 1162 MOV DPL,~00 05E7 BUFFER 1163 MOVX @DPTR,A
1165 PS_O:
05E9 20D002 1166 JB P,POLL_RO
05EC D2E7 1167 SETB ACC.7 1168 POLL_RO-05F0 F599 1170 MOV SBUF,A
05F2 1140 1171 CALL SETUP_EXIT
05F8 300F06 1174 JNB DIAG_REQ_FLG, POL_RO_l 05FB 759915 1175 MOV SBUF,#DIAG
05FE 020604 1176 JMP POL_RO_2 1177 POL_RO_l:
0601 759902 1178 MOV SBUF,~POL
1179 POL_RO_2:
0604 1133 1180 CALL SER_EXIT
060C 758A00 1184 MOV TL0,~00 060F 758C0 1185 MOV T~0,$01 0612 75419F 1186 MOV TOUT_LOW,~LOW
~235~28 POL_NR
0615 754006 1187 MOV TOVT_HIGH, ~HIGH POL_NR
061A 1133 1189 CALL SER_EXIT
061E 758A00 1191 MOV TLO,#00 0623 E599 1193 MOV A,SBUF
0625 B43DOA 1194 CJNE A,~IDL,POL_Rl 062A F0 1196 MOVX @DPTR,A
062C D209 1198 SETB MSO_IN
062E 1133 1199 CALL SER_EXIT
0630 llA7 1200 CALL ERROR_INT
12 n 1 POL_Rl:
0632 F0 1202 MOVX @DPTR,A
063t 1133 1204 CALL SER_EXIT
063~ 758A00 1206 MOV TL0,~00 063D E599 1208 MOV A,S8UF
063F FE 1209 MOV R6,A
0640 F0 1210 MOVX @DPTR,A
0642 F542 1212 MOV SUMCK,A
0644 1133 1213 CALL SER_EXIT
0648 758A00 1215 MOV TL0,~00 064D E599 1217 MOV A,SBUF
064F FF 1218 MOV R7,A
0650 F0 1219 MOVX ~DPTR,A
0652 2542 1221 ADD A,S~MCR
- 14 - ~Z352~8 0654 F542 1222 MOV SUMCK,A
1223 POL_R4:
0656 1133 1224 CALL SER_EXIT
065A 758A00 1226 MOV TLO;~00 065D C28D 1227 CLR tFO
065F E599 1228 MOV A,SBUF
0661 2542 1229 ADD A,SUMCR
0663 F542 1230 MOV S~MCR,A
0665 E599 1231 MOV A,SB~F
0667 FO 1232 MOVX @DPTR,A
066g E582 1234 MOV A,DPL
066B 7006 1235 JNZ POL_R5 0671 D203 1238 SETB BUFF_FULL
1239 POL_R5:
0673 DFEl 1240 DJNZ R7,POL_R4 0675 1133 1241 CALL SER_EXIT
067D E599 1245 MOV A,SBUF
067F F0 1246 MOVX @DPTR,A
0680 2542 1247 ADD A,SUMCK
0682 6004 1248 JZ POL_R7 0684 D202 1249 SETB BCC_ERR
0686 018B 1250 JMP WAIT_ NR
1252 POL_R7:
068C 75990E 1255 MOV SBUF,tACR
068F 1133 1256 CALL SER_EXIT
- 15 - lZ352Z8 0695 D297 125!3 SETB TEN
0697 D29C 1?60 SETB REN
0699 D209 1261 SETB MSG_IN
069B 1133 1262 CALL SER_EXIT
069D llA7 1263 CALL ERROR_INT
1266 POL_NR:
069F D204 1267 SETB NO_RESP
06Al D209 1268 SETB MSG_IN
06A3 C28C 1269 CLR TE~O
06A5 1133 1270 CALL SER_EXIT
06A7 llA7 1271 CALL ERROR_INT
1272 $EJECT
1284 CR_POLL_CMP:
06A9 200C02 1285 JB POL_IN_PRG, CPC_l 06AC 41A2 1286 JMP START_CK
1287 CPC_l:
06AE 200123 1288 JB IDL_LINE, POLL_E RR
06B1 200420 1289 JB NO_RESP, POLL_ERR
06B4 20021D 1290 JB BCC_ERR, POLL_E RR
1291 POLL_GOOD:
06B7 1208BD 1292 CALL UA_TO_POL
06BA 853783 1293 MOV DPH,POL_PT
3n 06BD 758201 1294 MOV DPL,~01 06C0 E0 129S MOVX A,QDPTR
06Cl B43DOD 1296 CJNE A,~IDL, P_M SG_1 06C4 30051A 1297 JNB NEW_UA, POLL_EX I T
06CC 1209E9 1300 CALL CNF_SETUP
06CF 41A2 1301 JMP START_CR
- 16 _ ~352~8 1302 P_MSG_l:
06D1 0206FO 1303 JMP POLL_PROCESS
1305 POLL_ER~:
06D4 200004 1306 JB S~COND_TRY, P_ERRl 06D9 AlB2 1308 JMP SEND_POLL
1309 P_ERRl:
06DB 2Q0503 1310 JB NEW_UA, POLL_EXIT
06DE 120809 1311 CALL UA_ERR
1312 POLL_EXIT.
06E1 300D04 1313 JNB DIAG_IN_PRG, 1 5 P_EX_1 06E4 C20D 1314 CLR DIAG_IN_PRG
06E6 C20F 1315 CLR DIAG_REQ_FLG
1316 P_EX_l:
06E8 D207 1317 SETB IDL_FLAG
06EA C20C 1318 CLR POL_IN_PRG
06EC C205 1319 CLR NEW_UA
06EE 41A2 1320 JMP START_CK
1321 ~EJECT
While the invention has been described in detail and with reference to specific embodiments thereof, it will be understood by those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention. For example, the RAM memory unit 58 (Fig. 4A) and the ROM memory unit 70 (Fig. 4B) may be either internal or external or both to the micropro-cessor devices 30, 32 or 44. Therefore, it is to be understood that the present invention is not to be limited beyond that as required by the appended claims.
POLLING MET~OP FQR DATA PRQC~ SY~TE~
~ackground of t~ Invention The present invention is directed to a data processing system which includes a central or master controlled processor and a number of remote processors and, more particularly, it relates to a method and apparatus for polling both active and inactive remote processors as part of the data processing system.
With the cost of microprocessor chips dropping, their use in relatively low-cost data pro-cessing system are increasing. In modern data termi-nal devices, microprocessors are incorporated in keyboards, displays, printers, etc. These devices are associated with the functional operation of the termi-nal device. Terminals are used in some businessenvironments which require that certain of the oper-ating devices such as a printer, keyboard and display may be added to the terminal or removed from the terminal at various times during the day in accordance with business conditions. Prior polling systems such as taught by United States Patent ~o. 3,766,530, No.
3,866,175 and No. 4rO71~908 set up groups of active remote devices which are then polled by the master processor. But if other remote devices are added to the communication network or removed, the polling system is unable to pick up the change in the polling sequence. It is therefore a principal object of this invention to provide a polling sequence which detects the removal or the addition of a remote processing device from the communication network. It i8 a fur-ther object of this invention to provide a high-speed polling sequence of both active and inactive remote processing devices associated with a communication network.
SummarY of the Invention These and other o~jects of the invention are fulfilled by providing a polling sequence in which a table of all the remote processing devices associated with a central processing device is set up for identi-fying each of the remote processing devices as being an active or inactive device. The central processing device will initiate a polling sequence by polling each of the active devices listed in the table. At the conclusion of polling all the active devices, the first inactive device listed on the table is polled after which all the active devices are again polled. At the conclusion of the polling of the active devices, the next inactive device in the table is polled. This sequence is repeated enabling the central processing device to poll all of the active/inactive devices in a very short time. If during the polling sequence, an active device becomes inactive or an inactive device becomes active, the polling of the devices using this polling system allows the central processor to make changes in the poll table at the time that such changes are found so that the polling of the devices will con-tinue in the above-cited se~uence. There is further provided a method for polling during a processing oper-ation a plurality of active and inactive remote proc-essing units interconnected in a communication network with a master processing unit having a memory compris-ing the steps of: a) sequentially transmitting a status message from the master processing unit to each of the remote processing units prior to the start of the proc-essing operation; b) transmitting a response message to the master processing unit from a remote processing unit that is active in response to receiving the status message; c) establishing in the memory a table of first and second bytes of binary signals in accordance with the response received to the status message in which ~Z3S2;~8 - 2a -each first byte of binary signals represents an active remote processing unit that h.as transmitted a response message to the master processing unit and each second byte of binary signals represents an inactive remote processing unit in the communication network that has not transmitted a response message to the master proc-essing unit; d) sequentially transmitting a polling message to each active remote processing unit in the order listed in the table; e~ at the conclusion of transmitting a polling message to the last active re-mote processing unit listed in the table, transmitting a polling message to the first inactive remote process-ing unit listed in the table; f) after transmitting a polling message to the first inactive remote processing unit, repeating step (d); g) at the conclusion of transmitting a polling message to the last active re-mote processing unit listed in the table, transmitting a polling message to the next inactive remote process-ing unit listed in the table; h) repeating steps td), (e), (f) and (g) until all of the active and inactive remote processing units listed in the table have been polled; i) generating first and second time-out periods by the master processing unit at the start of transmit-ting a polling word to an inactive processing unit;
j) storing a third byte of binary signals in the poll table representing the inactive processing unit polled if the inactive unit does not respond within the first time-out period; and k) changing the third byte of binary signals representing the inactive processing unit polled to said first byte of binary signals upon receiving a response message from the inactive processing unit polled to the transmission of the polling word within said second time-out period.
.,, v.
~. , v ~Z35X28 - 2b -Brief Description of the Drawin~
Additional advantages and features of the present invention will become apparent and fully understood from reading the following description, taken in conjunction with the annexed drawings, in which;
Fig. 1 is a schematic diagram of a multi-point data processing system including a central pro-cessor device connected to a plurality of data terminal devices in which the present invention may be used;
.
, 1~35~X~3 Fig. 2 is a schematic diagram of a communication bus of each of the data terminals of Fig. 1 showing the microprocessor device arrangement of the communication controller located therein;
Fig. 3 is a functional block diagram of each of the microprocessor devices found in the data pro-cessing system;
Figs. 4A and 4B taken together disclose a detailed block diagram of the microprocessor device of Fig. 3.
Fig. 5 is a flow chart of the overall polling sequence between the microprocessor device in the controller and the microprocessor devices in the various operating devices of the terminal device;
lS Fig. 6 is a detailed flow chart for the polling sequence step of Fig. 5 in which the active/inactive microprocessor devices are polled;
Fig. 7 is a detailed flow chart for the polling sequence of the last active/inactive micropro-cessor device;
Fig. 8 is a schematic diagram cf thepoll/select message:
Fig. 9 is a schematic diagram of the poll table stored in the RAM memory unit of the controller microprocessor device; and Fig. 10 is a schematic diagram of an address message transmitted between the microprocessor device of the controller and the microprocessor devices of the operating devices of the terminal device.
Detailed ~escription of the Invention Referring to Fig. 1, there is shown a schematic diagram of a typical multi-point data pro-cessing system forming a local area communication network which may include a central processor 20 and a 35 plurality of data terminal devices 22 connected to the processor 20 by a serial communication bus 24 and ~Z35X;~8 a serial sub-system transfer bus 26 on which data is transmitted between the processor 20 and the terminal devices 22 in a manner that is well known in the art. As shown in Fig. 2, the data appearing on the serial buses 24 and 26 are inputted into a communication interface unit or controller 28 in each of the terminal devices 22. Included in the controller 28 are a pair of microproces-sor devices 30, 32 interconnected by a serial communication bus 34. For a com-plete description of the communication network of the controller 28, reference should be made to the copending Canadian patent application "High Speed Data Transmission System" by Houser et al., Serial No. 482,435, filed on May 27~
1985 and assigned to the NCR Corporation. As is well known in the art, the controller 28 functions to control the transmission of data between the central processor 20 and the various remote operating devices associated with the ter-minal device 22 such as a printer 36, a keyboard 38, a CRT display 40, and a UPC scanner 42. Associated with each of the operating devices is a micropro-cessor device 44 which functions in the same manner as microprocessors 30 and 32. The microprocessor device 30 controls the transmission of data between the controller 28 and the central processor 20 (Fig. 1), while the microproces-sor device 32 controls the transmission of data over the serial bus 46 between the controller 28 and the microprocessor devices 44 associated with each of the operating devices 36-42 inclusive. The microprocessor devices 30, 32 and 44 referred to herein may comprise an Intel 8n51 microprocessor chlp which is commercially available from the Intel Corporation of Santa Clara, California.
A description of the Intel 8051 microprocessor chip may be found in the publi-cation "MCS-51 Family of Single Chip Microcomputer User's Manual" published by the Intel Corporation in July, 1981. "Intel" is a trademark owned by the lntel Corporation.
l.Z35228 t Referring now to Fig. 3, there is disclosed a functional block diagram of the microprocessor devic-es 30~ 32 and 44. Included in each of the micropro-cessor devices is a central processing unit (CPU) 50 which is operated by clock signals from an oscillator and timing circuit 52 which in turn receives a refer-ence frequency signal from an external clock (not shown). The processing unit 50 has access over data ~us 54 to a 4,096 byte program memory block 56, a 128 byte RAM memory block 58, a two 16 bit timer/event counter block 60, a 64R byte bus expansion control block 62, a programmable I/O control block 64 and a programmable serial port block 66 for either micropro-cessor communications or I/O expansion.
Referring now to Figs. 4A and 4B taken together, there is shown a detailed block diagram of the microprocessor devices 30, 32 and 44. Included in each of the microprocessor devices is a 4R x 8 ROM
memory unit 70 (Fig. 4B) for program storage, which may be internal or external to the microprocessor devices 30, 32 or 44, a 128 byte internal RAM memory unit generally indicated by the numeral 58 (Fig. 4A) which includes a general purpose register 73, four banks of eight 8-bit registers 74 and a plurality of special function registers 76. Included in the spe-cial function registers 76 (Fig. 4A) is an accumulator (ACC) 78, an 8-bit stack pointer register (SP) 80, a high-order data pointer (DPH) 82, a low-order data pointer ~DPL) 84, a timer/counter mode register (TMOD) 86 in which are stored the data bits that select which operation each timer/counter will perform, four timer/counter registers (THI) 88, (THO) 90, (TLI) 92 and (TLO) 94, and a timer/control register (TCON) 96 for controlling the operation of the timer/counter registers 88-94 inclusive. Further included in the microprocessor device is a program control section 98 (Fig. 4B) which controls the sequence in which the ~Z 3S Zz 8 t instructions of the program stored in the ROM 70 are executed and an arithmetic/logic unit 102 (Fig. 4A) for performing arithmetic operation in a manner that is well known in the art. The microprocessor device includes four ports in which port zero 104 (Fig. 4A) is used for data transfer and port three 100 contains the transmit/receive lines connected between the microprocessor device 32 in the controller 28 and the remote microprocessor devices 44 associated with the operating devices of the terminal device 22.
Referring now to Fig. 5, there is disclosed a flow chart of a polling sequence between the micro-processor device 32 (Fig. 2) and the microprocessor devices 44 each associated with one of the remote operating devices 36-42 inclusive. Prior to the start of a polling sequence, the microprocessor device 32 will have transmitted a status or configuration mes-sage to each of the microprocessor devices 44 associ-ated with the devices 36-42 inclusive (Fig. 2). This occurs at power-up or when the system is reset. If a microprocessor device 44 is active, that is, is pre-sent and in an operating mode, the microprocessor device 32 will establish a poll table 106 (Fig. 9) in the RAM general purpose register 73 (Fig. 4A) in which the binary bits FE are stored at an address of a microprocessor device 44 which is present and active.
If a device is inactive, the binary bits 00 are stored.
If the microprocessor device 32 attempts to poll but fails to communicate with a microprocessor device 44, the binary bits FF are stored in the table.
The microprocessor device 32 will again try to poll the device. If after two failures in a row to reach the device, the binary bits 00 are stored in the table 106. lf a polled microprocessor device 44 responds after the first re-try operation, the binary bits FE
are stored in the table. After establishing the i ~ 235;~Z8 table 106, the microprocessor device 32 will check (block 108) (Fig. 5) for a select buffer (not shown3 to see if any data has been received from the central processor 20 which is to be transmitted to an active microprocessor device 44 listed in the table 106. The select buffer is located in an external RAM memory unit connected to the microprocessor device 32. If the buffer contains data, the program stored in the ROM memory unit 70 (Fig. 4B) will send (block 110) a select message 115 ~Fig. 8) to see if the microproces-sor device 44 is available to receive a message. The construction of the message 115 ~Fig. 8) is the same for either a poll or select message with the code 02 representing a poll message and 04 representing a select message. The program will check (block 116) if the device is busy in accordance with the response message received from the polled device. If the polled microprocessor device 44 is busy, the program will again check the select buffers to see if there is any data to be transmitted to a listed active device.
If the device is not busy, the microprocessor device 32 will send a data message 112 (Fig. 10) to the microprocessor device 44 (block 118) which includes a four byte message identification field 114 and at least one byte data field 117, free the select buffer to receive further data from the remote processor 20 and check to see if further data has been received and stored in the select buffer.
If no further data has been received from the control processor 20, the program will start polling the microprocessor devices 44 by going to the poll table 106 (Fig. 9) and retrieve (block 120) (Figs. 5 and 6) the poll address of the first microprocessor device 44 listed in the table. The program will check (block 122) (Fig. 6) to see if the device is an active device. If it is, the program will exit (block 124) (Fig. 6) this sequence and send (block 126) (Fig. 5~
~L2352Z8 the poll message 115 (Fig. 8) to the active device asking if the device has any data to be sent to the remote processor 20. If at the time of polling, the polled device has no data to send to the remote pro-cessor 20 (Fig. 1) indicated by transmitting an idlemessage (block 128) to the microprocessor device 32 (Fig. 5), the program will loop back and again start the polling sequence by checking (block 108) to see if there is a select buffer containing data to be trans-mitted to one of the active devices.
If the microprocessor device 32 receives amessage for the central processor 20 in response to its poll message, the program will transmit (block 130) (Fig. 5~ the received message from the active device to the central processor 20 and again check (block 108) to see if there is a select buffer pre-sent. The program will continue polling the active devices (block 122) (Fig. 6) until the pointer in one of the registers 74 in the RAM memory unit 58 (Fig.
4A) points to a device address in the general purpose register 73 which is not active. The program will check (block 136) (Fig. 6) to see if it is the last active device listed in the poll table 106 (Fig. 9).
If it is not, the program will get the next active device address (block 120) in the poll table. If the device is the last active device in the poll table 106, the program will poll (block 138) the address of the next inactive device after polling the last active device.
In polling an inactive microprocessor device, the program will start (block 140) (Fig. 7) by sending the poll message 115 (Fig. 8) (block 142) and start (block 144) a 256 msec timer (not shown). The program will then check for a response (block 146) to the poll message. If it fails to get a response before the 256 msec timer times out, it will check (block 148) if the time out is the first time out. If it is the first time out, it will repeat sending the poll message (block 142). If no response is received before the second time out, the program will check (block 150) to see if the polled device is an active device. If it is not, it will exit (block 152) back into ~he polling sequence. If the device is an active device, the program will update the poll table 106 (Fig. 9) by replacing the code designation FE with ~0. If the polled device responds (block 146) within the first or second time out, the program will check the identity of the device (block 156). If it is an active device, it will exit (block 152) back into the polling se-quence. If it is an inactive device, it will update the poll table 106 by replacing the code designation 00 with FE. Upon returning to the polling sequence, the program will check (block 158) (Fig. 6) to see if it is at the end of the poll table. If it is not, it will repeat the polling sequence of the active devices (Figs. 5 and 6).
When the program reaches the end of the poll table 106 after polling the last inactive microproces-sor device 44, it will start a timing sequence in sounters 88 through 92 (Fig. 4A) inclusive to produce a 15 millisecond time-out. This time period allows the active operating devices of the terminal device 22 such as a keyboard to complete its operating cycle which may produce data required for transmission to the remote processor 20. After checking (block 160) (Fig. 6) for the presence of a time-out, and finding that a time-out has occurred, the program will restart the timer (block 162) and start again polling the table 106 of active devices and the next inactive device. This process will continue until all of the active and inactive microprocessor devices 44 have been polled.
The following comprises a detailed program listing for the polling sequence shown in Figs. 5, 6 ~235Z28 and 7. The actual machine codes and instructions shown relate to the Intel 8051 microprocessor chip in the embodiment described, however the techniques employed herein may be extended to other processors.
Definition ~f the various machine codes and instruc-tions may be obtained from, for example, the publica-tion entitled "8051 User Manual," which was published by Intel Corporation in 1982.
LOCA-~IQ~ OB~ECT 11~ SOURCE
300 POLL_LOOP:
0082 758DC5 301 MOV THl,~0C5H
0085 758B68 302 MOV TLl,~Q68H
0088 D20A 303 SETB POLL_TIME
306 WAIT_NR:
659 CT6:
02D7 201405 660 JB POLL_TOG,CT7 02DA D214 661 SETB POLL_TOG
02DC 02048C 662 JMP SEL_CHECR
663 CT7:
02DF 020584 664 JMP POL_CHECR
1106 ; POLL 10E FOR INPUT
1108 POL_CHECR:
0584 753205 1109 MOV STAT_TYPE, ~POL_STAT
0587 12081A 1110 CALL STAT_CR
058C 12082A ~112 CALL GET_BUFF
058F 7005 1113 JNZ PCO_5 0591 D215 1114 SETB POLL_ZERO
0593 0205A5 1115 JMP PCO_l 1116 PCO_5:
0596 7605 1117 MOV ~RO,~POL_STAT
0598 F537 1118 MOVI POL_~T,A
1119 PCO:
059A 300F08 1120 JNB DIAG_REQ_FLG, PCO_l 059D D20D 1121 SETB DIAG_IN_PRG
059F 85302E 1122 MOV UA,DIAG_tA
05A2 0205AE 1123 JMP PC_l 1124 PCO_l:
05A5 12086Bt 1125 CALL GET_POLL_ID
05A8 7004 1126 JNZ PC_l 05AA D214 1127 SETB POLL_TOG
05AC 41A2 1128 JMP START_CK
1129 PC_l:
005AE C207 1130 CLR IDL_FLAG
05B0 C200 1131 CLR SECOND_TRY
1132 SEND_POLL:
05B2 D206 1133 SETB POL_IN_PRG
05B4 C207 1134 CLR IDL_F1AG
C5B6 C201 1135 CLR IDL_LINE
05B8 C204 1136 CLR NO_RESP
05BA C202 1137 CLR BCC_ERR
05BC C209 1138 CLR MSG_IN
05BE 1205C5 1139 CALL POLL_SETUP
05C1 41A2 1140 JMP START_CX
1142 WAIT_NR_JMPl:
C5C3 018B 1143 JMP WAIT_NR
1145 POLL_SETUP:
05C9 75D018 1148 MOV PSW,~18H
05CC C582 1149 XCH A,DPL
05CE C8 1150 XCH A,R3 ~LZ3~Z8 05CF C583 1151 XCH A,DPH
05Dl CC 1152 XCH A,R4 05D2 7452 1153 MOV A,$STACK2 05D4 C581 1154 XCH A,SP
05D6 CD 1155 XCH A,R5 05DC 10150A 1159 JBC POLL_ZERO, PS_O
05E1 853783 1161 MOV DPH,POL_PT
05E4 758200 1162 MOV DPL,~00 05E7 BUFFER 1163 MOVX @DPTR,A
1165 PS_O:
05E9 20D002 1166 JB P,POLL_RO
05EC D2E7 1167 SETB ACC.7 1168 POLL_RO-05F0 F599 1170 MOV SBUF,A
05F2 1140 1171 CALL SETUP_EXIT
05F8 300F06 1174 JNB DIAG_REQ_FLG, POL_RO_l 05FB 759915 1175 MOV SBUF,#DIAG
05FE 020604 1176 JMP POL_RO_2 1177 POL_RO_l:
0601 759902 1178 MOV SBUF,~POL
1179 POL_RO_2:
0604 1133 1180 CALL SER_EXIT
060C 758A00 1184 MOV TL0,~00 060F 758C0 1185 MOV T~0,$01 0612 75419F 1186 MOV TOUT_LOW,~LOW
~235~28 POL_NR
0615 754006 1187 MOV TOVT_HIGH, ~HIGH POL_NR
061A 1133 1189 CALL SER_EXIT
061E 758A00 1191 MOV TLO,#00 0623 E599 1193 MOV A,SBUF
0625 B43DOA 1194 CJNE A,~IDL,POL_Rl 062A F0 1196 MOVX @DPTR,A
062C D209 1198 SETB MSO_IN
062E 1133 1199 CALL SER_EXIT
0630 llA7 1200 CALL ERROR_INT
12 n 1 POL_Rl:
0632 F0 1202 MOVX @DPTR,A
063t 1133 1204 CALL SER_EXIT
063~ 758A00 1206 MOV TL0,~00 063D E599 1208 MOV A,S8UF
063F FE 1209 MOV R6,A
0640 F0 1210 MOVX @DPTR,A
0642 F542 1212 MOV SUMCK,A
0644 1133 1213 CALL SER_EXIT
0648 758A00 1215 MOV TL0,~00 064D E599 1217 MOV A,SBUF
064F FF 1218 MOV R7,A
0650 F0 1219 MOVX ~DPTR,A
0652 2542 1221 ADD A,S~MCR
- 14 - ~Z352~8 0654 F542 1222 MOV SUMCK,A
1223 POL_R4:
0656 1133 1224 CALL SER_EXIT
065A 758A00 1226 MOV TLO;~00 065D C28D 1227 CLR tFO
065F E599 1228 MOV A,SBUF
0661 2542 1229 ADD A,SUMCR
0663 F542 1230 MOV S~MCR,A
0665 E599 1231 MOV A,SB~F
0667 FO 1232 MOVX @DPTR,A
066g E582 1234 MOV A,DPL
066B 7006 1235 JNZ POL_R5 0671 D203 1238 SETB BUFF_FULL
1239 POL_R5:
0673 DFEl 1240 DJNZ R7,POL_R4 0675 1133 1241 CALL SER_EXIT
067D E599 1245 MOV A,SBUF
067F F0 1246 MOVX @DPTR,A
0680 2542 1247 ADD A,SUMCK
0682 6004 1248 JZ POL_R7 0684 D202 1249 SETB BCC_ERR
0686 018B 1250 JMP WAIT_ NR
1252 POL_R7:
068C 75990E 1255 MOV SBUF,tACR
068F 1133 1256 CALL SER_EXIT
- 15 - lZ352Z8 0695 D297 125!3 SETB TEN
0697 D29C 1?60 SETB REN
0699 D209 1261 SETB MSG_IN
069B 1133 1262 CALL SER_EXIT
069D llA7 1263 CALL ERROR_INT
1266 POL_NR:
069F D204 1267 SETB NO_RESP
06Al D209 1268 SETB MSG_IN
06A3 C28C 1269 CLR TE~O
06A5 1133 1270 CALL SER_EXIT
06A7 llA7 1271 CALL ERROR_INT
1272 $EJECT
1284 CR_POLL_CMP:
06A9 200C02 1285 JB POL_IN_PRG, CPC_l 06AC 41A2 1286 JMP START_CK
1287 CPC_l:
06AE 200123 1288 JB IDL_LINE, POLL_E RR
06B1 200420 1289 JB NO_RESP, POLL_ERR
06B4 20021D 1290 JB BCC_ERR, POLL_E RR
1291 POLL_GOOD:
06B7 1208BD 1292 CALL UA_TO_POL
06BA 853783 1293 MOV DPH,POL_PT
3n 06BD 758201 1294 MOV DPL,~01 06C0 E0 129S MOVX A,QDPTR
06Cl B43DOD 1296 CJNE A,~IDL, P_M SG_1 06C4 30051A 1297 JNB NEW_UA, POLL_EX I T
06CC 1209E9 1300 CALL CNF_SETUP
06CF 41A2 1301 JMP START_CR
- 16 _ ~352~8 1302 P_MSG_l:
06D1 0206FO 1303 JMP POLL_PROCESS
1305 POLL_ER~:
06D4 200004 1306 JB S~COND_TRY, P_ERRl 06D9 AlB2 1308 JMP SEND_POLL
1309 P_ERRl:
06DB 2Q0503 1310 JB NEW_UA, POLL_EXIT
06DE 120809 1311 CALL UA_ERR
1312 POLL_EXIT.
06E1 300D04 1313 JNB DIAG_IN_PRG, 1 5 P_EX_1 06E4 C20D 1314 CLR DIAG_IN_PRG
06E6 C20F 1315 CLR DIAG_REQ_FLG
1316 P_EX_l:
06E8 D207 1317 SETB IDL_FLAG
06EA C20C 1318 CLR POL_IN_PRG
06EC C205 1319 CLR NEW_UA
06EE 41A2 1320 JMP START_CK
1321 ~EJECT
While the invention has been described in detail and with reference to specific embodiments thereof, it will be understood by those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention. For example, the RAM memory unit 58 (Fig. 4A) and the ROM memory unit 70 (Fig. 4B) may be either internal or external or both to the micropro-cessor devices 30, 32 or 44. Therefore, it is to be understood that the present invention is not to be limited beyond that as required by the appended claims.
Claims (5)
1. A method for polling during a processing operation a plurality of active and inactive remote processing units interconnected in a communication network with a master processing unit having a memory comprising the steps of:
a) sequentially transmitting a status message from the master processing unit to each of the remote processing units prior to the start of the processing operation;
b) transmitting a response message to the master processing unit from a remote processing unit that is active in response to receiving the status message;
c) establishing in the memory a table of first and second bytes of binary signals in accordance with the response received to the status message in which each first byte of binary signals represents an active remote processing unit that has transmitted a response message to the master processing unit and each second byte of binary signals represents an inactive remote processing unit in the communication network that has not transmitted a response message to the master processing unit;
d) sequentially transmitting a polling message to each active remote processing unit in the order listed in the table;
e) at the conclusion of transmitting a polling message to the last active remote processing unit listed in the table, transmitting a polling message to the first inactive remote processing unit listed in the table;
f) after transmitting a polling message to the first inactive remote processing unit, repeating step (d);
g) at the conclusion of transmitting a polling message to the last active remote processing unit listed in the table, transmitting a polling message to the next inactive remote processing unit listed in the table;
h) repeating steps (d), (e), (f) and (g) until all of the active and inactive remote processing units listed in the table have been polled, i) generating first and second time-out periods by the master processing unit at the start of transmitting a polling word to an inactive processing unit;
j) storing a third byte of binary signals in the poll table representing the inactive processing unit polled if the inactive unit does not respond within the first time-out period; and k) changing the third byte of binary signals representing the inactive processing unit polled to said first byte of binary signals upon receiving a response message from the inactive processing unit polled to the transmission of the polling word within said second time-out period.
a) sequentially transmitting a status message from the master processing unit to each of the remote processing units prior to the start of the processing operation;
b) transmitting a response message to the master processing unit from a remote processing unit that is active in response to receiving the status message;
c) establishing in the memory a table of first and second bytes of binary signals in accordance with the response received to the status message in which each first byte of binary signals represents an active remote processing unit that has transmitted a response message to the master processing unit and each second byte of binary signals represents an inactive remote processing unit in the communication network that has not transmitted a response message to the master processing unit;
d) sequentially transmitting a polling message to each active remote processing unit in the order listed in the table;
e) at the conclusion of transmitting a polling message to the last active remote processing unit listed in the table, transmitting a polling message to the first inactive remote processing unit listed in the table;
f) after transmitting a polling message to the first inactive remote processing unit, repeating step (d);
g) at the conclusion of transmitting a polling message to the last active remote processing unit listed in the table, transmitting a polling message to the next inactive remote processing unit listed in the table;
h) repeating steps (d), (e), (f) and (g) until all of the active and inactive remote processing units listed in the table have been polled, i) generating first and second time-out periods by the master processing unit at the start of transmitting a polling word to an inactive processing unit;
j) storing a third byte of binary signals in the poll table representing the inactive processing unit polled if the inactive unit does not respond within the first time-out period; and k) changing the third byte of binary signals representing the inactive processing unit polled to said first byte of binary signals upon receiving a response message from the inactive processing unit polled to the transmission of the polling word within said second time-out period.
2. The method of claim 1 in which said first byte of binary signals is FE and said third byte of binary signals is FF.
3. The method of claim 2 in which the second byte of binary signals is 00.
4. The method of claim 3 which further includes the steps of generating said first and second time-out periods by the master processing unit at the start of transmitting a polling word to an active processing unit;
storing said third byte of binary signals in the poll table if the active device does not respond within the first time-out period;
and changing the third byte of binary signals representing the active processing unit polled to said second byte of binary signals representing an inactive processing device upon not receiving the response to the transmission of the polling message within the second time-out period.
storing said third byte of binary signals in the poll table if the active device does not respond within the first time-out period;
and changing the third byte of binary signals representing the active processing unit polled to said second byte of binary signals representing an inactive processing device upon not receiving the response to the transmission of the polling message within the second time-out period.
5. The method of claim 4 which further includes the steps of generating a third time-out period by the master processing unit after all of the active and inactive remote processing units listed in the table have been polled;
checking to see if the third time-out period has elapsed;
and repeating the polling of the active and inactive remote processing units listed in the table upon finding the third time-out period has elapsed.
checking to see if the third time-out period has elapsed;
and repeating the polling of the active and inactive remote processing units listed in the table upon finding the third time-out period has elapsed.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US627,253 | 1984-07-02 | ||
| US06/627,253 US4683531A (en) | 1984-07-02 | 1984-07-02 | Polling method for data processing system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1235228A true CA1235228A (en) | 1988-04-12 |
Family
ID=24513887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000482438A Expired CA1235228A (en) | 1984-07-02 | 1985-05-27 | Polling method for data processing system |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4683531A (en) |
| EP (1) | EP0188522B1 (en) |
| JP (1) | JPS61502641A (en) |
| CA (1) | CA1235228A (en) |
| DE (1) | DE3573958D1 (en) |
| WO (1) | WO1986000733A1 (en) |
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| US4878176A (en) * | 1984-05-04 | 1989-10-31 | Asics Corporation | Production process control system |
| EP0183273B1 (en) * | 1984-11-30 | 1992-09-23 | Nec Corporation | Serial interface system flexibly applicable to a one-to-plurality connection |
| JPH0666765B2 (en) * | 1985-08-02 | 1994-08-24 | 河村電器産業株式会社 | Audio transmission method in data way system |
| ATE57288T1 (en) * | 1985-08-14 | 1990-10-15 | Siemens Ag | CIRCUIT ARRANGEMENT FOR TELECOMMUNICATION SYSTEMS, IN PARTICULAR TELEPHONE EXCHANGE SYSTEMS, WITH INFORMATION REQUEST DEVICES CYCLICLY CONTROLLING REQUEST POINTS. |
| US4750136A (en) * | 1986-01-10 | 1988-06-07 | American Telephone And Telegraph, At&T Information Systems Inc. | Communication system having automatic circuit board initialization capability |
| US5128664A (en) * | 1986-03-05 | 1992-07-07 | Ampex Corporation | Search technique for identifying slave devices connected to a serial bus |
| US5109484A (en) * | 1986-04-09 | 1992-04-28 | International Business Machines Corporation | Self configuring terminal which polls loop network and generates list of connected devices for use in selectively downloading control programs |
| JPH0789396B2 (en) * | 1986-04-23 | 1995-09-27 | 能美防災株式会社 | Fire alarm equipment |
| US4901316A (en) * | 1986-05-27 | 1990-02-13 | Nohmi Bosai Kogyo Co., Ltd. | Disaster prevention monitoring and control facility |
| US4829297A (en) * | 1987-05-08 | 1989-05-09 | Allen-Bradley Company, Inc. | Communication network polling technique |
| US5155857A (en) * | 1987-05-29 | 1992-10-13 | Hitachi, Ltd. | Communication processing system in which communication by terminals is controlled according to a terminal management table |
| JPS63314133A (en) * | 1987-06-16 | 1988-12-22 | Sharp Corp | Power source controlling system in terminal equipment |
| US5159686A (en) * | 1988-02-29 | 1992-10-27 | Convex Computer Corporation | Multi-processor computer system having process-independent communication register addressing |
| US5050070A (en) * | 1988-02-29 | 1991-09-17 | Convex Computer Corporation | Multi-processor computer system having self-allocating processors |
| US4896277A (en) * | 1988-05-03 | 1990-01-23 | Thermo King Corporation | Method of mapping refrigerated containers in a power line carrier based monitoring system |
| JPH0210454A (en) * | 1988-06-29 | 1990-01-16 | Canon Inc | Electronic apparatus |
| US5247659A (en) * | 1988-10-06 | 1993-09-21 | International Computers Limited | Method for bootstrap loading in a data processing system comprising searching a plurality of program source devices for a bootstrap program if initial data indicating a bootstrap program source device fails a validity check |
| IE883591L (en) * | 1988-12-01 | 1990-06-01 | Blackbird Technology Ltd | Data handling apparatus |
| JPH0748739B2 (en) * | 1988-12-09 | 1995-05-24 | 富士通株式会社 | Multiple access control method and multiple access control system implementing the method |
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| JPH0738612B2 (en) * | 1992-03-18 | 1995-04-26 | 日本電気株式会社 | Control device in satellite communication system |
| DE4224792A1 (en) * | 1992-07-27 | 1994-02-03 | Siemens Ag | Continuous organisation of contents of address memory in data processing network - involves each station being coupled over communication link with master processor units coupled to slave unit and with addressing structure in memory |
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| EP0644679A3 (en) * | 1993-09-03 | 1997-12-03 | Fujitsu Limited | Remote supervisory system for network elements |
| EP0652523B1 (en) * | 1993-11-10 | 1999-06-02 | Nec Corporation | Remote monitoring system |
| US5586150A (en) * | 1993-11-24 | 1996-12-17 | Rajupandaram K. Balasubramaniam | Method and apparatus for symbol synchronization in multi-level digital FM radio |
| EP0677975B1 (en) * | 1994-03-16 | 2002-07-17 | Siemens Aktiengesellschaft | Method for putting into operation an interface allocatable to different transmission links in a program controlled communication system |
| US5611074A (en) * | 1994-12-14 | 1997-03-11 | International Business Machines Corporation | Efficient polling technique using cache coherent protocol |
| JPH08256155A (en) * | 1995-03-17 | 1996-10-01 | Fujitsu Ltd | Method and device for rolling of digital processor |
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| US6006017A (en) * | 1995-05-02 | 1999-12-21 | Motorola Inc. | System for determining the frequency of repetitions of polling active stations relative to the polling of inactive stations |
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| CA2354177A1 (en) | 2001-07-26 | 2003-01-26 | Waverider Communications Inc. | Polling using multiple dynamically updated lists |
| US6990479B2 (en) * | 2001-10-04 | 2006-01-24 | Samsung Electronics Co., Ltd. | Communication system and method of non-intrusive performance data polling |
| JP2004032472A (en) * | 2002-06-27 | 2004-01-29 | Renesas Technology Corp | Network terminal |
| US7539168B2 (en) * | 2003-02-03 | 2009-05-26 | Avaya Inc. | Emergency call handling in contention-based wireless local-area networks |
| US7484125B2 (en) * | 2003-07-07 | 2009-01-27 | Hewlett-Packard Development Company, L.P. | Method and apparatus for providing updated processor polling information |
| US10210110B2 (en) * | 2016-09-14 | 2019-02-19 | Lenovo Enterprise Solutions (Singapore) Pte. Ltd. | Associating data buses and management bus connections for peripheral devices |
| CN110620609B (en) * | 2019-08-28 | 2021-05-14 | 无锡睿思凯科技股份有限公司 | Data communication method, main equipment and system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3652993A (en) * | 1970-07-24 | 1972-03-28 | Bell Telephone Labor Inc | Rapid polling method for digital communications network |
| US3866175A (en) * | 1974-04-24 | 1975-02-11 | Ncr Co | Data communication system between a central computer and a plurality of data terminals |
| US4251865A (en) * | 1978-12-08 | 1981-02-17 | Motorola, Inc. | Polling system for a duplex communications link |
| US4586128A (en) * | 1983-04-14 | 1986-04-29 | Burroughs Corporation | Arbitrator circuit and technique for use in a digital computing system having multiple bus controllers |
-
1984
- 1984-07-02 US US06/627,253 patent/US4683531A/en not_active Expired - Fee Related
-
1985
- 1985-05-27 CA CA000482438A patent/CA1235228A/en not_active Expired
- 1985-06-19 WO PCT/US1985/001155 patent/WO1986000733A1/en active IP Right Grant
- 1985-06-19 JP JP60503058A patent/JPS61502641A/en active Pending
- 1985-06-19 EP EP85903507A patent/EP0188522B1/en not_active Expired
- 1985-06-19 DE DE8585903507T patent/DE3573958D1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4683531A (en) | 1987-07-28 |
| EP0188522B1 (en) | 1989-10-25 |
| DE3573958D1 (en) | 1989-11-30 |
| WO1986000733A1 (en) | 1986-01-30 |
| EP0188522A1 (en) | 1986-07-30 |
| JPS61502641A (en) | 1986-11-13 |
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