CA1235520A - Maintenance subsystem for computer network - Google Patents

Maintenance subsystem for computer network

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Publication number
CA1235520A
CA1235520A CA000493716A CA493716A CA1235520A CA 1235520 A CA1235520 A CA 1235520A CA 000493716 A CA000493716 A CA 000493716A CA 493716 A CA493716 A CA 493716A CA 1235520 A CA1235520 A CA 1235520A
Authority
CA
Canada
Prior art keywords
subsystem
processor
data
maintenance
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000493716A
Other languages
French (fr)
Inventor
David A. Andreasen
John H. Armstrong
Zubair Hussain
Stephen D. Baumgardner
Harshad K. Desai
Jerrold E. Buggert
Kenneth E. Buckmaster
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Application granted granted Critical
Publication of CA1235520A publication Critical patent/CA1235520A/en
Expired legal-status Critical Current

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/273Tester hardware, i.e. output processing circuits
    • G06F11/2733Test interface between tester and unit under test
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2294Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by remote test

Abstract

ABSTRACT OF THE DISCLOSURE
MAINTENANCE SUBSYSTEM FOR COMPUTER NETWORK

A maintenance processor forms port of a computer network wherein the processor (also designated as the User Interface Processor) operates to initialize and maintain and communicate to remote diagnostic terminals for purposes of confirming integrity of the system and also for displaying data for locating any faults or problems in the network. The maintenance subsystem initiates start-up and self-test routines in a sequenced order for establishing the integrity of the units in the network. The subsystem includes means for testing two types of subsystems, that is, one having I/O
controllers with self test capability and another subsystem having I/O controllers without self-test capability. The UP provides means for complete control of the network. It can interface the network to a remote service center where all operations such as power up and initialization can be also effectuated.

Description

MAINTENANCE SUBSYSTEM FOR COMPUTER NETWORK

FIELD OF THE INVENTION
This disclosure relates to the area of computer networks and to specialized support units which operate a maintenance subsystem for the network.
CROSS REFERENCES TO RELATED APPLICATIONS
_ _ _ _ _ . ... _ This application is related to a cop ending applique-lion No. fulled October 24, 1985, entitled "User Interface Processor For Computer Network", - inventors David A. Anderson and Gerald E. Bogart. -- -;.

. .

,:
. .

~35i~

BACKGROUND OF THE INVENTION
. .
In the design and development of computer system networks, there are many considerations and tradeoffs which must be balanced in order to provide an optimum system and to decide what limits must be drawn in terms of economic factors, size and space factors and versatility of control of the system.
The presently described computer network system is designed not only to be used with a variety of peripheral type devices but also with data comma and telephone lines to remote terminals to provide rapid transference of data between the units and rapid data processing by a central processing unit in a fashion whereby reliability is maintained to a very high degree.
The system is organized so that each of the various elements and units will when initiated, provide its own self-test routines and report the results and information to a maintenance processor called the User Interface Processor 100. This processor works in conjunction with the various remote terminals, and the various types of peripheral devices through an IT
subsystem which is uniquely designed to handle units called "data link processors. These types of data link processing units were described in their earlier versions in U.S. Patent Nos. 4,415,986; 4,3~2,207; 4,313,162;
4,390,964 and 4,386,415.
The maintenance subsystem involved herein is so interconnected to the various elements of the system that self-test data may be collected and transported to a remote diagnostic unit which may be a central diagnostic unit for many, many computer networks in many different locations. The remote terminal will perform the basic diagnostic routines to any of the computer networks which have problems and will send messages which pinpoint the specific cause or location of the trouble so that a local operator may correct the fault by changing a card, replacing a module or fixing any other designated fault or outness.
SEYMOUR OF THE INVENTION
A maintenance subsystem for a computer network provides a processor interface card unit which connects a maintenance processor to a main host computer and to an external I/O subsystem which supports non-self testing data link processors (I/O controllers). A host dependent port of the maintenance processor provides a data link interface to another I/O subsystem having data link processors with self-test capabilities. A power control card unit connects the maintenance processor (User Interface Processor) to a remote diagnostic center.
The User Interface Processor or "maintenance processor" provides an interface to the central host processing unit and to various elements of the network such as the data link processors which connect to remote peripherals, to the operator display terminal which provides visual information and diagnostic information, to external cabinets and to the power control card which enables connection to a remote support center for comprehensive diagnostic and fault-location services.
Thea User Interface Processor connects to the central host processing unit through a processor _ 4 - ~35S~

interface card and to various peripherals and terminals through a data link interface/host dependent port controller.
The processor interface card unit provides means for detecting certain events and storing a history trace of a selected number of events for analysis purposes and for interfacing the main host computer.
The power control card unit provides a communication interface to a remote support service diagnostic center in addition to permitting power on/off control to the modules in the network.
Each one of a series of local computer networks may be locally checked on self-testing procedures and then connected to a remote support center for comprehensive diagnostics in order to locate specific problems within any given computer network system. Many differently located computer system networks may be connected to one remote support center which can service them all on a time shared basis.

_ 5 _ ~2~Z~

grief DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of the User Interface Processor used in the maintenance system network;
FIGS. lay lo, lo and lo are system and network drawings showing how the User Interface Processor module connects to other elements of the system network to provide a maintenance subsystem;
FIG. 2 is a block diagram of the serial communications controller elements of the User Interface Processor;
FIG. 3 is a block diagram showing the data paths involved in the serial communications controller;
FIG. 4 is a block diagram of the communications input/output unit elements of the User Interface Processor;
FIG. 5 is a block diagram showing the ports of the communication input/output unit;
FIG. 6 is a block diagram of the communications input/output port designated as port C;
FIG. 7 is a block diagram of the counter timers of the communications input/output unit of FIG. 4;
FIG. 8 is a block diagram of the priority interrupt controller ~PRITC) of the User Interface Processor;
FIG. 9 is a block diagram of the unit designated as the data link interface/host dependent port.
FIG. 10 is a network block diagram showing the maintenance subsystem of the network.

- 6 - ~23 GENERAL OVERVIEW
The Maintenance Subsystem: The maintenance subsystem of the computer network is organized around the User Interface Processor 100 which is shown in FIGS. lay lo, lo and lo.
As seen in these drawings, the User Interface Processor is connected to all the various elements of the computer system network, that is to say, it connects to the processor interface card and the main host processor on the one hand and, on the other hand, it connects to the power control card, the maintenance card III, the operator display terminals and the various data link processors.
FIG. 10 shows the maintenance subsystem connected to two different types of I/O subsystems The I/O
subsystem with self-test capability is connected by the DELI (data link interface) bus to a data-comm DIP (data link processor) to a printer-tape DIP, and to storage module disk (SOD) DIP. The other I/O subsystem involves non-self-testing Dips which are used with the maintenance card.
Thus, these combinations of elements connected to the User Interface Processor 100 provide the basic operational and maintenance functions for the computer network. For example, the User Interface Processor 100 will initialize and power up the entire computer network system. It will initiate self-testing procedures, whereby each of the interconnected data link processors will do their own self-test, do a check out routine and send the results back to the User Interface Processor.
Additionally, the User Interface Processor will connect - PA - ~æ3~2~

to the power control card in order to provide maintenance and diagnostic information and data to a remote unit which can then provide further diagnostics which will determine the location of any faulty areas in the system.
Further, the User Interface Processor will initiate its 'town self-testing" routines to make sure that it itself is in proper operating condition and i-t will display the results on the operator display terminal ~23~$~

Processor Interface Card (PI): The processor interface card 40, FIGS lay lo, in the maintenance subsystem is used to provide the basic system clocks, and in addition it provides data link interface input/output clocks of 8 megahertz It provides an interface to the processor back plane and also provides a unit called the system event analyzer, eye. Further, the PI provides 4,300 16-bit words of history trace 40h in order to maintain a history of any selected input signal Additionally, it provides a 16K byte memory which holds the error correction bits for the control store in the User Interface Processor.
The Power Control Card ( PCC?: The power control card 50, FIG. lay will control the power on/off sequencing and detect any DC failures for all power supply modules which are connected directly to the PCC.
The PCC also monitors any air loss and cabinet over temperature in order to provide sensing signals Jo this effect The power control card communicates with the User Interface Processor via an 8-bit parallel bus. It further communicates with any remote device using the RS-232C remove link interface. it can communicate with other power control cards on external basis by using two wire RS-422 direct connect data communication protocol.
The power control card 50 also maintains a battery backup with the time of day function, in addition to providing 256 bytes of non-volatile storage memory.
It also provides an automatic restart option after failure of the AC power lines DESCRIPTION OF PREFERRED EMBODIMENT:
FIG. lo shows the User Interface Processor 100 as part of a network configuration. The output bus 100b of microprocessor 110 connects to the processor interface card 40 and to the memory bus 30m which connects the main processor 30, FIG. lo, to the memory control unit 32 and main memory 34.
In FIG. lo the DRAM 150 provides output to the power control card 50 and the erasable Proms 150 connect to the operator display terminal loot The power control card 50 (FIG. lay functions to provide power up-down sequencing; to monitor for power failure, to initiate automatic restart (after power failure); to provide warning of over-temperature; to provide automatic power ON/OFF operation; to provide remote" power control of external cabinets; to maintain an internal time-of-day clock; and to provide a communication path (data link) for a remote support and diagnostic service.
` The processor interface card 40 (FIG. lay functions to provide control and data acquisition for diagnostic testing of memory 34 (FIG. lo), memory control unit 32, host dependent port 500 and the main processor 30; the PI 40 provides initialization functions such as microcode load initialization state and clock control, and distribution The PI 40 provides a history file, FIG. lay for real-time tracing of microcode addresses (break points; it provides 16 general purpose links for tracing of intermittent failures, and it permits performance monitoring so thaw a trap can be set to count the number of failure occurrences The PI 40 supplies a 9 ~235;5~

communication path (GULF register, SHAKEUP operator) so that the main system processor 30 can communicate to the UP
100 for maintenance information on power-off, time of day, reload, etc.
In FIG. lo the memory bus 30m connects the main processor 30 to the memory control unit tMCU) 32 and Jo the UP 100.
Also attached to memory bus 30m is the host dependent port 500 (HOP) which provides a DELI (data link interface) bus Ed to the I/O subsystem 500s, and a message level interface (MALI) bus em to the I/O expansion module eye which connects to peripheral devices Fig lo shows, in greater detail, the UP 100 connections to the DO 500 and to the processor interface card (PI) 40 which interconnect the main processor 30 and the HOP 500.
FIG. lo shows how the UP 100 connects to the processor interface card 40 and main processor 30 on one side, and to the I/O data link processor 100d, to maintenance card loom and to OUT 100t and remote link - 50mr-The User Interface Processor 100, FIG. 1, is designated with the acronym "Upon. The User Interface Processor consists of one logic board which can interface to a data link interface (DELI) back plane and also to four independent serial data communications interfaces.
Under certain software instructions, the User Interface Processor 100 can operate as a data link processor (DIP) and in so doing will support a burst rate of Up to eight megabytes per second. It can also be used as a host dependent port (HOP) where it will support a burst rate of 50 kilobytes per second. Thus, the same - 10 - ~L23S5i~

card of hardware can be made to assume different personalities and functions as required.
The User Interface Processor 100 operates on a maintenance philosophy whereby cards in a computer system as FIG lo can be isolated and replaced. A combination of "self test" and "peripheral test-driver" tests are used to isolate any failure to a replaceable module.
This is done by indicating to the operator (via operator display terminal, OUT, 100t) the identity of a failing board after the completion of the self-test.
Thus, the User Interface Processor 100 is basically a microcomputer system which is placed on a single printed circuit board. It includes a number of key components as follows:
(a) a 16 bit central processing unit 110, FIG. l;
(b) 192 kilobytes of PROM, Ahab (FIG. l);
(c) up to one-half megabytes of RAM, Ahab of FIG. l;
(d) programmable input-output ports (aye, 202b);
(e) serial data communication ports (aye 200b);
(f) a priority interrupt controller, (PRITC 800);
(g) programmable timers, (PIT 700);
(h) a DLI-HDP controller 180 (DELI = Data Link Interface);
(i) a DELI host dependent port HOP 500 of FIG. lo.
The User Interface Processor 100 can communicate via the controller 180 and through the RIO (universal input output) back plane to a host computer using a standard UIO-DLI back plane protocol which conforms to the Burroughs Message Level Interface as described in U.S.
Patent No. 4,074,352 at FIG. YE, this patent being entitled Modular Block Unit for Input-Output Subsystem.

i52~

The User Interface Processor is capable of simulating a DELI host dependent port, thus enabling it to communicate with data link processors in a common base that does not have a "distribution carol'. It emulates the priorly used Distribution Card. The description of data link processors and use of the distribution card"
have been described in U.S. Patents 4,313~162 entitled I/O Subsystem Using Data Link Processors/ and ~,390,964 entitled Input/Output Subsystem Using Card-Reader Peripheral Controller.
The User Interface Processor includes a back plane interface to a bus known as the back plane maintenance bus. These back plane lines can be used to initiate a data link processor sulfites routine and to read a result of that self-test as it is driven on to the back plane from a given data link processor.
In this disclosure, the two above-mentioned user interface processor ports will be referred to as the DIP
and the DO respectively.
The User Interface Processor 100, FIG. 1, is a microprocessor controlled system that contains:
(i) a microcomputer subsystem (110);
(ii) a data link interface controller (180~;
lilt) a host dependent port controller (180);
These three units allow the User Interface Processor to communicate with the host computer (30, 32, 34 J Fig lo, via the DELI controller 1~0 (FIG. 1) and also with other data link processors loud, FIG. lo, that are connected to the I/O back plane, via the host dependent port 500 of FIG. lo.

23g~

The UP 100 has certain communication restrictions in this regard. The host dependent port 500 is a DELI
(Data Link Interface) controller (1803 and as such does not provide a MALI (Message Level Interface), but merely provides a back plane DELI interface. In this regard it cannot be used with a distribution card, path selection module, or base control card as was done in the organization of data link processors which were described in the cited U.S. Patents 4,313,162 and 4,390,964, since it provides these functions for itself in firmware. This particular host dependent port 180, JIG. 1, must be used in a base that provides an eight megahertz clock, such as that provided from the maintenance card, 100m of FIG. lo MICROPROCESSOR SUBSYSTEM
The microcomputer subsystem includes both serial and parallel interfaces that are used to perform data communication operations.
The microprocessor subsystem consists of certain elements as follows:
it a microprocessor 110 (such as Intel 8086);
(ii) a dynamic RAY of 512R bytes (Ahab);
(iii3 a PROM of 192K bytes (EPROM) 170;
(ivy four serial data communication ports Ahab, Ahab);
(v) six parallel I/O ports (two units of 407, I 409);
(vim programmable interval timers (PIT 700);
(vii) a programmable interrupt controller (PRITC 800).
These elements are shown in FIG. 1 of the drawings, The microprocessor 110 is used to drive the user Interface Processor 100 and may constitute an eight megahertz chip designated as the INTEL*g086-2 (iAPX-86/10). This microprocessor chip is described at pages 3-1 through 3-24 in an INTEL publication entitled Microprocessor and Peripheral Handbook - 1983 (Order No.
210844-001) and published by INTEL Literature Dept., 3065 Bowers Avenue, Santa Clara, Cay 95051.
This processor is a high performance 16-bit CPU
which is implemented in AMOS technology and packaged in a 40 pin dual in-line package. This processor is capable of addressing up to one megabyte of memory, as well as 64k of I/O addresses. The 8086 microprocessor is operated in a minimum mode since it is used only in a single-processor environment, and as such it generates its own bus control signals.
rework I lion The microprocessor 110 is provided with access to a dynamic RAM array of 128 bytes. The array 150 of FIG. 1 is organized as 64X x 18 bits and it is byte-addressable by the microprocessor 110. The RAM
array 150 is controlled by a dynamic RUM controller chip, of which two preferred element is the National DO 8409.
This chip is described at pages 3~0-391 in a publication entitled NO 16000 Data Book, 1983, and published by the National Semiconductor Corp., 2900 Semiconductor Drive, Santa Clara, Cay 95051.
This chip provides all the necessary multiplexing of the row and column addresses, drivers, and the refresh logic. Since this chip is operated in its fastest mode, there is no wait state required. A "refresh request is requested every 1~6 microseconds by a refresh counter which, in turn, requests a 8086 hold sequence (in * Trade Mark ~3~2~

microprocessor 110) to occur. Once the sequence is granted, the RAM controller chip (UP 8409) accesses on row of RUM 150, thus refreshing it The duration of this access equals that of a microprocessor memory access cycle, thereby reducing the refresh overhead time to a minimum, With this type of configuration, the memory band width is 3083 megabytes per second. The memory is refreshed also during a "reset" of the microprocessor 110, thus preventing destruction of the memory contents.
Error detection in the RAM array 150 is accomplished by vertical byte parity via circuit 160, FIG. lo Thus, each 16-bit word of RAM 150 has two parity bits, one for each byte. Whenever a word, or a byte, of a dynamic RAM is accessed, the parity is checked for each byte regardless of whether the operation is a word-cycle or a byte-memory cycle. When such an error occurs, the microprocessor 110 has its non-masXable interrupt set to true", and the error logging can then be implemented to record the bad address (when such an Implementation has been provided in the UP 100 former PROM STORAGE MEMORY 170: The storage of firmware for the ._ User Interface Processor 100 it provided by an array of six I x 8) Proms which are arranged in a matrix of 24K
x 16. Thus, this results in a 48R byte storage capacity.
These Proms which are used are OK x 8 erasable and operate on a single cycle (no wait). The PROM memory 170 is mapped into the highest point of the microprocessor memory map. This is because of the fact what the microprocessor 110 resets to this point (which is the hex address FOE).

- US I

SERIAL PORTS: As will be seen in FIG. 1, the User if Interface Processor 100 uses two chips aye and 200b which are called serial communication controller chips SAC In the preferred embodiment, these chips are those manufactured by the Zilog Corporation whose address is 1315 Dell Avenue, Campbell, Cay 95008, and described in the publication entitled Counter Firmware Technical Manual" as Zilog*part Z8530 and published in March 1982 by Zilog Corporation.
The SAC chips aye and 200b each provide two independent serial full-duplex data communication channels with synchronous/asynchronous data rates of up to one megabit per second. They can provide up to 250k bits per second with FM (frequency-modulation) encoding, and they can provide up to 125k bits per second with NAZI
(non-return to zero inverted) encoding.
The SAC chip includes two receiver sections 232, 234, FIG. 3, each having a three byte FIFO (first in first out register) that allows buffering of four bytes (including the receive data register) of data in the "receive mode. The transmitter section incorporates a single holding register as well as a transmitter data register.
FIG 2 shows the typical internal features of the Zilog Z8530 SAC (serial communication controller) 200.
where are two channels, channel A (aye) and channel 8 (215b) which connect to remote terminals on serial data lines The control sisals for these channels are designated as "discrete control and status" for channel A, aye, and for channel B, 217b. An internal bus 212 * Trade Mark - 16 - ~æ3ss~

connects these channels and control units Jo the Baud rate generator A, aye, and also to the scud rate generator B, 210b.
The internal bus 212 also connects the channel A
registers aye and the channel B registers 211b, together with further connections to internal control logic 220 and interrupt control logic 222, which then connect to the CPU bus input-output unit 224.
The serial communication controller 200 is an operable part of the User Interface Processor 100 for use as an interrupt control device. It is capable of driving a programmable interrupt vector in response to a microprocessor interrupt acknowledge signal.
The use (in FIG. 1) of the priority interrupt tpRITc 800) controller's cascade output allows the SAC
200 to be operable as a slave interrupt controller. This usage allows implementation of the SAC 200 vectored interrupt capability. While the serial communication controller chip has an interrupt priority option, it is not used in the User Interlace Processor, since this function is allowed for in the interrupt control logic device 222 of FIG. 2.
By using two of the serial communication controller chips, this results in a total of four serial data communication lines shown in FIG. 1 as lines 1 and 2 and lines 3 and 4. These four lines are interfaced over to two external four plane connectors which allow the use of existing data communication paddle cards in order to provide the electrical interfaces for use with interfaces such as the RS~232C, or the TDI and so on.
The serial communication controller 200 has certain capabilities which will be described hereinbelow.

- 17 - ~3S5~

5, 6, 7, or 8 bits per character 1/2, or 2 stop bits - Odd or even parity - Times 1, 16, 32, or 64 clock modes - Break generation and detection - Parity, overrun, and framing error detection
(2) B~te-Oriented Synchronous Capabilities of the SAC:
- Internal or external character synchronization - 1 or 2 sync characters in separate registers - Automatic sync character insertion and deletion - Cyclic redundancy check (CRC) generation/detection - 6 or 8 bit sync character
(3) SDLC/HDLC Capabilities of the SAC
Abort sequence generation and checking - Automatic Nero insertion and deletion - Automatic flag insertion between messages - Address field recognition - I-field residue handling - CRC generation/detection - SOL loop mode with ED recognition/loop entry and exit to) - NRZ, NAZI, also FM encoding - Baud rate generator for each channel - Digital phase-looked loop for synchronous clock recovery period All the modes of communication used are established by the bit values of the Write registers 236, 238, FIG. 3.

As data is received or transmitted, the Read register (Ahab) values change. The values of these Read status registers can promote software action for further register changes.
Referring to FIG. 2 of the serial communication controller 200 block diagram, the resister set (aye and 211b) for each channel (A and B) includes 14 Write registers and seven Read registers. Ten of the Write registers are used for control, two are used for sync character generation, and two are used for Saud rate generation. The remaining two Write registers are shared by both channels; one is used as the n interrupt vector"
and one is used as the "master interrupt control Five Read registers indicate the "status" functions and two are used by the Baud rate generator aye, 210b; one is used for the interrupt vector", one is used for the receiver buffer, and one is used for reading the interrupt pending bits.
SKYE Transmitter: The transmitter section 240 of the serial communication controller 200 is shown in FIG. 3.
The transmitter section of the SAC has an eight bit transmit data register" 240 which is loaded from the internal data bus 212 (FIGS. 2 t 3) and also has a "transmit shift register" 244 which is loaded from either the sync character or the address register 238 WRY the sync character or the SDLC flag register 236 (WRY of FIG.
3) or the transmit data register 240.
In the byte oriented modes, the fog it lens WRY
(238) and WRY (236) of Fig 3 can be programmed with sync characters.
In the "monosync mode", an eight bit or a six bit sync character is used in WRY, whereas a 15 bit sync 19 - ~3~i5~

character it used in the "bisync mode" in registers WRY
and WR70 In the bit-oriented modes, the flag contained in register WRY (236) is loaded into the transmit shift register 244, FIG. 3, at the beginning and at the end of a message.
If asynchronous data is being processed, then registers WRY and WRY of FIG 3 are not used and the "transmit shift register" 244 is formatted with "start"
and n stop" bits shifted out to the transmit multiplexer (252) at the selected clock rate.
Synchronous data (except SDLC/~DLC) is shifted to the CRC (cyclic redundancy checker) generator 250 as well as to the transmit multiplexer 252 at the Al clock rate It should be understood that SDLC means "synchronous data link control while ~DLC is the European version.
The SDLC/~DLC data is shifted out through the zero insertion logic 248 which is disabled while the flags are being sent. The address bit A is inserted in all address, control, information, and frame clock fields following the five contiguous lo in the data stream.
The resultant ox the CRC generator 250 for the SDLC data is also routed through the zero insertion logic 248.
I Referring to FIG. 3, the receivers 232, 234 have three eight-bit FIFE buffer registers and an eight bit shift register. This arrangement creates a three-byte delay time which allows the ventral processing unit 30 9 FIG. lay time to service an interrupt at the beginning of a block of high speed data.

owe 23~i~2~

With each receipt of data in FIFO at 232, 234, an error FIFO eye is provided Jo swore parity and framing errors and other types of status information In FIG. 3 the incoming data is routed through one of several paths depending on the mode and the character length. In asynchronous mode, the serial data enters the three-bit delay at element 280 if a character length of seven or eight bits is selected, If a character length of five or six bits is selected then data enters the receive register 232, 234 directly.
In "synchronous" modes, the data path is determined by the phase of the "receive process"
currently in operation. A synchronous-receive operation begins with a "hunt" phase in which a bit pattern that matches the programmed sync characters to, 8 or 16 bits) is searched.
The incoming data then passes through the receive sync register 282 and is compared to a sync character stored in register WOKS (238) or register WRY (236), depending upon the mode being used.
The "monosync mode" matches the sync characters programmed in register WRY (236) and the character assembled in the receive sync register ~282) in order to establish synchronization Synchronization is achieved differently in the "bisyncn mode. Incoming data is shifted into the receive shift register 232, 234, while the next eight bits of the message are assembled in the receive sync register 282.
If these two characters match the programmed characters in WRY (238) and in register WRY (236), the synchronization is established. Incoming data can then bypass the receive sync register 282 and enter the three byte delay 280 directly.
The SDLC mode of operation uses the receive sync register 282 to monitor the receive data stream and to perform zero deletion (278) wren necessary, for example, when five continuous "ones are received, the sixth bit is inspected and deleted from the data stream if it is a zero, The seventh bit is inspected only if the sixth bit equals "one".
If the seventh bit is a zero, a flag sequence has been received and the receiver is synchronized to that particular flag. If the seventh bit is a "one", then an "abort" or an HOP (end of poll) is recognized, depending on the selection of either the normal SLICK mode or the SDLC loop mode.
Thus for both SDLC modes, the same path is taken by the incoming data The reformatted data enters the 3 bit delay and is transferred to the receive shift register (232, 234). The SDLC receive operation begins in the hunt phase by attempting to match the assembled character in the receive shift resister 232 (232) with the flag pattern in register WRY (236)~
When the flag character is recognized, subsequent data is routed through the same path regardless of the character length. Either the CRC-16 or the CRC SDLC
cyclic redundancy check polynomial can be used for both monosync and the bisync modes but only the CRC-SDLC
polynomial is used for the SDLC operation.
The data path taken for each mode is also different. Bisync protocol it a byte-oriented operation that requires the central processing system (host 30, FIX. lo) to decide whether or not a data character is to be included in the CRC calculation. An eight bit delay in all synchronous modes, except SDLC, is allowed for this process. In the SDLC mode, all bytes are included in the cyclic redundancy checker calculation.
Thy User Interface Processor 100 own use the serial communication controller 200 in two different ways. These are: (i) polled; and (ii) interrupt. Both of these require register manipulation during initialization and data transfer. However, when used in the interrupt mode, the SAC 200 can be programmed to use its vectored interrupt protocol for faster and more efficient data transfers.
SAC POLLING: During a polling sequence, the status of the Read register aye or 211b, FIG. 2, is examined in each channel. This register indicates whether or not a receive or a transmit data transfer is needed and whether or not any special conditions exist This method of I/O transfer avoids interrupts.
All interrupt functions must be disabled in order for a device Jo operate correctly. With no interrupts enabled, this mode of operation must initiate a Read cycle of the Read register "0" to detect an incoming character before jumping to a data-handler routine.
I: The serial communication controller 200 provides an interrupt capability similar Jo that of the PICK priority interrupt controller, 800 of Fig I
Through the use of this method, an increase in throughput is realized. Whenever the SAC interrupt pin is active, then the SAC 200 is ready to transfer data.
The Read and Write registers of FIG. 2 (aye, 211b) are programmed so that an interrupt vector points to an interrupt service routine. The interrupt vector can also be modified to indicate various status conditions. Thus, up to eight possible interrupt routines can be referenced.
Transmit, receive, and external status interrupts are the sources of these interrupts. Each interrupt source is enabled under program control with channel A of FIG. 2, having a higher priority than channel B, and with the receive, transmit, and external status interrupts being prioritized within each of the channels.
SAC Baud Rate Generator. The baud rate generator for each channel A and B is shown in FIG. 2 as aye for channel A and as 210b for channel B. Thus, each channel contains its own programmable baud rate generator. Each generator consists of two eight-bit, time constant registers forming a 16 bit time constant, a 16 bit down counter, and a flip-flop on the output that ensures a scurvy output. This baud generator uses a four megahertz clock derived from the eight megahertz processor clock in order to drive the baud raze venerator. Loading the time constant register causes the counter to toggle at the specified Al, X16, X32, or X64 baud rates.

Referring to FIG. 3, the serial communication controller 200 is shown to have a DULL unit 271 which can be used Jo receive clock information from a data stream with NAZI or FM encoding. NAZI is non return to zero, inverted while EM is frequency modulation The DULL 271 of FIG. 3 is driven by a clock which is normally 32 times (NAZI), or which is 16 times (FM) the data rate. The DULL uses this clock, along with the data stream, to construct a "receive clock" from the data. This clock can then be used as the SAC receive or the SAC transmit clock, or both.

~35i~

In order to provide access to external interfaces, there are provided, as seen in FIG
4, a pair of counter timer-parallel input-outpu~ ports (COO). These counter timer ports are provided through
5 the use of a Zilog chip (Z8536) which is described in a Zilog publication entitled "Zilog Tech Manual" and which is manufactured by Zilog Corporation of 7315 Dell Ave., Campbell, Cay 95008 and which was published in March, 1982.
This COO or counter input-output port (aye, 202b of FIG. 1) is a general purpose I/O port that provides two independent eight bit double buffered, bidirectional input-output ports, plus an extra four bit I/O port.
These types of ports feature a programmable polarity, and 15 a programmable direction ( in the bit mode); they provide "l's" catchers, and programmable open drain outputs.
This COO device also includes three lo bit counter timers each having three output duty cycles and up to four external access lines. These timers are programmable as being "retriggerable'~ or as being ~non~ret~-iggerableW. The COO 400 of FIG. 4 is capable of pattern recognition and generates an interrupt" upon recognition ox a specific pattern at a port.
As seen in FIG. 4, where are three I/O ports provided by the counter input-output device: Port AGO) and port B(408) are eight bit general purpose ports, while port C(409) is a four-bit special purpose port.
Two port configurations are available and are designated as (i) bit port and it port with hand shake. All three of these ports can be programmed as bit ports; however, only ports A and B are capable of operation as hand shake ports.

- 25 - ~23~

These are the two general"
purpose eight-bit ports, which are identical except that port B(408) can be programmed to provide external access to the counter timers 1 (401) and 2 (402) of FIG. 4.
Either port can be programmed to be "hand-shake" driven, as a single or double buffered port (input, output or bidirectional), or as a "control port" with the direction of each bit individually programmable.
Both ports A and B (FIG. 5) include pattern recognition logic 412 which allows interrupt generation when a specific pattern is detected. The pattern recognition logic 412 can be programmed to make the port function like a priority interrupt controller. The ports A and B can also be linked to a 16 bit input-output port with hand-shake capability.
Each of these ports has 12 control and status registers, which control these capabilities The data path of each port is made of three internal registers, which are: I) the input data register 411; (ii) the output data register 410; (iii) and the buffer register 415.
The output data register 410 is accessed by writing to the port data register, while the input data register is accessed by reading the port data register.
Two registers (the mode specification register and the hand shake" specification rejoicer are used to define the mode of the port and to specify which type of hand-shake, if any, is to be used.
In ports A and B, the reference pattern for the "pattern recognition logic" is specified by the contents of three registers (not shown) which are designated as:
(i) the pattern polarity register; (ii3 the pattern transition register; and lit the pattern mask register.
The detailed characteristics of each bit path (for example, the direction of data flow or whether a path is inverting or is non-inver~ing~ are programmed using the data path polarity register, the data direction register and a special I/O control register.
Referring Jo FIG. 5, there is seen a block diagram of certain details of each of the counter~imer input-output COO ports A and B. In FIG. 5 there is seen an output data register 410 and an input data register 411 connected to the internal data bus 212. Tube output data register 410 connects to a data multiplexer 420 which feeds a buffer register 415 having an output which can be conveyed to pattern recognition logic 412 or to input data register 411 or to the output buffer inventors 418. The output buffer inventors 418 can provide an output to the input buffer inventors 422 which can provide their outputs to the data multiplexer 420 or to the counter-timers 1 and 2 of port B (408, FIG. 4). The port control logic 413 of FIG. 5 can provide internal port control or hand-shake control while communicating with the internal data bus 212~
For each port, the primary control and status bits are grouped in a single register called the "command and status register". Once the port has been programmed this is the only register that is accessed for the most part. To facilitate initialization, the port control logic 413 is designed so that registers associated with a non-needed or unrequited capability are ignored and do not have to be programmed. The block diagram of FIG 5 us illustrative of the port configuration which is used and it applies both to port A and port B (407 and 408, FIG. 4).

Port C(409) of Fig 6: In FIG. 6 there is included a special purpose "four bit register" residing in port C(~09, FIG. 4). The function of this register depends upon the functions of ports Aye) and B(408) Port C(409) provides the hand-shake lines when required by the other two ports. A "request/wait" line can also be provided by port I 409) so thaw transfers by ports Aye) and B(408) can be synchronized with direct memory access units or central processing units CPU 30, FIG. lo. Any 10 hits of port C(409) which are not used as hand-shake lines can be used as input-output lines or as external access lines to the counter timer 3 (403 of Fig 4 ) Since the port Claus function is defined primarily by ports A and B (in addition to the internal input data and output data registers, which are similarly accessed as in ports A and B), here only the three bit-path registers are needed, what is the data path polarity register the data direction register, and the special I/O control register snot Sheehan In Fig 4 the three counter/timers 401, 402, 403 in the COO 400 are all identical type units. Each is made of a 16 bit down counter, a 16 bit time-constant register (which holds the value loaded into the down counter), a 16 bit current-count register which is used to read the contents of the down counter, and two eight-bit registers for control and status (that is, the mode specification, and the counter/timer command and status registries Up to four "port pins (counter input gate input, trigger input and counter/timer output) can be used as dedicated external access lines for each counter/timer (FIG. I There are three different counter/timer output duty cycles which are available These are: (i) pulse duty cycle; (ii) one-shot duty cycle; and (iii) a scurvy duty cycle The operation of the counter/timers can be programmed as either retriggerable or as non~retriggerable.
As seen in FIG. 7, each counter/timer connects to the internal data bus 212 and has two time constant registers, 710 and 711, which connect a 16-bit down counter 715, having outputs to the current count registers, 720 and 721. In addition, there is a counter/timer control logic unit 712 which has input lines from a port and which connects to the internal bus 212.
interrupt Control_Loqic For COO (Counter/Timer In Output Unit: The microprocessor 110 of FIG. 1 can receive interrupt signals from the COO 400 (FIG. 4) interrupt control logic 222, The interrupt control logic ox the COO no provides for five registers (not shown) which are:
(i) the master interrupt control register;
(ii) the current vector register;
(iii), (iv) and (v) the three interrupt vector registers associated with the interrupt logic In addition, each port and counter/timer command and status register includes three bits associated with the interrupt logic -- these are the interrupt pounding the interrupt under service" and the interrupt enable.
One interrupt per counter/timer input-output unit drives a priority interrupt controller t800, FIG. I input with the interrupt controller programmed to recognize the COO
400 as a slave interrupt controller. Similar to - 23 - ~35~2~

operation of the SAC 200, this implementation allows the full use of the COO 400 interrupt vector capabilities.
Programmable Interval Timers (PIT): As seen in FIG. 1, the User Interface processor includes a PIT 700 or programmable interval timers These incorporate three counter/timers which are used as interval timers. Each device is an eight megahertz programmable interval timer that consists of an I/O accessible set of three 16-bit counter/timers. These timers operate functionally similar to the three counters in the COO 400. Two outputs of the PIT 700 timers are "Owed" together and drive an interrupt level to the priority interrupt controller PRITC 800 of FIG. 1.
The individual outputs of these two timers are also routed to the COO 400, FIG. 4, so that the microprocessor 110 of FIG. 1 can determine (via a read from the COO port) which timer caused the interrupt. The other timer also directly drives the programmable priority interrupt controller, PRICK 800, via a different interrupt level.
The PIT 700 (FIG. 1, programmable interval timer) has six different modes of operation which may be described as follows:
Output on terminal count, A hardware retriggerable one-shot;
A rate generator;
A scurvy generator;
A software trigger able strobe;
A hardware triggered strobe.

- 30 - ~355~

Programmable Priority Interrupt Controller 800: In FIGS.
1 and 8 there is seen the PRITC 800 which is designated as the Programmable Priority narrate Controller. In order to accommodate the multiple interrupts provided on the User Interface Processor, this interrupt controller device 800 is incorporated.
The Programmable Priority Interrupt Controller is capable of handling eight possible interrupts and for generating a priority for each interrupt as well as an individual vector for each interrupt Various components of the User interface Processor l00 can provide an interrupt signal to the microprocessor ll0. These various types of interrupts are as follows-(a) SAC 1 interrupt;
(by SAC 2 interrupt;
I COO l interrupt;
(d) COO 2 interrupt;
(en Interval timer interrupt (8254) (2 Owed together);
(f) Interval timer interrupt (8254);
(go Fore plane receive interrupt;
oh) DELI controller interrupt These interrupts are given a priority rating and the interrupt controller device 800 will output a vector pointing to 2 service routine in microprocessor 110 in response to its corresponding interrupt input. The priority is under programmed control and can be used to assign a level of priority to each input. The programmable priority interrupt controller RETOOK 800 is shown in block diagram form in FIG. 8.

~35i~

The block diagram of FIG. 8 shows the basic elements of the PRITC 800, that is to say, the priority interrupt controller of the User Interface Processor lo.
Here, a data bus buffer 810 connects to the internal bus 212 which has a bidirectional connection to the interrupt mask register 822. The mask register 822 communicates to the in-service register 824, to the priority resolver 826, and to the interrupt request register 828 Jo provide outputs to the internal bus 212, and also to the control logic 820. The control logic 820 provides outputs to the read/write logic 812 and to the cascade buffer comparator 814.
The counter/timer input-output unit, COO 400, and the serial communication controller, SAC 200, require a separate interrupt acknowledge" term for each of the units. Since the microprocessor lo (8086) drives a common interrupt acknowledge (IOTA), there was provided means to implement a method of decoding separate n acknowledge n S it nets.
The PRITC 800 interrupt controller is programmed to see the COO 400 and the SAC 200 interrupts as though they were interrupts from another interrupt controller device (called "cascade mud. This causes the PRITC
800 interrupt controller to output a throb field (CAS0-CAS2, FIG 8) which is unique for each interrupt level programmed as a slave interrupt. These three outputs are decoded and are used as the separate "interrupt acknowledge" required by the SAC 200 and the COO 400 units, This permits full utilization of the interrupt vectoring capabilities of the SAC and the COO
chips.

The three mentioned cascade outputs (CAST, CAST, CAST, which exit from the cascade buffer 814 of FIG. 8) are also driven Jo the fore plane FOP to allow for another external interrupt control chip to be used which can thus increase the amount of interrupts to fifteen types of interrupts.
Fore lane Interface for Micro processor 110 (FOP 2 in P " ,, ..
FIG. 1: As seen in FIG. 1, the User Interface Processor 100 provides a buffered microprocessor interface that is brought to the fore plane connectors (FOP 2). This interface allows the UP 100 to be connected to application dependent logic via this interface. All necessary memory control signals are provided so that logic providing expanded memory can also be Implemented.
Input-output devices external to the UP 100 can Allah be connected. These can be input-output units or units memory-mapped to the UP 100.
Each interrupt is received by the Ups programmable priority interrupt controller PRITC 800.
More interrupts can be provided by the addition of another controller that uses the UP interrupt controller cascade outputs (KIWI, I 2 of 814 of FIG. 8). This can result in the expansion of up to eight interrupt signals.
For devices with very wow access times, a "ready input' (derived from the microprocessor 110) is brought to the fore plane (FOP 2) so that these slower components can meet the microprocessor timing constraints.
The microprocessor 110 has an output signal HLDA/
which is present on the CAL bus of the ore plane (FOP 2 of FIG. 1): however, the input signal TOLD is not present.
This means that the application dependent logic connected - 33 - ~3~2~

to the fore plane FOP 2 cannot, for example, perform direct memory access to the UP RAM array 150~ Further, the buffers which drive some signals on the fore plane are always enabled and they cannot be disabled by either the UP microprocessor 110 or by the application dependent logic, which may be attached to the fore plane (FOP 2, FIG. 1).
There are a group of signals brought out to the fore plane connectors FOP 2 of the User Interface Processor board. In the signals, the direction is indicated by B
f or bidirectional; by I for input; and by O f or output The list of signals on the fore plane connectors is as follows:
- Microprocessor Address Bus (20 bits) 0 - Microprocessor Data Bus (16 bits) B
- Interrupt Controller Cascade Bus (3 bits) 0 - Microprocessor Control Signals:
LYE/ - Byte sigh Enable ED/ Read Strobe 0 WRY - Write Strobe o MOE - Memory/IO o DT/R - Data Tran~mit/Receive 0 ALE - Address Latch Enable 0 DEN - Data Enable 0 HLDA - Hold Acknowledge 0 IT - Interrupt (input to interrupt controller) INTO - Interrupt Acknowledge 0 RAY - Ready (wait enable) In FIG. 9 a block diagram is shown of the DLI/HDP
controller The term "DELI" represents "Data Link Interface while the term HOP represents "Host Dependent Port.

_ 34 _ ~3~5~

Controller: The DLI/HDP controller 180 of FIG. 1 is shown in more detail by the block structure indicated in FIG 9.
The DELI controller provides an n interface" which consists of the "clear" and "self test" initiation logic, the DELI send/receive registers 922, a burst counter 916, a burst end logic 926, a longitudinal parity word (LOW) generator 923, vertical parity generation and routing, request and emergency request logic, and DLI/microprocessor communication logic.
A 24 bit state machine (925 and 910) with parity accepts the conditions from and controls these data elements. The microprocessor 110 also accepts status from, and provides control of, portions of these elements.
FIG. 9 also shows a block diagram of the DLI/HDP
interface. A data bus 909 connects control store 910, DO register 911, a DIP status send/receive register 912, a DIP reques~/address logic 913, data latches 914, host pointer 91S and burst counter 916. The control store 910 has outputs which provide signals to a condition selector 917 and to a parity check circuit 918.
The data latches 914 have a data bus connection to the DELI send/receive register 922. The host printer 915 provides addresses to RAM 920 which is connected to a vertical parity generator checker 923.
The microprocessor address bus Lola connects to an address buffer 919 and a device decoder 921.
Cl-ar/Self-Te~~ IAiti~ti~ The "clear" and self test initialization logic (112i, FIG. 1) detects when various types of clear signals and self-test signals are . 35 I

required. Clear signals detected by the clear/self-test PAL 112i, FIG. 1 ( Programmable Array Logic) are as follows:
LCLCLR - Local clear MSTRCLR -- Master clear SULKILY -- Select clear PUPCLR -- Power Up clear SLUG - Path selection module generated clear These signals are received and latched by the Clear self-test PAL 112i and a non-maskable interrupt is generated by the self test PAL (112i), thus informing the microprocessor 110 that a clear condition has occurred The microprocessor lo can then read this PAL (112i) and determine which condition occurred and what action to wake as a result.
The Clear self-test PAL (112i) also performs the function of controlling the microprocessor lo reset signal. The UP 100 resets and clears for the following listed conditions (i) PUPCLR -- power up clear;
(ii) A fore plane paddle card - mounted push-button clear;
(iii) Jumper selectable option of selective clear ~SELCLR);
(iv) All other clear signals generate the 8086 microprocessor's (lo, FIG. 1) non-maskable interrupt.
Incorporated into the clear self-test PAL (112i) is the dynamic RAM parity error signal. This term also generates a non~maskable interrupt and can be read by the microprocessor lo to determine which clear signal or parity error caused the NMI interrupt.

DELI Send/Receive Registers: In FIG. 9 the DELI
send/receive registers 912 and 922 are implemented in two AYE bidirectional register/latches. The AYE is a register/latch manufactured by Advanced Micro Devices Inc. whose address is 901 Thompson Place, PRO. Box 453, Sunnyvale, Cay yo-yo and the AYE unit is described in bipolar Microprocessor Logic and Interface Data Book, which was published by Advanced Micro Devices Inc. in 1981. The "output enable" on to the DELI status bus FUGUE
9) is generated by the signal called "CONNECT and the signal "IOSND".
This control signal (CONNECT and IOSND) is generated in the request logic 913. The combination of CONNECT and a "DIP request generates an "output enable"
for the DELI buffers 922, thus allowing data to be driven on to the DELI data bus PHASE. lo and 9) from a connected data link processor DIP. The microprocessor 110 is also capable of wending DIP request" as true" as well as resetting it to false The unlatch enable to receive data from the DELI
into the receive register 922 is controlled by the signal A synchronized STOOL). The clocking of data into the DELI send register is controlled by the DELI state machine (925 and 910). The use of the term "Plan will be meant to indicate programmable Array Logicna DELI Burst Counter 916: The burst counter 916 of FIG. 9 is implemented as a PAL programmed as an eight-b t up-counter. It can be read and also loaded by the microprocessor 110, with the continuable generated by the DELI state machine (910, 925). An overflow term designated UPHILL is also generated by the burst counter 916 that causes a "burst exit" when the counter overflows.
The burst-end logic 926 uses the signal TERM
(terminate), the signal BUFFALO (carry out of the burst counter), and the signal STOOL (strobe I/O level). These signals are used to provide a condition input to the DELI
state machine (925, 910) to halt the burst mode, as well as to reset the burst flip-flop 926.
Longitudinal Parity Generat_on~Checki~ The parity check circuit 918 provides a longitudinal parity generator which is implemented in two Pals (923) which are programmed to perform the longitudinal parity word (LOW) accumulation. A data pipe lining latch means consists of two latches 914 and 923 which are used to meet the timing requirements on the internal DELI data bus 909 ("DATA", FIG. 9).
The microprocessor 110 of Fig 1 controls the clearing and also examines the NEQZERO status from the LOW generator (923). The DELI state machine (910, 925) controls the accumulation and the reading of the longitudinal parity word LOW generator 923. The "pipe lining latch enable (923) is also controlled by the DELI state machine (910, 925).
Vertical parity generation and routing are performed by two nine-bit parity generators with a quad 2 x 1 instate multiplexer g22. A bidirectional register/latch (AYE) is used to send and receive the parity bit on the DELI data bus (FIG. 1).

Vertical parity is generated and written into the parity RAM 920 when writing into the dual port RAM 920 from the microprocessor system of 110. Vertical parity is checked when writing into the dual port RAM 920 from the DELI interlace 922 and the actual DELI parity is written into the parity RAM 920.
Vertical parity is read from the parity RAM when reading into the DELI send/receive registers 922. A
flip-flop is used to store the parity checking result end used to produce the vertical parity error status signal (VPERR) to the microprocessor 110. VPERR is a status input which Jay be read by microprocessor 110.
Request Logic for DIP. Request and emergency request logic is handled in the request PAL 913. The microprocessor 110 controls the sending and removing of the DIP request signal The request monitors the emergency request input from DELI (FIG. lo) to remove the UP request when an emergency request is present from another data link processor on the DELI back plane (FIG. lo).
The signal IOSND (input-output send) is Allah generated by the request PAL 913. The signal IOSND is set automatically when the UP 100 is requesting service and the signal CONNECT it "true. This situation occurs 25 when the UP 100 is returning a descriptor link to the host computer 30, FIG. lo. The signal IOSND is also wettable by the microprocessor llQ~

~3~21:~

SYSTEM INITIALIZATION
Reference to FIGS. lo, lo, lo and lo will indicate the system network connections of the User Interface Processor QUIP 100) and its relationship to the other units in the system network such as the processor interface card 40, the operator display terminal 100t, the power control card 50 and power modules 50p, the modem 50m and the remote support center 50r~ all of which are indicated in FIG lay In FIG. lo there is seen further relationships of the User Interface Processor 100 to the host dependent port HOP 500 and the I/O subsystem 500S and the expansion I/O base eye and additionally the connections to the main processor 30, the memory bus 30m and the memory control unit 32 and memory storage cards 34.
FIG. lo shows further inter connective relationships of the Veer Interface Processor 100 to the processor interface card 40~ the main host processor 30, the memory control unit 32 and the host dependent port 5~0.
FIG. lo shows the interface relationships of the User Interface Processor 100 in relationship to the processor interface card 40 and the main host processor 30 and additionally the relationship to the group of data link processors 100d, to the maintenance card loom to the local terminals 100t and to the power control card 50 and remote support link 50mr.

The User Interface Processor 100 plays a significant part in the operation and especially the n initialization" of the system network.
The computer network system shown in JIGS. lay lo, lo, lo will porn" and initialize in approximately three minutes. When the hardware and software are properly installed in the system when no operator intervention is required during the porn" sequence.
The operational functioning of this sequence and ways for handling exception conditions that may occur are discussed hereinbelow.
POW There is a power button located in the upper left hand corner of the computer cabinet whereby pressing of this button will initiate either the "power-on" or the purify sequence, depending on the current state of the system. The npower-on" button will connect power to the system's main processor 30 and also Jo disaccustom units which are built into the cabinet. It is required that there be at least one operable in-built disk for the power-on sequence to be completed successfully.
After power is successfully established, the UP
maintenance subsystem will be in control of the system network in order to handle the next phase of the "power-up" sequence.
Computer MAINTENANCE SUBSYSTEM SELF TEST: The computer maintenance subsystem will f first perform a ~self-~est~ in order to verify that its own processing elements and memory are operable. Thus, in FIG lo a sulfites procedure will be generated to verity the microprocessor 110, the timers 700, the memories EPROM 170 and the DRAM
150 and also the DLI/HDP controller 180. This self-test will take only a few seconds, and if the self-test routine successfully passes all of the participating units then where will be displayed a "greeting" at the operators display terminal console 100t (FIG. lay.
STARTING SYSTEM INITIALIZATION: In the described computer network this initialization will take an approximate time of three minutes. If the "reading" does not appear on the console display 100t within a few seconds, then it indicates that the maintenance subsystem is not operable and the following problems are likely to be encountered:
(a) There is no external power being supplied to top console cabinet. It is necessary to restore power and then to press the "power-on" button again.
lo (b) The "self-test" procedures have encountered a failure. It is necessary again to push the button for rpower~off/power-on" another time.
Elere a repeated failure to display the greeting on the OUT screen 100t indicates that there are problems in the system hardware or the firmware.
lo) There is some problem that exists in the Connection" from the maintenance subsystem over to the operator's console 100t. Here it is necessary to make sure that the operator's terminal loot is properly powered and turned on and also to check that the cable from the camp or cabinet to the terminal 100t is securely plugged into the terminal. After this check is made, it is necessary to press the Hutton for "power-off/power own again.

~35~
- I -LOADING MAINTENANCE SUBSYSTEM SOFTWARE: It is now necessary that the maintenance subsystem load its own software from a file designated BOOT CODE which code is located on the in-built disk which connects to the User Interface Processor 100 by means of the data link interface line at Ed of FIG. lo.
If there is no BOOT CODE file which is available, then one must be created for use Normally, this file would be available and required software loaded in a Jew seconds, after which the operator can recognize that the BOOT CODE file has been found by observing the messages that will appear briefly on the console display.
These messages will appear as follows:
BOOT~DLP xx BOOT-UNIT xxx Sec~or-Address xxxxx When numbers appear for the BOOT-DLP, BOOT-unit and sector-address, the unit containing the TOOT CODE
file has thus then been selected.
In addition, the status line at the bottom of the screen will indicate loading maintenance software".
INURE TO LOAD BOOT CODE: Any failure to load the maintenance software will be displayed on the operator's display screen The status line at the bottom of the screen will indicate the cause of the failure and will make a request that the operator take some action. Thus, the possible causes of failure will may be displayed are:
(a BOOT unit was not found;
(b) No BOOT CODE file was found on the input unit xxx.
(c) Input unit xxx was not ready _ I - I

As a result of this, the operator will be instructed to specify a valid unit number The operator must then maze sure that the appropriate unit is powered-up and ready to go 7 after which he can type in the unit number to be used. The maintenance I/O
configuration will be displayed on the console to show the operator the set of units found on the last attempt to find or to access the BOOT CODE file.
If the correct unit does not appear in the table, then it is likely that there are problems in the I/O
subsystem 500S of FIG. lo.
If the unit is in the table, but the BOOT COD
file is not found on the specifying unit, it is then likely that a BOOT CODE file was never created on that particular unwept Another possibility is that the disk in question has been damaged or corrupted, and the operator should then specify a backup unit if one exists or else he should load the software from the BOOT CODE tape which it also supplied in the described computer network system.
If the backup" 800T unit exists, it may be specified as the next unit to try However, if no BOOT
unit has been found, it is then not useful to attempt one of the units already displayed in the I/O configuration table since that list would have already been searched.
It is necessary to make sure that the expected BOOT unit is operable, and if not, to take action to bring the BOOT
unit to an operable state, after which the operator should retry the operation by specifying the unit number.
It is possible that a BOOT CODE unit may be located but that parity errors are encountered while - I

loading the software. When that situation occurs the operator will be instructed to specify another BOOT unit.
Thus, a backup unit should be specified if there is one in existence and available, If the software loading consistently fails due Jo errors in the maintenance subsystem memory, the system must be serviced to replace the failing elements before the porn sequence can be successfully completed.
TAPE LOADING MAINTENANCE SUBSYSTEM SOFTWARE: This procedure for tape loading the maintenance software is necessary only in the event of a catastrophic loss of the BOOT unit (for example a head crash) or if the computer system has never had its BOOT unit initialized If no BOOT code file is available, the maintenance subsystem must be "tape-loaded". This procedure is done by first mounting the 800T CODE tape on a tape unit visible to the maintenance subsystem and then to specify this unit as the BOOT unit (the screen on the operator's console loot should then be waiting on the operator to specify it).
The maintenance subsystem will then operate off of the tape unit rather than the disk unit. The tape unit must remain mounted throughout the initialization sequence in order to allow subsequent ties Jo be read.
When the MOP (master control program operating system) is finally up and running, the operator must create a TOOT
CODE file on an in-built disk and again he must initiate the switch for "power-off/power-on" for the system. The next and all subsequent uses of "porn will find and use the BOOT CODE file on the disk and thus the BOOT CODE
tape may then be dismounted, So LOADING SYSTEM MICROCODE: The next step is done automatically in the power on cyclones This step is the loading of the computer system microcode from the BOOT
CODE file (or from the tape depending on whether or not the system is being tape loaded).
The "status line" at the bottom of the operator's screen will indicate that state. This loading will take approximately 30 seconds If the loading fails, the reason will then be shown on the console of the display unit Tao If the failure is due to I/O problems on the BOOT unit, then the operator should restart the system by specifying a backup BOOT unit if possible.
If the loading fails because of errors in the control store of the processor 30 (memory into which the system microcode is stored), then the failing elements must be serviced.
SYSTEM CONFIDENCE TEST: After the system microcode is loaded, then a confidence test will be run on the computer network. The jests take about 30 seconds each and indicate that the control store in the processor 30 is properly loaded and that the system processing elements are operable. the system is now ready to BOOT
the master control program.

INITIALIZING THE OPERATING System At this point the maintenance subsystem has one more task left to perform in the power-up sequence. Here, it must load a program designated as n SYSTEM/UTILOADER~ into the computer system. This program is loaded from the BOOT CODE file and this takes approximately 30 seconds.
Any failure to load the SYSTEM/UITLOADER program may be due to I/O problems with the BOOT unit or certain system preboils In the event of a failure, the cause of the problem will be displayed on the operator's console 100t. Then the operator must take appropriate action by either restarting the porn sequence on a backup BOOT unit or by servicing the failing elements.

_ MAINTENANCE PHILOSOPEIY
Since the requirements for initialization and maintenance in a computer system network are similar, this similarity has been made use of in order Jo yield a particularly significant cost reduction by sharing the access interface hardware. The sharing of the hardware for initialization and for maintenance allows the reporting of failures either locally or remotely and also permits initialization to occur with only a small functional set of circuitry.
A further advantage of this shared hardware is the high degree of visibility to all of the subsystems within the overall system network. This direct visibility permits excellent analysis for faults and for fault resolution.
The access and viability of the initialization and maintenance junctions for the computer network system is provided through the use of the User Interface Processor 100 .
The particular computer network system disclosed here is composed of the following items:
The main central processor which includes data cards and control cards;
The memory control unit (MU);
The host dependent port (HOP);
The data link processors (Dips).
The maintenance subsystem" which is basically the maintenance and initialization subsystem of this disclosed computer network is comprised of the following items:
The User Interface Processor 100;
The processor interface card (PI);
The power control card (PCC).

- I - ~3~2~

DIAGNOSTIC REQUIREMENTS:
. _ .
In order for diagnostic routines to occur in the described computer system network there are certain parameters and requirements which are involved. These are:
(a) All diagnostic jests must run both locally and remotely (and they must appear in the same format and accept the same commands);
IBM The diagnostic testing must isolate any system failures down to or at the "card"
level;
(c) The diagnostic testing must be usable both to support engineering debug, to support the customer's sites, and for test engineering The following elements are required for initialization of the disclosed computer network:
(a) the initialization of the system can be accomplished either from the local site and/or the remote site;
(by Initialization of a system can be possible without operator intervention of any sort, that is to say, the operator at the local sit;
(c ) Structural failures (interconnections and line faults) during initialization can be detected before detection can be made of the violation of machine integrity.

9 sly DIAGNOSTIC TEST OPERATIONS-The diagnostic program involved in this system has two main functions, first to serve as a confidence test on any well defined subsystem; and second to resolve any S failures detected by the confidence routine to the location of a specific card unit.
SELF-TEST:
All subsystems which have a microprocessor must be able to perform self-test. For those units which do not have a microprocessor, the diagnostic access hardware for the self test is provided on each printed circuit board.
Self-test is accomplished by connecting with the User Interface Processor 100 which provides the intelligence to drive the test via the processor interface card 40.
SYSTEM TEST:
These tests are developed as diagnostic tests which provide means for dynamic testing at the system level. This dynamic testing incorporates the event analyzer of the processor interface card 40 and the history file of the processor interface card 40.
FAULT TYPES:
The fault types to be detected in this system are categorized by the level of the test required to detect the fault, the level of skill required to correct the fault, and the time at which the fault is detected.
There are four fault types which are considered for detection in the computer system network.
Fault Tao These types of faults are faults such as failure to power-up; no response on the console unit (operator display terminal); or failure to resolve an operational problem which arises.

~3~i2~7 Here there is no diagnostic program which is readily available or there is more than one failure present. The probability is high that the fault is in the core logic circuitry. This type of failure cannot be verified from a remote service center.
Fault Type II: These types of faults are detected at the time of system initialization when a console message is displayed which specifies the logic card and fault.
Type II faults are also detected when running diagnostic programs, where the same console message is displayed.
The characteristics of this type of fault are structural failures -- stuck at 1, stuck at 0, or short-circults. Correction of this type of problem merely requires replacing the card or cards called out on the Maintenance Display Console.
Fault Type III:
Type III failures are detected by a high number of device failures reported in the maintenance log; the failure of the master control program (MOP) to initialize; continuous dumps which are not cleared by a halt-load; and/or an error message displayed by running internal diagnostic (E-mode diagnostics) programs.
The characteristics of this fault type III are:
peripheral device failure or a memory unit failure; and a failure which can be verified from a remote service center.
The corrective factors in this type of problem may involve the adjustment of peripheral devices or replacement of logic cards, or both.

Fault Type IV: The examples of this type of fault are a system dump caused by a machine check; or an event trap for capturing data about a particular event.
The characteristics of this type of fault are:
a data dependent failure, an intermittent hardware failure or software failure. However, these failures must be such that they can be verified from a remote support center. This type of problem requires high skill for correction. The problem can only be identified in a running system environment or ox analysis of dumps.
TESTING LEVELS:
The diagnostic tests involved are divided into four levels where each is intended to deal with a particular fault type Generally, the execution of a test case depends on the successful execution of the preceding test case unless the tests are used to handle or cover completely independent logic. Each test case is so arranged as to avoid the use of previously untested hardware, BASIC BOARD TESTS AND SELF-TESTS-LEVEL lo This type of test is used to gain a minimal level of structural and functional confidence in the hardware involved. Its purpose is to verify the initialization path during system power-up, to serve as a confidence test during debug and later as a manufacturing test.
These tests use diagnostic codes running either on the UP (basic board tests) or the on-board microprocessor state machine (self-tests).

The level 1 jests cover jests involving the main central processor 30, the memory control unit 32, the host dependent port 500, and the processor interface card 40, whereby each of these four units are given a basic board test which is driven by the User Interface Processor 100.
The level 1 tests also cover certain other units which are defined as a "self-test" which is driven by an on-board microprocessor unit. These units which are given the self-test via the microprocessor are the User Interface Processor 100, the power control card 50, the storage module disk-data link processor, the printer tape-data link processor and the data comma data link processor.
MICRO-CODED DIAGNOSTICS - LEVEL 2:
These tests are used to obtain a higher level of confidence in main frame hardware by testing the interactions between sub-modules in a controlled environment and are also used as memory sub-unit exercises. These tests are written in ONE microcode and are run on the central processor 30 at normal clock speed (4 megahertz) with a driver running on the User Interface Processor 100 that controls the execution of test cases and monitors the results. These level 2 tests cover the following items:
(a) the central processor 30;
(b) the memory control unit 32 and the memory storage boards 34;
I the host dependent port 500 (FIG. lo);
(d) the maintenance subsystem which includes the User Interface Processor 100, the processor interface card 40 and the power control card 50.

- 53 _ ~23~5~

E-MODE STAND ALONE DIAGNOSTICS - LEVEL 3:
The E-mode stand alone diagnostics are NEW (New Programming Language) compiled E-mode programs that run on top of the normal system microcode. The "E-mode"
involves Burroughs stack architecture and is described in a paper entitled "An E-Machine Workbench" by G. Wagner and JAW. Maine, published by ACM association for Computing Machinery) in the proceedings of the Thea annual workshop on Micro programming, October 11-14, 1983.
They are used to obtain a higher level of confidence in the main frame hardware by arranging for the testing of the following:
(a) the interaction between sub-modules in a controlled E-mode environment;
(b) the interaction between microcode and hardware;
(c) the system and I/O interfaces not covered in the lower level tests.
These level 3 tests fall into two groups -- the processor group and the I/O group.
The processor group tests are designed to test E-mode Opus in an environment where the complexities of the master control program are not involved. Standard test cases are provided that run Opus in singles, pairs and triples. There is also the option to generate test cases using a patched NEW compiler in order to enable a few engineers to take a failing code from the master control processor environment and run it in a diagnostic environment using the computer network features of "event and history logic" in order to aid the diagnosis, as well as using the extensive debug features which are brought into this particular program.

- 54 - ~3~5%~

The I/O group are diagnostic which are designed to test the complete path from the E-mode, through the processor 30 and the host dependent port 500 microcode-hardware, the message level in~erface/data link interface (MLI/DLI) and the data link processors to the peripheral itself. This is in a relatively simple controlled environment which can use the event and history logic and the extensive debug features of these programs.

The level 4 tests are used to find failures which only occur in a "system environment". After the computer main frame 30 is verified to be functioning properly, the master control program can drive the interactive tests (POD and SYSTESTS) in order to further diagnose the problem in a master control program environment.
Further, the event and history logic can alto be used to trap failures that only occur while running the system or while running the application software.
DIAGNOSTIC RESOLUTION AND ERROR HANDLING:
. . . 7 . , . _ .
When there is an occurrence of an error, the diagnostic system will provide "error messages"
indicating which boards have malfunctioned.
At the basic board or at the interactive level, the hardware it tested in separate building blocks with the testing of one block depending on the successful test completion of a preceding block. Thus, the diagnostic test will terminate upon the occurrence of an error within the module under test, but it will continue to run tests on other modules providing that they are not dependent on the previous test in order to further diagnose failures in areas such as the M bus or the control bus that can potentially affect more than one module.
Upon the occurrence of a recoverable error, for example, data miscompares in a pattern sensitivity test, the diagnostic tests will log all information relating to an error when it occurs and will continue until completion.
DIAGNOSTIC GRADING:
The diagnostics are graded by running against a list of faults which can be generated by DRY
(program for generating test cases). The number of faults detected by the diagnostic tests can be used to detennine the percentage of testing necessary.

- 56 - ~23~52~

MAINTENANCE INTERFACES:
There are six maintenance interfaces which will be discussed as follows:
(a) TEST RUNNER interfaced to ma intendance software;
(b) Computer system main frame diagnostic interface;
(c) Computer system I/O diagnostic interface;
(d) Maintenance terminal and operator display terminal functions;
(e) The data link interface (DELI) interface;
(d) User Interface Processor diagnostic capabilities.
TEST RUNNER INTERFACE TO MAINTENANCE SOFTWARE:
In order to provide a unified approach, an interface to the diagnostics, an executive program called the "TEST RUNNER" will control the execution, the interface and error logging of all of the off-line diagnostics. The TEST RUNNER is a simple menu driven program which gives unambiguous details of failures at the board level and is designed to complement the overall maintenance philosophy of resolving problems to units which can be replaced.
There are two modes of operation for the TEST
RUNNER. First, there is the automatic mode which is involved during the system initialization sequence and which runs a subset of the diagnostics. Any critical failure detected during this mode will take the system out of automatic and put into manual initialization mode, where diagnostics can be run to verify or further isolate the problem. Any noncritical failure detected (for example, memory module other than a module or data link _ 57 _ I

processor which is not required for initialization) will be flagged to the operator, but will now allow initialization to be continued.
Secondly there is the MANUAL or INTERACTIVE MODE
This mode can be entered during system initialization or it will ye entered as a result of a critical failure during the automatic mode. This mode allows the specification of which diagnostics are to be run and it also allows the use of hardware/software screens and event/history logic in order to trap and/or examine the system's state.
COMPUTER_YSTEM MAIN FRAME DIAGNOSTIC INTERFACE:
The diagnostic tests for the main processor 30, the memory control unit 32, and the host dependent port 500 are initiated from the User Interface Processor 100.
Here, the User Interface Processor functions as follows:
(a) it initializes the computer system network;
(b) it provides for on site and remote service access to the computer system network. This includes the interface to the main central processor 30, and the manipulation of shift chains into the computer network system, and control of the system clocks and event analysis in order to halt the computer system network;
(c) it responds to real time interrupts such as control store parity and super halt interrupts from the computer system;
(d) it provides the software (soft front panel for the coup utter system network.

The User Interface Processor hardware and its functionality are discussed in conjunction with FIGS. l through 9 of the specification COMPUTER SYSTEM INPUT/OUTPUT DIAGNOSTIC INTERFACE:
, The User Interface Processor loo is a processor that has a limited input/output capability. The UP loo can communicate with peripheral devices that are configured into the system via the data link interface.
The User Interface Processor loo through the power control card 40 provides the link to the remote support center shown as 50r in FIG. I This is to permit remote diagnostic functions.
The User Interface Processor 100 also provides the link to the local terminals for maintenance and for operative display terminal loot functions Additionally, the User Interface Processor loo provides the Test Bus function via the Burroughs direct interface (BID shown in FIG. lo and FIG. lo).
The UP loo has the ability to communicate with peripherals in order to provide system maintenance, to load the operator microcode into RAM to perform diagnostics, to enable remote maintenance and to provide for Halt-LoadO The software programs which do this reside on peripheral devices whose data link processors are connected on the data link interface (that is, system maintenance programs that are used by the User Interface Processor 100).
MAINTENANCE TERMINAL AND OPERATOR DISPLAY TERMINAL
FUNCTIONS:
__ _ The UP communicates with terminals via a TDI link (Terminal Direct Interface).

These terminals provide the separate windows to the computer system network. One window occurs when the system is in the "maintenance mode" and the terminal is a maintenance display terminal MET In this mode, the user may access state, may perform system diagnostics, and perform other low level functions. The other window occurs when the system is under master control program (MOP) control. The terminal then is a OUT or operator display terminal. The UP 100 provides the function of the operator display terminal-data link processor for the system. Up to two operator display terminals may be configured in any one computer system network.
THE DATE LINT INTERFACE:
The UP 10U can communicate with data link processors via the data link interface shown in FIGS. lo, lo, and lo. To the data link processor, the UP 100 commands will look like commands sent by the host dependent port 500, FIGS. lo and lo, what is to say, the User Interface Processor 100 has the ability to control devices connected on to the data link interface There are eight available addresses (0~7) for data link processors on the data link interface. The UP 100 occupies the first address (0) on a data link interface.
A printer tape-data link processor occupies one slot, since it is a one-card data link processor and because it is logically considered as two data link processors communicating with two types of peripheral devices.
A SMD-DLP Starkey module disk-data link processor) occupies a fourth address on the data link interface. This leaves four addresses available for expansion.

- 60 - æ US

The User Interface Processor 100 can communicate with peripheral devices by sending I/O descriptors to the data lynx processors and receiving back I/O result descriptors from the data link processors, In order to determine the system configuration, the UP 100 sends a Test I/O operation to the peripheral devices on the data link interface. From this information a data link interface configuration table can be built.
The computer system network disclosed herein may have several RIO (universal input output) bases. One base includes all of the data link processors and the peripherals on the data link interface. A separate base may also be configured on the message level interface (MALI) port on the DO 500 as seen in FIGS. lo and lo, The UP 100 cannot communicate directly with the peripherals on the message level interface. Thus, the software programs an the files that are used by the UP
100 to perform diagnostics and other maintenance functions must reside on peripherals whose data link processors are on the data link interface The power-up of the described computer system network it an automatic sequence of events that does not generally require operator intervention, except in certain specific cases If the default path is not functional (for example, a system disk is no operational, then other means of bringing up the system are provided. Several options that require operator intervention here are as follows:
tax operator intervention as required to perform a cold start or a cool start which requires loading an E-mode program (called Loader);

(b) operator intervention is required to determine the configuration of the I/O system on the message link interface -- this also requires loading an E-mode program called Utiload~r;
I using a Halt-Load unit that is not the default halt load unit -- this requires intervention on part of the operator as does the loading of alternate operator microcode.
It may be noted that both the Utiloader and the Loader must reside on the peripheral devices which are connected to the data link interface.
USER INTERFACE PROCESSOR DIAGNOSTIC CAPABILITY:
, The UP 100 has provision fox some diagnostic capabilities for the I/O subsystem. The UP 100 can determine the configuration on the data link interface, thus to provide a basic interface test. In addition, the UP 100 can initiate self-test on the storage module disk and the printer-tape data link processors.
Finally, the UP performs tests on other data link processors that axe part of the system configuration via the Burroughs direct interface (BID), that is, the test bus function.
The UP 100 (via the PCC 40) also provides the link to the remote support center 50r for remote diagnostics.
While a preferred embodiment of the User Interface Processor and its maintenance subsystem has been described, other equivalent embodiments may be developed within the concepts of this disclosure which are hereinafter defined by the following claims:

Claims (14)

What is claimed is:
1. In a computer network involving a host computer and I/O subsystem connected to remote peripheral units via data link processors and also connected to a maintenance subsystem for initialization, testing and diagnostic operations, the maintenance subsystem comprising:
(a) user interface processor means connected to said host computer and I/O subsystem and having further connections to a remote service-diagnostic center via a power control card unit, said interface processor means including:
(a1) means to power-up the computer network;
(a2) means to initiate self-test operations within said interface processor means;
(a3) means to initiate self-test routines in said data link processors;
(a4) means to transmit/receive diagnostic information to/from a remote support-diagnostic center;
(a5) means to display data, instructions and diagnostic information on an operator display terminal;
(b) processor interface card unit means, connected to said main host computer and said I/O subsystem, for providing a data transfer interface to said host computer and data link processors, said processor interface card unit means including:

(b1) interface means to said main host computer for data transfer operations;
(b2) means for storing a multi-word history trace of data resulting from a given input signal;
(b3) means for recording a series of events for analysis of operations;
(c) said operator display terminal, connected to said interface processor means, for displaying data, instructions and diagnostic information to a human operator;
(d) power control card unit means, connected to said interface processor means and said remote support-diagnostic center, said power control card unit means including:
(d1) protocol circuit means providing bidirectional communication with said remote support center means;
(d2) means to execute instructions for powering up or powering down any connected unit in the said computer network;
(d3) means to detect power failures in the power modules of any unit connected in the computer network;
(d4) means to transmit power status information to said interface processor means and to said remote support-diagnostic center;

(e) remote support-diagnostic center means for receiving data from said power control card unit means and said interface processor means, said diagnostic center means including:
(e1) means to analyze said received data and to generate remedial instructions to said interface processor means for display on said operator display terminal.
2. The maintenance subsystem of claim 1, wherein said processor interface card unit means further includes:
(a) event analyzer means including:
(a1) pattern register means to detect a selected event occurrence;
(a2) counter means for programming the number "N" of events to be detected;
(a3) delay means, connected to a clock signal generation means, to set "M"
clocks of delay after recording the said "No" events before responding with a result data signal to said user interface processor means, said delay means including:
(i) means for halting said main host computer;
(b) interface connection means to said user interface processor means;
(c) host interface means to said main host computer for transferring command and control signals between said main host computer and said user interface processor means;
(d) said clock signal generation means providing clock signals for said entire computer network and including:
(d1) distribution means for conveying clock signals to said network.
3. The subsystem of claim 2, wherein said processor interface card unit means further includes:
(a) error correction control storage memory means for storing and providing error correction bits to any word detected, by said processor interface card unit means, as having defective bits, under instructions from said user interface processor means.
4. The subsystem of claim 3, wherein said processor interface card unit means further includes:
(a) shift chain controller means for exercising diagnostic routines on said I/O subsystem and said power control card unit means.
5. The subsystem of claim 1, which includes:
(a) maintenance card means, initiated by said user interface processor means, for executing test operations on data link processors which do not have internal self-test capability.
6. The subsystem of claim 1, which includes:
(a) disk memory means, connected to a data link processor in said I/O subsystem, for loading initialization and diagnostic routines for use by said user interface processor means.
7. In a computer network having a main host computer with an I/O subsystem connected to peripheral units via a plurality of data link processors including a maintenance subsystem for power on/off control and initialization with testing and diagnostic operations, the maintenance subsystem comprising:
(a) maintenance microprocessor subsystem means for providing serial and parallel data transfer operations to/from said main host computer and said data link processors in said I/O subsystem, and including:
(a1) means to power up or power down said computer network via a connected power control card means;
(a2) means to initiate self-test routines in connected data link processors and in a connected processor interface card means;
(a3) means to display test and diagnostic data on a connected operator display terminal;
(b) processor interface card means connecting said microprocessor subsystem to said main host computer;
(c) data link interface bus means connecting said maintenance microprocessor means to data link processors having self-test capability;
(d) said power control card means connecting said maintenance microprocessor subsystem to a remote service center;
(e) an operator display terminal connected to said microprocessor subsystem for displaying test and maintenance data.
8. The maintenance subsystem of claim 7, wherein said remote service center includes:
(a) means to generate and transmit diagnostic routines to said maintenance microcomputer system for testing said microcomputer system, testing said processor interface card means and said power control card means, and for testing said data link processors;
(b) means to transmit data to isolate faulty units and display the data on said operator display terminal.
9. The subsystem of claim 7, which includes:
(a) maintenance card means, connected to said microprocessor subsystem, for testing data link processors which do not have self-test capability.
10. The maintenance subsystem of claim 8, wherein said maintenance microprocessor subsystem includes:
(a) means to self-test its own operations before communicating to said remote support center;
(b) means to test and verify operability of all I/O communication paths.
11. The maintenance subsystem of claim 8, wherein said remote service center includes:
(a) means to test each module to the card level and to diagnose each faulty card unit;
(b) means to cause said microprocessor subsystem to display the identity of a faulty card unit.
12. The maintenance subsystem of claim lo wherein said microprocessor subsystem includes:
(a) means to initiate self-test routines in data link processors which have self-test routine means;
(b) means to initiate diagnostic test routines in non-self-test data link processors by initiating said maintenance card unit connected to said non-self-test data link processors.
13. The maintenance subsystem of claim 8, wherein said remote service center includes:
(a) means for testing and diagnosing peripheral units connected to said data link processors;
(b) means to transmit diagnostic result data to said microprocessor subsystem for display on said operator display terminal.
14. The maintenance subsystem of claim 7, wherein said processor interface card means includes:
(a) history memory means for storing a sequence of event data starting from a selected program event pattern of bits;
(b) event logic analyzer means for starting a count sequence or a halt period upon occurrence of said selected pattern of bits.
CA000493716A 1984-10-25 1985-10-24 Maintenance subsystem for computer network Expired CA1235520A (en)

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Families Citing this family (162)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5157595A (en) * 1985-07-19 1992-10-20 El Paso Technologies, Company Distributed logic control system and method
US5119489A (en) * 1985-10-02 1992-06-02 International Business Machines Corporation Method of monitoring the bring up of all units in a multiple system from a remote unit including diagnostic testing with visual indicator illumination indicating operability
US5109484A (en) * 1986-04-09 1992-04-28 International Business Machines Corporation Self configuring terminal which polls loop network and generates list of connected devices for use in selectively downloading control programs
NZ220423A (en) * 1986-05-30 1989-07-27 Honeywell Bull Multiprocessor system; shared resource status appears on bus
US5274797A (en) * 1986-05-30 1993-12-28 Bull Hn Information Systems Inc. Multiprocessor system with centralized initialization, testing and monitoring of the system and providing centralized timing
US4989176A (en) * 1986-11-28 1991-01-29 Ag Communication Systems Corporation Remote maintenance system
JPS6473559A (en) * 1987-09-14 1989-03-17 Pioneer Electronic Corp Controller for automatic changer for writable disk
CA1293042C (en) * 1988-02-04 1991-12-10 Ian Macmillan Communication system supporting remote operations
JPH0290335A (en) * 1988-09-28 1990-03-29 Hitachi Ltd Remote operation control system for computer system
US5020081A (en) * 1988-09-30 1991-05-28 Data General Corporation Communication link interface with different clock rate tolerance
US4910754A (en) * 1988-09-30 1990-03-20 Data General Corporation Initialization and synchronization method for a two-way communication link
US5014193A (en) * 1988-10-14 1991-05-07 Compaq Computer Corporation Dynamically configurable portable computer system
US5212774A (en) * 1988-12-09 1993-05-18 Dallas Semiconductor Corporation Two processor communications system with processor controlled modem
GB2228114B (en) * 1989-02-13 1993-02-10 Westinghouse Brake & Signal A system comprising a processor
JP2892675B2 (en) * 1989-04-07 1999-05-17 株式会社日立製作所 Console device monitoring method and information processing system console control method
US5038319A (en) * 1989-04-24 1991-08-06 Xerox Corporation System for recording and remotely accessing operating data in a reproduction machine
US5333286A (en) * 1989-12-13 1994-07-26 Joseph Weinberger Two way copier monitoring system
US5214772A (en) * 1989-12-13 1993-05-25 Joseph Weinberger System for automatically monitoring copiers from a remote location
US6009284A (en) * 1989-12-13 1999-12-28 The Weinberger Group, L.L.C. System and method for controlling image processing devices from a remote location
FR2657182A1 (en) * 1990-01-15 1991-07-19 Cit Alcatel Device for aiding diagnosis
FR2658934B1 (en) * 1990-02-28 1992-04-30 Bull Sa SYSTEM ARCHITECTURE AND USE OF THIS ARCHITECTURE IN A CARD REPLACEMENT METHOD.
US5253359A (en) * 1990-06-11 1993-10-12 Supercomputer Systems Limited Partnership Control and maintenance subsystem network for use with a multiprocessor computer system
EP0470030A3 (en) * 1990-08-02 1993-04-21 International Business Machines Corporation Fast memory power-on diagnostics using direct memory addressing
JPH0727445B2 (en) * 1990-09-04 1995-03-29 インターナショナル・ビジネス・マシーンズ・コーポレイション User interface for computer processor operation
US5295244A (en) * 1990-09-17 1994-03-15 Cabletron Systems, Inc. Network management system using interconnected hierarchies to represent different network dimensions in multiple display views
US5727157A (en) * 1990-09-17 1998-03-10 Cabletron Systems, Inc. Apparatus and method for determining a computer network topology
US5261044A (en) * 1990-09-17 1993-11-09 Cabletron Systems, Inc. Network management system using multifunction icons for information display
US5559955A (en) * 1990-09-17 1996-09-24 Cabletron Systems, Inc. Method and apparatus for monitoring the status of non-pollable device in a computer network
US5751933A (en) * 1990-09-17 1998-05-12 Dev; Roger H. System for determining the status of an entity in a computer network
DE69126666T2 (en) 1990-09-17 1998-02-12 Cabletron Systems Inc NETWORK MANAGEMENT SYSTEM WITH MODEL-BASED INTELLIGENCE
US5117430A (en) * 1991-02-08 1992-05-26 International Business Machines Corporation Apparatus and method for communicating between nodes in a network
GB2259588A (en) * 1991-09-12 1993-03-17 Dowty Communications Ltd Testing data terminal equipment
US5396636A (en) * 1991-10-21 1995-03-07 International Business Machines Corporation Remote power control via data link
US5307482A (en) * 1992-01-28 1994-04-26 International Business Machines Corp. Computer, non-maskable interrupt trace routine override
US5586254A (en) * 1992-02-13 1996-12-17 Hitachi Software Engineering Co., Ltd. System for managing and operating a network by physically imaging the network
US5452401A (en) * 1992-03-31 1995-09-19 Seiko Epson Corporation Selective power-down for high performance CPU/system
FR2696256B1 (en) * 1992-09-30 1994-11-25 Bull Sa Use of "tubes" for the transfer of states between different remote systems.
AU5616694A (en) * 1992-11-30 1994-06-22 Base 10 Systems, Inc. A safety critical processor and processing method for a data processing system
US6230286B1 (en) * 1993-01-28 2001-05-08 Siemens Information And Communication Products Llc Computer system failure reporting mechanism
ES2106254T3 (en) * 1993-11-18 1997-11-01 Siemens Ag COMPUTER ASSISTED DESIGN PROCEDURE FOR A PROGRAMMABLE AUTOMATION SYSTEM.
US5446876A (en) * 1994-04-15 1995-08-29 International Business Machines Corporation Hardware mechanism for instruction/data address tracing
US5513351A (en) * 1994-07-28 1996-04-30 International Business Machines Corporation Protecting a system during system maintenance by usage of temporary filenames in an alias table
GB2295299B (en) * 1994-11-16 1999-04-28 Network Services Inc Enterpris Enterprise network management method and apparatus
US5864659A (en) * 1995-03-07 1999-01-26 Intel Corporation Computer server with improved reliability, availability and serviceability
US6067407A (en) * 1995-06-30 2000-05-23 Canon Information Systems, Inc. Remote diagnosis of network device over a local area network
US5678002A (en) * 1995-07-18 1997-10-14 Microsoft Corporation System and method for providing automated customer support
US6199172B1 (en) 1996-02-06 2001-03-06 Cabletron Systems, Inc. Method and apparatus for testing the responsiveness of a network device
US5742754A (en) * 1996-03-05 1998-04-21 Sun Microsystems, Inc. Software testing apparatus and method
US5915119A (en) * 1996-10-01 1999-06-22 Ncr Corporation Proxy terminal for network controlling of power managed user terminals in suspend mode
US5884073A (en) * 1996-10-28 1999-03-16 Intel Corporation System and method for providing technical support of an electronic system through a web bios
US6243838B1 (en) 1997-05-13 2001-06-05 Micron Electronics, Inc. Method for automatically reporting a system failure in a server
US6269412B1 (en) 1997-05-13 2001-07-31 Micron Technology, Inc. Apparatus for recording information system events
US6282673B1 (en) 1997-05-13 2001-08-28 Micron Technology, Inc. Method of recording information system events
US6269417B1 (en) 1997-05-13 2001-07-31 Micron Technology, Inc. Method for determining and displaying the physical slot number of an expansion bus device
US5987554A (en) * 1997-05-13 1999-11-16 Micron Electronics, Inc. Method of controlling the transfer of information across an interface between two buses
US6122758A (en) * 1997-05-13 2000-09-19 Micron Electronics, Inc. System for mapping environmental resources to memory for program access
US6219734B1 (en) 1997-05-13 2001-04-17 Micron Electronics, Inc. Method for the hot add of a mass storage adapter on a system including a statically loaded adapter driver
US6292905B1 (en) 1997-05-13 2001-09-18 Micron Technology, Inc. Method for providing a fault tolerant network using distributed server processes to remap clustered network resources to other servers during server failure
US6249834B1 (en) 1997-05-13 2001-06-19 Micron Technology, Inc. System for expanding PCI bus loading capacity
US6182180B1 (en) 1997-05-13 2001-01-30 Micron Electronics, Inc. Apparatus for interfacing buses
US6266721B1 (en) 1997-05-13 2001-07-24 Micron Electronics, Inc. System architecture for remote access and control of environmental management
US6134673A (en) * 1997-05-13 2000-10-17 Micron Electronics, Inc. Method for clustering software applications
US6170028B1 (en) 1997-05-13 2001-01-02 Micron Electronics, Inc. Method for hot swapping a programmable network adapter by using a programmable processor to selectively disabling and enabling power thereto upon receiving respective control signals
US6249828B1 (en) 1997-05-13 2001-06-19 Micron Electronics, Inc. Method for the hot swap of a mass storage adapter on a system including a statically loaded adapter driver
US6192434B1 (en) 1997-05-13 2001-02-20 Micron Electronics, Inc System for hot swapping a programmable adapter by using a programmable processor to selectively disabling and enabling power thereto upon receiving respective control signals
US6134668A (en) * 1997-05-13 2000-10-17 Micron Electronics, Inc. Method of selective independent powering of portion of computer system through remote interface from remote interface power supply
US6195717B1 (en) 1997-05-13 2001-02-27 Micron Electronics, Inc. Method of expanding bus loading capacity
US6272648B1 (en) 1997-05-13 2001-08-07 Micron Electronics, Inc. System for communicating a software-generated pulse waveform between two servers in a network
US6363497B1 (en) 1997-05-13 2002-03-26 Micron Technology, Inc. System for clustering software applications
US6173346B1 (en) 1997-05-13 2001-01-09 Micron Electronics, Inc. Method for hot swapping a programmable storage adapter using a programmable processor for selectively enabling or disabling power to adapter slot in response to respective request signals
US6202111B1 (en) 1997-05-13 2001-03-13 Micron Electronics, Inc. Method for the hot add of a network adapter on a system including a statically loaded adapter driver
US6418492B1 (en) 1997-05-13 2002-07-09 Micron Electronics Method for computer implemented hot-swap and hot-add
US6253334B1 (en) 1997-05-13 2001-06-26 Micron Electronics, Inc. Three bus server architecture with a legacy PCI bus and mirrored I/O PCI buses
US6202160B1 (en) 1997-05-13 2001-03-13 Micron Electronics, Inc. System for independent powering of a computer system
US6499073B1 (en) 1997-05-13 2002-12-24 Micron Electronics, Inc. System using programmable processor for selectively enabling or disabling power to adapter in response to respective request signals
US6247080B1 (en) 1997-05-13 2001-06-12 Micron Electronics, Inc. Method for the hot add of devices
US6243773B1 (en) 1997-05-13 2001-06-05 Micron Electronics, Inc. Configuration management system for hot adding and hot replacing devices
US6163849A (en) * 1997-05-13 2000-12-19 Micron Electronics, Inc. Method of powering up or powering down a server to a maintenance state
US6179486B1 (en) 1997-05-13 2001-01-30 Micron Electronics, Inc. Method for hot add of a mass storage adapter on a system including a dynamically loaded adapter driver
US6170067B1 (en) 1997-05-13 2001-01-02 Micron Technology, Inc. System for automatically reporting a system failure in a server
US6338150B1 (en) 1997-05-13 2002-01-08 Micron Technology, Inc. Diagnostic and managing distributed processor system
US6073255A (en) * 1997-05-13 2000-06-06 Micron Electronics, Inc. Method of reading system log
US6145098A (en) * 1997-05-13 2000-11-07 Micron Electronics, Inc. System for displaying system status
US6330690B1 (en) 1997-05-13 2001-12-11 Micron Electronics, Inc. Method of resetting a server
US6138250A (en) * 1997-05-13 2000-10-24 Micron Electronics, Inc. System for reading system log
US6249885B1 (en) 1997-05-13 2001-06-19 Karl S. Johnson Method for managing environmental conditions of a distributed processor system
US6324608B1 (en) 1997-05-13 2001-11-27 Micron Electronics Method for hot swapping of network components
US6304929B1 (en) 1997-05-13 2001-10-16 Micron Electronics, Inc. Method for hot swapping a programmable adapter by using a programmable processor to selectively disabling and enabling power thereto upon receiving respective control signals
US6247079B1 (en) * 1997-05-13 2001-06-12 Micron Electronics, Inc Apparatus for computer implemented hot-swap and hot-add
US6065053A (en) * 1997-10-01 2000-05-16 Micron Electronics, Inc. System for resetting a server
US6154835A (en) * 1997-10-01 2000-11-28 Micron Electronics, Inc. Method for automatically configuring and formatting a computer system and installing software
US6199173B1 (en) 1997-10-01 2001-03-06 Micron Electronics, Inc. Method for mapping environmental resources to memory for program access
US6263387B1 (en) 1997-10-01 2001-07-17 Micron Electronics, Inc. System for automatically configuring a server after hot add of a device
US6138179A (en) * 1997-10-01 2000-10-24 Micron Electronics, Inc. System for automatically partitioning and formatting a primary hard disk for installing software in which selection of extended partition size is not related to size of hard disk
US6088816A (en) * 1997-10-01 2000-07-11 Micron Electronics, Inc. Method of displaying system status
US6212585B1 (en) 1997-10-01 2001-04-03 Micron Electronics, Inc. Method of automatically configuring a server after hot add of a device
US6101419A (en) * 1998-01-15 2000-08-08 Lam Research Corporation Modular control system for manufacturing facility
US6247145B1 (en) * 1998-05-11 2001-06-12 The United States Of America As Represented By The Secretary Of The Air Force Automated reliability and maintainability process
US6223234B1 (en) 1998-07-17 2001-04-24 Micron Electronics, Inc. Apparatus for the hot swap and add of input/output platforms and devices
US6205503B1 (en) 1998-07-17 2001-03-20 Mallikarjunan Mahalingam Method for the hot swap and add of input/output platforms and devices
US6622264B1 (en) 1999-10-28 2003-09-16 General Electric Company Process and system for analyzing fault log data from a machine so as to identify faults predictive of machine failures
US6947797B2 (en) * 1999-04-02 2005-09-20 General Electric Company Method and system for diagnosing machine malfunctions
US6636771B1 (en) 1999-04-02 2003-10-21 General Electric Company Method and system for analyzing continuous parameter data for diagnostics and repairs
US6336065B1 (en) 1999-10-28 2002-01-01 General Electric Company Method and system for analyzing fault and snapshot operational parameter data for diagnostics of machine malfunctions
US6380971B1 (en) * 1999-05-28 2002-04-30 Qwest Communications International Inc. VDSL video/data set top test equipment
US6500070B1 (en) 1999-05-28 2002-12-31 Nintendo Co., Ltd. Combined game system of portable and video game machines
US6371854B1 (en) 1999-08-20 2002-04-16 Ninetendo Co., Ltd. Combined game system
US7783507B2 (en) * 1999-08-23 2010-08-24 General Electric Company System and method for managing a fleet of remote assets
US20110208567A9 (en) * 1999-08-23 2011-08-25 Roddy Nicholas E System and method for managing a fleet of remote assets
US6263265B1 (en) 1999-10-01 2001-07-17 General Electric Company Web information vault
US6301666B1 (en) 1999-08-31 2001-10-09 Everdream, Inc. Method and apparatus for remotely enabling a preinstalled and previously disabled application on a computer system
US6281894B1 (en) 1999-08-31 2001-08-28 Everdream, Inc. Method and apparatus for configuring a hard disk and for providing support for a computer system
US6795935B1 (en) 1999-10-28 2004-09-21 General Electric Company Diagnosis of faults in a complex system
US6324659B1 (en) 1999-10-28 2001-11-27 General Electric Company Method and system for identifying critical faults in machines
US6625589B1 (en) 1999-10-28 2003-09-23 General Electric Company Method for adaptive threshold computation for time and frequency based anomalous feature identification in fault log data
US7051044B1 (en) 1999-10-28 2006-05-23 General Electric Company Method and system for remotely managing communication of data used for predicting malfunctions in a plurality of machines
US6338152B1 (en) 1999-10-28 2002-01-08 General Electric Company Method and system for remotely managing communication of data used for predicting malfunctions in a plurality of machines
US6643801B1 (en) 1999-10-28 2003-11-04 General Electric Company Method and system for estimating time of occurrence of machine-disabling failures
US6405108B1 (en) 1999-10-28 2002-06-11 General Electric Company Process and system for developing predictive diagnostics algorithms in a machine
US6543007B1 (en) 1999-10-28 2003-04-01 General Electric Company Process and system for configuring repair codes for diagnostics of machine malfunctions
US6959235B1 (en) * 1999-10-28 2005-10-25 General Electric Company Diagnosis and repair system and method
US6615367B1 (en) * 1999-10-28 2003-09-02 General Electric Company Method and apparatus for diagnosing difficult to diagnose faults in a complex system
US6446026B1 (en) 1999-10-28 2002-09-03 General Electric Company Method and system for identifying performance degradation of a cooling subsystem in a locomotive
US6651034B1 (en) * 1999-10-28 2003-11-18 General Electric Company Apparatus and method for performance and fault data analysis
US6286479B1 (en) 1999-10-28 2001-09-11 General Electric Company Method and system for predictably assessing performance of a fuel pump in a locomotive
DE60113518T2 (en) * 2000-03-14 2006-07-06 Yamatake Corp. REMOTE CONTROL SYSTEM
US6751794B1 (en) 2000-05-25 2004-06-15 Everdream Corporation Intelligent patch checker
US6697962B1 (en) 2000-10-20 2004-02-24 Unisys Corporation Remote computer system monitoring and diagnostic board
JP4691268B2 (en) 2001-05-02 2011-06-01 任天堂株式会社 Game system and game program
US7058860B2 (en) * 2001-06-29 2006-06-06 Hewlett-Packard Development Company, L.P. System and method of automatic parameter collection and problem solution generation for computer storage devices
CN1185579C (en) * 2001-07-30 2005-01-19 英业达股份有限公司 Debugging method by using serial port when system is in shutdown time and inactive state
GB0118665D0 (en) * 2001-07-31 2001-09-19 Hewlett Packard Co Remote monitoring of computer devices
US6636857B2 (en) 2001-12-18 2003-10-21 Bluecurrent, Inc. Method and system for web-based asset management
US6983398B2 (en) * 2002-04-24 2006-01-03 Hewlett-Packard Development Company, L.P. Testing processors
US6993675B2 (en) * 2002-07-31 2006-01-31 General Electric Company Method and system for monitoring problem resolution of a machine
US6810312B2 (en) * 2002-09-30 2004-10-26 General Electric Company Method for identifying a loss of utilization of mobile assets
US20060123428A1 (en) * 2003-05-15 2006-06-08 Nantasket Software, Inc. Network management system permitting remote management of systems by users with limited skills
US8490064B2 (en) * 2004-05-21 2013-07-16 Oracle International Corporation Hierarchical debug
US7359831B2 (en) * 2004-05-21 2008-04-15 Bea Systems, Inc. Diagnostic context
US8542574B2 (en) * 2005-06-29 2013-09-24 Honeywell International Inc. Apparatus and method for network error prevention
US7882380B2 (en) * 2006-04-20 2011-02-01 Nvidia Corporation Work based clock management for display sub-system
US7937606B1 (en) 2006-05-18 2011-05-03 Nvidia Corporation Shadow unit for shadowing circuit status
US7479714B1 (en) 2006-11-13 2009-01-20 Sprint Communications Company L.P. Apparatus and method for multiple-module electronic system power control
KR101400597B1 (en) 2008-02-18 2014-05-27 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. Systems and methods of communicatively coupling a host computing device and a peripheral device
US7908519B2 (en) * 2008-11-21 2011-03-15 At&T Intellectual Property I, L.P. Trouble emulator for a rules-based diagnostic system
US8560903B2 (en) 2010-08-31 2013-10-15 Cisco Technology, Inc. System and method for executing functional scanning in an integrated circuit environment
US8560474B2 (en) 2011-03-07 2013-10-15 Cisco Technology, Inc. System and method for providing adaptive manufacturing diagnoses in a circuit board environment
US8510200B2 (en) 2011-12-02 2013-08-13 Spireon, Inc. Geospatial data based assessment of driver behavior
US10169822B2 (en) 2011-12-02 2019-01-01 Spireon, Inc. Insurance rate optimization through driver behavior monitoring
WO2013109653A1 (en) * 2012-01-16 2013-07-25 Maxim Integrated Products, Inc. Integrated standard-compliant data acquisition device
US10539625B2 (en) 2012-01-16 2020-01-21 Maxim Integrated Products, Inc. Integrated standard-compliant data acquisition device
GB2504326A (en) * 2012-07-26 2014-01-29 Wunelli Ltd Driving behaviour monitoring system
US9779379B2 (en) 2012-11-05 2017-10-03 Spireon, Inc. Container verification through an electrical receptacle and plug associated with a container and a transport vehicle of an intermodal freight transport system
US8933802B2 (en) 2012-11-05 2015-01-13 Spireon, Inc. Switch and actuator coupling in a chassis of a container associated with an intermodal freight transport system
US9779449B2 (en) 2013-08-30 2017-10-03 Spireon, Inc. Veracity determination through comparison of a geospatial location of a vehicle with a provided data
US20150186991A1 (en) 2013-12-31 2015-07-02 David M. Meyer Creditor alert when a vehicle enters an impound lot
US9551788B2 (en) 2015-03-24 2017-01-24 Jim Epler Fleet pan to provide measurement and location of a stored transport item while maximizing space in an interior cavity of a trailer
JP6542148B2 (en) * 2016-03-18 2019-07-10 株式会社東芝 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM
US10095594B2 (en) * 2016-05-31 2018-10-09 Bristol, Inc. Methods and apparatus to implement communications via a remote terminal unit
US10360125B2 (en) 2016-05-31 2019-07-23 Bristol, Inc. Methods and apparatus to communicatively couple field devices to a remote terminal unit
US9767914B1 (en) 2016-10-10 2017-09-19 Wingyu Leung Durable maintenance of memory cell electric current sense window following program-erase operations to a non-volatile memory
CN111260501B (en) * 2020-01-08 2021-02-26 山东山大电力技术股份有限公司 Remote online maintenance system and method for distributed acquisition terminal

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3771131A (en) * 1972-04-17 1973-11-06 Xerox Corp Operating condition monitoring in digital computers
US3825901A (en) * 1972-11-09 1974-07-23 Ibm Integrated diagnostic tool
US3838260A (en) * 1973-01-22 1974-09-24 Xerox Corp Microprogrammable control memory diagnostic system
US4057847A (en) * 1976-06-14 1977-11-08 Sperry Rand Corporation Remote controlled test interface unit
GB1536046A (en) * 1976-06-30 1978-12-20 Ibm Data processing system power control
JPS5825292B2 (en) * 1977-09-30 1983-05-26 日本電気株式会社 Automatic power cut-off control device
GB2019622B (en) * 1978-04-14 1982-04-07 Lucas Industries Ltd Digital computing apparatus
US4313162A (en) * 1979-12-14 1982-01-26 Burroughs Corporation I/O Subsystem using data link processors
US4322792A (en) * 1979-12-14 1982-03-30 Burroughs Corporation Common front-end control for a peripheral controller connected to a computer
US4334307A (en) * 1979-12-28 1982-06-08 Honeywell Information Systems Inc. Data processing system with self testing and configuration mapping capability
US4322846A (en) * 1980-04-15 1982-03-30 Honeywell Information Systems Inc. Self-evaluation system for determining the operational integrity of a data processing system
US4500993A (en) * 1980-06-17 1985-02-19 Zehntel, Inc. In-circuit digital tester for testing microprocessor boards
US4553201A (en) * 1983-03-28 1985-11-12 Honeywell Information Systems Inc. Decoupling apparatus for verification of a processor independent from an associated data processing system

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EP0179425B1 (en) 1993-05-26
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JPS61180340A (en) 1986-08-13
US4695946A (en) 1987-09-22
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