CA1235630A - Etching techniques - Google Patents

Etching techniques

Info

Publication number
CA1235630A
CA1235630A CA000457419A CA457419A CA1235630A CA 1235630 A CA1235630 A CA 1235630A CA 000457419 A CA000457419 A CA 000457419A CA 457419 A CA457419 A CA 457419A CA 1235630 A CA1235630 A CA 1235630A
Authority
CA
Canada
Prior art keywords
region
tantalum
silicon
halogen fluoride
group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000457419A
Other languages
French (fr)
Inventor
Joel M. Cook
Vincent M. Donnelly
Daniel L. Flamm
Dale E. Ibbotson
John A. Mucha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Application granted granted Critical
Publication of CA1235630A publication Critical patent/CA1235630A/en
Expired legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/53—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone involving the removal of at least part of the materials of the treated article, e.g. etching, drying of hardened concrete
    • C04B41/5338—Etching
    • C04B41/5346—Dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K13/00—Etching, surface-brightening or pickling compositions
    • C09K13/04—Etching, surface-brightening or pickling compositions containing an inorganic acid
    • C09K13/08—Etching, surface-brightening or pickling compositions containing an inorganic acid containing a fluorine compound
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/4401—Means for minimising impurities, e.g. dust, moisture or residual gas, in the reaction chamber
    • C23C16/4405—Cleaning of reactor or parts inside the reactor by using reactive gases
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/12—Gaseous compositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/105—Masks, metal

Abstract

Abstract A highly selective --greater than 100 to 1-- etch for silicon, tantalum, molybdenum and tungsten and non-oxidic tantalum, molybdenum and tungsten compositions such as tantalum silicide and tantalum nitride, molybdenum silicide and tungsten silicide,relative to their oxidic counterparts and silicon nitride is achieved by using polyatomic halogen fluorides. The selectivity (3) which is greater than 100 to 1 for silicon, tantalum and non-oxidic tantalum, is achievable without employing plasmas or wet etching.

Description

~L~3~&3g~

ETCHING TECHNIQUES

Background of the Invention 1~ Field of the Invention .
5This invention relates to device processing and, in particular, to semiconductor processing.
2. Art 8ackground The selective etching of materials in processes such as semiconductor device processing is often required.
For example, it is desirable in cer-tain situations, such as in the production of appropriately configured gate oxides, to remove a region of silicon essentially without causing significant damage to an underlying or adjacent region of a silicon oxide, e.g., silicon dioxide. Processes such as plasma etching and reactive ion etching are often utilized to accomplish these results. In these techniques a gas is typically introduced in proximity to the body to be etched and a plasma is established in the gaseous medium producing molecular fragments, atoms, and ions. The resulting energetic entities produced by the plasma are directed towards the substrate and through various mechanisms remove the impacted material. By a particular choice of processing conditions and gases the rate of removal of a given material is, to an extent, controlled relative to the removal rate of other materials.
While in many situations etching involving energetic entities is advantageously employed, it is not without associated difficulties. The energetic particles produced in the plasma often affect even materials which are not etched at a substantial rate by, for example, inducing pitting or by unacceptably modifying surface electronic states. Pitting and electronic state modification for many device applications are not desirable since they often lead to defective device structures and thus device failure. Additionally, the use of a plasma also often leads to the deposition of contaminating ~Z3S~i3~

materials onto the substrate surface. These contaminating materials, such as compounds produced from the plasma gas, and/or non-volatile metals from the reaction vessel/ e.g., aluminum, either degrade device properties or hinder subsequent processing procedures.
Wet etching, i.e., use of a liquid based chemical that rapidly reacts with the material to be etched as compared to its rate of reaction with underlying or masked adjacent materials, is an alternative to plasma etching.
Again, although wet chemical etching is advantageously employed in many procedures, it too is not without difficulties. For example, wet chemical etching leads to difficulties in handling and disposal of the associated chemicals. Additionally, if the temperature and concentration of the reagents are not caxefully maintained, inconsistent results are obtained. Inconsistent results also arise from the wet etchant failing to reach micron features due to surface tension effects.
Although in many circumstances etching techniques, e.g., plasma etching and wet chemical etching, exhibit a degree of selectivity between the material being etched and adjoining material, this level of selectivity is generally not particularly high. For typical etching systems, selectivity, i.e., the rate of etching of the desired region relative to underlying or unmasked adjacent regions of different compositions, is not greater than 20 to 1. However, there are many applications, for example, the selective removal of silicon filaments from extremely thin silicon dioxide gates in high-speed field effect transistors, that require selectivity which is greater than 100 to 1.
Xenon difluoride in the absence of a plasma has been shown to produce selective etching between silicon dioxide and silicon. (See H. F Winters et al, Applied Physics Letters, _ , 70 (1979).) However, rare gas halides are generally unstable and relatively costly. As a result, the use of rare gas halides is not a particularly ~Z3~63(~
-- 3 ~

satisfactory solution to the problems associated with other procedures. Therefore, cornmon etching procedures have shortcomings and are not sufficiently selective for some important applications.
Summary of the Invention The present invention is directed to a process for manufacturing a device comprising the steps of (1) subjecting a substrate to an etchant to produce selective etching of a first region of said substrate relative to a l(J second region and (2) completing said device characterized in that said etchant comprises a polyatomic halogen fluoride and said first region comprises a non-oxide tantalum composition wherein said substrate is subjected to said polyatomic halogen fluoride in the substantial absence of a plasma.
The present invention is fur-ther directed to a process for treating a body comprising a first region and a second region, said process comprising the step of subjecting said body to an etchant to etch said first region, characterized in that said etchant comprises a polyatomic halogen fluoride wherein said substrate is subjected to said polyatomic halogen fluoride in the substantial absence of a plasma and wherein a substantial fraction o the thickness of said first region is removed.

.

1235~30 - 3a -High selectivity, i.e., selectivity greater than 40 to 1, indeed greater than 100 to 1, is achieved in the etching of a variety materials as compared to underlying or unmasked adjacent regions of a second material by the use of polyatomic halogen fluorides either alone, as mixtures, or combined with inert gases, e.g., argon. For example, materials such as silicon, non~oxidic molybdenum compositions, non-oxidic tantalum compositions, e.g., tantalu.~, tantalum nitride, (materials represented by the formula TaxNy where x > o and y > o) and tantalum silicide, are readily etched as compared to a tantalum oxide, a silicon oxide, or a silicon nitride. The excellent selectivity of the invention is achieved in the absence of a plasma and without liquid etchants. In particular, materials such as BrF5, BrF3, ClF3, and IF5, have been found to produce this result. In contrast, diatomic halogen fluorides such as F2, ClF, and C12 either 1) do not etch materials such as silicon or tantalum compositions, e.g., the silicide, nitride or elemental metal at all or 2) demonstrate extremely low etch rates. The selective etching achieved is quite useful in many device applications such as for the processing of gate oxides in field effect transistors, or for the production of tantalum nitride thin film resistors in conjunction with tantalum oxide thin film capacitors in hybrid, film integrated circuits. Additionally, the selectivity in the case of silicon is particularly advantageous for cleaning silicon deposits from the walls of chemical vapor deposition reactors.
Detailed Description -Selective etching is accomplished by simply subjecting the body to be etched to a composition including ~ ,`r ~

1235~i3~

a polyatomic halogen fluoride in gaseous form. (In this context, a polyatomic molecule is considered one wi~h three or more atoms.) In general, non-oxidic compositions such as silicon, tantalum compositions, e.g., tantalum, tantalum nitrides, tantalum silicides, molybdenum, molybdenum compositions, e.g., molybdenum silicide, tungsten, and tungsten compositions such as tungsten silicide, are typically selectively etched by polyatomic halogen fluorides as compared to a second material if these compositions have a reaction rate of at least 1 x 1014 molecules per cm2 per sec as compared to a rate of at least 40 times smaller for that of the second material and provided that only volatile fluoride products, i.e., fluorides with vapor pressures at 26 degrees C that are greater than 0.1333 Pa (0.001 Torr), are formed. In contrast silicon nitride, the oxides of silicon, the oxides of tantalum, and the oxides of molybdenum and their mixtures that do not have these properties are essentially unetched. The number of fluorine atoms in the polyatomic halogen fluoride is not significant, provided they are present in conjunction with a non-fluorine, halogen atom~
For example, polyatomic halogen fluorides such as BrF5, BrF3, ClF3, and IF5 produce the desired degree of selectivity. (Although these compositions are commercially available, the source of these compounds is not critical and it is possible to generate them even in situ through reactions such as fluorination of bromine gas before etching. See N. V. Sidgwick, The Chemical Elements and Their _mpounds, (London: Oxford University Press, 1952).) The material to be etched is contacted with the appropriate gas simply by, in one embodiment, introducing this gas into a vessel containing the material. For example, it is possible to evacuate the chamber and then backfill it with any of the polyatomic halogen fluorides.
(The use of the term polyatomic halogen fluoride includes not only polyatomic halogen fluoride gases but mixtures of polyatomic halogen fluoride gases.) Alternatively, it is " ~3.~3~

possible to mix the polyatomic halogen fluoride with another gas, e.g., an inert gas, and introduce this mixture into the vessel. (An inert material is one which does not substantially react with the polyatomic halogen fluoride and which also does not react with the substrate in a way which retards the selectivity of the halogen fluoride.) Typically, with or without an inert gas, partial pressures of polyatomic halogen fluorides in the range 0.1333 to 101325 Pa (1 mTorr to 1 atm) are employed. Generally, polyatomic halogen fluoride partial pressures less than 0.1333 Pa (1 mTorr) yield extremely low etch rates while partial pressures significantly higher than 101325 Pa (1 atm) lead to undesirably fast etch rates with the related difficulties in processing control, and thus are not preferred. High partial pressures also have a tendency to lead to the condensation of the product fluorides from the etching process.
Etching is continued until the desired thickness of material is removed. Typical etch rates of materials such as silicon and tantalum compositions for polyatomic halogen fluoride partial pressures in the range 13.33 to 1,333 Pa (0.1 to 10 Torr) are respectively 5 to 500 nm/min and 20 to 300 nm/min. Therefore7 quite nominal etching times are required for material thicknesses less than 100 Mm. For most applications etching is limited to only a portion of a substrate through conventional lithography such as the use of patterned organic resists. However, as discussedt if, for example, a silicon region is to be etched, exposed regions of a silicon oxide need not be masked. After the etching is performed, the device is completed by conventional techniques such as described by S. Sze, VLSI Technology, (McGraw Hill, 1983) in the case of integrated circuits and by R. W. Berry et al, Thin Film Technology, (New York: R. E. Krieger Publishing Company, 1979) in the case of hybrid, film integrated circuits.
The cleaning of deposition equipment, e.g., CVD
reactors is similarly performed by introducing the - - \
lZ35~3~

previously discussed concentrations of polyatomic halogen fluorides into the reactorO Etching is continued until the contamination, e.g., silicon, which is formed on the reactive walls -- typically quartz or glass walls -- is removed. Again for silicon deposits having thicknesses in the range 0.5 nm to 100 m, nominal etching times are required.
The following examples are illustrative of the invention.

Example 1 A hybrid, film integrated circuit on an alumina substrate was etched utilizing a polyatomic halogen fluoride. This circuit contained both thin film capacitors and resistors. The former were fabricated with anodically grown Ta2O5 as the dielectric, a Ta composition containing 13 to 16 atomic percent nitrogen as the bottom electrode and Au as the counterelectrode. The resistors were defined by a photoresist pattern generated on a thin Ta2N film deposited after the capacitor anodization step.
The hybrid, film integrated circuit structure was placed on the sample holder of an aluminum chamber. The chamber was evacuated utilizing a mechanical roughing pump and booster stage to a pressure of approximately 0.6666 Pa (5 mTorr). A flow of ClF3 was then introduced into the chamber while vacuum pumping of the chamber was continued.
The ClF3 flow was adjusted to produce a pressure in the chamber of approximately 666.6 Pa (5 Torr). The ClF3 flow was maintained for approximately 3 minutes and then terminated. Inspection of the hybrid, film integrated circuit with an optical microscope indicated that the tantalum nitride was completely removed in regions where it had been contacted by the gas while exposed regions of gold or tantalum oxide were essentially untouched. The regions of tantalum nitride underlying the photoresist were not affected by the ClF3 nor was the photoresist significantly removed.

~23~3~

Example 2 The procedure of Example 1 was followed except that BrF3 was utilized as the etchant gas. The results were the same as those of Example 1.

Example 3 The procedure of Example 1 was followed except the etching was done at a total pressure of 101325 Pa (1 atm). This pressure was established by preparing a mixture of ClF3 diluted to 5 percent in helium. The chamber was purged with a flow of argon and a sufficient flow of the helium/chlorine trifluoride mixture was introduced into the chamber and continued so that the measured pressure in the chamber remained at approximately 101325 Pa (1 atm). Additionally, the sample was heated to a temperature of 86 degrees C utilizing a resistively heated substrate holder. This heating was utilized to ensure that any products produced from the etching procedure were not deposited onto the hybrid, film integrated circuit.

Example 4 An n-type silicon wafer measuring 7.62 cm (3 inches) in diameter and having its major surface in the (100) crystallographic plane was masked with a 1 Mm thick pattern of silicon dioxide. This pattern was formed from squares of silicon dioxide 5 mm on a side coverlng the entire wafer surface and separated from each adjoining square by a 285 micrometer wide region of the silicon substrate. Samples typically measuring 3 mm on a side were cleaved from the masked wafer. The samples were cleaned by sequential rinses in methylene chloride, acetone, and methanol and then dipped in a 50 percent HF aqueous solution to remove any native oxide. Before use, the sample was rinsed in deionized water and blown dry in clean nitrogen.

1235~3~

The sample wa5 placed on the sample holder of an aluminum chamber. The apparatus was evacuated to a pressure of approximately 0.6666 Pa (5 mTorr~ and the sample was maintained at a temperature of approximately 23 degrees C utilizing the resistively heated sample holder. A flow of BrF3 was introduced into the chamber and was regulated to produce a pressure in the chamber of approximately 133.3 Pa (1 Torr). After approximately 5 minutes, the BrF3 flow was terminated, the reactor was again evacuated, and the apparatus was then backfilled with 101325 Pa (1 atm) of helium.
The sample was removed from the etching apparatus and was immersed in a 50 percent aqueous HF solution for sufficient time to remove the silicon oxide masked material. The samples were then inspected utilizing an optical microscope. This inspection indicated that etch depths of approximately 25 micrometers were observed in exposed regions of the silicon wafer. This corresponded to an etch rate of approximately 5 micrometers per minute.

Example 5 To measure the etch rate of silicon dioxide in BrF3, the same experiment as in Example 4 was performed except the treatment time was extended to 30 minutes. The tbickness of the silicon oxide mask was measured before and after gas exposure utilizing a Nanospec optical thickness monitor. There was no detectable change in thickness of the oxide mask. [The smallest detectable thickness change for the measuring equipment was approximately 0.2 nm per minute per 133.3 Pa (Torr)].

Example _ An n-type silicon wafer measuring 10.16 cm (4 inches) in diameter and having its major surface in the (100) crystallographic plane was entirely masked with a 1 Mm thick layer of silicon dioxide. A 1 Mm thick layer of TaSi2 was then deposited over the silicon dioxide. Samples 12~S~3~
g measuring 1 cm on a side were cleaved from the wafer. The samples were cleaned in sequential rinses in methylene chloride, acetone and methanol and blown dry with clean nitrogen. The samples were placed on the sample holder of an aluminum chamber. The apparatus was evacuated to a pressure of 0.6666 Pa (5 mTorr) and the samples were maintained at a temperature of approximately ~0 degrees C.
A flow of BrF3 was established and regulated to produce a pressure of 666.6 Pa (5 Torr) of BrF3 in the chamber.
After approximately 2 minutes, the Br~3 flow was terminated, the reactor was again evacuated, and the apparatus was then backfilled with 101325 Pa (1 atm) of helium. All TaSi2 was totally removed from the entire surface of the silicon dioxide layer.

lS Example 7 The procedure of Example 6 was followed except Ta was deposited on the 1 Mm thick silicon dioxide. The Ta layer was subjected to ClF3 at a pressure of 666.6 Pa (1 Torr) for a period of 2 minutes while maintaining the sample at 70 degrees C. This film was totally removed from the entire surface of the silicon dioxide layer.

Claims (22)

Claims:
1. A process for manufacturing a device comprising the steps of (1) subjecting a substrate to an etchant to produce selec-tive etching of a first region of said substrate relative to a second region and (2) completing said device characterized in that said etchant comprises a polyatomic halogen fluoride and said first region comprises a non-oxide tantalum composition wherein said substrate is subjected to said polyatomic halogen fluoride in the substantial absence of a plasma.
2. The process of claim 1 wherein said polyatomic halogen fluoride is chosen from the group consisting of BrF5, BrF3, ClF3, and IF5.
3. The process of claim 1 wherein said device comprises a hybrid, film integrated circuit.
4. The process of claim 1 wherein said tantalum composition comprises a member chosen from the group consisting of tantalum, tantalum nitride, and tantalum silicide.
5. The process of claim 1 wherein said second region comprises a tantalum oxide.
6. The process of claim 1 wherein said first region comprises a member chosen from the group consisting of silicon, molybdenum silicide, molybdenum, tungsten, and tungsten silicide.
7. The process of claim 1 wherein said device is a semiconductor device.
3. A process for treating a body comprising a first region and a second region, said process comprising the step of subjecting said body to an etchant to etch said first region, characterized in that said etchant comprises a polyatomic halogen fluoride wherein said substrate is subjected to said polyatomic halogen fluoride in the substantial absence of a plasma and wherein a substantial fraction of the thickness of said first region is removed.
9. The process of claim 8 wherein said polyatomic halogen fluoride is chosen from the group consisting of BrF5, BrF3, ClF3, and IF5.
10. The process of claim 8 wherein said first region comprises a silicon oxide and said second region comprises silicon.
11. The process of claim 8 wherein said body comprises a contaminated deposition apparatus where said first region is said contamination.
12. A process for manufacturing a device comprising the steps of (1) subjecting a substrate to an etchant to produce selec-tive etching of a first region of said substrate relative to a second region and (2) completing said device characterized in that said etchant comprises a polyatomic halogen fluoride wherein said substrate is subjected to said polyatomic halogen fluoride in the substantial absence of a plasma, and wherein a substantial fraction of the thickness of said first region is removed.
13. The process of claim 12 wherein said polyatomic halogen fluoride is chosen from the group consisting of BrF5, BrF3, ClF3, and IF5.
14. The process of claim 12 wherein said device is a semiconductor device.
15. The process of claim 12 wherein said device comprises a hybrid, film integrated circuit.
16. The process of claim 12 wherein said first region comprises a non-oxide tantalum composition.
17. The process of claim 16 wherein said tantalum composition comprises a member chosen from the group consisting of tantalum, tantalum nitride, and tantalum silicide.
18. The process of claim 12 wherein said second region comprises a tantalum oxide.
19. The process of claim 12 wherein said first region comprises a member chosen from the group consisting of silicon, molybdenum silicide, molybdenum, tungsten, and tungsten silicide.
20. The process of claim 12 wherein said second region comprises a member chosen from the group consisting of a silicon oxide and a silicon nitride.
21. A process for manufacturing a device comprising the steps of (1) subjecting a substrate to an etchant to produce selective etching of a first region of said substrate relative to a second region and (2) completing said device characterized in that said etchant comprises a polyatomic halogen fluoride wherein said substate is subjected to said polyatomic halogen fluoride in the substantial absence of a plasma and wherein said first region comprises a member chosen from the group consisting of silicon, molybdenum silicide, molybdenum, tungsten, and tungsten silicide.
22. The process of claim 21 wherein said second region comprises a member chosen from the group consisting of a silicon oxide and a silicon nitride.
CA000457419A 1983-07-27 1984-06-26 Etching techniques Expired CA1235630A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/517,754 US4498953A (en) 1983-07-27 1983-07-27 Etching techniques
US517,754 1983-07-27

Publications (1)

Publication Number Publication Date
CA1235630A true CA1235630A (en) 1988-04-26

Family

ID=24061096

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000457419A Expired CA1235630A (en) 1983-07-27 1984-06-26 Etching techniques

Country Status (9)

Country Link
US (1) US4498953A (en)
JP (1) JPS6053027A (en)
KR (1) KR900001664B1 (en)
CA (1) CA1235630A (en)
DE (1) DE3427599A1 (en)
FR (1) FR2551583B1 (en)
GB (1) GB2144083B (en)
HK (1) HK37388A (en)
NL (1) NL8402360A (en)

Families Citing this family (154)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6094757A (en) * 1983-10-20 1985-05-27 Fujitsu Ltd Resistor
US4637129A (en) * 1984-07-30 1987-01-20 At&T Bell Laboratories Selective area III-V growth and lift-off using tungsten patterning
US4689115A (en) * 1985-04-26 1987-08-25 American Telephone And Telegraph Company, At&T Bell Laboratories Gaseous etching process
DE3714144C2 (en) * 1986-05-31 1994-08-25 Toshiba Kawasaki Kk Dry chemical etching process
US4713141A (en) * 1986-09-22 1987-12-15 Intel Corporation Anisotropic plasma etching of tungsten
US4816294A (en) * 1987-05-04 1989-03-28 Midwest Research Institute Method and apparatus for removing and preventing window deposition during photochemical vapor deposition (photo-CVD) processes
US4998979A (en) * 1988-06-06 1991-03-12 Canon Kabushiki Kaisha Method for washing deposition film-forming device
JP2646811B2 (en) * 1990-07-13 1997-08-27 ソニー株式会社 Dry etching method
JPH0496223A (en) * 1990-08-03 1992-03-27 Fujitsu Ltd Manufacture of semiconductor device
US6674562B1 (en) * 1994-05-05 2004-01-06 Iridigm Display Corporation Interferometric modulation of radiation
US7830587B2 (en) * 1993-03-17 2010-11-09 Qualcomm Mems Technologies, Inc. Method and device for modulating light with semiconductor substrate
US8081369B2 (en) * 1994-05-05 2011-12-20 Qualcomm Mems Technologies, Inc. System and method for a MEMS device
US8014059B2 (en) * 1994-05-05 2011-09-06 Qualcomm Mems Technologies, Inc. System and method for charge control in a MEMS device
US7839556B2 (en) * 1994-05-05 2010-11-23 Qualcomm Mems Technologies, Inc. Method and device for modulating light
US7550794B2 (en) * 2002-09-20 2009-06-23 Idc, Llc Micromechanical systems device comprising a displaceable electrode and a charge-trapping layer
US5534107A (en) * 1994-06-14 1996-07-09 Fsi International UV-enhanced dry stripping of silicon nitride films
US6124211A (en) * 1994-06-14 2000-09-26 Fsi International, Inc. Cleaning method
JPH0864559A (en) * 1994-06-14 1996-03-08 Fsi Internatl Inc Method of deleting unnecessary substance from substrate surface
US5635102A (en) 1994-09-28 1997-06-03 Fsi International Highly selective silicon oxide etching method
JP3512496B2 (en) * 1994-11-25 2004-03-29 株式会社半導体エネルギー研究所 Manufacturing method of SOI type semiconductor integrated circuit
JPH08153700A (en) * 1994-11-25 1996-06-11 Semiconductor Energy Lab Co Ltd Anisotropic etching of electrically conductive coating
JP3370806B2 (en) 1994-11-25 2003-01-27 株式会社半導体エネルギー研究所 Method for manufacturing MIS type semiconductor device
JPH08153711A (en) * 1994-11-26 1996-06-11 Semiconductor Energy Lab Co Ltd Etching device
JPH08153879A (en) 1994-11-26 1996-06-11 Semiconductor Energy Lab Co Ltd Fabrication of semiconductor device
JP3609131B2 (en) * 1994-12-06 2005-01-12 株式会社半導体エネルギー研究所 Cleaning method of ion doping apparatus
US7898722B2 (en) * 1995-05-01 2011-03-01 Qualcomm Mems Technologies, Inc. Microelectromechanical device with restoring electrode
US6849471B2 (en) * 2003-03-28 2005-02-01 Reflectivity, Inc. Barrier layers for microelectromechanical systems
US6969635B2 (en) * 2000-12-07 2005-11-29 Reflectivity, Inc. Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates
JPH11513846A (en) * 1995-10-19 1999-11-24 マサチューセッツ インスティテュート オブ テクノロジー Metal removal method
KR0170902B1 (en) * 1995-12-29 1999-03-30 김주용 Method of manufacturing semiconductor device
US5782986A (en) * 1996-01-11 1998-07-21 Fsi International Process for metals removal using beta-diketone or beta-ketoimine ligand forming compounds
US6077451A (en) * 1996-03-28 2000-06-20 Kabushiki Kaisha Toshiba Method and apparatus for etching of silicon materials
US6132522A (en) * 1996-07-19 2000-10-17 Cfmt, Inc. Wet processing methods for the manufacture of electronic components using sequential chemical processing
US7929197B2 (en) * 1996-11-05 2011-04-19 Qualcomm Mems Technologies, Inc. System and method for a MEMS device
US7830588B2 (en) * 1996-12-19 2010-11-09 Qualcomm Mems Technologies, Inc. Method of making a light modulating display device and associated transistor circuitry and structures thereof
AU6037698A (en) * 1997-01-22 1998-08-07 California Institute Of Technology Gas phase silicon etching with bromine trifluoride
US5954884A (en) 1997-03-17 1999-09-21 Fsi International Inc. UV/halogen metals removal process
US6042738A (en) * 1997-04-16 2000-03-28 Micrion Corporation Pattern film repair using a focused particle beam system
US6514875B1 (en) * 1997-04-28 2003-02-04 The Regents Of The University Of California Chemical method for producing smooth surfaces on silicon wafers
US6635185B2 (en) 1997-12-31 2003-10-21 Alliedsignal Inc. Method of etching and cleaning using fluorinated carbonyl compounds
US6120697A (en) * 1997-12-31 2000-09-19 Alliedsignal Inc Method of etching using hydrofluorocarbon compounds
US8928967B2 (en) 1998-04-08 2015-01-06 Qualcomm Mems Technologies, Inc. Method and device for modulating light
KR100703140B1 (en) * 1998-04-08 2007-04-05 이리다임 디스플레이 코포레이션 Interferometric modulation and its manufacturing method
US6186154B1 (en) * 1998-12-07 2001-02-13 Taiwan Semiconductor Manufacturing Company Find end point of CLF3 clean by pressure change
US6248704B1 (en) 1999-05-03 2001-06-19 Ekc Technology, Inc. Compositions for cleaning organic and plasma etched residues for semiconductors devices
US6207570B1 (en) 1999-08-20 2001-03-27 Lucent Technologies, Inc. Method of manufacturing integrated circuit devices
WO2003007049A1 (en) 1999-10-05 2003-01-23 Iridigm Display Corporation Photonic mems and structures
US6942811B2 (en) * 1999-10-26 2005-09-13 Reflectivity, Inc Method for achieving improved selectivity in an etching process
US6960305B2 (en) * 1999-10-26 2005-11-01 Reflectivity, Inc Methods for forming and releasing microelectromechanical structures
US6290864B1 (en) * 1999-10-26 2001-09-18 Reflectivity, Inc. Fluoride gas etching of silicon with improved selectivity
US7041224B2 (en) * 1999-10-26 2006-05-09 Reflectivity, Inc. Method for vapor phase etching of silicon
US6949202B1 (en) 1999-10-26 2005-09-27 Reflectivity, Inc Apparatus and method for flow of process gas in an ultra-clean environment
KR100327341B1 (en) * 1999-10-27 2002-03-06 윤종용 Method for manufacturing semiconductor device using polysilicon hard mask and apparatus for the same
US6500356B2 (en) * 2000-03-27 2002-12-31 Applied Materials, Inc. Selectively etching silicon using fluorine without plasma
US20030010354A1 (en) * 2000-03-27 2003-01-16 Applied Materials, Inc. Fluorine process for cleaning semiconductor process chamber
US7019376B2 (en) * 2000-08-11 2006-03-28 Reflectivity, Inc Micromirror array device with a small pitch size
US6843258B2 (en) * 2000-12-19 2005-01-18 Applied Materials, Inc. On-site cleaning gas generation for process chamber cleaning
US6503845B1 (en) * 2001-05-01 2003-01-07 Applied Materials Inc. Method of etching a tantalum nitride layer in a high density plasma
WO2002095800A2 (en) * 2001-05-22 2002-11-28 Reflectivity, Inc. A method for making a micromechanical device by removing a sacrificial layer with multiple sequential etchants
US7189332B2 (en) 2001-09-17 2007-03-13 Texas Instruments Incorporated Apparatus and method for detecting an endpoint in a vapor phase etch
US20030073302A1 (en) * 2001-10-12 2003-04-17 Reflectivity, Inc., A California Corporation Methods for formation of air gap interconnects
US6835616B1 (en) 2002-01-29 2004-12-28 Cypress Semiconductor Corporation Method of forming a floating metal structure in an integrated circuit
US7026235B1 (en) 2002-02-07 2006-04-11 Cypress Semiconductor Corporation Dual-damascene process and associated floating metal structures
US6649535B1 (en) * 2002-02-12 2003-11-18 Taiwan Semiconductor Manufacturing Company Method for ultra-thin gate oxide growth
US7027200B2 (en) * 2002-03-22 2006-04-11 Reflectivity, Inc Etching method used in fabrications of microstructures
US6965468B2 (en) * 2003-07-03 2005-11-15 Reflectivity, Inc Micromirror array having reduced gap between adjacent micromirrors of the micromirror array
US7781850B2 (en) 2002-09-20 2010-08-24 Qualcomm Mems Technologies, Inc. Controlling electromechanical behavior of structures within a microelectromechanical systems device
WO2004026804A1 (en) 2002-09-20 2004-04-01 Integrated Dna Technologies, Inc. Anthraquinone quencher dyes, their methods of preparation and use
US6730600B2 (en) * 2002-09-27 2004-05-04 Agere Systems, Inc. Method of dry etching a semiconductor device in the absence of a plasma
US6913942B2 (en) 2003-03-28 2005-07-05 Reflectvity, Inc Sacrificial layers for use in fabrications of microelectromechanical devices
US6980347B2 (en) * 2003-07-03 2005-12-27 Reflectivity, Inc Micromirror having reduced space between hinge and mirror plate of the micromirror
US7645704B2 (en) * 2003-09-17 2010-01-12 Texas Instruments Incorporated Methods and apparatus of etch process control in fabrications of microstructures
US6939472B2 (en) * 2003-09-17 2005-09-06 Reflectivity, Inc. Etching method in fabrications of microstructures
WO2006014929A1 (en) * 2004-07-29 2006-02-09 Idc, Llc System and method for micro-electromechanical operating of an interferometric modulator
US7944599B2 (en) * 2004-09-27 2011-05-17 Qualcomm Mems Technologies, Inc. Electromechanical device with optical function separated from mechanical and electrical function
US7372613B2 (en) 2004-09-27 2008-05-13 Idc, Llc Method and device for multistate interferometric light modulation
US7420725B2 (en) 2004-09-27 2008-09-02 Idc, Llc Device having a conductive light absorbing mask and method for fabricating same
US7130104B2 (en) * 2004-09-27 2006-10-31 Idc, Llc Methods and devices for inhibiting tilting of a mirror in an interferometric modulator
US7936497B2 (en) * 2004-09-27 2011-05-03 Qualcomm Mems Technologies, Inc. MEMS device having deformable membrane characterized by mechanical persistence
US7304784B2 (en) * 2004-09-27 2007-12-04 Idc, Llc Reflective display device having viewable display on both sides
US7289259B2 (en) * 2004-09-27 2007-10-30 Idc, Llc Conductive bus structure for interferometric modulator array
US7527995B2 (en) * 2004-09-27 2009-05-05 Qualcomm Mems Technologies, Inc. Method of making prestructure for MEMS systems
US7564612B2 (en) * 2004-09-27 2009-07-21 Idc, Llc Photonic MEMS and structures
US8008736B2 (en) 2004-09-27 2011-08-30 Qualcomm Mems Technologies, Inc. Analog interferometric modulator device
US7630119B2 (en) * 2004-09-27 2009-12-08 Qualcomm Mems Technologies, Inc. Apparatus and method for reducing slippage between structures in an interferometric modulator
US7583429B2 (en) 2004-09-27 2009-09-01 Idc, Llc Ornamental display device
US7226869B2 (en) * 2004-10-29 2007-06-05 Lam Research Corporation Methods for protecting silicon or silicon carbide electrode surfaces from morphological modification during plasma etch processing
US7192875B1 (en) 2004-10-29 2007-03-20 Lam Research Corporation Processes for treating morphologically-modified silicon electrode surfaces using gas-phase interhalogens
US7291286B2 (en) * 2004-12-23 2007-11-06 Lam Research Corporation Methods for removing black silicon and black silicon carbide from surfaces of silicon and silicon carbide electrodes for plasma processing apparatuses
TW200628877A (en) * 2005-02-04 2006-08-16 Prime View Int Co Ltd Method of manufacturing optical interference type color display
US7884989B2 (en) * 2005-05-27 2011-02-08 Qualcomm Mems Technologies, Inc. White interferometric modulators and methods for forming the same
KR20080040715A (en) * 2005-07-22 2008-05-08 콸콤 인코포레이티드 Support structure for mems device and methods therefor
EP2495212A3 (en) * 2005-07-22 2012-10-31 QUALCOMM MEMS Technologies, Inc. Mems devices having support structures and methods of fabricating the same
DE102005047081B4 (en) * 2005-09-30 2019-01-31 Robert Bosch Gmbh Process for the plasma-free etching of silicon with the etching gas ClF3 or XeF2
US7795061B2 (en) * 2005-12-29 2010-09-14 Qualcomm Mems Technologies, Inc. Method of creating MEMS device cavities by a non-etching process
US7863197B2 (en) * 2006-01-09 2011-01-04 International Business Machines Corporation Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification
US7916980B2 (en) 2006-01-13 2011-03-29 Qualcomm Mems Technologies, Inc. Interconnect structure for MEMS device
US7382515B2 (en) 2006-01-18 2008-06-03 Qualcomm Mems Technologies, Inc. Silicon-rich silicon nitrides as etch stops in MEMS manufacture
US7550810B2 (en) * 2006-02-23 2009-06-23 Qualcomm Mems Technologies, Inc. MEMS device having a layer movable at asymmetric rates
US7450295B2 (en) * 2006-03-02 2008-11-11 Qualcomm Mems Technologies, Inc. Methods for producing MEMS with protective coatings using multi-component sacrificial layers
US7649671B2 (en) * 2006-06-01 2010-01-19 Qualcomm Mems Technologies, Inc. Analog interferometric modulator device with electrostatic actuation and release
KR101094913B1 (en) * 2006-06-09 2011-12-16 소이텍 Manufacturing process system for forming a group iii-v semiconductor material
US7527998B2 (en) * 2006-06-30 2009-05-05 Qualcomm Mems Technologies, Inc. Method of manufacturing MEMS devices providing air gap control
EP2066496B1 (en) 2006-11-22 2013-04-10 Soitec Equipment for high volume manufacture of group iii-v semiconductor materials
ATE546570T1 (en) 2006-11-22 2012-03-15 Soitec Silicon On Insulator METHOD FOR EPITACTICAL DEPOSITION OF SINGLE CRYSTALLINE III-V SEMICONDUCTOR MATERIAL
US9481944B2 (en) 2006-11-22 2016-11-01 Soitec Gas injectors including a funnel- or wedge-shaped channel for chemical vapor deposition (CVD) systems and CVD systems with the same
US8545628B2 (en) 2006-11-22 2013-10-01 Soitec Temperature-controlled purge gate valve for chemical vapor deposition chamber
US9481943B2 (en) 2006-11-22 2016-11-01 Soitec Gallium trichloride injection scheme
WO2008064077A2 (en) * 2006-11-22 2008-05-29 S.O.I.Tec Silicon On Insulator Technologies Methods for high volume manufacture of group iii-v semiconductor materials
JP5656184B2 (en) 2006-11-22 2015-01-21 ソイテック Gallium trichloride injection system
WO2008064080A1 (en) * 2006-11-22 2008-05-29 S.O.I.Tec Silicon On Insulator Technologies High volume delivery system for gallium trichloride
US8115987B2 (en) * 2007-02-01 2012-02-14 Qualcomm Mems Technologies, Inc. Modulating the intensity of light from an interferometric reflector
US7733552B2 (en) * 2007-03-21 2010-06-08 Qualcomm Mems Technologies, Inc MEMS cavity-coating layers and methods
US7643202B2 (en) * 2007-05-09 2010-01-05 Qualcomm Mems Technologies, Inc. Microelectromechanical system having a dielectric movable membrane and a mirror
US7719752B2 (en) * 2007-05-11 2010-05-18 Qualcomm Mems Technologies, Inc. MEMS structures, methods of fabricating MEMS components on separate substrates and assembly of same
US7630121B2 (en) * 2007-07-02 2009-12-08 Qualcomm Mems Technologies, Inc. Electromechanical device with optical function separated from mechanical and electrical function
CN101809471B (en) 2007-07-31 2013-12-25 高通Mems科技公司 Devices for enhancing colour shift of interferometric modulators
US7773286B2 (en) * 2007-09-14 2010-08-10 Qualcomm Mems Technologies, Inc. Periodic dimple array
US7847999B2 (en) 2007-09-14 2010-12-07 Qualcomm Mems Technologies, Inc. Interferometric modulator display devices
US20090078316A1 (en) * 2007-09-24 2009-03-26 Qualcomm Incorporated Interferometric photovoltaic cell
JP5209727B2 (en) * 2007-10-19 2013-06-12 クォルコム・メムズ・テクノロジーズ・インコーポレーテッド Display with integrated photovoltaic device
US8058549B2 (en) * 2007-10-19 2011-11-15 Qualcomm Mems Technologies, Inc. Photovoltaic devices with integrated color interferometric film stacks
EP2203765A1 (en) * 2007-10-23 2010-07-07 Qualcomm Mems Technologies, Inc. Adjustably transmissive mems-based devices
US20090293955A1 (en) * 2007-11-07 2009-12-03 Qualcomm Incorporated Photovoltaics with interferometric masks
US8941631B2 (en) * 2007-11-16 2015-01-27 Qualcomm Mems Technologies, Inc. Simultaneous light collection and illumination on an active display
US7906274B2 (en) * 2007-11-21 2011-03-15 Molecular Imprints, Inc. Method of creating a template employing a lift-off process
EP2231898A2 (en) * 2007-12-20 2010-09-29 S.O.I.Tec Silicon on Insulator Technologies Methods for in-situ chamber cleaning process for high volume manufacture of semiconductor materials
CA2710198A1 (en) * 2007-12-21 2009-07-09 Qualcomm Mems Technologies, Inc. Multijunction photovoltaic cells
TWI619153B (en) 2008-02-11 2018-03-21 恩特葛瑞斯股份有限公司 Ion source cleaning in semiconductor processing systems
US8164821B2 (en) * 2008-02-22 2012-04-24 Qualcomm Mems Technologies, Inc. Microelectromechanical device with thermal expansion balancing layer or stiffening layer
US7944604B2 (en) * 2008-03-07 2011-05-17 Qualcomm Mems Technologies, Inc. Interferometric modulator in transmission mode
US7612933B2 (en) * 2008-03-27 2009-11-03 Qualcomm Mems Technologies, Inc. Microelectromechanical device with spacing layer
US7898723B2 (en) * 2008-04-02 2011-03-01 Qualcomm Mems Technologies, Inc. Microelectromechanical systems display element with photovoltaic structure
US7969638B2 (en) * 2008-04-10 2011-06-28 Qualcomm Mems Technologies, Inc. Device having thin black mask and method of fabricating the same
US7851239B2 (en) * 2008-06-05 2010-12-14 Qualcomm Mems Technologies, Inc. Low temperature amorphous silicon sacrificial layer for controlled adhesion in MEMS devices
US8023167B2 (en) * 2008-06-25 2011-09-20 Qualcomm Mems Technologies, Inc. Backlight displays
US7859740B2 (en) * 2008-07-11 2010-12-28 Qualcomm Mems Technologies, Inc. Stiction mitigation with integrated mech micro-cantilevers through vertical stress gradient control
US8358266B2 (en) * 2008-09-02 2013-01-22 Qualcomm Mems Technologies, Inc. Light turning device with prismatic light turning features
US20100096011A1 (en) * 2008-10-16 2010-04-22 Qualcomm Mems Technologies, Inc. High efficiency interferometric color filters for photovoltaic modules
WO2010044901A1 (en) * 2008-10-16 2010-04-22 Qualcomm Mems Technologies, Inc. Monolithic imod color enhanced photovoltaic cell
US8270056B2 (en) * 2009-03-23 2012-09-18 Qualcomm Mems Technologies, Inc. Display device with openings between sub-pixels and method of making same
US9121979B2 (en) * 2009-05-29 2015-09-01 Qualcomm Mems Technologies, Inc. Illumination devices and methods of fabrication thereof
US8270062B2 (en) * 2009-09-17 2012-09-18 Qualcomm Mems Technologies, Inc. Display device with at least one movable stop element
US8488228B2 (en) 2009-09-28 2013-07-16 Qualcomm Mems Technologies, Inc. Interferometric display with interferometric reflector
KR20130100232A (en) 2010-04-09 2013-09-10 퀄컴 엠이엠에스 테크놀로지스, 인크. Mechanical layer of an electromechanical device and methods of forming the same
JP5123349B2 (en) * 2010-04-19 2013-01-23 Ｈｏｙａ株式会社 Multi-tone mask manufacturing method
JP2013544370A (en) 2010-08-17 2013-12-12 クォルコム・メムズ・テクノロジーズ・インコーポレーテッド Operation and calibration of charge neutral electrodes in interference display devices
US9057872B2 (en) 2010-08-31 2015-06-16 Qualcomm Mems Technologies, Inc. Dielectric enhanced mirror for IMOD display
US8963159B2 (en) 2011-04-04 2015-02-24 Qualcomm Mems Technologies, Inc. Pixel via and methods of forming the same
US9134527B2 (en) 2011-04-04 2015-09-15 Qualcomm Mems Technologies, Inc. Pixel via and methods of forming the same
US8659816B2 (en) 2011-04-25 2014-02-25 Qualcomm Mems Technologies, Inc. Mechanical layer and methods of making the same
US8736939B2 (en) 2011-11-04 2014-05-27 Qualcomm Mems Technologies, Inc. Matching layer thin-films for an electromechanical systems reflective display device
JP7053991B2 (en) * 2017-03-28 2022-04-13 セントラル硝子株式会社 Dry etching method, semiconductor device manufacturing method and chamber cleaning method
JPWO2021171986A1 (en) * 2020-02-26 2021-09-02

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB952543A (en) * 1961-03-07 1964-03-18 Western Electric Co Shaping of bodies by etching
NL275192A (en) * 1961-06-30
US3095341A (en) * 1961-06-30 1963-06-25 Bell Telephone Labor Inc Photosensitive gas phase etching of semiconductors by selective radiation
US3511727A (en) * 1967-05-08 1970-05-12 Motorola Inc Vapor phase etching and polishing of semiconductors
BE756807A (en) * 1969-09-29 1971-03-29 Motorola Inc PROCESS FOR NON-PREFERENTIAL ENGRAVING OF SILICON BY A GAS MIXTURE, AND GAS MIXTURE FOR THIS ENGRAVING
US3669774A (en) * 1969-11-20 1972-06-13 Rca Corp Low temperature silicon etch
JPS6012779B2 (en) * 1976-04-28 1985-04-03 株式会社日立製作所 Manufacturing method of semiconductor device
US4310380A (en) * 1980-04-07 1982-01-12 Bell Telephone Laboratories, Incorporated Plasma etching of silicon
US4314875A (en) * 1980-05-13 1982-02-09 Bell Telephone Laboratories, Incorporated Device fabrication by plasma etching
JPS57193035A (en) * 1981-05-22 1982-11-27 Toshiba Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
GB2144083A (en) 1985-02-27
GB8418797D0 (en) 1984-08-30
KR850000775A (en) 1985-03-09
HK37388A (en) 1988-05-27
FR2551583B1 (en) 1988-09-09
DE3427599C2 (en) 1990-07-05
FR2551583A1 (en) 1985-03-08
NL8402360A (en) 1985-02-18
JPS6053027A (en) 1985-03-26
KR900001664B1 (en) 1990-03-17
GB2144083B (en) 1986-11-26
DE3427599A1 (en) 1985-02-07
US4498953A (en) 1985-02-12

Similar Documents

Publication Publication Date Title
CA1235630A (en) Etching techniques
EP0801606B1 (en) Method for treating a surface
US5716495A (en) Cleaning method
EP0008347B1 (en) A method of etching a surface
US6635185B2 (en) Method of etching and cleaning using fluorinated carbonyl compounds
US6500356B2 (en) Selectively etching silicon using fluorine without plasma
US4361461A (en) Hydrogen etching of semiconductors and oxides
US4431477A (en) Plasma etching with nitrous oxide and fluoro compound gas mixture
EP1788120A1 (en) Removal of titanium nitride with xenon difluoride
US4605479A (en) In-situ cleaned ohmic contacts
US8278222B2 (en) Selective etching and formation of xenon difluoride
US4264409A (en) Contamination-free selective reactive ion etching or polycrystalline silicon against silicon dioxide
US4226666A (en) Etching method employing radiation and noble gas halide
US4836887A (en) Chlorofluorocarbon additives for enhancing etch rates in fluorinated halocarbon/oxidant plasmas
JP3300632B2 (en) Semiconductor device etching method
TWI475611B (en) Selective etching and formation of xenon difluoride
US6162733A (en) Method for removing contaminants from integrated circuits
GB2183204A (en) Nitrogen trifluoride as an in-situ cleaning agent
KR101977132B1 (en) Method for Dry Etching of Copper Thin Films
US6559060B2 (en) Process for the structuring of a substrate
JPH07193055A (en) Dry etching method
JPH0218577B2 (en)
JPH0290521A (en) Manufacture of semiconductor device
WO1999044227A1 (en) Surface treating agent for micromachining and method for surface treatment
WO1999034428A1 (en) Method of etching and cleaning using interhalogen compounds

Legal Events

Date Code Title Description
MKEX Expiry