CA1236534A - Vco centering circuit - Google Patents
Vco centering circuitInfo
- Publication number
- CA1236534A CA1236534A CA000481997A CA481997A CA1236534A CA 1236534 A CA1236534 A CA 1236534A CA 000481997 A CA000481997 A CA 000481997A CA 481997 A CA481997 A CA 481997A CA 1236534 A CA1236534 A CA 1236534A
- Authority
- CA
- Canada
- Prior art keywords
- vco
- frequency
- operable
- oscillator
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
Abstract
VCO CENTERING CIRCUIT
ABSTRACT OF THE DISCLOSURE
A circuit arrangement for recovering data from a communications network includes a phase lock loop (PLL) with a voltage controlled oscillator (VCO) and a circuit for automatically centering the VCO. The circuit arrangement includes a counter that stores a changeable digital word.
The digital word provides an adjustable current for driving the VCO. Initially, the VCO is driven so that its output signal falls within a predetermined frequency range. An error voltage representing the difference between a pre-determined voltage range is developed and is used to change the contents of the counter until the VCO is centered.
Thereafter the count that causes centering of the VCO is locked in the counter and normal PLL function is enabled.
ABSTRACT OF THE DISCLOSURE
A circuit arrangement for recovering data from a communications network includes a phase lock loop (PLL) with a voltage controlled oscillator (VCO) and a circuit for automatically centering the VCO. The circuit arrangement includes a counter that stores a changeable digital word.
The digital word provides an adjustable current for driving the VCO. Initially, the VCO is driven so that its output signal falls within a predetermined frequency range. An error voltage representing the difference between a pre-determined voltage range is developed and is used to change the contents of the counter until the VCO is centered.
Thereafter the count that causes centering of the VCO is locked in the counter and normal PLL function is enabled.
Description
~Z3~3~
RA9~4023 VCO CENTERING CIRCUIT
Background of the Invention 1. Field of the Invention The invention relates to phase lock loops in general and more particularly to apparatus for centering the Voltage Control Oscillator (VCO).
RA9~4023 VCO CENTERING CIRCUIT
Background of the Invention 1. Field of the Invention The invention relates to phase lock loops in general and more particularly to apparatus for centering the Voltage Control Oscillator (VCO).
2. Prior Art , The use of phase lock loops in various types of commun-ication systems is well known in the prior art. A typical phase lock loop consists of a phase comparator, a loop ; filter and a voltage controlled oscillator (VCO). The phase comparator compares the phase of an input reference signal with the phase of the VCO and generates an error voltage which is used to drive the VCO until it is phase locked with the input reference signal. It is desirable to have as large a dynamic range of correction voltage as possible.
This would allow the ma~imum correction for phase transients and frequency variations in the reference signal.
O
In integrated circuit technology r design of VCO cir-cuits usually has a variation in the natural frequency (fc) of ~ 8%. In addition, the timing capacitor which is an integral part of the VCO usually has a tolerance of + 5%.
As a result, the VCO natural frequency will vary by ~ 13%.
The variation means that as the PLL locks onto an input signal, at a particular frequency, the VCO will be forced to that frequency by an adjustment in the correction voltage at its input. This consumes a large part of the availa~le voltage range and limits the dynamic range of the PLL for ~3,, "~"
~Z3653~
tracking phase and/or frequency changes in the incoming signal.
In the past using up a large part of the available voltage range presents no problems since linear circuits were designed using voltages with a potential difference of at least 10 volts. In cases where the optimum range was required, a potentiometer was used to adjust the VCO to the desired frequency when the input voltage was at the center of the allowed range.
There are several technologies in which the ranye of voltages available for adjustin~ the VCO is relatively narrow. For example, in a VLSI chip a potential difference of 4.5 volts or less is available. In addition, there is an effort in the C~OS technology to design chips comprising of logic circuits, processors and memories. It is believed that these designs will probably have a larger variation in the natural frequency (fc) of the VCO. In fact, it is believed that as the integration and/or compaction of devices on a single chip increase, the variation in the natural frequency of the VCO will also increase. The use of a potentiometer to manually set the center frequency is very undesirable. With the variation in the natural frequency of the VCO and ~he limited range for the correction volta~e, it is obvious that some efficient method is needed to adjust the center frequency of the VCO.
Summary of the Invention It is therefore the general object of the present invention to provide a more efficient PLL apparatus than was heretofore possible.
It is still another object of the present invention to provide a PLL with a device and method for automatically adjusting the fc (center frequency) of the VCO.
At the start of an adjustment cycle the VCO in the PLL
is forced to operate at the frequency of a local crystal.
lZ3653a~
Preferably, the frequency is equivalent to the nominal frequency of the input signal. An error voltage is devel-oped and is compared to the voltage available for adjusting the VCO. Preferably, the voltage should be at the midpoint of the adjustment range. If the error voltage falls outside of an allowable range, a counter means is activated and provides a bias current which drives the VCO. The process of forcing the VCO to the crystal rrequency and comparing the correction or error voltage is repeated until ths compare means finds that the VCO correction voltage falls within the allowable range whereupon the proper bias current is locked into the counter means.
In one feature of the invention, means is provided for issuing a signal indicating that the adjustment is complete and the normal PLL function is enabled.
Brief Description of the Drawings Fig. 1 shows a block diagram of an improved PLL accord-ing to the teachings of the present invention.
Fig. 2 shows the details of a circuit for adjusting the center frequency o~ the PLL.
Detailed Description of the Preferred Embodiment Fig. 1 shows a block diagram of a circuit arrangement embodying the teaching of the present invention. The circuit arrangement cornprises of a phase locked lo~p identi-fied by numeral lO, a local oscillator centering circuit means 12 connected by conductors 14 and 16, respectively, to the phase locked loop and a signal indicating means 18 connected by conductors 20, 22, and 24, respectively, to the phase locked loop and the local oscillator centering circuit means 12. The phase locked loop 10 receives data on the received data line and adjusts the frequency of current control oscillator 26 until the phase of the output signal from the current control oscillator locks onto the phase of the incoming data signal. Thereafter, a signal labeled ~Z3~534 ~A~84023 4 recovered clock is outputted on conductor 28. The local oscillator centering circuit means 12, when activated by a control signal on the line identified as frequency acquisi-tion line, initiates a series of adjustment routines until a suitable bisync current is outputted on conductor 16. The bisync current is sufficient to drive the current control oscillator so that the output frequency-is positioned at the free-running frequency of the oscillator. Although obvious to those skilled in the art, it should be noted that current controlled oscillator 26, amplifier means 50 and summing means 52 may be identified as VCO 51.
Thereafter, the signal indicating means 18 monitors the condition on the phase locked loop and whenever the center-ing routine is completed outputs a ready signal on conductor 30. Thereafter, the phase locked loop ils enabled to run in its normal operating condition. The adjustment routine which is provided by local oscillator centering circuit means 12 allows the full range of the available voltage to be used in adjusting the current control oscillator to lock onto the incoming data and as a result improves the opera-tional characteristics of the phase lock loop.
Still referring to Fig. 1, the phase lock loop 10 comprises of a current control oscillator 26 having con-ductor 28 connected to its ou-tput terminal and conductor 30 connected to its input terminal. A feedback conductor identified by numeral 32 connects the output terminal of the current controlled oscillator to one of the inputs on phase detector means 34 and frequency detector means 36. In particular, the phase detector means 34 accepts the feedback signal from the current controlled oscillator and compares it with input data signal on the received data line.
Whenever there is a phase difference between the signals, the phase detector means outputs a voltage signal on conduc-tor 38.
Likewise, frequency detector means 36 accepts the feedback signal from current controlled oscillator 26, compares it with a control signal on the crystal (xtal) ~3~;S3~
r~Ag8~023 5 frequency line and whenever there is a difference in the fre~uency outputs a signal on conductor ~0. The signals on conductor 38 and 40 are fed into Multiple~or (~lUX) means 42.
The multiplexor means 42 is a conventional off-the-shelf multiple~ing device and as such the details will not be given. The multiplexing means 42 is controlled by a series of control pulses outputted on the frequency acquisition line. Depending on the signal on the frequency acquisition line, the multiplexing means 42 is cause to select the output of either the phase detector means 34 or the output of the frequency detector means 36. The signal which is selected is fed over conductor 44 into charge pump means 46.
The charge pump means 46 is a conventional off-the-shelf device and the details will not be given. Output signals from the charge pump means 46 are fed over conductor 48 into amplifier means 50. The amplifier means 50 accepts a signal from conductor 48, amplifies the signal and drives the signal into summing means 52 from whence it adjusts the current into the current controlled oscillator, thereby forcing the oscillator into lock with incoming signals.
Still referring to Fig. 1, signal indicating means 18 comprises AND cir~uit means 54 which is connected to energy detection means 56 and phase lock loop (PLL) detecting means 58 over conductors 60 and 62, respectively. The o~tput from energy detection means 56 is connected over conductor 24 to phase detector 34. The energy detection 56 monitors the output of phase detector means 34 and outputs a signal on terminal 60 when energy is outputted from the phase detector means. Similarly, phase lock loop lock detection means 58 is connected by conductor 22 to the output of charge pump means 46. The function of the phase lock loop lock detec-tion means 58 is to indicate, by means o~ outputting a signal on terminal 62, when the loop is not locked. The signals on conductors 60 and 62 are combined in ~ND circuit means 54 to generate a ready signal on conductor 30.
Fig. 2 shows the details of the local oscillator centering circuit means 12. In order to simplify the description, coMmon numerals are used to identify elements 1~236~34~
P~ 4 0 2 3 6 which are common to both Figs. 1 and 2. The local oscilla-tor centering circuit means 12 comprises of a pair of comparators identified by numerals 60 and 62. The corn-parators are used to set a ~oltage reference window within which the phase locked loop filter voltage must be posi-tioned in order the ~requency of the output signal, from the control oscillator, is positioned about its center fre-quency. As will be explained subsequently, once ~he phase locked loop filter voltage is positioned within this window, the bias voltage which provides the current on conductor 16 is locked into place and thereafter the loop is energized for normal operation. In the preferred embodiment of this invention the voltage available for driving the controlled oscillator is approximately 5V distributed on both the positive and the negative directions relative to a 0 voltage reference line. With this distribution comparator 60 which sets the upper limit of the window is supplied with a 2.5V
+~ on conductor 64. Similarly, comparator 62 sets the lower limit of the window and is supplied with a voltage value 2.5V - ~on conductor 66. It should be no~ed that the comparators may be used to set a voltage window other than 5V. Therefore, the use of 5V as a desirable voltage window is only representative of a particular voltage range and ought not to be construed as a limitation of the scope oE
~5 the present invention.
The output signals from comparators 60 and 62 are fed over conductors 68 and 70, respectively, into AND blocks 71 and 72. With the aid of a control signal on conductor 74 (to be described later) AND blocks 71 and 72 generate the increment counter pulses on conductor 76 and the decrement counter pulses on conductor 80. The increment/decrement pulses are fed into counter 82. As will be explained subsequently, counter 82 is used as a variable register to hold a digital word corresponding to the bias current which is used to center the control oscillator. The output from counter 82 is fed over conductor 84 into digital to analog (D/A) converter 86. The D/A converter converts the digital words stored in the counter to a corresponding bias current which is fed over conductor 16 into summin~ means 52.
~Z36S3~
R~4Q23 7 Still referring to Fig. 2, a clock pulse and a reset pulse are generated and applied to counter 82 on conductors 88 and 90, respectively. The clock pulse is used for stepping the counter and is generated from AND block 73.
The input into ~D block 73 is from a low frequency oscilla-tor and a controlled signal (to be described later) gener-ated on conductor 74. Likewise, the reset pulse on conduc-tor 90 is enabled to reset the counter at the beginning of an adjustment cycle and is generated from single shot (SS) circuit 9?. The single shot circuit is activated by the control signals on conductor 74. The control signal on conductor 74 is generated from the Q output of a D type latch identified by numeral 94. The latch is the primary controller ~or the centering circuit 12. To this end, the latch detects whenever the input signal "frequency acquisi-tion" mode is selected. This selection is indicated by placing a control pulse on the frequency acquisition line.
The pulse sets the counter and starts a new bias adjustment cycle to center the local oscillator. The latch is reset with a pulse generated from OR circuit block 96. The OR
block detects when both comparators are indicating that the phase lock loop correction voltage is within the desired window. The pulse is delayed by delay block 98 from whence it is fed over conductor 100 into the reset terminal o~ the latch. A supply ~oltage ~Vcc is provided on the data (D) terminal o~ the latch.
O~eration The circuit arrangement operates as follows:
.
When the signal on the frequency acquisition line (Fig.
2) goes from the low "phase detector" mode to the high "frequency detector" mode, latch 94 is triggered. The data (D) input is tied to +VCC so that the Q output goes high.
This enables the increment/decrement gates 71 and 72, respectively, and the clock gate 73. Also, the single shot 92 is triggered causing the counter to preset to its mid-range. The D/A converter establishes a DC bias current is established on conductor 16 and is summed ~ith the 36S3~
~84023 8 current on conductor 29. The current on conductor 29 is obtained from the amplifier stage of the phase lock loop.
The phase lock loop in frequency acquisition mode will drive the voltage on the filter until the crystal frequency is acqulred. If the voltage filter is not within the window set by 2.5V + ~or 2.5V ~~ then either the increment or decrement gate is enabled. This drives the counter in the direction to achieve 2.5V when the VCO is at the crystal frequency.
Similarly, the low frequency oscillator is at a fre-quency 10W enough to allow frequency acquisition at each new DC bias current, thus after each clock pulse the system will settle at the crystal frequency. The phase lock filter voltage will be compared to the window and additional steps will be taken until the window voltage is reached. At this time the latch will be reset so that the Q output is low, holding the counter at the value that gives proper bias current towards either window voltage and the phase locked filter. The ~ output enables one leg of the AND circuit 54.
When the lock and energy detect circuits are satisfied, a ready signal is forwarded to the system. The VCO natural frequency has now been adjusted to the desired frequency with its input volta~e at the mid-range point.
The described circuit arrangement elin~inates the deviation from the middle of the VCO input range and allows lower gain VCO circuits. Another benefit is that the above-described system can be integrated into an LSI chip design and does not require any more card space. In addi-tion, the available signal range is expanded by a factor of 4 or 5.
Although the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those s]cilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inven-tion.
This would allow the ma~imum correction for phase transients and frequency variations in the reference signal.
O
In integrated circuit technology r design of VCO cir-cuits usually has a variation in the natural frequency (fc) of ~ 8%. In addition, the timing capacitor which is an integral part of the VCO usually has a tolerance of + 5%.
As a result, the VCO natural frequency will vary by ~ 13%.
The variation means that as the PLL locks onto an input signal, at a particular frequency, the VCO will be forced to that frequency by an adjustment in the correction voltage at its input. This consumes a large part of the availa~le voltage range and limits the dynamic range of the PLL for ~3,, "~"
~Z3653~
tracking phase and/or frequency changes in the incoming signal.
In the past using up a large part of the available voltage range presents no problems since linear circuits were designed using voltages with a potential difference of at least 10 volts. In cases where the optimum range was required, a potentiometer was used to adjust the VCO to the desired frequency when the input voltage was at the center of the allowed range.
There are several technologies in which the ranye of voltages available for adjustin~ the VCO is relatively narrow. For example, in a VLSI chip a potential difference of 4.5 volts or less is available. In addition, there is an effort in the C~OS technology to design chips comprising of logic circuits, processors and memories. It is believed that these designs will probably have a larger variation in the natural frequency (fc) of the VCO. In fact, it is believed that as the integration and/or compaction of devices on a single chip increase, the variation in the natural frequency of the VCO will also increase. The use of a potentiometer to manually set the center frequency is very undesirable. With the variation in the natural frequency of the VCO and ~he limited range for the correction volta~e, it is obvious that some efficient method is needed to adjust the center frequency of the VCO.
Summary of the Invention It is therefore the general object of the present invention to provide a more efficient PLL apparatus than was heretofore possible.
It is still another object of the present invention to provide a PLL with a device and method for automatically adjusting the fc (center frequency) of the VCO.
At the start of an adjustment cycle the VCO in the PLL
is forced to operate at the frequency of a local crystal.
lZ3653a~
Preferably, the frequency is equivalent to the nominal frequency of the input signal. An error voltage is devel-oped and is compared to the voltage available for adjusting the VCO. Preferably, the voltage should be at the midpoint of the adjustment range. If the error voltage falls outside of an allowable range, a counter means is activated and provides a bias current which drives the VCO. The process of forcing the VCO to the crystal rrequency and comparing the correction or error voltage is repeated until ths compare means finds that the VCO correction voltage falls within the allowable range whereupon the proper bias current is locked into the counter means.
In one feature of the invention, means is provided for issuing a signal indicating that the adjustment is complete and the normal PLL function is enabled.
Brief Description of the Drawings Fig. 1 shows a block diagram of an improved PLL accord-ing to the teachings of the present invention.
Fig. 2 shows the details of a circuit for adjusting the center frequency o~ the PLL.
Detailed Description of the Preferred Embodiment Fig. 1 shows a block diagram of a circuit arrangement embodying the teaching of the present invention. The circuit arrangement cornprises of a phase locked lo~p identi-fied by numeral lO, a local oscillator centering circuit means 12 connected by conductors 14 and 16, respectively, to the phase locked loop and a signal indicating means 18 connected by conductors 20, 22, and 24, respectively, to the phase locked loop and the local oscillator centering circuit means 12. The phase locked loop 10 receives data on the received data line and adjusts the frequency of current control oscillator 26 until the phase of the output signal from the current control oscillator locks onto the phase of the incoming data signal. Thereafter, a signal labeled ~Z3~534 ~A~84023 4 recovered clock is outputted on conductor 28. The local oscillator centering circuit means 12, when activated by a control signal on the line identified as frequency acquisi-tion line, initiates a series of adjustment routines until a suitable bisync current is outputted on conductor 16. The bisync current is sufficient to drive the current control oscillator so that the output frequency-is positioned at the free-running frequency of the oscillator. Although obvious to those skilled in the art, it should be noted that current controlled oscillator 26, amplifier means 50 and summing means 52 may be identified as VCO 51.
Thereafter, the signal indicating means 18 monitors the condition on the phase locked loop and whenever the center-ing routine is completed outputs a ready signal on conductor 30. Thereafter, the phase locked loop ils enabled to run in its normal operating condition. The adjustment routine which is provided by local oscillator centering circuit means 12 allows the full range of the available voltage to be used in adjusting the current control oscillator to lock onto the incoming data and as a result improves the opera-tional characteristics of the phase lock loop.
Still referring to Fig. 1, the phase lock loop 10 comprises of a current control oscillator 26 having con-ductor 28 connected to its ou-tput terminal and conductor 30 connected to its input terminal. A feedback conductor identified by numeral 32 connects the output terminal of the current controlled oscillator to one of the inputs on phase detector means 34 and frequency detector means 36. In particular, the phase detector means 34 accepts the feedback signal from the current controlled oscillator and compares it with input data signal on the received data line.
Whenever there is a phase difference between the signals, the phase detector means outputs a voltage signal on conduc-tor 38.
Likewise, frequency detector means 36 accepts the feedback signal from current controlled oscillator 26, compares it with a control signal on the crystal (xtal) ~3~;S3~
r~Ag8~023 5 frequency line and whenever there is a difference in the fre~uency outputs a signal on conductor ~0. The signals on conductor 38 and 40 are fed into Multiple~or (~lUX) means 42.
The multiplexor means 42 is a conventional off-the-shelf multiple~ing device and as such the details will not be given. The multiplexing means 42 is controlled by a series of control pulses outputted on the frequency acquisition line. Depending on the signal on the frequency acquisition line, the multiplexing means 42 is cause to select the output of either the phase detector means 34 or the output of the frequency detector means 36. The signal which is selected is fed over conductor 44 into charge pump means 46.
The charge pump means 46 is a conventional off-the-shelf device and the details will not be given. Output signals from the charge pump means 46 are fed over conductor 48 into amplifier means 50. The amplifier means 50 accepts a signal from conductor 48, amplifies the signal and drives the signal into summing means 52 from whence it adjusts the current into the current controlled oscillator, thereby forcing the oscillator into lock with incoming signals.
Still referring to Fig. 1, signal indicating means 18 comprises AND cir~uit means 54 which is connected to energy detection means 56 and phase lock loop (PLL) detecting means 58 over conductors 60 and 62, respectively. The o~tput from energy detection means 56 is connected over conductor 24 to phase detector 34. The energy detection 56 monitors the output of phase detector means 34 and outputs a signal on terminal 60 when energy is outputted from the phase detector means. Similarly, phase lock loop lock detection means 58 is connected by conductor 22 to the output of charge pump means 46. The function of the phase lock loop lock detec-tion means 58 is to indicate, by means o~ outputting a signal on terminal 62, when the loop is not locked. The signals on conductors 60 and 62 are combined in ~ND circuit means 54 to generate a ready signal on conductor 30.
Fig. 2 shows the details of the local oscillator centering circuit means 12. In order to simplify the description, coMmon numerals are used to identify elements 1~236~34~
P~ 4 0 2 3 6 which are common to both Figs. 1 and 2. The local oscilla-tor centering circuit means 12 comprises of a pair of comparators identified by numerals 60 and 62. The corn-parators are used to set a ~oltage reference window within which the phase locked loop filter voltage must be posi-tioned in order the ~requency of the output signal, from the control oscillator, is positioned about its center fre-quency. As will be explained subsequently, once ~he phase locked loop filter voltage is positioned within this window, the bias voltage which provides the current on conductor 16 is locked into place and thereafter the loop is energized for normal operation. In the preferred embodiment of this invention the voltage available for driving the controlled oscillator is approximately 5V distributed on both the positive and the negative directions relative to a 0 voltage reference line. With this distribution comparator 60 which sets the upper limit of the window is supplied with a 2.5V
+~ on conductor 64. Similarly, comparator 62 sets the lower limit of the window and is supplied with a voltage value 2.5V - ~on conductor 66. It should be no~ed that the comparators may be used to set a voltage window other than 5V. Therefore, the use of 5V as a desirable voltage window is only representative of a particular voltage range and ought not to be construed as a limitation of the scope oE
~5 the present invention.
The output signals from comparators 60 and 62 are fed over conductors 68 and 70, respectively, into AND blocks 71 and 72. With the aid of a control signal on conductor 74 (to be described later) AND blocks 71 and 72 generate the increment counter pulses on conductor 76 and the decrement counter pulses on conductor 80. The increment/decrement pulses are fed into counter 82. As will be explained subsequently, counter 82 is used as a variable register to hold a digital word corresponding to the bias current which is used to center the control oscillator. The output from counter 82 is fed over conductor 84 into digital to analog (D/A) converter 86. The D/A converter converts the digital words stored in the counter to a corresponding bias current which is fed over conductor 16 into summin~ means 52.
~Z36S3~
R~4Q23 7 Still referring to Fig. 2, a clock pulse and a reset pulse are generated and applied to counter 82 on conductors 88 and 90, respectively. The clock pulse is used for stepping the counter and is generated from AND block 73.
The input into ~D block 73 is from a low frequency oscilla-tor and a controlled signal (to be described later) gener-ated on conductor 74. Likewise, the reset pulse on conduc-tor 90 is enabled to reset the counter at the beginning of an adjustment cycle and is generated from single shot (SS) circuit 9?. The single shot circuit is activated by the control signals on conductor 74. The control signal on conductor 74 is generated from the Q output of a D type latch identified by numeral 94. The latch is the primary controller ~or the centering circuit 12. To this end, the latch detects whenever the input signal "frequency acquisi-tion" mode is selected. This selection is indicated by placing a control pulse on the frequency acquisition line.
The pulse sets the counter and starts a new bias adjustment cycle to center the local oscillator. The latch is reset with a pulse generated from OR circuit block 96. The OR
block detects when both comparators are indicating that the phase lock loop correction voltage is within the desired window. The pulse is delayed by delay block 98 from whence it is fed over conductor 100 into the reset terminal o~ the latch. A supply ~oltage ~Vcc is provided on the data (D) terminal o~ the latch.
O~eration The circuit arrangement operates as follows:
.
When the signal on the frequency acquisition line (Fig.
2) goes from the low "phase detector" mode to the high "frequency detector" mode, latch 94 is triggered. The data (D) input is tied to +VCC so that the Q output goes high.
This enables the increment/decrement gates 71 and 72, respectively, and the clock gate 73. Also, the single shot 92 is triggered causing the counter to preset to its mid-range. The D/A converter establishes a DC bias current is established on conductor 16 and is summed ~ith the 36S3~
~84023 8 current on conductor 29. The current on conductor 29 is obtained from the amplifier stage of the phase lock loop.
The phase lock loop in frequency acquisition mode will drive the voltage on the filter until the crystal frequency is acqulred. If the voltage filter is not within the window set by 2.5V + ~or 2.5V ~~ then either the increment or decrement gate is enabled. This drives the counter in the direction to achieve 2.5V when the VCO is at the crystal frequency.
Similarly, the low frequency oscillator is at a fre-quency 10W enough to allow frequency acquisition at each new DC bias current, thus after each clock pulse the system will settle at the crystal frequency. The phase lock filter voltage will be compared to the window and additional steps will be taken until the window voltage is reached. At this time the latch will be reset so that the Q output is low, holding the counter at the value that gives proper bias current towards either window voltage and the phase locked filter. The ~ output enables one leg of the AND circuit 54.
When the lock and energy detect circuits are satisfied, a ready signal is forwarded to the system. The VCO natural frequency has now been adjusted to the desired frequency with its input volta~e at the mid-range point.
The described circuit arrangement elin~inates the deviation from the middle of the VCO input range and allows lower gain VCO circuits. Another benefit is that the above-described system can be integrated into an LSI chip design and does not require any more card space. In addi-tion, the available signal range is expanded by a factor of 4 or 5.
Although the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those s]cilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inven-tion.
Claims (10)
1. An improved phase lock loop circuit arrangement comprising:
an oscillator means having an input terminal and an output terminal;
a phase detector means coupled to the output terminal;
a frequency detector means coupled to said output terminal;
a multiplexor means coupled to the frequency detector means and the phase detector means;
a charge pump means coupled to the multiplexor;
an amplifier means coupled to the charge pump;
an adjustable centering circuit means coupled to the charge pump and operable for providing a control signal for centering the frequency of the oscillator means;
a summing means operable for summing electrical signals outputted from the adjustable centering circuit means and the amplifier means to form a single signal for driving the oscillator means; and an enabling signal means operable for periodically enabling the multiplexor means to allow the passing of signals from the frequency detector means only and for periodically enabling the adjustable centering circuit means to adjust its output signal until the frequency of the oscillator means falls within a predetermined range.
an oscillator means having an input terminal and an output terminal;
a phase detector means coupled to the output terminal;
a frequency detector means coupled to said output terminal;
a multiplexor means coupled to the frequency detector means and the phase detector means;
a charge pump means coupled to the multiplexor;
an amplifier means coupled to the charge pump;
an adjustable centering circuit means coupled to the charge pump and operable for providing a control signal for centering the frequency of the oscillator means;
a summing means operable for summing electrical signals outputted from the adjustable centering circuit means and the amplifier means to form a single signal for driving the oscillator means; and an enabling signal means operable for periodically enabling the multiplexor means to allow the passing of signals from the frequency detector means only and for periodically enabling the adjustable centering circuit means to adjust its output signal until the frequency of the oscillator means falls within a predetermined range.
2. The phase lock loop of Claim 1 further including means operable for periodically generating a control signal indicating that the frequency of the oscillator means is within the predetermined range.
3. The phase lock loop of Claim 2 wherein the means for periodically generating the control signal includes an energy detector having an input coupled to the phase detec-tor means; a phase lock loop detector having an input coupled to the charge pump means; and an "AND" circuit means connected with the energy detector and the phase lock loop detector.
4. The phase lock loop of Claim 1 wherein the adjust-able centering circuit means includes: a D/A converter, a counting means being coupled to the converter;
first means being coupled to tile counter and operable to determine the range over which the counter is active;
clock means operable for stepping the counter; and second means operable for controlling the counter.
first means being coupled to tile counter and operable to determine the range over which the counter is active;
clock means operable for stepping the counter; and second means operable for controlling the counter.
5. The phase lock loop of Claim 4 wherein the first means includes a pair of comparator means one of which being operable to define the top limit of the range and the other being operable to define the bottom limit of the range and a pair of "AND" circuits one of each being coupled to an output from the comparator means; said "AND" circuits being operable to combine the signals generated from the com-parators with a control signal to provide signals indicating the direction for stepping the counter.
6. The phase lock loop of Claim 4 wherein the clock means includes a low frequency oscillator; and an "AND" circuit connected to the low frequency oscillator.
7. The phase lock loop of Claim 4 wherein the second means includes a latch means; and a single shot circuit connected to the latch means.
8. In a phase lock loop circuit arrangement having a voltage control oscillator with a center operating frequency fc and output frequency fo, a reference means that provides a reference frequency fr, a phase comparator means connected to the reference means and the voltage control oscillator and operable for providing an error signal representative of the difference between fr and fo, the improvement compris-ing:
a D/A converter means coupled to the VCO;
a counting means connected to the D/A converter means and operable for storing a count representative of a current being needed for driving the VCO so that the output fre-quency fo is being centered;
a first means for presetting the counter;
a second means for incrementing the counter;
a third means for decrementing the counter;
means operable for setting a predetermined voltage range within which an error voltage must fall whenever fo = fc and for comparing the error voltage with the pre-determined range and to apply range signals to the second and third means if the error voltage falls outside of the predetermined range; and control means operable for providing control signals for enabling the first, second and third means.
a D/A converter means coupled to the VCO;
a counting means connected to the D/A converter means and operable for storing a count representative of a current being needed for driving the VCO so that the output fre-quency fo is being centered;
a first means for presetting the counter;
a second means for incrementing the counter;
a third means for decrementing the counter;
means operable for setting a predetermined voltage range within which an error voltage must fall whenever fo = fc and for comparing the error voltage with the pre-determined range and to apply range signals to the second and third means if the error voltage falls outside of the predetermined range; and control means operable for providing control signals for enabling the first, second and third means.
9. In a phase lock loop circuit arrangement having a voltage control oscillator with a center operating frequency fc and output frequency fo, reference means that provides a reference frequency fr, a phase comparator means connected to the reference means and the voltage controlled oscillator and operable for providing an error signal representative of the differences between fr and fo, a method for biasing the VCO so that fo = fc comprising the steps of:
(a) providing a local crystal oscillator for periodi-cally driving the VCO;
(b) providing a biasing means with a count for period-ically supplying a bias current to the VCO;
(c) providing a reference window representative of a voltage range available for driving the VCO;
(d) forcing the VCO with an output signal from the crystal oscillator until fo is substantially equivalent to the local crystal frequency.
(e) monitoring the output signal of the VCO;
(f) comparing the signal with the reference window;
(g) adjusting the bias current if the signal falls outside of the reference window; and repeating steps (e) - (g) until the output signal falls within the reference window.
(a) providing a local crystal oscillator for periodi-cally driving the VCO;
(b) providing a biasing means with a count for period-ically supplying a bias current to the VCO;
(c) providing a reference window representative of a voltage range available for driving the VCO;
(d) forcing the VCO with an output signal from the crystal oscillator until fo is substantially equivalent to the local crystal frequency.
(e) monitoring the output signal of the VCO;
(f) comparing the signal with the reference window;
(g) adjusting the bias current if the signal falls outside of the reference window; and repeating steps (e) - (g) until the output signal falls within the reference window.
10. The method of Claim 9 further including the steps of locking the biasing means with the count that causes the output signal to fall within the predetermined range; and providing a signal indicating that the adjustment is completed.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/681,767 US4593254A (en) | 1984-12-14 | 1984-12-14 | VCO centering circuit |
| US681,767 | 1984-12-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1236534A true CA1236534A (en) | 1988-05-10 |
Family
ID=24736710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000481997A Expired CA1236534A (en) | 1984-12-14 | 1985-05-21 | Vco centering circuit |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4593254A (en) |
| EP (1) | EP0184700B1 (en) |
| JP (1) | JPS61144125A (en) |
| CA (1) | CA1236534A (en) |
| DE (1) | DE3587141T2 (en) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4829545A (en) * | 1986-08-25 | 1989-05-09 | Guzik Technical Enterprises, Inc. | Method and apparatus for data window centering ina multifrequency data separator |
| US4712076A (en) * | 1986-10-27 | 1987-12-08 | Magnetic Peripherals Inc. | Circuit for phase locking a clock signal to a series of pulses |
| US4787097A (en) * | 1987-02-11 | 1988-11-22 | International Business Machines Corporation | NRZ phase-locked loop circuit with associated monitor and recovery circuitry |
| US5359727A (en) * | 1987-04-27 | 1994-10-25 | Hitachi, Ltd. | Clock generator using PLL and information processing system using the clock generator |
| US4804928A (en) * | 1987-05-12 | 1989-02-14 | Texas Instruments Incorporated | Phase-frequency compare circuit for phase lock loop |
| US4876518A (en) * | 1988-12-02 | 1989-10-24 | Motorola Inc. | Frequency tracking system |
| JPH0736515B2 (en) * | 1989-09-14 | 1995-04-19 | 株式会社東芝 | Phase comparator |
| KR910019345A (en) * | 1990-04-06 | 1991-11-30 | 정용문 | Magnetic frequency automatic synchronization control circuit of display device |
| US5119043A (en) * | 1990-06-27 | 1992-06-02 | Digital Equipment Corporation | Auto-centered phase-locked loop |
| DE4031939A1 (en) * | 1990-10-09 | 1992-05-07 | Rohde & Schwarz | Presetting phase-regulated VCO - reading-out corresp. adjusting values for several frequencies from memory for respective voltages |
| JP2854777B2 (en) * | 1992-04-27 | 1999-02-03 | 株式会社東芝 | Phase locked loop circuit and signal extraction method |
| DE4228834A1 (en) * | 1992-08-29 | 1994-03-03 | Thomson Brandt Gmbh | Oscillating signal generating stage e.g. PLL balancing method - superimposing signal on oscillator control signal causing control signal value to correspond to neutral value |
| KR100546541B1 (en) * | 1995-08-14 | 2006-03-23 | 가부시끼가이샤 히다치 세이사꾸쇼 | Pll circuit and picture reproducing device |
| US5764712A (en) * | 1996-04-18 | 1998-06-09 | International Business Machines Corporation | Phase locked loop circuit having automatic range setting logic |
| JPH1084278A (en) * | 1996-09-10 | 1998-03-31 | Nec Corp | Pll circuit |
| JP3094977B2 (en) * | 1997-11-28 | 2000-10-03 | 日本電気株式会社 | PLL circuit |
| US6683930B1 (en) | 1999-12-23 | 2004-01-27 | Cypress Semiconductor Corp. | Digital phase/frequency detector, and clock generator and data recovery PLL containing the same |
| US6310521B1 (en) * | 1999-12-23 | 2001-10-30 | Cypress Semiconductor Corp. | Reference-free clock generation and data recovery PLL |
| US6366135B1 (en) | 1999-12-23 | 2002-04-02 | Cypress Semiconductor Corp. | Data frequency detector |
| US20060002501A1 (en) * | 2004-06-30 | 2006-01-05 | Nokia Corporation | Ultra-fast hopping frequency synthesizer for multi-band transmission standards |
| US7439816B1 (en) | 2005-09-28 | 2008-10-21 | Cypress Semiconductor Corporation | Phase-locked loop fast lock circuit and method |
| US7728675B1 (en) | 2006-03-31 | 2010-06-01 | Cypress Semiconductor Corporation | Fast lock circuit for a phase lock loop |
| US7683685B2 (en) * | 2008-02-05 | 2010-03-23 | Sony Corporation | System and method for implementing a digital phase-locked loop |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3965438A (en) * | 1974-10-29 | 1976-06-22 | Tektronix, Inc. | Frequency locking system for a voltage controlled sweep frequency oscillator |
| US4069462A (en) * | 1976-12-13 | 1978-01-17 | Data General Corporation | Phase-locked loops |
| JPS5469018A (en) * | 1977-11-11 | 1979-06-02 | Sony Corp | Color demodulator circuit |
| US4151485A (en) * | 1977-11-21 | 1979-04-24 | Rockwell International Corporation | Digital clock recovery circuit |
| JPS56137736A (en) * | 1980-03-31 | 1981-10-27 | Anritsu Corp | Phase-synchronizing circuit |
| US4365211A (en) * | 1980-10-31 | 1982-12-21 | Westinghouse Electric Corp. | Phase-locked loop with initialization loop |
| JPS57141437A (en) * | 1981-02-25 | 1982-09-01 | Sakai Chem Ind Co Ltd | Chlorine-containing resin composition |
| JPS57190491A (en) * | 1981-05-18 | 1982-11-24 | Sony Corp | Variable oscillating circuit |
| US4456890A (en) * | 1982-04-05 | 1984-06-26 | Computer Peripherals Inc. | Data tracking clock recovery system using digitally controlled oscillator |
| FR2538656B1 (en) * | 1982-12-23 | 1985-06-07 | Thomson Csf | METHOD AND CIRCUIT FOR FREQUENCY AND PHASE SERVO OF A LOCAL OSCILLATOR IN TELEVISION |
-
1984
- 1984-12-14 US US06/681,767 patent/US4593254A/en not_active Expired - Fee Related
-
1985
- 1985-05-21 CA CA000481997A patent/CA1236534A/en not_active Expired
- 1985-08-16 JP JP60179572A patent/JPS61144125A/en active Pending
- 1985-11-22 EP EP85114817A patent/EP0184700B1/en not_active Expired - Lifetime
- 1985-11-22 DE DE8585114817T patent/DE3587141T2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US4593254A (en) | 1986-06-03 |
| EP0184700A3 (en) | 1988-06-01 |
| EP0184700B1 (en) | 1993-03-03 |
| EP0184700A2 (en) | 1986-06-18 |
| DE3587141T2 (en) | 1993-09-23 |
| DE3587141D1 (en) | 1993-04-08 |
| JPS61144125A (en) | 1986-07-01 |
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