CA1237533A - Deformable integrated circuit chip carrier - Google Patents

Deformable integrated circuit chip carrier

Info

Publication number
CA1237533A
CA1237533A CA000481872A CA481872A CA1237533A CA 1237533 A CA1237533 A CA 1237533A CA 000481872 A CA000481872 A CA 000481872A CA 481872 A CA481872 A CA 481872A CA 1237533 A CA1237533 A CA 1237533A
Authority
CA
Canada
Prior art keywords
chip carrier
carrier
die
chip
contact pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000481872A
Other languages
French (fr)
Inventor
Graham K. Whitehead
Kenneth Taylor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
British Telecommunications PLC
Original Assignee
British Telecommunications PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by British Telecommunications PLC filed Critical British Telecommunications PLC
Application granted granted Critical
Publication of CA1237533A publication Critical patent/CA1237533A/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
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    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
    • H05K2201/10886—Other details
    • H05K2201/10909—Materials of terminal, e.g. of leads or electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

ABSTRACT

A chip carrier is disclosed which includes a body having a central region and sidewalls connected to the central region by an elastically deformable region, in order to reduce thermal strains. Also for the same reason a heat sink may be attached underneath the carrier below the carrier's die attachment site and thermally conductive material may connect them together. The heat sink may be used for mechanical anchorage. The chip carrier can be produced by injection moulding from an aromatic thermoplastic polymer. A carrier may be moulded with more than one die attachment site or a circuit board with die attachment sites could be moulded, preferably with the die attachment site recessed so that the surface of the die is co-planar with conductive tracks on the board.

Description

1~37533 This invention relates to an integrated circuit chip carrier. More particularly it relates to a chip carrier made from a plastics material.
Known forms of chip carrier consist of a usually square base of ceramic material. A central area on the base is provided on to which an integrated circuit chip or die is mounted and secured, for example using a eutectic (gold/silicon) bond or an epoxy resin adhesive.
Connections are then made between the appropriate points on the ~ie to metal bonding pads provided on the carrier base. A preformed metallisation patte m on the carrier base connects the bonding pads to terminal contacts fonmed around the periphery of the base or to leads. A ceramic lid is then secured over the base so as to enclose and protect the die. The chip earrier is thereafter mounted on a printed eircuit board together with a series of other ehip carriers and electronic components that go to form the complete cireuit.
These packaoes, though available in large quantities, do require that the chip is bonded to the carrier before the combination is encapsulated in the protective cover. As a consequence the chip manufacturer is usually involved in the package production. This is often convenient for those chips that are considered to be "large production runsn. However, increasingly it would be convenient if there was a source of pre-manufactured packages, of the required shape, into which the chips could be introduced for protection.
Because the process by which a ceramic package is ~1237533 made precludes the introduction of the device until the package is complete, they were until recently the most readily available packages for this application. ~owever, the use of ceramic material for the chip carrier is expensive and problems can also arise when the ceramic base is later bonded to a conventional epoxy-glass printed circuit board, due to the differential expansion between the two materials. In extreme environmental conditions the ceramic chip carrier can break away from the printed circuit board.
It is also known to make chip carriers of plastics materials, and with these it is possible to match the t, thermal coefficient of expansion (T OE ) of the carrier to that of the circuit board. However, even with matched T OE s there may still be problems with differential expansion - the chip within the carrier is a source of heat which will tend to heat the carrier more rapidly than the circuit board, and hence even with identical T OE s the carrier can expand more rapidly than the circuit board.
Certain plastics chip carriers also suffer from the disadvantage that their wire bonding pads and their terminal pads are metallised in the same operation, with the result that the thickness of gold (which is the preferred final coat) is the same on both pad types. This causes problems where the terminal pads are to be soldered to, as the thickness of gold on the terminal pads must be kept below about 0.2 micrometres to prevent excessive enbrittlement of the solder. This requirement that terminal pads have gold less than 0.2 micrometres thick conflicts with the need for 2 micrometres thickness gold for optimum bonding of wires to the bonding pads. The additional complexity and expense involved in providing the optimum thickness of gold to each pad type makes such an approach unattractive, and in consequence poor wire 1~37533 bonding is accepted.
According to the present invention, there is provided a leadless chip carrier comprising a body having a die attachment site; first contact pads; a side wall connected to the body laterally spaced therefrom, the underside of which has second contact pads for attaching, in use, the chip carrier to a circuit board, the second contact pads being electrically connected to the first contact pads; a link region connecting the side wall to the body and spaced from an underside of the side wall, the link region being an elastically deformable region such that, in use, thermally induced strains of the carrier relative to the circuit board are accommodated by the link region.
In a preferred embodiment, the body is formed from an aromatic thermoplastic polymer by injection moulding.
Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings in which:
Figure la is a perspective view of a chip carrier prior to bonding its lid to its body;
Figure lb is a cross sectional view of the carrier and lid of Figure la taken on the line xx;
Figure lc is a cross-sectional view of a chip carrier having an alternative form of construction;

Figure 2a is a plan view of a 10 x lO array of chip carriers prior to separation;
Figure 2b shows details of the conductors of the array of Figure 2a;
Figure 2c shows a multiple chip carrier according to the present invention;
Figure 3a shows a cross-sectional view of a chip carrier having an alternative form of construction;
Figure 3b is a plan view from beneath of the chip carrier of Figure 3a;
Figure 3c is a perspective view of a corner part of the chip carrier of Figure 3a;
Figure 4 is a cross-sectional view through a chip carrier having plated through holes to provide improved heat shedding capacity;
Figure 5 is a cross-sectional view through a chip carrier having an inserted combination die bond pad and thermal pillars;
Figure 6 is a perspective view of a chip carrier having staggered contacts; and Figure 7 shows the chemical formula of a polymer for use in forming the chip carrier.
Referring now to Figure la, a chip carrier 1 is moulded with a central die mounting cavity 2. About the edge of the chip carrier a plurality of metallised contacts 4 are provided. Each of the contacts comprises a metallisation which extends from the carrier's upper surface, down the side wall, and onto the carrier's lower surface. A part 6 of the contact on the carrier's upper surface is coated with gold to form a pad suitable for wire bonding. The corresponding contact part 7 on the lower surface is coated with a metal such as tin or an alloy such as tin/lead suitable for forming a solderable contact pad.
In the die mounting cavity a die bonding pad 8 is formed by metallisation. A die 9 is shown bonded If or ~37533 .. 5 ..

e~ample, with an epoxy resin) to the die bonding pad.
Electrical contact is made to the various parts of the die by bonding aluminium or gold wires 10 to the die 9 and to the wire bonding pads 6.
A chip carrier as described above can be fabricated by injection moulding techniques. Suitable plastics for use in moulding such a chip carrier include aromatic polymers such as polyether ether ketone (PEEK) and polyethersulphone (PES) sold under the name VICTREX by ICI; polysulphone sold under the name UDEL by Union Carbine; and polyetherimide sold under the name ULTEM by General Electric. The structure of these polymers is as follows:
Polyether ether ketone [-C6H4-C0-C6H4-û-C6H4-0-]n Polyethersulphone [-C6H4-S02-C6H4-0-]n UDEL PolysulPhone [-C6H4-S02-C6H4-0-C6~4 C3H6 C6 4 ]
Polyetherimide - see Figure 7.
The principal factors ~hich have to be taken into consideration when choosing a poly~er for use in moulding chip carriers according to the present invention are:
1) ability to withstana subsequent processing conditions, notably temperatures encountered during soldering - generally at least 215C in vapour phase tanks. This requires a glass transition temperature (Tg) of about 23Pc or more - although lower soldering temperature and/or shorter transit times may allow the use of polymers having lower glass transition temperatures.
2) The polymer should be free of undesirable outgassing so that circuit reliability is not jeopardised.
3) The polymer should be mouldable, prefera~ly by injection moulding.
* trademarks 1;~37533 .. 6 ..
4) The polymer should preferably be weldable (ultrasonically or otherwise) so that it is not necessary to use glues or adhesives (which can give rise to contamination problems in service).
5) The polymer should accept metallisation, and preferably should be compatible with fully additive processing.
6) The polymer should preferably accept pigments as some circuits are light activated and require opaque carriers.
7) The polymer should preferably have a coefficient of expansion comparable to that of the circuit board material with which the carriers are to be used -typically this would be about 17 to 23 x 10-6 oc-l .
Referring again to Figure la, in order to protect the die and the wire bonding from direct physical contact and contamination, a lid 11 is provided. The lid 11 is moulded from a material compatible with that of the body of the chip carrier to enable them to be joined without the use of glues, eg by ultrasonic welding. ~ecause the contacts 4 are deposited on the surface of the chip carrier, they provide a stepped surface, and it is to this that the lid has to be sealed. For this reason the lid's lower surface is provided with indentations 12 in positions corresponding to the positions of contacts 4.
In order to provide effective sealing, the indentations are made somewhat smaller than the contacts 4 which they are to receive, and in the example shown they are triangular, with the apex uppermost. During the welding of the lid to the base, pressure is applied to urge the lid towards the base, causing the lid to deform around the contacts to provide an effective seal to the contacts and the base. If desired an encapsulant (junction coating) ~37~33 .. 7 ..

can be applied to the wire bonded chip to provide additional mechanical and environmental protection during handling. The combined lid and body cavity serves to retain any such encapsulant. However, since encapsulant often flows too freely prior to the bonding of the lid to the body the lid may be made in t~o parts: the first part 13 comprises a sidewall, ar,d the second part 14 a cap.
The sidewall 13 is welded to the carrier body, encapsulant can then be applied to the wire bonded chip, and the cap 14 is then welded onto the sidewall 13.
It is possible to achieve a high degree of sealing with the chip carriers and they may be particularly L
suitable for use in high humidity environments. ~¦
In Figure lb the construction of the chip carrier 1 and contacts 4 can more clearly be seen. The contacts 4 comprise multiple metallic coatings; a first coating 15 of copper, a .25mm nickel coating 16 over the copper, a gold coating 17 over the nickel on the upper end of the contact 2G to form the wire bonding pad 6, and a tin or tin/lead alloy coating 18 over the nickel of the lower end of the contact to form a solderable terminal pad 7.
In an alternative form of construction, the die bonding pad 8 can advantageously have a construction whereby differential thermal expansion between the chip carrier and the die 9 itself is better accommodatea. (It will be appreciated that, whereas the carrier material has a typical T OE of 23xlO 6 C 1, that of silicon is about 2xlO 6 C 1.) This construction (see Figure 3G lc) could be such that the die bonding pad 8 comprises a relief pattern 30 such as series of ribs, concentric rings, or a plurality of "pillarsn, or be "maze" shaped (the latter two constructions being even more advantageous than the first because they admit differential expansion in all directions in the relevant plane).

.. 8 ..

The chip carriers made by injection moulding in thermcplastic may conveniently be moulded in a matri~ of for example lOxlO. Such a matrix is shown in Figure 2a, and details of the arrangement of conductors etc between adjacent carriers is shown in Figure 2b The matrix is moulded as a generally flat sheet containing the die cavities and the necessary holes for producing conductors 4. Note that chip carriers may be moulded without lû cavities, deeper lids being provided to supply the die mounting cavity. Preferably, however, the carrier body will have a moulded-in die mounting cavity, as this offers a number of advantages, including some protection against accidental damage during processing.
The described embodiments of the invention contemplate two alternative methods of producing the conductors 4 and die bonding pads 8. In the first ~subtractive" method, a copper coating is formed by lamination or electroless deposition and etched using 2û conventional resist techniques: desired coatings of nickel, gold, tin, etc can then be selectively plated. In the second "additive" method, all metallisation is initially carried out by electroless deposition and etching is unnecessary. The pattern, once defined, can be built up either electrolessly or by electroplating. Both methods have the advantage, as compare~ with processes ~here the final finish is used as a mask for etching the copper beneath, of avoiding the dePosition of gold in areas where it is undesirable (for the reasons discussed earlier). This approach is made practicable by injection moulding whereby holes can be formed, easily at the moulding stage, avoiding a prohibitive amount of drilling being required to produce- the necessary through-hole connections.
In the "additive" method, the conductors 4 and die - 12;~7533 .. g ..

bonding pads 8 are produced after the matrix is moulded, and, for this reason, it is not necessary to provide any metallic inserts during moulding. Processing may be facilitated by producing platinq bars 21 in rows or as a grid between the individual chip carriers. In this way it is possible, if desired, to connect together all the chip carriers to form a single electrode.
The first stage in defining the conductor pattern involves rendering the surface of the plastic sufficiently sensitive to accept an electroless copper deposition.
This may be done in any convenient way, although the preferred method is to use the resistless imaging process devised by PCK Technology of Melville New York and known as Photoforming. In this process the moulding is chemically etched to render this surface hydrophilic to enable deposition of a catalyst and electroless copper.
After etching, the surface is activated with a solution containing an ultra violet (UV) photo initiator and copper salts. On exposure to UV light the copper ions present in the solution are reduced to metallic copper. It is therefore possible to produce the deslred ,~tallisation pattern in copper simply by exposing their requisite areas to UV light. Following this initial copper deposition, electroless copper deposition can be used to produce a thicker copper layer which can be used as an electrode in subsequent electroplating steps. It should be noted that for use in such processes the polymers discussed require treatment, such as doping with titanium dioxide to render them opaque to ultra-violet light.
Of course, other techniques, involving plating masks or resists can be used, but these will generally require many more process steps and are likely to increase production costs.

1~375~3 .. 10 ., If plating bars (ie broad tracks) such as those shown at 21 in Figure 2b are used, it may be possible to dispense with the electroless copper plating step, and simply electroplate on the patte m defined in the photoforming step.
Following deposition of copper either electrolessly or electrolytically, a nickel coating is electro plated over the copper.
As can be seen in Figures 2a and 2b, all those parts of the chip carrier which are to be metallised, ie the contacts and the die bonding pads 8, can all be interconnected (the die bonding pads may be formed by insertion of a metallic stud or in some other way which does not require the pads to be plated, in which case they need not form part of the electrode). The tracks 21 serve to interconnect these regions on all the carriers and are removed when the matrix is separated to form individual carriers. This is most easily done by arranging the tracks 21 in the form of a lattice with one chip carrier per cell. As can be seen, there are no contacts 4 at the corners of the chip carriers (as this could result in different path lengths between the die and the different terminal pads 7), and these spaces allow tracks 23 to be run from the die bonding pads to the tracks 21 of the lattice. Alternatively tracks could be run directly from a contact 4 at the centre of one side of the carrier to the die bonding pad. These could be cut at a later stage or (if external connection to the semiconductor substrate is required) allowed to remain.
At the site of each contact 4 a hole or slot 24 is provided through the board. At each end of these holes or slots a metallised pad, (which on the upper surface of the chip carrier will form wire bonding pads 6 or on the lower side of the chip carrier will form the terminal pads 7) is ~23~75~3 .. 11 ..

provided. The photoforming step provides sufficient metallic copper on the walls of the holes 24 for subsequent ~etallisation to give fully plated--through holes.
Following the nickel plating step the wire bonding pads are plated with 2 micrometres of gold. ~y using taped resists (ie resists or masks in the form of adhesive tapes) it is possible to quickly and easily mask both ends of the holes 4 and those surfaces of the carrier (including the underside) which are not to be plated with gold. It is thus possible to selectively plate with gold, so that none is applied to the terminal pads thereby avoiding subsequent embrittlement of the solder used to ¦~
attach the chip carrier to a circuit board. As previously mentioned, the terminal pads may be pre-coated with a tin or lead alloy.
After completing the metallisation steps, the matrix of chip carriers can be divided into individual carrlers either before or after dies are bonded and wired to the carriers, although usually the chip carriers will be separated before dies are bonded to them.
The matrix of chip carriers can have lines of weakness moulded into it, along the edges of the plating bars for example, so that it is possible (depending upon the material used) to snap off lines of carriers or individual carriers. If the precursors of the contacts 4 are slots or a combination of slots and holes, it may be possible to use them so the line of weakness along which the chip carriers may be separated by 'snapping' apart.
Alternatively, the matrix may be divided up using a saw, for example a circular saw. In either case the conductive tracks which have been used during electroplating are removed during separation of adjacent carriers. Where each of the boundaries of each chip carrier is defined by .. 12 ..

a separate row of holes, as in Figure 2b, so that bet~ee~
any two adjacent carriers there are two rows of holes, the material removed during separation (for a leaded carrier) comprises that between the two rows of holes - viz b~
severing along lines 22 leaving each separated chlF
carrier with edges comprising flat portions bet~eer concave conductors 4. Where a single row of holes is usec to produce the conductors 4 of two adjacent carriers lû separation must be carried out carefully to ensure that nc conductors 4 are lost from any carrier during separatior.
Alte matively, for a leadless carrier, separation is alons lines 52 leaving the holes 24 into which leads can be inserted. ¦~
lS If a totally electroless metallisation process is used, on the other hand, the plating bars become unnecessary, and in that case the carriers could be moulded as individual items joined only by fine webs at (for example) the corners.
2û A further advantage of making chip carriers by injection moulding is that the material used can have a coefficient of thermal expansion similar to that of most of the metal cored printed circuit boards (PCB) anC
substrates. As a result whole PC3s could be mouldec having recesses at the chip sites like a multiple-chi~
carrier - and metallized as previously described. The chip would then be bonded into the cavities and protecte-with junction coatings. Then lids of the same nature as those proposed for the single-chip carrier could be weldec into place to afford mechanical protection. The addec benefit of this solution is that the tracking on the Poe could be taken directly into the chip housing and thus the problems of the packageAboard interface are removed.
Figure 2c is a perspective view of part of such a construction in which a chip 9 is accommodated in a rectangular recess 26 in an injection moulded substrate 27, a lid 11 is shown covering another recess. Another advantage of this arrangement is that the absence of a se-parate carrier between the chip and a PCB, coupled with the location of the chip in a recess means that the upper, connecting~ surface of the chip can be arranged to be co-planar with conductive tracks 28 on the substrate, providing superior transmission - line properties for highspeed/high frequency operation.
The problems of thermal strain in chip carriers pro-duced by injection moulding or otherwise can be combatted by a variety of techniques; in addition to the provision of a relief profile in the die bonding pad, which is particu-larly advantageously produced by injection moulding tech-niques. Referring now to Figure 3; Figure 3a shows a chip carrier in which the side walls 31, which are metallised to form the contacts 4, are each separated from the main chip carrler body by a slot 3Z, which extends to virtually the full height of the side wall; this side wall being con-nected to the main body by only a thin elastically deform-able portion 33. The provision of these deformable portions enables the chip carrier to repeatedly accommodate relative-ly large strains resulting from differential thermal expan-sion without imposing large stresses on the solder joints between the terminal pads and the circuit board.
In Figure 3b it can be seen that at each corner of the chlp carrier there is a gap 34 between the adjacent side walls. This gap allows the carrier to accommodate strain along lts length and across its width. Where the amount of strain is expected to vary along the side wall, which may occur when the chip carrier is very large, it may be desirable to provide gaps in the side walls. There may be occasions when it is desirable to divide the side .. 14 ..

~alls further, even to the point of having one side ~all segment for each of the contacts 4. This is shown ln Figure 3c, where the metallised parts 4 of the contacts are shown hatched; the underlying plastics part 31', which is integrally moulded with the rest of the carrier body, remains unshaded. It should be understood that the metallisation is formed over the divided sidewall, and that Figure 3c does not show separately added legs.
Alternatively for use with highly heat dissipative chips a thermal path may be incorporated in the die bond~
pad, and various arrangements are sho~n in Figures 4 and 5.
The chip carrier shown in Figure 4 has several plated through holes 40 in the die bonding pad 8. These holes are produced at the same time and in the same ~ay as the interconnection holes used to fonm the contacts 4.
Alternatively, the holes can be left unplated and slugs of a thermally conductive material (eg copper) inserted. In either case, a thermal pad 41 on the underside of the chip carrier, corresponding to the die bonding pad 8, would enhance heat transfer. For efficient heat transfer the thermal pad may be soldered to a correspondi~;g contact on th!e circuit board to which the chip carrier is to be attached. Indeed, this form of attachment couid be used as a means of mechanical anchorage even in the absence of thermally conductive material extending through the carrier. This solder connection can be replaced with a high heat conductivity grease to bridge any gap oetween the thermal pad and the circuit board. Alternatively the 30 ~ thermal pad may not be connecte~ to the circuit board but left to radiate heat, as for instance, when included in an injection moulded multiple chip carrier.
Greater thenmal transport may be provided by means of a legged platform or stud 42 (Figure 5) which can either be incoroorated into the matrix during injection 1~3~
.. 15 ..

moulding, or inserted into a suitable hole fonmed during moulding. Alternatively, this stud may consist of two parts, an upper and a lower, which can be inserted or ~oulded in separately.
Where the thermal pad is to be soldered to the substrate it is preferable that the surface ~hich is to be soldered comprises a number of discrete areas so that the fonmation of voids is minimised.
In addition to the improvement in heat transfer provided by solderinq the thermal pad to the circuit board, there is a further advantage in that the gauge length over which the thermal stress acts is considerably reduced. Without the central attachment provided by the thermal pad the gauge length would be the distance between the side walls. With a thermal pad this is reduced to just twice the distance between the thermal pad and the side wall, ie the gauge length is reduced by the width of the thermal pad.
The problems of soldering the thermal pad 41 or an anchorage pad to a circuit board increase as the size of the chip (and carrier) increases. Reflow soldering is carried out by pre--coating the pad and contact pads with a solder paste comprising powdered solder, powdered flux and 2' an organic binder. The application of heat (as uniformly as possible) by any of a number of known techniques, eg vapour phase soldering, causes flow of the solder and flux and a solder joint is formed.
The proposed construction further allows the use of a small circuit board track width and separation which may enable greater circuit densities to be realised. This can be achieved by offsetting adjacent terminal contacts on the carrier, for example by providing an inner and an outer row of terminal contacts as shown in Figure 6. It can be seen that the edge of the chip carrier is 37~;33 .. 16 ..

castellated, ~ith an inner and an outer ro~ of contacts 4a, 4b; the size and offset being such that the inner terminal contacts can be inspected by looking through the gaps between adjacent outer terminal contacts. In this way, it is possible for all the contacts between a chip carrier and a circuit board to be visually inspected. The provision of an inner and an outer row of terminal contacts allows the pitch of the contacts to be reduced, lû and hence allows denser packing, while maintaining adjacent solder pad separation.
The chip carriers may also be made compatible with circuit boards using plated-through hole (pth) technology by providing them with leads. Such chip carriers are made as has been described above talthough there is no need to provide terminal contacts on the carrier's lower surface), with each chip carrier having its own array of holes 24 which are to be used to provide contacts 4. The leads are inserted into the holes 24, either singly or in a ganged operation into several holes simultanecusly using for example an automatic leading machine. The leads should be suitably sized to provide an efficient seal to the holes through which they pass.
After insertion the connecting pieces between ganged ~eads can be removed, and the leads left straight for through board insertion or '~oggled' to form a surface mounting footprint.

Claims (11)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A leadless chip carrier comprising a body having a die attachment site; first contact pads; a side wall connected to the body laterally spaced therefrom, the underside of which has second contact pads for attaching, in use, the chip carrier to a circuit board, the second contact pads being electrically connected to the first contact pads; a link region connecting the side wall to the body and spaced from an underside of the side wall, the link region being an elastically deformable region such that, in use, thermally induced strains of the carrier relative to the circuit board are accommodated by the link region.
2. A chip carrier as claimed in claim 1 in which the sidewall is divided between adjacent second contact pads.
3. A chip carrier as claimed in claim 2 in which adjacent second contact pads are offset.
4. A chip carrier as claimed in claim 1, in which the body is formed from an aromatic thermoplastic polymer by injection moulding.
5. A chip carrier as claimed in claim 4, in which the aromatic thermoplastic polymer is a polyether ether ketone, polyethersulphone, polysulphone or polyetherimide.
6. A chip carrier as claimed in claim 4 or 5, in which the die attachment site comprises a relief pattern.
7. A chip carrier as claimed in claim 4 or 5 in which the chip carrier is produced in a matrix of injection moulded carriers and separated after molding.
8. A chip carrier as claimed in claim 1 in which the die attachment site is recessed into the body of the chip carrier.
9. A chip carrier as claimed in claim 8 having a die mounted on the die attachment site in which the connecting surface of the die is co-planar with the first contact pads.
10. A chip carrier as claimed in claim 1 including a metallised attachment pad on its underside whereby the carrier may be mounted on the circuit board with the attach-ment pad and the contact pads soldered to corresponding areas on the circuit board.
11. A chip carrier as claimed in claim 10 in which the die attachment site comprises a region having a higher thermal conductivity than the body and including thermally conductive means extending through the body between the die attachment site and the attachment pad.
CA000481872A 1984-05-18 1985-05-17 Deformable integrated circuit chip carrier Expired CA1237533A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB848412674A GB8412674D0 (en) 1984-05-18 1984-05-18 Integrated circuit chip carrier
GB8412674 1984-05-18

Publications (1)

Publication Number Publication Date
CA1237533A true CA1237533A (en) 1988-05-31

Family

ID=10561134

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000481872A Expired CA1237533A (en) 1984-05-18 1985-05-17 Deformable integrated circuit chip carrier

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US4682270A (en) 1987-07-21
IE56754B1 (en) 1991-12-04
GB8412674D0 (en) 1984-06-27
EP0165705A1 (en) 1985-12-27
AU590514B2 (en) 1989-11-09
AU4259885A (en) 1985-11-21
IE851233L (en) 1985-11-18
JPS6134963A (en) 1986-02-19

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