CA1239995A - Digital signal repeater including means for controlling a transmitter - Google Patents
Digital signal repeater including means for controlling a transmitterInfo
- Publication number
- CA1239995A CA1239995A CA000489294A CA489294A CA1239995A CA 1239995 A CA1239995 A CA 1239995A CA 000489294 A CA000489294 A CA 000489294A CA 489294 A CA489294 A CA 489294A CA 1239995 A CA1239995 A CA 1239995A
- Authority
- CA
- Canada
- Prior art keywords
- signal
- receiver
- output
- providing
- digital signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/155—Ground-based stations
- H04B7/15528—Control of operation parameters of a relay station to exploit the physical medium
- H04B7/15542—Selecting at relay station its transmit and receive resources
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
Abstract
ABSTRACT
The present invention relates to a digital signal repeater of the type in-cluding a controller for controlling activation/non-activation of a radio trans-mitter. The repeater has an improved controller to avoid activation by inter-ference signals as well as a receiver. The controller is responsive to the out-put of the receiver for providing a control signal controlling the transmitting operation of the transmitter. The controller comprises a first decision circuit for detecting the level of the modulated carrier wave of an intermediate fre-quency band of the receiver and providing a first signal, a second decision cir-cuit for detecting a clock frequency component in the output of the receiver and providing a second signal, logic circuitry responsive to the first and second signals for providing a third signal, a circuit for smoothing the third signal, and a comparator circuit for comparing the output of the smoothing circuit with a reference level and providing the control signal.
The present invention relates to a digital signal repeater of the type in-cluding a controller for controlling activation/non-activation of a radio trans-mitter. The repeater has an improved controller to avoid activation by inter-ference signals as well as a receiver. The controller is responsive to the out-put of the receiver for providing a control signal controlling the transmitting operation of the transmitter. The controller comprises a first decision circuit for detecting the level of the modulated carrier wave of an intermediate fre-quency band of the receiver and providing a first signal, a second decision cir-cuit for detecting a clock frequency component in the output of the receiver and providing a second signal, logic circuitry responsive to the first and second signals for providing a third signal, a circuit for smoothing the third signal, and a comparator circuit for comparing the output of the smoothing circuit with a reference level and providing the control signal.
Description
~z;~
DIGITAL SIGNAL REPEAT~R
INCLUDING MEANS FOR CONTROLLING A TRANSMITTER
Background of the Invention The present invention relates to a digital signal repeater for repeating digital signals and, more particularly, to a repeater of the type including a controller for controlling activation/non-activation of a radio transmitter.
A repeater of the type described is generally made up of a radio receiver, a radio transmitter, and a controller. The receiver receives a modulated wave from a terminal station or the like and demodulates it to provide a digital signal, while the transmitter transforms the digital signal again to a modulated wave which is sent to another terminal station or the like.
The controller controls the transmitter such that while a modulated wave is xeceived the transmitter is activated (turned on) to repeat a digital signal to another terminal station or the like and, while a modulated wave is not received, it is not activated (turned off) not to repeat a digital signal. Whe-ther or not a modulated wave has been received may be determined by detecting the level of a modulated wave in the intermediate frêquency IIF) band of the receiver.
~7~
Ho~ever, this kind of approach has the drawback that the IF band modulated wave level sometimes reaches a sufficient value even when an interference wave from another system is received, thereby undesirably activating the transmitter to repeat needless signals.
Summary of the Invention It is therefore an object of the present invention to provide a digital signal repeater having an improved controller which is free from the above-described drawback.
In accordance with the present invention, there is provided a digital signal repeater having a receiver for receiving a modulated carrier wave and demodulating a digital signal, a transmitter -Eor transmitting a carrier wave modulated by the digital signal, and a controller responsive to the output of the receiver for providing a control signal controlling the transmitting operation of the transmitter. ~he controller comprises first decision means for detecting the level of the modulated carrier wave of an intermediate frequency band of the receiver and providing a first signal, second decision means for detecting a clock frequency component in the output of the receiver and pro~iding a second signal, logic means responsive to the first and second signals for providing a third signal, first means for smoothing ~5 the third signal, and comparator means -Eor comp~i~
~2~
the output of the first means with a reference level and providing the control signal. ..
Brief Description of the Drawings The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken with the accompanying drawings in which.
FIG. 1 is a circuit diagram showiny a first embodiment of a digital signal repeater in accordance with the present invention;
FIGS. 2A - 2I are timing charts representative of the operation of the repeater shown in FIG. l; and FIG. 3 is a circuit diagram showing another embodiment of the pr~sent invention.
Detailed Description of the Invention Referring to FIG. 1 of the drawings, a digital signal repeater embodying the present invention is shown and generally comprises a receiver 1, a transmitter 2, and a controller 100. A carrier wave modulated by a digital signal and coming in through an antenna is applied to and amplified by a radio frequency (RF) amplifier 31 which is included in the receiver 1. The output of the RF amplifier 31 is converted by a frequency converter 32 to an intermediate frequency (IF) and, then, amplified by ~3 ~ 4 an IF amplifier 33. The modulated wave in the IF band is demodulated by a demodulator 3~ and, then, transformed into a digital signal (DATA).
In the transmitter 2, a modulator 41 modulates a r carrier wave again by the digital signal (DATA) and applies its output to a frequency converter 42 which converts the input to the RF band. The modulated wave in the RF band is transmitted via a power amplifier 43 to a terminal .station or another repeater (not shown) which follows the illustrated repeater.
The transmission control over the power amplifier 43 is performed by the controller 100 as will be described in detail hereinafterO
The controller 100 comprises a first aecision circuit 3, a second decision circuit 4, an ~ND gate 5, a time constant circuit 6, and a comparison circuit 7. The firs~ decision circuit 3 is adapted to detect the level of the IF modulated ~ave outputted from the IF amplifier 33 so as to determine whether nor not the receiver 1 is receiving a signal and, for this purpose, it comprises a level detector 8, a comparator or differential amplifier 9, and a potentiometer 10. As shown in FIG. 2A, the modulated wave IF has under-gone level fluctuation due to fading particular to a radio section. The level detector 8 is adapted to detect the modulated wave IF. As shown in FIG. 2B, the output x~ of 3~
the level detector 8 appears as an envelope. The comparator 9 compares the detector output x8 with a reference voltage Vcl which is determined by the potentiometer 10 and, if the former is higher than the latter, produces an output X3 showing that the receiver 1 is receiving a signal. The comparator output X3 is delivered to the AND gate 5 as an output of the first decision circuit 3 ~FIG. 2C).
The second decision circuit 4 is made up of a bandpass filter 11, a level detector 12, a comparator or differential amplifier 13, and a potentiometer 14.
The function assigned to the decision circuit 4 is detecting the level of a recovered clock which is synchronous with a received digital signal in order to see if the receiver 1 is receiving a digital signal.
Applied to the input terminal of the decision circuit 4 is a signal CF which contains a clock frequency component obtained by full-wave rectification of the output of the demodulator 34.
The bandpass filter 11 separates the clock frequsncy component from the input signal CF of the decision circuit 4, khereby producing an OlltpUt signal xll as shown in FIG. 2D. Comparing FIGS. 2A and 2D, it will be seen that the signal xll appears as noise so long as the receiver 1 does not receive a signal and, hence, the q'3~
-- 6 ~
~andpass filter 11 olltpUts a clock frequency component which is contained in the noise; as the receiver 1 receives a signal, the signal xll greatly flucturates because the clock frequency is significantly lower than the intermediate fre~uency and because the clock frequency component is effected by a code pattern of information which is being transmitted.
The level detector 12 detects a level of the signal xll to deliver an output xl2. As shown in F~G. 2~, the detector output xl2 appears as an envelope. The comparator 13 compares the signal xl2 with a reference voltage Vc2 which is determined by the pctentiometer 14 and, if the Eormer is higher than the latter, produces an output X4 (FIG. 2F) as an output of the decision circuit 4, showin~
that the receiver 1 is receiving a digital signal.
What is of prime importance here is how to mix the output X3 of the decision circuit 3 (FIG. 2C) and the output X4 of the decision circuit 4 (FIG. 2F). ~'he output X3 of the decision circuit 3 which shows whether or not a received intermediate frequency is present rises even when interference waves such as attributable to adjacent channels are receivedl if the interEerence waves are sufficient in level. Therefore, should the transmitter 2, i.e., the power amplifier 43 be activa-ted by the output X3 25 of the decision circuit 3 only, there would be brought about the problem oE erroneous repeating.
~z;~
Although the transmitter 2 may be activated by direc-tly using the output x~ of the decision circuit 4 only, such an approach also involves the fear of erroneous repeating considering the fact that the clock frequency contained in the noise waveform sometimes reaches a sufficient level even if the receiver is not receiving a signal.
In accordance with the present invention, the shortcoming of the decision circuits 3 and 4 as discussed above is compensated for by applying the output X3 of the decision circuit 3 and the output X4 of the decision circuit 4 to the time constant circuit 6 after the AND
gate 5. Specifically, when the output X3 of the decision circuit 3 has built up responsive to an interference wave as derived from another system or from adjacent channel, the output of the AND gate 5 does not rise because the clock frequency component cannot rise to a sufficient level.
When the output X4 of the decision circuit 4 has risen responsive to noise in a non-receiving condition of the receiver 1, it is not reflected by the outpu-t X5 of the AND gate 5 because the ou-tput of the decision circuit 3 remains logical "0" then.
The output X5 of the AND gate 5 (FIG. 2G) is routed to the time constant circuit 6. As shown, the time constant circuit 6 comprises an RC circuit made up of a resistor 15 and a capacitor 18 and, in addition, a series connection of a resistor 16 and a diode 17 which is connected in parallel with the resist~r 15, thereby attaining a fast rise response and a slow fall response.
Such a response characteristic of the time constant circuit 6 not only allows the response at the start of signal reception to be designed fast but also eliminates the influence of the logical "0" level of the output X5 of the AND gate 5 which may occur momentarily when the level of the modulated wave I~ has lowered due to fading or when the clock component of the input CF to the decision circuit 4 has decreased effected by a code pattern of information.
The output x6 of the time constant circuit 6 (FIG. 2H) is compare~ by a differential amplifier 19 of the comparison circuit 7 with a reference voltage Vc3 which is determined by a potentiometer 20, whereby a transmission control signal X7 ~FIG. 2I) is produced. The control signal ~7 is adapted to selectively enable and disenable the transmission of a wave by on-off controlling a power source associated with the power amplifier 43 or controlling an attenuator which is connected to the former stage of the power amplifier ~3.
In the particular embodiment shown in FIG. 1, each of the level detectors 8 and 12 is provided with a relatively fast response characteristic, that is, it responds within a relatively short period of time. Although such fast ...
response will be reflected by fast changes of "1" or "0"
in the output X5 of the AND gate 5, the time constant circuit 6 successfully removes the fluctuation of the output X5. Since the ~ND gate 5 shows a fast response at the time of rising, even the whole circuitry 3-7 is capable of rapidly operating when signal reception is started.
Referring to Fig. 3, a digital signal repeater in accordance with another embodiment of the presen~ invention is shown. As shown, the repeater in this particular embodiment is constructed by adding to the repeater of FIG. 1 a time constant circuit 21, a comparison circuit 22, and a resistor 27, so that even more positive operation than the repeater of FIG. 1 may be accomplished at -the time of signal reception. Specifically, in Fig n 3, data indicative of a level of recovered clock is picked up from the output xl2 of the detector 12 and applied to the time constant circuit 21. Comprising a resistor 23 and a capacitor 24, the time constant circuit 21 removes fluctuation taking a substantial period of time. The comparison circuit 22, i.e., a differential amplifier 25 compares an output of the time constant circuit 21 with a reference voltage Vc4 which is determined by a lZ3~
potentiometer 26. In this construction, the output of the comparison circuit 22 becomes low level when the recovered clocX has been decided to be at a sufficient level taking a comparatively long period of time.
In this manner, the result of decision appearing at the output terminal of the comparator 22 is free from the influence of noise and that of a code pattern and, hence, it can be positively regarded as indicating that the receiver 1 is receiving a digital signal. At this instant, the level of the reference voltage Vc3 applied to the comparator 7 may be lowered by a suitable value by the output of the comparator 22 via a res~stor 2~ in order to stably mainta~n the output of the comparator 7 constant even when the output of the time constant circuit 6 undergoes significant fluctuation due to fading or any other cause.
In summary, it will be seen that the present invention provides a digital signal repeater which is immune to interference due to adjacent channels and the like and, yet, rapidly identifies reception of a digital signal.
The repeater, therefore, is desirably applicable to transmission control in a digital signal repeating system.
~ ;:
.
~ .: "~
DIGITAL SIGNAL REPEAT~R
INCLUDING MEANS FOR CONTROLLING A TRANSMITTER
Background of the Invention The present invention relates to a digital signal repeater for repeating digital signals and, more particularly, to a repeater of the type including a controller for controlling activation/non-activation of a radio transmitter.
A repeater of the type described is generally made up of a radio receiver, a radio transmitter, and a controller. The receiver receives a modulated wave from a terminal station or the like and demodulates it to provide a digital signal, while the transmitter transforms the digital signal again to a modulated wave which is sent to another terminal station or the like.
The controller controls the transmitter such that while a modulated wave is xeceived the transmitter is activated (turned on) to repeat a digital signal to another terminal station or the like and, while a modulated wave is not received, it is not activated (turned off) not to repeat a digital signal. Whe-ther or not a modulated wave has been received may be determined by detecting the level of a modulated wave in the intermediate frêquency IIF) band of the receiver.
~7~
Ho~ever, this kind of approach has the drawback that the IF band modulated wave level sometimes reaches a sufficient value even when an interference wave from another system is received, thereby undesirably activating the transmitter to repeat needless signals.
Summary of the Invention It is therefore an object of the present invention to provide a digital signal repeater having an improved controller which is free from the above-described drawback.
In accordance with the present invention, there is provided a digital signal repeater having a receiver for receiving a modulated carrier wave and demodulating a digital signal, a transmitter -Eor transmitting a carrier wave modulated by the digital signal, and a controller responsive to the output of the receiver for providing a control signal controlling the transmitting operation of the transmitter. ~he controller comprises first decision means for detecting the level of the modulated carrier wave of an intermediate frequency band of the receiver and providing a first signal, second decision means for detecting a clock frequency component in the output of the receiver and pro~iding a second signal, logic means responsive to the first and second signals for providing a third signal, first means for smoothing ~5 the third signal, and comparator means -Eor comp~i~
~2~
the output of the first means with a reference level and providing the control signal. ..
Brief Description of the Drawings The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken with the accompanying drawings in which.
FIG. 1 is a circuit diagram showiny a first embodiment of a digital signal repeater in accordance with the present invention;
FIGS. 2A - 2I are timing charts representative of the operation of the repeater shown in FIG. l; and FIG. 3 is a circuit diagram showing another embodiment of the pr~sent invention.
Detailed Description of the Invention Referring to FIG. 1 of the drawings, a digital signal repeater embodying the present invention is shown and generally comprises a receiver 1, a transmitter 2, and a controller 100. A carrier wave modulated by a digital signal and coming in through an antenna is applied to and amplified by a radio frequency (RF) amplifier 31 which is included in the receiver 1. The output of the RF amplifier 31 is converted by a frequency converter 32 to an intermediate frequency (IF) and, then, amplified by ~3 ~ 4 an IF amplifier 33. The modulated wave in the IF band is demodulated by a demodulator 3~ and, then, transformed into a digital signal (DATA).
In the transmitter 2, a modulator 41 modulates a r carrier wave again by the digital signal (DATA) and applies its output to a frequency converter 42 which converts the input to the RF band. The modulated wave in the RF band is transmitted via a power amplifier 43 to a terminal .station or another repeater (not shown) which follows the illustrated repeater.
The transmission control over the power amplifier 43 is performed by the controller 100 as will be described in detail hereinafterO
The controller 100 comprises a first aecision circuit 3, a second decision circuit 4, an ~ND gate 5, a time constant circuit 6, and a comparison circuit 7. The firs~ decision circuit 3 is adapted to detect the level of the IF modulated ~ave outputted from the IF amplifier 33 so as to determine whether nor not the receiver 1 is receiving a signal and, for this purpose, it comprises a level detector 8, a comparator or differential amplifier 9, and a potentiometer 10. As shown in FIG. 2A, the modulated wave IF has under-gone level fluctuation due to fading particular to a radio section. The level detector 8 is adapted to detect the modulated wave IF. As shown in FIG. 2B, the output x~ of 3~
the level detector 8 appears as an envelope. The comparator 9 compares the detector output x8 with a reference voltage Vcl which is determined by the potentiometer 10 and, if the former is higher than the latter, produces an output X3 showing that the receiver 1 is receiving a signal. The comparator output X3 is delivered to the AND gate 5 as an output of the first decision circuit 3 ~FIG. 2C).
The second decision circuit 4 is made up of a bandpass filter 11, a level detector 12, a comparator or differential amplifier 13, and a potentiometer 14.
The function assigned to the decision circuit 4 is detecting the level of a recovered clock which is synchronous with a received digital signal in order to see if the receiver 1 is receiving a digital signal.
Applied to the input terminal of the decision circuit 4 is a signal CF which contains a clock frequency component obtained by full-wave rectification of the output of the demodulator 34.
The bandpass filter 11 separates the clock frequsncy component from the input signal CF of the decision circuit 4, khereby producing an OlltpUt signal xll as shown in FIG. 2D. Comparing FIGS. 2A and 2D, it will be seen that the signal xll appears as noise so long as the receiver 1 does not receive a signal and, hence, the q'3~
-- 6 ~
~andpass filter 11 olltpUts a clock frequency component which is contained in the noise; as the receiver 1 receives a signal, the signal xll greatly flucturates because the clock frequency is significantly lower than the intermediate fre~uency and because the clock frequency component is effected by a code pattern of information which is being transmitted.
The level detector 12 detects a level of the signal xll to deliver an output xl2. As shown in F~G. 2~, the detector output xl2 appears as an envelope. The comparator 13 compares the signal xl2 with a reference voltage Vc2 which is determined by the pctentiometer 14 and, if the Eormer is higher than the latter, produces an output X4 (FIG. 2F) as an output of the decision circuit 4, showin~
that the receiver 1 is receiving a digital signal.
What is of prime importance here is how to mix the output X3 of the decision circuit 3 (FIG. 2C) and the output X4 of the decision circuit 4 (FIG. 2F). ~'he output X3 of the decision circuit 3 which shows whether or not a received intermediate frequency is present rises even when interference waves such as attributable to adjacent channels are receivedl if the interEerence waves are sufficient in level. Therefore, should the transmitter 2, i.e., the power amplifier 43 be activa-ted by the output X3 25 of the decision circuit 3 only, there would be brought about the problem oE erroneous repeating.
~z;~
Although the transmitter 2 may be activated by direc-tly using the output x~ of the decision circuit 4 only, such an approach also involves the fear of erroneous repeating considering the fact that the clock frequency contained in the noise waveform sometimes reaches a sufficient level even if the receiver is not receiving a signal.
In accordance with the present invention, the shortcoming of the decision circuits 3 and 4 as discussed above is compensated for by applying the output X3 of the decision circuit 3 and the output X4 of the decision circuit 4 to the time constant circuit 6 after the AND
gate 5. Specifically, when the output X3 of the decision circuit 3 has built up responsive to an interference wave as derived from another system or from adjacent channel, the output of the AND gate 5 does not rise because the clock frequency component cannot rise to a sufficient level.
When the output X4 of the decision circuit 4 has risen responsive to noise in a non-receiving condition of the receiver 1, it is not reflected by the outpu-t X5 of the AND gate 5 because the ou-tput of the decision circuit 3 remains logical "0" then.
The output X5 of the AND gate 5 (FIG. 2G) is routed to the time constant circuit 6. As shown, the time constant circuit 6 comprises an RC circuit made up of a resistor 15 and a capacitor 18 and, in addition, a series connection of a resistor 16 and a diode 17 which is connected in parallel with the resist~r 15, thereby attaining a fast rise response and a slow fall response.
Such a response characteristic of the time constant circuit 6 not only allows the response at the start of signal reception to be designed fast but also eliminates the influence of the logical "0" level of the output X5 of the AND gate 5 which may occur momentarily when the level of the modulated wave I~ has lowered due to fading or when the clock component of the input CF to the decision circuit 4 has decreased effected by a code pattern of information.
The output x6 of the time constant circuit 6 (FIG. 2H) is compare~ by a differential amplifier 19 of the comparison circuit 7 with a reference voltage Vc3 which is determined by a potentiometer 20, whereby a transmission control signal X7 ~FIG. 2I) is produced. The control signal ~7 is adapted to selectively enable and disenable the transmission of a wave by on-off controlling a power source associated with the power amplifier 43 or controlling an attenuator which is connected to the former stage of the power amplifier ~3.
In the particular embodiment shown in FIG. 1, each of the level detectors 8 and 12 is provided with a relatively fast response characteristic, that is, it responds within a relatively short period of time. Although such fast ...
response will be reflected by fast changes of "1" or "0"
in the output X5 of the AND gate 5, the time constant circuit 6 successfully removes the fluctuation of the output X5. Since the ~ND gate 5 shows a fast response at the time of rising, even the whole circuitry 3-7 is capable of rapidly operating when signal reception is started.
Referring to Fig. 3, a digital signal repeater in accordance with another embodiment of the presen~ invention is shown. As shown, the repeater in this particular embodiment is constructed by adding to the repeater of FIG. 1 a time constant circuit 21, a comparison circuit 22, and a resistor 27, so that even more positive operation than the repeater of FIG. 1 may be accomplished at -the time of signal reception. Specifically, in Fig n 3, data indicative of a level of recovered clock is picked up from the output xl2 of the detector 12 and applied to the time constant circuit 21. Comprising a resistor 23 and a capacitor 24, the time constant circuit 21 removes fluctuation taking a substantial period of time. The comparison circuit 22, i.e., a differential amplifier 25 compares an output of the time constant circuit 21 with a reference voltage Vc4 which is determined by a lZ3~
potentiometer 26. In this construction, the output of the comparison circuit 22 becomes low level when the recovered clocX has been decided to be at a sufficient level taking a comparatively long period of time.
In this manner, the result of decision appearing at the output terminal of the comparator 22 is free from the influence of noise and that of a code pattern and, hence, it can be positively regarded as indicating that the receiver 1 is receiving a digital signal. At this instant, the level of the reference voltage Vc3 applied to the comparator 7 may be lowered by a suitable value by the output of the comparator 22 via a res~stor 2~ in order to stably mainta~n the output of the comparator 7 constant even when the output of the time constant circuit 6 undergoes significant fluctuation due to fading or any other cause.
In summary, it will be seen that the present invention provides a digital signal repeater which is immune to interference due to adjacent channels and the like and, yet, rapidly identifies reception of a digital signal.
The repeater, therefore, is desirably applicable to transmission control in a digital signal repeating system.
~ ;:
.
~ .: "~
Claims (3)
1. A digital signal repeater having a receiver for receiving a modulated carrier wave and demodulating a digital signal, a transmitter for transmitting a carrier wave modulated by the digital signal, and a controller responsive to the output of the receiver for providing a control signal controlling the transmitting operation of the transmitter, characterized in that the controller comprises:
first decision means for detecting the level of the modulated carrier wave of an intermediate frequency band of the receiver and providing a first signal;
second decision means for detecting a clock frequency component in the output of the receiver and providing a second signal;
logic means responsive to the first and second signals for providing a third signal;
first means for smoothing the third signal; and comparator means for comparing the output of the first means with a reference level and providing the control signal.
first decision means for detecting the level of the modulated carrier wave of an intermediate frequency band of the receiver and providing a first signal;
second decision means for detecting a clock frequency component in the output of the receiver and providing a second signal;
logic means responsive to the first and second signals for providing a third signal;
first means for smoothing the third signal; and comparator means for comparing the output of the first means with a reference level and providing the control signal.
2. A digital signal repeater as claimed in Claim 1, wherein the first means shows a fast response to the start of the third signal and a slow response to the end of the third signal.
3. A digital signal repeater as claimed in Claim 1, wherein the controller further comprises third decision means for detecting that the clock frequency component in the output of the receiver has a sufficient level for a comparatively long period of time and varying the reference level.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP175844/1984 | 1984-08-25 | ||
| JP59175844A JPS6154743A (en) | 1984-08-25 | 1984-08-25 | Transmission control system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1239995A true CA1239995A (en) | 1988-08-02 |
Family
ID=16003201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000489294A Expired CA1239995A (en) | 1984-08-25 | 1985-08-23 | Digital signal repeater including means for controlling a transmitter |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4680772A (en) |
| EP (1) | EP0173526B1 (en) |
| JP (1) | JPS6154743A (en) |
| AU (1) | AU576124B2 (en) |
| CA (1) | CA1239995A (en) |
| DE (1) | DE3574213D1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2191067B (en) * | 1986-05-27 | 1990-07-11 | Motorola Israel Ltd | Broadcast re-transmission system |
| FR2628273B1 (en) * | 1988-03-02 | 1994-08-12 | Saleeby Robert | PULSE TRAIN TRANSMITTER |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3045185A (en) * | 1958-05-19 | 1962-07-17 | Rca Corp | Repeater station having diversity reception and full hot standby means |
| US3110768A (en) * | 1960-06-14 | 1963-11-12 | Bell Telephone Labor Inc | Pulse modulation regenerative repeater with selectively suppressed timing wave |
| US3383465A (en) * | 1964-03-30 | 1968-05-14 | Boeing Co | Data regenerator |
| US3621401A (en) * | 1969-09-23 | 1971-11-16 | Sierra Research Corp | Frequency spectrum responsive noise reduction system |
| US4327356A (en) * | 1979-06-19 | 1982-04-27 | Gilliland John D | Arrangement for monitoring the performance of a digital transmission system |
| DE3008076C2 (en) * | 1980-03-03 | 1982-05-06 | Siemens AG, 1000 Berlin und 8000 München | Device for switching off the receiver in the event of a small signal-to-noise ratio for a digitally modulated radio system with frequency modulation |
| GB2112607B (en) * | 1981-12-18 | 1986-01-02 | Senelco Ltd | Transmitter/responder systems |
| US4535460A (en) * | 1984-02-01 | 1985-08-13 | The United States Of America As Represented By The Secretary Of The Army | Method and apparatus to filter pulsed RF signals |
-
1984
- 1984-08-25 JP JP59175844A patent/JPS6154743A/en active Granted
-
1985
- 1985-08-16 US US06/766,262 patent/US4680772A/en not_active Expired - Fee Related
- 1985-08-16 EP EP85305861A patent/EP0173526B1/en not_active Expired
- 1985-08-16 DE DE8585305861T patent/DE3574213D1/en not_active Expired
- 1985-08-23 CA CA000489294A patent/CA1239995A/en not_active Expired
- 1985-08-23 AU AU46596/85A patent/AU576124B2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| EP0173526A2 (en) | 1986-03-05 |
| EP0173526B1 (en) | 1989-11-08 |
| AU576124B2 (en) | 1988-08-11 |
| US4680772A (en) | 1987-07-14 |
| EP0173526A3 (en) | 1987-04-15 |
| DE3574213D1 (en) | 1989-12-14 |
| JPH0213981B2 (en) | 1990-04-05 |
| JPS6154743A (en) | 1986-03-19 |
| AU4659685A (en) | 1986-02-27 |
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