CA1240034A

CA1240034A - Printer used for a television receiver

Info

Publication number: CA1240034A
Application number: CA000455773A
Authority: CA
Inventors: Shunichi Nakamura
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1983-06-08
Filing date: 1984-06-04
Publication date: 1988-08-02
Also published as: GB8414678D0; KR870001840B1; KR850000852A; DE3421446C2; GB2143065B; DE3421446A1; GB2143065A; US4626926A

Abstract

ABSTRACT OF THE DISCLOSURE
A printing system for a TV receiver comprises a memory for storing digital signals corresponding to the analog video signals input into the TV receiver;
read-out control circuit for reading out the digital signals stored in the memory; and a printer for print ing out the signals read out by the read-out control circuit, thereby making copies of the images shown on the TV screen.

Description

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The present invention relates to a printing sys-tem for a -television (hereinafter referred to merely as TV) receiver, and more particularly, to a printing system for making printed copies of the pictures shown on TV screens.
In general, there are T.V. programs from which viewers wan-t to record broadcast information for future reference. For example, in a "How-To-Cook"
program the housewives may want -to record -the cooking inEormation on the T.V. screens. However, under the present system of television receivers they have to write it down in their notebooks while watching the T.V. screen. This is very troublesome, and is actually a difficult task because they must keep up with the constant flow of the images on the screen, which go on without considering the viewers' convenience.
Recently, videotape recorders have developed, and it is true that they have solved this problem to a greater extent. However, in reproducing the videotape it is necessary to search and select tha-t part of the tape in which the information wanted by the viewer is recorded.
As generally known, the re-playing of selected parts of . ~, . . . :

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the tape i.s time- and labor-consuming, so that the housewives are often discouraged from reproducing -the vldeotape in spite of the eEEort exerted by them in recording.
It is an object of the present invention to provide a printing system Eor a TV receiver which enables printed copies to be made oE pictures shown on the TV screen, thereby eliminating the inconvenience involved in note-taking and reproducing selected parts of a videotape.
According to one aspect o the present invention~
there is provided apparatus for printing images corr~sponding to a TV video signal, comprising, means Eor writing digital representations of the video signal to predeterrnined memory addresses, each memory address corresponding to a respect.ive pixel of the video signal, a read-out control circuit means for reading out the stored digital representations in the same order as they were written into the memory addresses, and a printer arranged to print an image corresponding to the stored digital representations under the control of the read-out control circuit.
The invention further provides in another aspect thereoE, apparatus for printing images corresponding to a TV video slgnal, comprising, a writing address control circuit for generating row address signalsy and column address signals except when generating the :row address signals, a shift reyister to which digital signals corresponding to the TV video signal are input, and which outputs the :input digital signals as non-delayed output signals and delayed signals which are delayed by a strobe signal time which is required for delivering the row address, a multiplexer to which the outputs o~ the shift register are input, and which generates output signals delayed relative to any previous outputs therefrom by a strobe signal time which is required for delivering the row address when and aEter each row address signal is generated, a video memory having memory addresses to which respective output signals oE the multiplexer are input, ~2~ 3~
- 2a -and which store the signals input in accordance with the row and column address signals from the writing address control circuit, a read-out control circuit for reading out the signals stored in the video memory, and a printer for printing out the signals read out by the read-out control circuit.
The invention wilL be more readily apparent from the following description oE a preEerred embodiment thereof when taken in conjunction with the accompanying drawings, in which:-Figure 1 is a block diagram exempliEying the basic i3~

principle o:E -the present inven-tion;
Figure 2 is a block diagram illustrating a print-ing sys-tem em~odyina the ~resent lnven-tion;
Figure 3 is a circuit diagram of a counter used in the printing sys-tem oE Figure 2;
Figure 4 is a circuit diagram of a shiEt register used in the printLng sys-tem of Figure 2;
Figure 5 is a circuit diagram of a multiplexer used in the printing system of Figure 2;
Figure 6 is a circuit diagram of an address counter used in the printing system of Figure 2;
Figure 7 is a circuit diagram oE an address switching circuit used in the printing system o E Figure 2;
Figure 8 is a time table showing the -transfer time for each gradation density pattern;
Figure 9 is a table showing the relation between the gradation density patterns and the signal of "1" or "0" used in an operation of the printing sys-tem oE Figure 2;
Figure 10 is a flow chart showing the operation of -the read-out control circuit shown in Figure 2 Figures 11 and 12 are graphs showing the relationship between the optical density on a thermal paper and the applied temperature thereto, and between the optical density on a thermal paper and the time for current passing through thermal paper; and ~, . . .

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Figure 13 is a timing diagram exemplifying the sequence of operation of the system illustrated in Figure 2.
seEore entering into a de-tailed description, -the basic principle of the present invention wil:L firstly be described.
When the images appearing on -the TV screen are to be hard-copied, the copying speed is normally slower than the scanning speed of the video signals.
As a resul-t, it is necessary to conver-t -the video signals in-to sui-table corresponding signals, which are then -temporarily stored in a memory. Finally, the stored signals are read out for print-out.
ReEerring -to Figure 1, there are provided an A/D
(analog/digltal) converter I which receives analog video input signals V of a TV receiver at its input, and outputs digital gradation density signals in response to the video input signals V, the gradation densi-ty signals being divided into a predetermined number of levels corresponding to the varying densi-ty of -the video signals V: a memory II, which stores the gradation density signals from the A/D converter: a read~out control circuit III which reads out the gradation density signals stored in the memory; and a printer IV which prints out the signals read out by the read-out control circuit.
I'he A/D converter can be any -type iE it can output 16 gradation density signals, such as "0000", "0001", ..., "1101", ..., "1111" so as to represent 16-gradated densities in response to the video signals. A/D
converters available in the market are effectively applicable. Eor the memory II a random-access-memory (RAM) can be effectively used.
A first method of writing the gradation density signals in the memory II in the above-mentioned sys~
tem will now be described.
The gradation density signals from the A/D
converter are stored in a shift register, and each oE a plurality of picture elements, such as 4 elements, is written in its corresponding RAM in 4 sets of RAMs.
~nder this method, if the sampling is performed in one scanning line at 167 nsec, the picture elements in the scanning line will amount to 2~0. rhere are 234 scanning lines in one video field. AS a result, four RAMs each having 16Kbits are required. In addition, each of the picture elements has 16-gradated densities.
Accordingly, four sets of RAMs are provided, and as a , whole sixteen RA~Is constitute the memory II.
A second method of writing in the memory II is performea by a page-mode access method. According to this method, at first a row address strobe signal (hereinafter referred to as RAS signal) is made "l", thereby providing a row address signal, and for the row address a column address strobe signal (hereinafter referred to as CAS signal) is periodically made "1".
Each time when it is made "1", the column address signal is given, thereby effecting the column addressing. This page-mode address method is advantageous in that after a row address signal has been given, it is no longer necessary to repeat it, and it has only to give column address signals. This secures a real-time writing. According to this method, it is possible to store gradation density signals for one video field in the four 64-Kbit RAMs, thereby reducing the required number of RAMs. Advantageously, four RAMs are effectively sufficient, which leads to simplicity and economy in production, particularly itl comparison with the first-mentioned method under which each four picture elemen-ts are written in Eour RAMs at the same time. However, under the page-mode access method a period of time for which the RAS signal is "0"
is lO~ sec at maximum. Furthermore, the 64-Kbit RAM

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has a disadvantage that if the column addresses exceed 256 addresses, it becomes necessary to give new address signals because of the change in the column address.
As a result, it is required to change the RAS signals into "1" several times within one scanning line, and while it is "1", no data can be written in. The mere employment of the page-mode access method cannot solve this problem. In this case, it is likely to happen that the pictures are void of the picture elements which correspond to the unwritten data, which resulting in the abnormal images.
A third method of writing in the memory II is achieved as follows:
The gradation density signals obtained from the video signals are temporarily stored in the RAM under the page-mode access method, and the s-tored signals are read out for print-out, wherein the gradation density signals are input to the shift register, and wherein an output signal from the shift register which is delayed relative to the previous output therefrom by a period of time for the RAS signal is selected for being input to the RA~ when and after each row address signal is generated in one scanning line of the video signals.
Accordiny to this method the images of the TV receiver are au-tomatically printed out with the use of a small ~2~ 3~

number of RAMS. In addition, the images on the print are very normal.
This third method of writing in the memory II will be more particularly described with reference to Figures 2 and 3:
The reference numerals la to ld each designate a serial writing data, which is each bit of a 4-blt gradation density signal. As described above, these gradation density signals are those which are obtained by converting videa signals into digital signals by the A/D converter, and consist o~ sixteen signals of "00001' , . . ., ~ 50 as to represent 16-gradated densities corresponding to the video signals. The reference numeral 2 designates a clock pulse generator which generates clock signals having a period of 167 nsec. The reference numeral 3 designates a counter which counts the clock signals Eor a period of time when the count-enable signal a is input thereto, an example of which is illustrated in Fig. 3. In Figure 3, the reference symbols CG7-CG9 and CGll-CG14 designate logic gates, and the reference symbols CF6 to CF8 designate Elip-flops, respectively. There are provided four shiEt registers 4, to each of which the writing data la to ld are input at timings of its own clock signals.
The data 1a to ld are output from the outpu-t QA of each ~2~ 3~
g shift register ~, whereas from each of the ou-tpu-ts Qs -to QF -the data la to ld are output wi-th predetermined time delays. An example of the shi-f-t register 4 is illustrated in Figure 4. In Figure 4 showing a 6-bit shift register, the reference symbols SG20 to SG22designate logic ga-tes, and the reference symbols SF1 to SF3 designa-te flip-flops, respectively.
The reference numeral 5 (Fig. 2) designates mul-ti-plexers loca-ted in opposition -to the ou-tputs QA -to QF of the shift registers 4, -the multiplexers selective-ly outputting signals from -the outputs QA to QF in accordance with the values counted by -the counter 3, an example of which is illustrated in Figure 5. In Figure 5 showing a 6-bi-t multiplexer, the reference symbols SG~ to SGl4 designate logic ga-tes, and the reference symbols STlO to STll designate logical cir-cuits, respectively. In the Figure 2 the shift re-gisters and the multiplexers -to which the data lc and ld are to be input are omitted for simplicity.
There is provided a video memory 6, which s-tores gradation density signals to be printed out. The out-pu-ts from -the multiplexer 5 are input to -the video memory 6, which consists of Eour 64-Kbit RAMs~ The reference numeral 7 designates a RAS/CAS control circuit, which delivers to the video memory 6 RAS

, f. ....

- 10 ~

signals (row address strobe signals) and CAS signals (column address strobe signals), and generates address switching signal b. The reference numeral 8 designates an address counter, which counts up clock signals and generates an 8-~it row address signal as the upper address as well as an 8-bit column address signal as the lower address, an example of which is illustra-ted in Figure 6. In Figure 6, the re~erence symbols JGl -to JG53 designate loyic ga-tes, the reference symbols KO9 to KO17 designate logical circuits, and the reEer-ence symbols KF9 to KF16 designate flip-flops, res-pectively.
The reference numeral 9 (Fig. 2) designates an adaress swi-tching circuit, which delivers to the video memory 6 either -the row address signal or the column address signal in accordance with an address switching signal b from the RAS~CAS control circuit 7, wherein the row or the column address signal is delivered from the address coun-ter 8.
An example of the address switching circuit 9 is illustrated in Figure 7. In Figure 7, -the reEerence symbols SG6 and SG7 designa-te logic gates, and the reEerence symbols ST2 to ST9 designate flip-Elops, respec-tively. The reference numeral 10 designates an address decoder, to which -the column address signal is inpu-t, and which outputs the sigral "1" each time thirty-two column addresses are ou-tput therefrom. The address decoder 10 is constituted by a NOR circuit.
The reference numeral 11 designates a flip-flop, which outputs the signal "1" in synchronism with the nex-t clock from -the clock pulse generator 2 in response to the signal "1" outpu-t by the address decoder 10. The signal "1" of the flip-Elop 11 becomes a coun-t-disenable signal c and a control signal d directed -to the RAS/CAS
control circuit 7.
In Figure 2 -the frame defined by do-tted lines 12 is a writing address control circuit. This circui-t 12 is designed to deliver row address signals to the video memory 6, at each beginning of the row and subse-quently at time-intervals not exceeding 10 ~sec for the same row, and also to count up and deliver column address signals except when i-t aelivers the row address signals. The reference numeral 13 designates a read-out control circuit which reads out -the gradation densi-ty signals stored in the video memory 6, which includes a memory section in which such a -time table as shown in Figure 8 is s-tored, a CPU including a coun-ter capable of counting up the counts corresponding to the transfer -time shown in Figure 8 stored in the memory section, wherein one count is 5.5/~s, and a head drive circui-t operating on -the output ~rom the CP~. For example, when a "0100" signal whose gradation densi-ty is 4 is output from the video memory 6, the 1st -to 4th gradation density patterns (hereinafter referred to as GDPl to GDP4) are represented by signal "1", whereas 5th to 15th gradation density patterns (GDP5 to GDP15) are represented by signal "0" in the CPU, and the output "1" is output from the counter in the CPU for a period of time which corresponds to the sum of the transfer times for gradation density patterns for which the siynal is made "1", that is, the patterns from GDPl to GDP~ in this case, with which output "1" the head drive circuit is driven. Figure 10 shows a flow chart of the operation in sequence of the read-out control circuit 13.
The reference numeral 1~ designates a printer which prints out the signals read out by the read-out control circuit 13. The printer can be a thermal printer with a thermal head. The paper on which data is printed is susceptible to -temperature, and changes its color density as shown in Figure 11. The temperature of the thermal head is proportional to the applied voltage squared and also to the time for which an electric current passes through the thermal head.
When the applied voltage is constant, it is exclusively proportional -to the current passing -time. The relationship between the color density on the paper and ~2~
- 13 - .

the current passing time is as shown in Figu~e 12. As a result, the thermal head is energized for a period of time based on the gradation density signals input from the read-out control circuit 13 with the relation shown in the time table, wherein the thermal head is constructed of thermal thyristor. In this way the characters are printed on the paper with density depending on the gradation density signals or in other words, the video signals.
Referring to Figure 13, which shows a timing diagram of the input and ou-tput signal in each element, the operation of the system will be described:
When the copy key (no-t shown) is turned on, the writing data la to ld in the first scanning line are input to the shift registers 4 at timings of clock pulses Erom the clock pulse generator 2. The multiplexer 5 selects the QA output of the shift regis-ter 4, and the non-delayed 4-bit data la to ld from the QA output are output to the video memory 6 in such timing as shown in Figure 13 (c). In the writing address control circuit 12 the RAS signal is delivered to the video memory 6 Erom the RAS/CAS control circuit ~ 7 as shown in Figure 13 (a). In response to the address switching signal b from the RAS/CAS control circuit 7 the address switching circuit 9 selects the :.~

~2~ 3~

row address bus 15, and the row address signal from the address counter 8 is delivered to the videom memory 6 in synchronism with the falling of the RAS signal. In response to the delivery of the row address signal the CAS signal is delivered to the video memory 6 from the RAS/CAS control circuit 7 as shown in Figure 13 (b).
At the same time the address switching circuit 9 selects the column address bus 16 in accordance with the address switching signal b ~rom the RAS/CAS control circuit 7, and the column address signal ~rom the address counter 8 which counts up the clock signals is delivered to the video memory 6 in synchronism wi-th the falling of the C~S signal. When the column address is established (Refer to A in Figure 13 (b)), the non-delayed data la to ld from the multiplexer 5 are written in the video memory 6.
The column address signal Erom the address counter 8 is also input to the address decoder 10, and when -the 32nd column address signal is delivered to the video memory 6, thereby allowing the 32nd data la -to ld to be written in the video memory 6, the signal of the address decoder 10 becomes "1" at the reception of the ~ 32nd column address signal as shown in Figure 13 (c).
- The signal "1" is input to the flip-Elop 11, and at the same time, i-t is added to the counter 3 as the 33~

count-enable signal a, thereby causing the counter 3 to count the clock signals, and the multiplexer 5 selects the l-bit delayed Qs output of the shift register 4 in accordance with the value counted by the counter 3, and in such timing as shown in Figure 13 ~d) the l-bit delayed data la to ld are written in the video memory 6 (Figure 13 (g)). At this time the writing address control circuit 12, as shown in Figure 13 (f), allows the flip-flop 11 to ou-tput the signal "1" in synchronism with the next clock si.gnal in response to the signal "1'l generated by the address decoder 10.
The signal "1" is added as the count-disenable signal c to the address counter 8, which stops its operation after having counted the clock signal. At the same time the signal ~ of the flip-flop 11 is added as the control signal d to the RAS/CAS control circuit 7, from which the RAS signal is added to the videom memory 6.
In addition, in accordance with the address switching signal b from the RAS/CAS control circuit 7 the address switching circuit 9 selects the row address bus 15, thereby delivering the same row address signal as the initial one, to the video memory 6. Then, the CAS
signal and the column address signal are delivered to the video memory 6 in the same manner. In this way the l-bit delayed data la to ld are written in the video 3~

memory 6, wherein the l-bit delay corresponds to the period of -time for which the row address signal is added to the video memory in the above-mentioned manner. Each time when the thirty-two data la to ld are written in the video memory 6, the RAS signal becomes "1", and the row address signals in this particular row are delivered, and afterwards a l-bit delayed data la to ld are written in.
When the data la to ld are written in the last address "255" among the 0-to-255 addresses in the first row of the video memory, the address signal for the last address "255" (which is the 256th address, amounting to the integral multiplication oE 32) allows the signal of the address decoder 1~ to become "1". At the next clock pulse the signal of the flip-flop 11 becomes "1", and the address counter 8 counts 256 and stops its operation. Immediately upon the stoppage of the counting, the RAS signal is added to the video memory 6. Simultaneously, the row address signals oE
the second row are delivered -thereto, and the remaining data la to ld oE the first scanning line are also written in these addresses oE the second row.
If the scanning lines to be written vary, the output selected by the multiplexer 5 re-turns to the QA
output of the shift register ~, and the data la to ld ... .

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of the varied scanning lines are writ-ten in the video memory 6 in the same manner as described above.
When the data la to ld of one field are completely written in the video memory 6, the read-out control circuit 13 starts to read the data la to ld in this field one after another, and based on each data, outputs the data so as to control the time for which the thermal head is energi~ed. In this way the printer 14 prints out the data in one field, thereby allowing each image to be hard-copied.
As evident from the foregoing description, according to the present invention i-t is easy to make hard-copies of the pic-tures on T.V. screen, which provides a great facility for T.V. viewers. Each time -the row address signal is genera-ted, -that output of the shift register which is delayed by a period of time for a row address strobe signal to deliver this particular row address signal is selected and written in the video memory 6. This ensures that all the gradation density signals can be stored in seq~ence and at exact positions, thereby creating a normal clear picture. In addition, the real-cime writing is possible, and therefore, the number of RAMs used is considera~ly reduced, thereby resulting in an economical production cost. In this regard the present D3~

invention is more advantageous than the conventional method in which the picture elements are converted into parallel data and written in the video memory.
The present invention is not limited to the embodiment described above, but as referred to in the beginning, various changes and modifications within the spirit and scope of the invention are possible: For example, the time for the RAS signal being "1" is not limited to a time for 1 bit, but may be a time for multiple bits. The gradation number of gradation densities is not limited to 16, but may be other gradation number. In general, when the gradation number is 2n, the video memory can be constructed with n pieces of RAMs.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. Apparatus for printing images corresponding to a TV
video signal, comprising:
means for writing digital representations of said video signal to predetermined memory addresses, each said memory address corresponding to a respective pixel of said video signal:
a read-out control circuit means for reading out the said stored digital representations in the same order as they were written into said memory addresses and a printer arranged to print an image corresponding to said stored digital representations under the control of said read-out control circuit.

2. Apparatus as claimed in Claim 1, wherein said stored digital representations are multi-bit density gradation signals representative of the brightness of said pixels.

3. Apparatus as claimed in Claim 1, further comprising addressing means for addressing said memory addresses, said addressing means being arranged to address said memory locations by a page mode access method wherein each row address is readdressed at predetermined intervals before the next row address is addressed and said digital representations are written to said memory locations with time delays corresponding to the time taken to readdress said row address locations.

4. Apparatus as claimed in Claim 3 wherein said digital representations are fed through a shift register and outputs of said shift register are sequentially selected to achieve successively greater time delays of said digital representations, successive delays being synchronized with the re-addressing of rows of address locations.

5. Apparatus as claimed in Claim 4 wherein said addressing means is arranged to generate either row address signals or column address signals according to the state of a two-state control signal.

6. Apparatus as claimed in Claim 5 including counting means coupled to said addressing means and said shift register, said counting means being arranged to select an output of said shift register in accordance with the currently addressed memory locations.

7. Apparatus as claimed in Claim 2, 3 or 4, wherein different bits of the same digital representation are written in parallel to respective memory locations.

8. Apparatus for printing images corresponding to a TV
video signal, comprising:-a writing address control circuit for generating row address signals, and column address signals except when generating the row address signals;
a shift register to which digital signals corresponding to said TV video signal are input, and which outputs the input digital signals as non-delayed output signals and delayed signals which are delayed by a strobe signal time which is required for delivering the row address;
a multiplexer to which the outputs of the shift register are input, and which generates output signals delayed relative to any previous outputs therefrom by a strobe signal time which is required for delivering the row address when and after each row address signal is generated;
a video memory having memory addresses to which respective output signals of the multiplexer are input, and which store the signals input in accordance with the row and column address signals from the writing address control circuit;
a read-out control circuit for reading out the signals stored in the video memory; and a printer for printing out the signals read out by the read-out control circuit.

9. Apparatus printer as defined in Claim 8, wherein the digital signals are gradation density signals established in accordance related densities of said TV video signal.

10. Apparatus for printing images corresponding to a TV
video signal, comprising:
a writing address control circuit for generating row address signals at each beginning of a row and subsequently at time-intervals not exceeding a predetermined period of time for the same row, and for counting up and generating column address signals except when generating the row address signals;
a shift register to which gradation density signals corresponding to the TV video signal are input, and which outputs input digital signals as non-delayed output signals and delayed output signals which are delayed by a strobe signal time which is required for delivering a row address;
a multiplexer to which the outputs of the shift register are input, and which generates output signals delayed relative to previous outputs therefrom by a strobe signal time which is required for delivering the row address when and after each row address signal is generated from the writing address control circuit;
a video memory to which the output signals of the multiplexer are input, and which stores the signals input in accordance with the row and column Address signals from the writing address control circuit;
a read-out control circuit for reading out the signals stored in the video memory; and a printer for printing out the signals read out by the read-out control circuit.

11. A printer as defined in Claim 10, wherein the number of gradation density levels is 2n, and wherein the video memory comprises n separate RAMs.

12. Apparatus for printing images corresponding to a TV
video signal, comprising:
a writing address control circuit for generating row address signals at each beginning of a row and at each address exceeding the row, and for counting up and generating column address signals except when generating the row address signals;
a shift register to which gradation density signals corresponding to the TV video signal are input, and which outputs input digital signals as non-delayed output signals and delayed output signals which are delayed by a strobe signal time which is required for delivering the row address;
a multiplexer to which the outputs of the shift register are input, and which generates output signals delayed relative to previous outputs by a strobe signal time which is required for delivering a row address when and after each row address signal is generated within one scanning line of the video signal;
a video memory to which the output signals of the multiplexer are input, and which stores the signals input in accordance with the row and column address signals from the writing address control circuit;
a read-out control circuit for reading out the signals stored in the video memory; and a printer for printing out the signals read out by the read-out control circuit.