CA1240081A - Overlaying information on a video display - Google Patents
Overlaying information on a video displayInfo
- Publication number
- CA1240081A CA1240081A CA000475192A CA475192A CA1240081A CA 1240081 A CA1240081 A CA 1240081A CA 000475192 A CA000475192 A CA 000475192A CA 475192 A CA475192 A CA 475192A CA 1240081 A CA1240081 A CA 1240081A
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- CA
- Canada
- Prior art keywords
- video signal
- transistor
- voltage level
- response
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
- G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
- G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
- G09G1/16—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
- G09G5/026—Control of mixing and/or overlay of colours in general
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/12—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
Abstract
Abstract Of The Disclosure A normal video signal and an overlay video signal are combined by supplying the normal video signal to the base of a first emitter follower transistor while the overlay video signal is supplied to the base of a second emitter follower transistor. The two transistors are biased such that the first transistor is at a slightly lower voltage than the second (overlay) transistor and is reversed biased (off) any time data is available from the overlay video signal.
Description
OVERLAYING INFORMATION ON A VID~O DISP~AY
This invention rela-tes to displaying information on a video display. In oae aspect, this invention relates to method and apparatus for displaying at least two different displays of informa-tion on a video display.
Brief Description of the Drawings All of the drawings are briefly described as follows:
FIGURE 1 is a diagrammatic illustration of a conventional system for displaying data provided by a computer on a CRT using one display generator;
FIGURE 2 is a diagrammatic illustration of the use of two display generators to provide information from a computer to a video display;
FIGURE 3 is an illustration of a problem which may occur using the display system of FIGURE 2;
FIGURE 4 is an illustration of a desired display of both graphical and alphanumeric data;
FIGURE 5 is an illustration of the circuitry used in accordance with the present invention to combine a normal ~ideo signal and an ~ overlay video signal for a black and white display;
;~ 20 FI&UR~ 6 is an illustration of part of the circui~ of FIGURE 5 ; with speciic xesistance and voltage values; and FI&URE 7 is an illustration of circuitry which may be utilized in accordance with the present i~ention to combine the normal video signal and overlay video signal for a color system.
A con~entional system utilizing a video display (typically a CR~) is -i~lustrated in FIGURE 1. A computer 11 is mterfaced to the t ~"s ?~
~ , ., display generator 12. In general, the display generator 12 takes data supplied from Lhe computer 11 and converts the data into an EIA Standard RS-170 format which can be utilized to drive the CRT 14. EIA S~andard RS~170 defilles a method for combining the sync~ blanking and video signals required by a CRT onto a s:ingle coaxia:L cable. The thus combined signal is generally referred to as a composite video waveform. For a color system, only the green channel contalns the sync signal.
Additional coaxial cables are required for the red and blue video signals.
The display genera-tor 12 typically contains at least interfacing circuitry, a refresh memory, a character generator and video processing circuitry. In many applications, character addressing is used for the display generator 12. In character addressing, each location (address) in the refresh memory corresponds -to one character on a CRT
screen rather than one dot. A character will generally be made up of an array of dots on a CRT screen. A typical arrangement is a matrix of 7 dots x 10 dots to form a character. This yields 70 dots per character ; which may be "on" or "off" in any combination to form any particular character.
The refresh memory location corresponding to any particular CRT
screen position may contain as little as a 6 to 3 bit code (typically ASCII) specifying which character (of a set) is desired at that position.
Thus, the 70 dots in the character on the screen are compressed into 6 to 8 bits in the refresh memory. Character addressing thus res-tricts the amount of information which can be displayed on the CRT and also the location at which the data can be displayed, but character addressing does have several advantages such as the reduced size of the refresh memory required as opposed to a system in which dot addressing is utilized.
In many applications it is frequen-tly desired to display two different sets of information such as a graphical representation and alphanumeric information. An example of such an application is process control where it may be desired to display a graphical representation of a yrocess and periodically add alphanumeric information for process conditions.
For the system illustrated in FIGURE 1, alphanumeric data must be placed on the CRT in such a way as not to overwrite any graphical ~ 31402CA
display characters or the graphical display chaYacters ~ill be destroyed.
This occurs because, if an alphanumeric character is written over a graphical character in a character addressed video display system, the entire graphical character is destroyed even though only a few of the 70 dots in the character may be used for the alphanumeric character.
It would be desirable to overlay or superimpose the alphanumeric character over the graphical character in such a manner that the alphanumeric character may be read but the graphical character, and thus the continuity of -the graphical display, is not des-troyed. One method which has been sugges-ted for accomplishing this is as illustrated in U.S. 4,200,869. The solution of U.S. 4,200,g69 is very broadly illustrated in a block diagram format in FIGURE 2.
Referring now to FIGURE 2, computer 11 is again interfaced to the display generator 12. However, a second display generator 16, which is addressed in parallel with the display generator 12, is added in the teachings of U.S. 4,200,869. Parallel addressing refers to addressing such that the video signals of display generators 12 an~ 16 would be applied to the same dot on the CRT 14. The output from both the display genera-tor 12 and display generator 16 are provided to the OR gate 18 with the output of the OR gate 18 being utilized to drive the CRT 14.
The display generator 12 may be utilized -to generate the video signal required for the graphical display. In like manner, -the display generator 16 may be utilized to generate the video signal required for the alphanumeric informa-tion. These two signals are combined and provided to the CRT 14. The result is an overlay of the graphical display and the alphanumeric information.
One of the problems with the system illustrated in FIGURE 2 is illustrated in FIGURE 3. Referring now to FIGURE 3, assume that the graphical character is a solid block. Also, assume that the alphanumeric word is the word BAD. Because no priority can be assigned in the system of FIGURE 2, the letter A would completely disappear. Thus, the use of an OR gate to combine the two video signals is feasible only where neither video signal utilizes a major number of the dots in a character on a ~RT screen.
FIGURE 4 illustra-tes a more desired overlay of the graphical and alphanumeric data. Referring now to EIGURE 4, it can be seen that, in the more desired sltuation, the overlay video ~alphanumeric) has been ~.
made brighter than the graphical display. This results in a true overlay in that the alphanumeric word can be read an~ the graphical display remains undisturbed except to the extent of the dots re~uired to form the letter A. Other dots remaining in the character block utilized to form the letter A can continue to be used for the graphical display.
It is thus an object oE this invention to provide method and apparatus for displaying alphanumeric and graphical data on a character oriented video display in such a manner that a priority is assigned to the alphanumeric data such that the alphanumeric data can be seen as illustrated in FIGURE 4.
As used herein, the term "overlay video signal" refers to the video signal which is given priority and the term 1'normal video signal"
refers to -the video signal which i5 not given priority. In most cases -the normal video signal will produce a graphical display and the overlay video signal will produce an alphanumeric display. Thus the present invention is sometimes described herein in ~erms of displaying both graphical and alphanumeric informa-tion. However, the invention is not limited to the display of such in~ormation and could be utilized to display other types of inEormation or could be u~ilized to display two sets of the same type of information (such as graphical) where it is desired to give priority to one set.
In accordance with the present invention, two transistors, configured as emitter followers and sharing a common emitter resistor, are u-tilized to combine the normal video signal and -the overlay video signal in such a manner that the reslllts illustrated in FIGURE 4 are achieved. Essentially, the normal video signal is supplied to the base of a first e~itter follower t~ansistor while the overlay video signal is supplied to the base of a second emitter follower transistor. The two transistors are biased such that the first transistor is at a slightly lower voltage than the second (overlay) transistor and is reversed biased (off) any time data is availab:Le from the overlay video signal. Thus, the selection of the video signals is accomplished based on the video signals and very fast and clean s~itching is provided. Also, the visibllity of the overlay video signal is improved by using a higher voltage for the overlay video signal than for the normal video signal.
., , ~2~
Other objec-ts and advantages of the inven-tion will be apparent from the foregoing brief description of the invention and the claims as well as from the description of the drawings.
The invention is described in terms of the use of two display generators for the sake of convenience. However, the invention is applicable to combining the video signals Eroln more than two display genèrators iE desired.
The invention is also described in terms of specific electronic components. However, the invention is a-pplicable to different electronic circuit configurations which carry ou-t the purpose of the present invention and is also applicable to different circuit components which are supplied by a plura]ity of vendors.
Referring now to ~IGURE 5, there is again illustrated the host computer 11, display generators 12 and 16 and the CRT 14. Any suitable computer and CRT can be utilized. The computer and CRT utilized in the particular system to which the present invention was applied were the Motorola MC6800 MPV and Aydin 8830 Color C~T.
The display generators 12 and 16 may be any desired display generators. Display generators are well known in the art and, as has previously been stated, will g~nerally contain an interface to the computer 11, a refresh memory, a charac-ter generator which may be either a random access memory or an erasable programmable read-only memory and other video processing circuitry. Since the present invention is concerned with combining of video signals and no-t with generation of the video signals, the display generators 12 and 16 will not be more fully described hereinafter.
Display generator 12 provides a normal video signal 21 to the base of the transistor 23 which is an NPN transistor configured as an emit-ter follower. The normal video signal 21 may be a composite video waveform containing sync, blanking and video signals, as previously described, or may be a serial video waveform containing only video signals. If the video waveform 21 is a serial video waveform, then the blanking and sync signals would typically be added before a signal is provided to the CRT 14 but since the addition of such signals plays no part in the description of the present invention, such addition is not illustrated~
The overlay video signal 2~ is provided from the disp:Lay generator 16 to the base of the transistor 26 which, 1ike transistor 23 is an NPN transistor configured as an emitter follower. The video waveform 24 will not contain sync signals since these signals are S provided by the "normal" channel and will thus be serial video only.
The video signal 21 will be a stream of serial data. The normal v:ideo signal 21 is actually provided to the base of transistor 23 by "modulating" the voltage at node 27 which is established by the bias resistors 28 and 29 in conjunction with the supply voltage 32. Since the driving devices in display generators are open collector devices, the voltage at node 22 will ei-ther be essen-tially zero when the normal video signal 21 is not in a state which will cause a do-t on the CRT to be illuminated (referred to hereinafter as "low"~ or will be at a voltage level determined by the magnitude of the supply voltage and the values of the bias resistors 28 and 29 if the video signal is in a state which will cause a dot on the CRT to be illuminated (referred to hereinafter as "high"). Thus, either an ~ssentially zero voltage is applied to the base of the transistor 23 or a vo]tage level greater -than zero but less than 5 volts is applied.
In li~e manner~ the overlay video signal 24 modulates the voltage at node 34. Again, the voltage at node 34 will either be essentially zero when the data in the overlay video signal is low or will be at some positive voltage level determined by the magnitude of the supply voltage 32 and the value of the bias resistors 37 and 38 if the da-ta in the overlay video signal is high. Thus, as with transistor 23, the voltage applied to the base of -the transistor 26 will either be essentially æero or will be a positive voltage.
Transistors 23 and 26 share a common emi-tter resistor 41. The emitters of transistors 23 and 26 are also -tied to the CRT 14 -through the coupling resistor 44.
For almost all CRT's, the screen is filled beginning at the upper left hand corner and continuing horiæontally across the screen to the upper right hand corner on a dot-by-dot basis. The electron beam then goes to the left-hand side oE the screen on the second row during a blanking pulse and the second row is filled. This process continues until the electron beam reaches the lower right-hand corner of the screen . *
at which time the vertical sync pulse occurs causing the electron beam to return to the upper left-hand corner of the screen.
When the screen is being filled, the normal video signal 21 will be at a high value if a first dot is to be illuminated or will be at a low value if -the first dot is to be left off. In like manner, at the same time, overlay video signal 24 will be at a hlgh level if the first dot is to be illuminated and will be at a low level if the first dot is to be left off. Priority is assigned to overlay video signal 24 by the circuitry illustrated in FIG~RE S as will be more fully described hereinafter. Thus, if the normal video signal 21 would require the first dot to be illuminated and overlay video signal 24 would require the first dot to be illuminated, then the first dot will be illuminated in response to overlay video signal 24. The manner in which this is accomp:Lished is illustrated in FIGURE 6 where specific voltage and resistance values have been assigned for the sake of illus-tration.
Referring now to FIGURE 6, for the resistor and voltage values illustrated in FIG~RE 6 and the particular system to which the present invention was applied, node 27 will have a voltage level of about 3.33 vol-ts if the normal video signal 21 is high and will have a voltage level of essentially zero if the normal video signal 21 is low. Node 34 will have a voltage level of about 3.57 volts if the overlay video signal 24 is high and will have a voltage level of essentially zero if the overlay video signal 24 is low.
If, for a particular point (dot 1) on -the CRT screen, video signal 21 is high and video signal 24 is low, then transistor 23 will be turned on and transistor 26 will be reversed biased or off. Due to the typical 0.6 volt base emit-ter drop, the voltage level at node 51 will be about 2.73 volts. Thus, dot 1 will be illuminated in response to video signal 21.
The opposite situa-tion would be if video signal 21 is low for dot 1 and video signal 24 is high for dot 1. Transistor 26 would be turned on and transistor 23 would be reversed biased or off. The voltage at node 51 would be about 2.97 volts and dot 1 would be illuminated in response to video signal 24. It is noted that the voltage produced by video signal 24 at node 51 is higher than the voltage pKoduced by video signal 21. This results :in dot 1 being illuminated at a higher intensity in response to video signal 24 which enables an alphanumeric character to ,, be seen even if all dots around the alphanumeric character have also been illuminated for the graphical display produced by signal 21.
I~ both video signal 21 and video signal 24 are high for dot 1, then the voltage at ~he base of transistor 23 will be about 3.33 vol-ts and the voLtage at the base of transistor 26 w:ill be about 3.57 vol-ts.
This results in transistor 26 being -turned on but transistor 23 will again be reversed biased or -turned off even though there is a voltage present at the base of transistor 23 because of the higher voltage present at the base of transistor 26. Thus, the voltage at node 51 will be controlled by video signal 24 even if video signal 21 is also high.
This results in a priority being assigned to video signal 24.
If both video signals 21 and 24 are low, then the voltage at node 51 will be essentially ~ero and dot 1 will not be illuminated.
In summary with respect to FIG~RES 5 and 6, for a black and white display, the overlay video signal is given priority on a dot-by-do-t basis. Also, the intensity of the characters produced by the overlay video signal are enhanced with respect to the display produced by the normal video signal which aids in viewing the alphanumeric characters even if the alphanumeric characters are directly superimposed over a por-tion of the graphical display.
A color system is illustrated in ~IGU~E 7. Computer 11 again addresses the display generators 12 and 16 in parallel. ~owever, video signals 21 and 24 are provided to the ~ input of flip-flops 61 and 62, respectively, instead of being provided directly -to the combining circuitry as illustrated in FIGURE 5. The use o the flip-flops 61 and 62 as well as the AMD gate 63 will be described more fully hereinafter.
~ssentially~ video signal 21 is applied as video signal 66 to the color generator 68. In like manner, video signal 24 is applied as video signal 69 to the color generator 71.
The color generators 68 and 71 are conventional and are essentially programmable read-only memories with associated registers.
Additional information is supplied ~rom the refresh memory portion of the display generators ~or color selection In response to signal 66, the color generator 68 provides three output video signals 72-74 tred, blue 3S and green, respectively). In like manner, in response to video signal 69, the color generator 71 provides three output video signals 77-79 (red, blue and green, respectively). The two red signals are provided to ~2~
the combining circuit 81 which is the same as the combining circuit illustrated in FIGVRES 5 and 6. In like manner, the blue signals are provided to the combining circuit 83 and the green signals are provided to the combining circuit 85.
A single video signal is provided from each combining circuit to the red, blue or green gun of the color C~T 14.
As was the case for the combining circuits illustrated in FIGURES 5 and 6, video signals 77, 78 and 7g are given priority.
However, for a color system, bo-th the red and green signals from color generator 68 may be high for a first dot to produce a yellow color on the CRT for -the first dot. For the same dot, only the red signal from the color generator 71 may be high. To give priority to only the red signal 77 wi-th respect to the red signal 72 would result in the wrong color on the CRT since green would be added in response to signal 74 because signal 79 is low. This is avoided by disabling all color signals from the color generator 78 when video signal 24 goes high indicating that alphanumeric data is available for the first dot~ This is accomplished using flip-flops 61 and 62 and the AND gate 63.
The dot clock 91, which is the master timing signal for the generation of the video signals, is provided to the clock input of both flip-flops 61 and 62. Thus, flip-flops 61 and 62 may change state each time the digital value of the video signals 21 or 24 may change. If video signal 21 is high for a firs-t dot and video signal 24 is low, then the Q not output from flip-flop 62, which is provided as a first input to the AND gate 63, will be high. In like manner, -the Q output from flip-flop 61 will be high and signal 66 will be high. Thus, signal 66 will have the same magnitude as signal 21.
If the video signal 21 is low for a first dot and the video signal 24 is high, then signal 66 will be low and signal 69 will be high.
3~ The disabling effect occurs when both signals 21 and 2~ are high for a first dot. The Q output from flip-flop 61 will be high but the Q not output from flip-flop 62 will be low. Thus, signal 66 will be low which effectively disables all normal video signals 72, 73 and 74 for the first dot. Signal 69 will be high and the first dot will be illuminated in response to signal 69. Thus, an override is provided for the overlay video signal and also the correct color will be vis:ible on the CRT scre~n for the first ~lot.
8~
The invention has been described in terms of a preferred embodimen~ in which a detailed schematic has been set forth for the combining circ~litry. Circuit values have been given and the transistors 23 and 27 cou:Ld be 2N3904s. The flip-flops could be 74LS74 and the AND
gate could be 74LS08.
While the invention has been described in terms of the presently preferred embodiment, reasonable variations and modifications are possible by those s~illed in the art and such variations and modifications are within -the scope of the described invention and the appended claims.
This invention rela-tes to displaying information on a video display. In oae aspect, this invention relates to method and apparatus for displaying at least two different displays of informa-tion on a video display.
Brief Description of the Drawings All of the drawings are briefly described as follows:
FIGURE 1 is a diagrammatic illustration of a conventional system for displaying data provided by a computer on a CRT using one display generator;
FIGURE 2 is a diagrammatic illustration of the use of two display generators to provide information from a computer to a video display;
FIGURE 3 is an illustration of a problem which may occur using the display system of FIGURE 2;
FIGURE 4 is an illustration of a desired display of both graphical and alphanumeric data;
FIGURE 5 is an illustration of the circuitry used in accordance with the present invention to combine a normal ~ideo signal and an ~ overlay video signal for a black and white display;
;~ 20 FI&UR~ 6 is an illustration of part of the circui~ of FIGURE 5 ; with speciic xesistance and voltage values; and FI&URE 7 is an illustration of circuitry which may be utilized in accordance with the present i~ention to combine the normal video signal and overlay video signal for a color system.
A con~entional system utilizing a video display (typically a CR~) is -i~lustrated in FIGURE 1. A computer 11 is mterfaced to the t ~"s ?~
~ , ., display generator 12. In general, the display generator 12 takes data supplied from Lhe computer 11 and converts the data into an EIA Standard RS-170 format which can be utilized to drive the CRT 14. EIA S~andard RS~170 defilles a method for combining the sync~ blanking and video signals required by a CRT onto a s:ingle coaxia:L cable. The thus combined signal is generally referred to as a composite video waveform. For a color system, only the green channel contalns the sync signal.
Additional coaxial cables are required for the red and blue video signals.
The display genera-tor 12 typically contains at least interfacing circuitry, a refresh memory, a character generator and video processing circuitry. In many applications, character addressing is used for the display generator 12. In character addressing, each location (address) in the refresh memory corresponds -to one character on a CRT
screen rather than one dot. A character will generally be made up of an array of dots on a CRT screen. A typical arrangement is a matrix of 7 dots x 10 dots to form a character. This yields 70 dots per character ; which may be "on" or "off" in any combination to form any particular character.
The refresh memory location corresponding to any particular CRT
screen position may contain as little as a 6 to 3 bit code (typically ASCII) specifying which character (of a set) is desired at that position.
Thus, the 70 dots in the character on the screen are compressed into 6 to 8 bits in the refresh memory. Character addressing thus res-tricts the amount of information which can be displayed on the CRT and also the location at which the data can be displayed, but character addressing does have several advantages such as the reduced size of the refresh memory required as opposed to a system in which dot addressing is utilized.
In many applications it is frequen-tly desired to display two different sets of information such as a graphical representation and alphanumeric information. An example of such an application is process control where it may be desired to display a graphical representation of a yrocess and periodically add alphanumeric information for process conditions.
For the system illustrated in FIGURE 1, alphanumeric data must be placed on the CRT in such a way as not to overwrite any graphical ~ 31402CA
display characters or the graphical display chaYacters ~ill be destroyed.
This occurs because, if an alphanumeric character is written over a graphical character in a character addressed video display system, the entire graphical character is destroyed even though only a few of the 70 dots in the character may be used for the alphanumeric character.
It would be desirable to overlay or superimpose the alphanumeric character over the graphical character in such a manner that the alphanumeric character may be read but the graphical character, and thus the continuity of -the graphical display, is not des-troyed. One method which has been sugges-ted for accomplishing this is as illustrated in U.S. 4,200,869. The solution of U.S. 4,200,g69 is very broadly illustrated in a block diagram format in FIGURE 2.
Referring now to FIGURE 2, computer 11 is again interfaced to the display generator 12. However, a second display generator 16, which is addressed in parallel with the display generator 12, is added in the teachings of U.S. 4,200,869. Parallel addressing refers to addressing such that the video signals of display generators 12 an~ 16 would be applied to the same dot on the CRT 14. The output from both the display genera-tor 12 and display generator 16 are provided to the OR gate 18 with the output of the OR gate 18 being utilized to drive the CRT 14.
The display generator 12 may be utilized -to generate the video signal required for the graphical display. In like manner, -the display generator 16 may be utilized to generate the video signal required for the alphanumeric informa-tion. These two signals are combined and provided to the CRT 14. The result is an overlay of the graphical display and the alphanumeric information.
One of the problems with the system illustrated in FIGURE 2 is illustrated in FIGURE 3. Referring now to FIGURE 3, assume that the graphical character is a solid block. Also, assume that the alphanumeric word is the word BAD. Because no priority can be assigned in the system of FIGURE 2, the letter A would completely disappear. Thus, the use of an OR gate to combine the two video signals is feasible only where neither video signal utilizes a major number of the dots in a character on a ~RT screen.
FIGURE 4 illustra-tes a more desired overlay of the graphical and alphanumeric data. Referring now to EIGURE 4, it can be seen that, in the more desired sltuation, the overlay video ~alphanumeric) has been ~.
made brighter than the graphical display. This results in a true overlay in that the alphanumeric word can be read an~ the graphical display remains undisturbed except to the extent of the dots re~uired to form the letter A. Other dots remaining in the character block utilized to form the letter A can continue to be used for the graphical display.
It is thus an object oE this invention to provide method and apparatus for displaying alphanumeric and graphical data on a character oriented video display in such a manner that a priority is assigned to the alphanumeric data such that the alphanumeric data can be seen as illustrated in FIGURE 4.
As used herein, the term "overlay video signal" refers to the video signal which is given priority and the term 1'normal video signal"
refers to -the video signal which i5 not given priority. In most cases -the normal video signal will produce a graphical display and the overlay video signal will produce an alphanumeric display. Thus the present invention is sometimes described herein in ~erms of displaying both graphical and alphanumeric informa-tion. However, the invention is not limited to the display of such in~ormation and could be utilized to display other types of inEormation or could be u~ilized to display two sets of the same type of information (such as graphical) where it is desired to give priority to one set.
In accordance with the present invention, two transistors, configured as emitter followers and sharing a common emitter resistor, are u-tilized to combine the normal video signal and -the overlay video signal in such a manner that the reslllts illustrated in FIGURE 4 are achieved. Essentially, the normal video signal is supplied to the base of a first e~itter follower t~ansistor while the overlay video signal is supplied to the base of a second emitter follower transistor. The two transistors are biased such that the first transistor is at a slightly lower voltage than the second (overlay) transistor and is reversed biased (off) any time data is availab:Le from the overlay video signal. Thus, the selection of the video signals is accomplished based on the video signals and very fast and clean s~itching is provided. Also, the visibllity of the overlay video signal is improved by using a higher voltage for the overlay video signal than for the normal video signal.
., , ~2~
Other objec-ts and advantages of the inven-tion will be apparent from the foregoing brief description of the invention and the claims as well as from the description of the drawings.
The invention is described in terms of the use of two display generators for the sake of convenience. However, the invention is applicable to combining the video signals Eroln more than two display genèrators iE desired.
The invention is also described in terms of specific electronic components. However, the invention is a-pplicable to different electronic circuit configurations which carry ou-t the purpose of the present invention and is also applicable to different circuit components which are supplied by a plura]ity of vendors.
Referring now to ~IGURE 5, there is again illustrated the host computer 11, display generators 12 and 16 and the CRT 14. Any suitable computer and CRT can be utilized. The computer and CRT utilized in the particular system to which the present invention was applied were the Motorola MC6800 MPV and Aydin 8830 Color C~T.
The display generators 12 and 16 may be any desired display generators. Display generators are well known in the art and, as has previously been stated, will g~nerally contain an interface to the computer 11, a refresh memory, a charac-ter generator which may be either a random access memory or an erasable programmable read-only memory and other video processing circuitry. Since the present invention is concerned with combining of video signals and no-t with generation of the video signals, the display generators 12 and 16 will not be more fully described hereinafter.
Display generator 12 provides a normal video signal 21 to the base of the transistor 23 which is an NPN transistor configured as an emit-ter follower. The normal video signal 21 may be a composite video waveform containing sync, blanking and video signals, as previously described, or may be a serial video waveform containing only video signals. If the video waveform 21 is a serial video waveform, then the blanking and sync signals would typically be added before a signal is provided to the CRT 14 but since the addition of such signals plays no part in the description of the present invention, such addition is not illustrated~
The overlay video signal 2~ is provided from the disp:Lay generator 16 to the base of the transistor 26 which, 1ike transistor 23 is an NPN transistor configured as an emitter follower. The video waveform 24 will not contain sync signals since these signals are S provided by the "normal" channel and will thus be serial video only.
The video signal 21 will be a stream of serial data. The normal v:ideo signal 21 is actually provided to the base of transistor 23 by "modulating" the voltage at node 27 which is established by the bias resistors 28 and 29 in conjunction with the supply voltage 32. Since the driving devices in display generators are open collector devices, the voltage at node 22 will ei-ther be essen-tially zero when the normal video signal 21 is not in a state which will cause a do-t on the CRT to be illuminated (referred to hereinafter as "low"~ or will be at a voltage level determined by the magnitude of the supply voltage and the values of the bias resistors 28 and 29 if the video signal is in a state which will cause a dot on the CRT to be illuminated (referred to hereinafter as "high"). Thus, either an ~ssentially zero voltage is applied to the base of the transistor 23 or a vo]tage level greater -than zero but less than 5 volts is applied.
In li~e manner~ the overlay video signal 24 modulates the voltage at node 34. Again, the voltage at node 34 will either be essentially zero when the data in the overlay video signal is low or will be at some positive voltage level determined by the magnitude of the supply voltage 32 and the value of the bias resistors 37 and 38 if the da-ta in the overlay video signal is high. Thus, as with transistor 23, the voltage applied to the base of -the transistor 26 will either be essentially æero or will be a positive voltage.
Transistors 23 and 26 share a common emi-tter resistor 41. The emitters of transistors 23 and 26 are also -tied to the CRT 14 -through the coupling resistor 44.
For almost all CRT's, the screen is filled beginning at the upper left hand corner and continuing horiæontally across the screen to the upper right hand corner on a dot-by-dot basis. The electron beam then goes to the left-hand side oE the screen on the second row during a blanking pulse and the second row is filled. This process continues until the electron beam reaches the lower right-hand corner of the screen . *
at which time the vertical sync pulse occurs causing the electron beam to return to the upper left-hand corner of the screen.
When the screen is being filled, the normal video signal 21 will be at a high value if a first dot is to be illuminated or will be at a low value if -the first dot is to be left off. In like manner, at the same time, overlay video signal 24 will be at a hlgh level if the first dot is to be illuminated and will be at a low level if the first dot is to be left off. Priority is assigned to overlay video signal 24 by the circuitry illustrated in FIG~RE S as will be more fully described hereinafter. Thus, if the normal video signal 21 would require the first dot to be illuminated and overlay video signal 24 would require the first dot to be illuminated, then the first dot will be illuminated in response to overlay video signal 24. The manner in which this is accomp:Lished is illustrated in FIGURE 6 where specific voltage and resistance values have been assigned for the sake of illus-tration.
Referring now to FIGURE 6, for the resistor and voltage values illustrated in FIG~RE 6 and the particular system to which the present invention was applied, node 27 will have a voltage level of about 3.33 vol-ts if the normal video signal 21 is high and will have a voltage level of essentially zero if the normal video signal 21 is low. Node 34 will have a voltage level of about 3.57 volts if the overlay video signal 24 is high and will have a voltage level of essentially zero if the overlay video signal 24 is low.
If, for a particular point (dot 1) on -the CRT screen, video signal 21 is high and video signal 24 is low, then transistor 23 will be turned on and transistor 26 will be reversed biased or off. Due to the typical 0.6 volt base emit-ter drop, the voltage level at node 51 will be about 2.73 volts. Thus, dot 1 will be illuminated in response to video signal 21.
The opposite situa-tion would be if video signal 21 is low for dot 1 and video signal 24 is high for dot 1. Transistor 26 would be turned on and transistor 23 would be reversed biased or off. The voltage at node 51 would be about 2.97 volts and dot 1 would be illuminated in response to video signal 24. It is noted that the voltage produced by video signal 24 at node 51 is higher than the voltage pKoduced by video signal 21. This results :in dot 1 being illuminated at a higher intensity in response to video signal 24 which enables an alphanumeric character to ,, be seen even if all dots around the alphanumeric character have also been illuminated for the graphical display produced by signal 21.
I~ both video signal 21 and video signal 24 are high for dot 1, then the voltage at ~he base of transistor 23 will be about 3.33 vol-ts and the voLtage at the base of transistor 26 w:ill be about 3.57 vol-ts.
This results in transistor 26 being -turned on but transistor 23 will again be reversed biased or -turned off even though there is a voltage present at the base of transistor 23 because of the higher voltage present at the base of transistor 26. Thus, the voltage at node 51 will be controlled by video signal 24 even if video signal 21 is also high.
This results in a priority being assigned to video signal 24.
If both video signals 21 and 24 are low, then the voltage at node 51 will be essentially ~ero and dot 1 will not be illuminated.
In summary with respect to FIG~RES 5 and 6, for a black and white display, the overlay video signal is given priority on a dot-by-do-t basis. Also, the intensity of the characters produced by the overlay video signal are enhanced with respect to the display produced by the normal video signal which aids in viewing the alphanumeric characters even if the alphanumeric characters are directly superimposed over a por-tion of the graphical display.
A color system is illustrated in ~IGU~E 7. Computer 11 again addresses the display generators 12 and 16 in parallel. ~owever, video signals 21 and 24 are provided to the ~ input of flip-flops 61 and 62, respectively, instead of being provided directly -to the combining circuitry as illustrated in FIGURE 5. The use o the flip-flops 61 and 62 as well as the AMD gate 63 will be described more fully hereinafter.
~ssentially~ video signal 21 is applied as video signal 66 to the color generator 68. In like manner, video signal 24 is applied as video signal 69 to the color generator 71.
The color generators 68 and 71 are conventional and are essentially programmable read-only memories with associated registers.
Additional information is supplied ~rom the refresh memory portion of the display generators ~or color selection In response to signal 66, the color generator 68 provides three output video signals 72-74 tred, blue 3S and green, respectively). In like manner, in response to video signal 69, the color generator 71 provides three output video signals 77-79 (red, blue and green, respectively). The two red signals are provided to ~2~
the combining circuit 81 which is the same as the combining circuit illustrated in FIGVRES 5 and 6. In like manner, the blue signals are provided to the combining circuit 83 and the green signals are provided to the combining circuit 85.
A single video signal is provided from each combining circuit to the red, blue or green gun of the color C~T 14.
As was the case for the combining circuits illustrated in FIGURES 5 and 6, video signals 77, 78 and 7g are given priority.
However, for a color system, bo-th the red and green signals from color generator 68 may be high for a first dot to produce a yellow color on the CRT for -the first dot. For the same dot, only the red signal from the color generator 71 may be high. To give priority to only the red signal 77 wi-th respect to the red signal 72 would result in the wrong color on the CRT since green would be added in response to signal 74 because signal 79 is low. This is avoided by disabling all color signals from the color generator 78 when video signal 24 goes high indicating that alphanumeric data is available for the first dot~ This is accomplished using flip-flops 61 and 62 and the AND gate 63.
The dot clock 91, which is the master timing signal for the generation of the video signals, is provided to the clock input of both flip-flops 61 and 62. Thus, flip-flops 61 and 62 may change state each time the digital value of the video signals 21 or 24 may change. If video signal 21 is high for a firs-t dot and video signal 24 is low, then the Q not output from flip-flop 62, which is provided as a first input to the AND gate 63, will be high. In like manner, -the Q output from flip-flop 61 will be high and signal 66 will be high. Thus, signal 66 will have the same magnitude as signal 21.
If the video signal 21 is low for a first dot and the video signal 24 is high, then signal 66 will be low and signal 69 will be high.
3~ The disabling effect occurs when both signals 21 and 2~ are high for a first dot. The Q output from flip-flop 61 will be high but the Q not output from flip-flop 62 will be low. Thus, signal 66 will be low which effectively disables all normal video signals 72, 73 and 74 for the first dot. Signal 69 will be high and the first dot will be illuminated in response to signal 69. Thus, an override is provided for the overlay video signal and also the correct color will be vis:ible on the CRT scre~n for the first ~lot.
8~
The invention has been described in terms of a preferred embodimen~ in which a detailed schematic has been set forth for the combining circ~litry. Circuit values have been given and the transistors 23 and 27 cou:Ld be 2N3904s. The flip-flops could be 74LS74 and the AND
gate could be 74LS08.
While the invention has been described in terms of the presently preferred embodiment, reasonable variations and modifications are possible by those s~illed in the art and such variations and modifications are within -the scope of the described invention and the appended claims.
Claims (5)
1. Apparatus comprising:
a video display;
a first transistor;
a second transistor;
means for electrically connecting the emitter of said first transistor and said second transistor to ground through a first resistor;
means for electrically connecting the collector of said first transistor to the collector of said second transistor;
means for generating a first video signal and for supplying said first video signal to the base of said first transistor, wherein the voltage at the base of said first transistor is at a first voltage level when it is desired to illuminate a first dot on the screen of said video display in response to said first video signal and is at a second voltage level, which is lower than said first voltage level, when it is not desired to illuminate said first dot in response to said first video signal;
means for generating a second video signal and for supplying said second video signal to the base of said second transistor, wherein the voltage at the base of said second transistor is at a third voltage level when it is desired to illuminate said first dot in response to said second video signal and is at a fourth voltage level, which is lower than said third voltage level, when it is not desired to illuminate said first dot in response to said second video signal and wherein said third voltage level is higher than said first voltage level; and means for supplying the voltage at the emitter of said first transistor and said second transistor as the video signal to said video display.
a video display;
a first transistor;
a second transistor;
means for electrically connecting the emitter of said first transistor and said second transistor to ground through a first resistor;
means for electrically connecting the collector of said first transistor to the collector of said second transistor;
means for generating a first video signal and for supplying said first video signal to the base of said first transistor, wherein the voltage at the base of said first transistor is at a first voltage level when it is desired to illuminate a first dot on the screen of said video display in response to said first video signal and is at a second voltage level, which is lower than said first voltage level, when it is not desired to illuminate said first dot in response to said first video signal;
means for generating a second video signal and for supplying said second video signal to the base of said second transistor, wherein the voltage at the base of said second transistor is at a third voltage level when it is desired to illuminate said first dot in response to said second video signal and is at a fourth voltage level, which is lower than said third voltage level, when it is not desired to illuminate said first dot in response to said second video signal and wherein said third voltage level is higher than said first voltage level; and means for supplying the voltage at the emitter of said first transistor and said second transistor as the video signal to said video display.
2. Apparatus in accordance with claim 1 wherein said means for generating said first video signal and for supplying said first video signal to the base of said first transistor and said means for generating said second video signal and for supplying said second video signal to the base of said second transistor comprises:
means for electrically connecting the base of said first transistor to a supply voltage through a second resistor;
means for electrically connecting the base of said first transistor to ground through a third resistor, wherein a first node is formed by the electrical connection between said second resistor and said third resistor;
a first display generator having an open collector driver;
means for electrically connecting the open collector driver of said first display generator to said first node to thereby supply said first video signal to the base of said first transistor;
means for electrically connecting the base of said second transistor to said supply voltage through a fourth resistor;
means for electrically connecting the base of said second transistor to ground through a fifth resistor, wherein a second node is formed by the electrical connection between said fourth resistor and said fifth resistor and wherein the resistance value of said fourth resistor is lower than the resistance value of said second resistor;
a second display generator having an open collector driver;
means for electrically connecting the open collector driver of said second display generator to said second node to thereby supply said second video signal to the base of said second transistor; and means for electrically connecting the collector of said first transistor and the collector of said second transistor to said positive supply voltage.
means for electrically connecting the base of said first transistor to a supply voltage through a second resistor;
means for electrically connecting the base of said first transistor to ground through a third resistor, wherein a first node is formed by the electrical connection between said second resistor and said third resistor;
a first display generator having an open collector driver;
means for electrically connecting the open collector driver of said first display generator to said first node to thereby supply said first video signal to the base of said first transistor;
means for electrically connecting the base of said second transistor to said supply voltage through a fourth resistor;
means for electrically connecting the base of said second transistor to ground through a fifth resistor, wherein a second node is formed by the electrical connection between said fourth resistor and said fifth resistor and wherein the resistance value of said fourth resistor is lower than the resistance value of said second resistor;
a second display generator having an open collector driver;
means for electrically connecting the open collector driver of said second display generator to said second node to thereby supply said second video signal to the base of said second transistor; and means for electrically connecting the collector of said first transistor and the collector of said second transistor to said positive supply voltage.
3. Apparatus comprising:
a first display generator;
a second display generator;
a first flip-flop having a data input, a clock input, a Q
output and a Q not output;
a second flip-flop having a data input, a clock input a Q
output and a Q not output;
means for supplying a first video signal from said first display generator to the data input of said first flip-flop;
means for supplying a second video signal from said second display generator to the data input of said second flip-flop;
means for providing the dot clock utilized to generate said first video signal and said second video signal to the clock input of said first flip-flop and said second flip-flop;
an AND gate;
means for electrically connecting the Q output of said first flip-flop to a first input of said AND gate;
means for electrically connecting the Q not output of said second flip-flop to a second input of said AND gate;
a first color generator;
a second color generator;
means for providing the output from said AND gate as a first input video signal to said first color generator;
means for providing the Q output from said second flip-flop as a second input video signal to said second color generator, wherein said first input video signal has a voltage level equal to said first video signal if said second video signal has a voltage level of essentially zero and has a voltage level of essentially zero if said second video signal has a positive voltage level, wherein said first color generator provides a first red video signal, a first blue video signal and a first green video signal in response to said first input video signal and wherein said second color generator provides a second red video signal, a second blue video signal and a second green video signal in response to said second input video signal;
a video display having a red gun, a blue gun and a green gun;
a first transistor;
a second transistor;
means for electrically connecting the emitter of said first transistor and said second transistor to ground through a first resistor;
means for electrically connecting the collector of said first transistor to the collector of said second transistor;
means for supplying said first red video signal to the base of said first transistor, wherein the voltage at the base of said first transistor is at a first voltage level when it is desired to illuminate a first dot on the screen of said video display in response to said first red video signal and is at a second voltage level, which is lower than said first voltage level, when it is not desired to illuminate said first dot in response to said first red video signal;
means for supplying said second red video signal to the base of said second transistor, wherein the voltage at the base of said second transistor is at a third voltage level when it is desired to illuminate said first dot in response to said second red video signal and is at a fourth voltage level, which is lower than said third voltage level, when it is not desired to illuminate said first dot in response to said second red video signal and wherein said third voltage level is higher than said first voltage level;
means for supplying the voltage at the emitter of said first transistor and said second transistor as the video signal to the red gun of said video display;
a third transistor;
a fourth transistor;
means for electrically connecting the emitter of said third transistor and said fourth transistor to ground through a second resistor;
means for electrically connecting the collector of said third transistor to the collector of said fourth transistor;
means for supplying said first blue video signal to the base of said third transistor, wherein the voltage at the base of said third transistor is at said first voltage level when it is desired to illuminate said first dot in response to said first blue video signal and is at said second voltage level when it is not desired to illuminate said first dot in response to said first blue video signal;
means for supplying said second blue video signal to the base of said fourth transistor, wherein the voltage at the base of said fourth transistor is at said third voltage level when it is desired to illuminate said first dot in response to said second blue video signal and is at said fourth voltage level when it is not desired to illuminate said first dot in response to said second blue video signal;
means for supplying the voltage at the emitter of said third transistor and said fourth transistor as the video signal to the blue gun of said video display;
a fifth transistor;
a sixth transistor;
means for electrically connecting the emitter of said fifth transistor and said sixth transistor to ground through a third resistor;
means for electrically connecting the collector of said fifth transistor to the collector of said sixth transistor;
means for supplying said first green video signal to the base of said fifth transistor, wherein the voltage at the base of said fifth transistor is at said first voltage level when it is desired to illuminate said first dot in response to said first green video signal and is at said second voltage level when it is not desired to illuminate said first dot in response to said first green video signal;
means for supplying said second green video signal to the base of said sixth transistor, wherein the voltage at the base of said sixth transistor is at said third voltage level when it is desired to illuminate said first dot in response to said second green video signal and is at said fourth voltage level when it is not desired to illuminate said first dot in response to said second green video signal; and means for supplying the voltage at the emitter of said fifth transistor and said sixth transistor as the video signal to the green gun of said video display.
a first display generator;
a second display generator;
a first flip-flop having a data input, a clock input, a Q
output and a Q not output;
a second flip-flop having a data input, a clock input a Q
output and a Q not output;
means for supplying a first video signal from said first display generator to the data input of said first flip-flop;
means for supplying a second video signal from said second display generator to the data input of said second flip-flop;
means for providing the dot clock utilized to generate said first video signal and said second video signal to the clock input of said first flip-flop and said second flip-flop;
an AND gate;
means for electrically connecting the Q output of said first flip-flop to a first input of said AND gate;
means for electrically connecting the Q not output of said second flip-flop to a second input of said AND gate;
a first color generator;
a second color generator;
means for providing the output from said AND gate as a first input video signal to said first color generator;
means for providing the Q output from said second flip-flop as a second input video signal to said second color generator, wherein said first input video signal has a voltage level equal to said first video signal if said second video signal has a voltage level of essentially zero and has a voltage level of essentially zero if said second video signal has a positive voltage level, wherein said first color generator provides a first red video signal, a first blue video signal and a first green video signal in response to said first input video signal and wherein said second color generator provides a second red video signal, a second blue video signal and a second green video signal in response to said second input video signal;
a video display having a red gun, a blue gun and a green gun;
a first transistor;
a second transistor;
means for electrically connecting the emitter of said first transistor and said second transistor to ground through a first resistor;
means for electrically connecting the collector of said first transistor to the collector of said second transistor;
means for supplying said first red video signal to the base of said first transistor, wherein the voltage at the base of said first transistor is at a first voltage level when it is desired to illuminate a first dot on the screen of said video display in response to said first red video signal and is at a second voltage level, which is lower than said first voltage level, when it is not desired to illuminate said first dot in response to said first red video signal;
means for supplying said second red video signal to the base of said second transistor, wherein the voltage at the base of said second transistor is at a third voltage level when it is desired to illuminate said first dot in response to said second red video signal and is at a fourth voltage level, which is lower than said third voltage level, when it is not desired to illuminate said first dot in response to said second red video signal and wherein said third voltage level is higher than said first voltage level;
means for supplying the voltage at the emitter of said first transistor and said second transistor as the video signal to the red gun of said video display;
a third transistor;
a fourth transistor;
means for electrically connecting the emitter of said third transistor and said fourth transistor to ground through a second resistor;
means for electrically connecting the collector of said third transistor to the collector of said fourth transistor;
means for supplying said first blue video signal to the base of said third transistor, wherein the voltage at the base of said third transistor is at said first voltage level when it is desired to illuminate said first dot in response to said first blue video signal and is at said second voltage level when it is not desired to illuminate said first dot in response to said first blue video signal;
means for supplying said second blue video signal to the base of said fourth transistor, wherein the voltage at the base of said fourth transistor is at said third voltage level when it is desired to illuminate said first dot in response to said second blue video signal and is at said fourth voltage level when it is not desired to illuminate said first dot in response to said second blue video signal;
means for supplying the voltage at the emitter of said third transistor and said fourth transistor as the video signal to the blue gun of said video display;
a fifth transistor;
a sixth transistor;
means for electrically connecting the emitter of said fifth transistor and said sixth transistor to ground through a third resistor;
means for electrically connecting the collector of said fifth transistor to the collector of said sixth transistor;
means for supplying said first green video signal to the base of said fifth transistor, wherein the voltage at the base of said fifth transistor is at said first voltage level when it is desired to illuminate said first dot in response to said first green video signal and is at said second voltage level when it is not desired to illuminate said first dot in response to said first green video signal;
means for supplying said second green video signal to the base of said sixth transistor, wherein the voltage at the base of said sixth transistor is at said third voltage level when it is desired to illuminate said first dot in response to said second green video signal and is at said fourth voltage level when it is not desired to illuminate said first dot in response to said second green video signal; and means for supplying the voltage at the emitter of said fifth transistor and said sixth transistor as the video signal to the green gun of said video display.
4. A method for displaying information from first and second video signals on a video display comprising the steps of:
modulating the voltage at the base of a first transistor in response to said first video signal, wherein the voltage at the base of said first transistor is at a first voltage level when it is desired to illuminate a first dot on the screen of said video display in response to said first video signal and is at a second voltage level, which is lower than said first voltage level, when it is not desired to illuminate said first dot in response to said first video signal;
modulating the voltage at the base of a second transistor in response to said second video signal, wherein the voltage at the base of said second transistor is at a third voltage level when it is desired to illuminate said first dot in response to said second video signal and is at a fourth voltage level, which is lower than said third voltage level, when it is not desired to illuminate said first dot in response to said second video signal, wherein said third voltage level is higher than said first voltage level, wherein the emitters of said first and second transistors are electrically connected to ground through a first resistor and wherein the collectors of said first and second transistors are electrically connected; and supplying the voltage at the emitter of said first transistor and said second transistor as the video signal to said video display.
modulating the voltage at the base of a first transistor in response to said first video signal, wherein the voltage at the base of said first transistor is at a first voltage level when it is desired to illuminate a first dot on the screen of said video display in response to said first video signal and is at a second voltage level, which is lower than said first voltage level, when it is not desired to illuminate said first dot in response to said first video signal;
modulating the voltage at the base of a second transistor in response to said second video signal, wherein the voltage at the base of said second transistor is at a third voltage level when it is desired to illuminate said first dot in response to said second video signal and is at a fourth voltage level, which is lower than said third voltage level, when it is not desired to illuminate said first dot in response to said second video signal, wherein said third voltage level is higher than said first voltage level, wherein the emitters of said first and second transistors are electrically connected to ground through a first resistor and wherein the collectors of said first and second transistors are electrically connected; and supplying the voltage at the emitter of said first transistor and said second transistor as the video signal to said video display.
5. A method for displaying information from first and second video signals on a video display, said method comprising the steps of:
supplying said first video signal to the data input of a first flip-flop having a data input, a clock input, a Q output and a Q not output;
supplying said second video signal to the data input of a second flip-flop having a data input, a clock input, a Q output and a Q
not output;
clocking said first flip-flop and said second flip-flop in response to the dot clock utilized to generate said first video signal and said second video signal;
supplying the Q output of said first flip-flop to a first input of an AND gate;
supplying the Q not output of said second flip-flop to a second input of said AND gate;
providing the output signal from said AND gate as a first input video signal to a first color generator;
providing the Q output from said second flip-flop as a second input video signal to a second color generator, wherein said first input video signal has a voltage level equal to said first video signal if said second video signal has a voltage level of essentially zero and has a voltage level of essentially zero if said second video signal has a positive voltage level, wherein said first color generator provides a first red video signal, a first blue video signal and a first green video signal in response to said first input video signal and wherein said second color generator provides a second red video signal, a second blue video signal and a second green video signal in response to said second input video signal;
modulating the voltage at the base of a first transistor in response to said first red video signal, wherein the voltage at the base of said first transistor is at a first voltage level when it is desired to illuminate a first dot on the screen of said video display in response to said first red video signal and is at a second voltage level, which is lower than said first voltage level, when it is not desired to illuminate said first dot in response to said first red video signal;
modulating the voltage at the base of a second transistor in response to said second red video signal, wherein the voltage at the base of said second transistor is at a third voltage level when it is desired to illuminate said first dot in response to said second red video signal and is at a fourth voltage level, which is lower than said third voltage level, when it is not desired to illuminate said first dot in response to said second red video signal, wherein said third voltage level is higher than said first voltage level, wherein the emitters of said first and second transistors are electrically connected to ground through a first resistor and wherein the collectors of said first and second transistors are electrically connected;
supplying the voltage at the emitter of said first transistor and said second transistor as the video signal to the red gun of said video display;
modulating the voltage at the base of a third transistor in response to said first blue video signal, wherein the voltage at the base of said third transistor is at said first voltage level when it is desired to illuminate said first dot in response to said first blue video signal and is at said second voltage level when it is not desired to illuminate said first dot in response to said first blue video signal;
modulating the voltage at the base of a fourth transistor in response to said second blue video signal, wherein the voltage at the base of said fourth transistor is at said third voltage level when it is desired to illuminate said first dot in response to said second blue video signal and is at said fourth voltage level when it is not desired to illuminate said first dot in response to said second blue video signal, wherein the emitters of said third and fourth transistors are electrically connected to ground through a second resistor and wherein the collectors of said third and fourth transistors are electrically connected;
supplying the voltage at the emitter of said third transistor and said fourth transistor as the video signal to the blue gun of said video display;
modulating the voltage at the base of a fifth transistor in response to said first green video signal, wherein the voltage at the base of said fifth transistor is at said first voltage level when it is desired to illuminate said first dot in response to said first green video signal and is at said second voltage level when it is not desired to illuminate said first dot in response to said first green video signal;
modulating the voltage at the base of a sixth transistor in response to said second green video signal, wherein the voltage at the base of said sixth transistor is at said third voltage level when it is desired to illuminate said first dot in response to said second green video signal and is at said fourth voltage level when it is not desired to illuminate said first dot in response to said second green video signal, wherein the emitters of said fifth and sixth transistors are connected to ground through a third resistor and wherein the collectors of said fifth and sixth transistors are electrically connected; and supplying the voltage at the emitter of said fifth transistor and said sixth transistor as the video signal to the green gun of said video display.
supplying said first video signal to the data input of a first flip-flop having a data input, a clock input, a Q output and a Q not output;
supplying said second video signal to the data input of a second flip-flop having a data input, a clock input, a Q output and a Q
not output;
clocking said first flip-flop and said second flip-flop in response to the dot clock utilized to generate said first video signal and said second video signal;
supplying the Q output of said first flip-flop to a first input of an AND gate;
supplying the Q not output of said second flip-flop to a second input of said AND gate;
providing the output signal from said AND gate as a first input video signal to a first color generator;
providing the Q output from said second flip-flop as a second input video signal to a second color generator, wherein said first input video signal has a voltage level equal to said first video signal if said second video signal has a voltage level of essentially zero and has a voltage level of essentially zero if said second video signal has a positive voltage level, wherein said first color generator provides a first red video signal, a first blue video signal and a first green video signal in response to said first input video signal and wherein said second color generator provides a second red video signal, a second blue video signal and a second green video signal in response to said second input video signal;
modulating the voltage at the base of a first transistor in response to said first red video signal, wherein the voltage at the base of said first transistor is at a first voltage level when it is desired to illuminate a first dot on the screen of said video display in response to said first red video signal and is at a second voltage level, which is lower than said first voltage level, when it is not desired to illuminate said first dot in response to said first red video signal;
modulating the voltage at the base of a second transistor in response to said second red video signal, wherein the voltage at the base of said second transistor is at a third voltage level when it is desired to illuminate said first dot in response to said second red video signal and is at a fourth voltage level, which is lower than said third voltage level, when it is not desired to illuminate said first dot in response to said second red video signal, wherein said third voltage level is higher than said first voltage level, wherein the emitters of said first and second transistors are electrically connected to ground through a first resistor and wherein the collectors of said first and second transistors are electrically connected;
supplying the voltage at the emitter of said first transistor and said second transistor as the video signal to the red gun of said video display;
modulating the voltage at the base of a third transistor in response to said first blue video signal, wherein the voltage at the base of said third transistor is at said first voltage level when it is desired to illuminate said first dot in response to said first blue video signal and is at said second voltage level when it is not desired to illuminate said first dot in response to said first blue video signal;
modulating the voltage at the base of a fourth transistor in response to said second blue video signal, wherein the voltage at the base of said fourth transistor is at said third voltage level when it is desired to illuminate said first dot in response to said second blue video signal and is at said fourth voltage level when it is not desired to illuminate said first dot in response to said second blue video signal, wherein the emitters of said third and fourth transistors are electrically connected to ground through a second resistor and wherein the collectors of said third and fourth transistors are electrically connected;
supplying the voltage at the emitter of said third transistor and said fourth transistor as the video signal to the blue gun of said video display;
modulating the voltage at the base of a fifth transistor in response to said first green video signal, wherein the voltage at the base of said fifth transistor is at said first voltage level when it is desired to illuminate said first dot in response to said first green video signal and is at said second voltage level when it is not desired to illuminate said first dot in response to said first green video signal;
modulating the voltage at the base of a sixth transistor in response to said second green video signal, wherein the voltage at the base of said sixth transistor is at said third voltage level when it is desired to illuminate said first dot in response to said second green video signal and is at said fourth voltage level when it is not desired to illuminate said first dot in response to said second green video signal, wherein the emitters of said fifth and sixth transistors are connected to ground through a third resistor and wherein the collectors of said fifth and sixth transistors are electrically connected; and supplying the voltage at the emitter of said fifth transistor and said sixth transistor as the video signal to the green gun of said video display.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/591,760 US4599610A (en) | 1984-03-21 | 1984-03-21 | Overlaying information on a video display |
| US591,760 | 1984-03-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1240081A true CA1240081A (en) | 1988-08-02 |
Family
ID=24367823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000475192A Expired CA1240081A (en) | 1984-03-21 | 1985-02-26 | Overlaying information on a video display |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4599610A (en) |
| CA (1) | CA1240081A (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2162726A (en) * | 1984-07-31 | 1986-02-05 | Ibm | Display of overlapping viewport areas |
| US4818979A (en) * | 1986-02-28 | 1989-04-04 | Prime Computer, Inc. | LUT output for graphics display |
| JPS6378197A (en) * | 1986-09-22 | 1988-04-08 | フアナツク株式会社 | Image display device |
| US4876533A (en) * | 1986-10-06 | 1989-10-24 | Schlumberger Technology Corporation | Method and apparatus for removing an image from a window of a display |
| US4845488A (en) * | 1987-02-09 | 1989-07-04 | Siemens Aktiengesellschaft | Display data conversion |
| US5003491A (en) * | 1988-03-10 | 1991-03-26 | The Boeing Company | Multiplying video mixer system |
| US5155588A (en) * | 1990-02-06 | 1992-10-13 | Levien Raphael L | Color correction and apparatus for photographic reproduction |
| US5319384A (en) * | 1991-06-10 | 1994-06-07 | Symantec Corporation | Method for producing a graphical cursor |
| US5254984A (en) * | 1992-01-03 | 1993-10-19 | Tandy Corporation | VGA controller for displaying images having selective components from multiple image planes |
| US6342900B1 (en) * | 1996-12-06 | 2002-01-29 | Nikon Corporation | Information processing apparatus |
| JP6919628B2 (en) * | 2018-06-25 | 2021-08-18 | 株式会社オートネットワーク技術研究所 | Current detection circuit and power supply |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US31200A (en) * | 1861-01-22 | I H S White | Newspaper-file | |
| US3872461A (en) * | 1972-10-26 | 1975-03-18 | Mennen Greatbatch Electronics | Waveform and symbol display system |
| US4258362A (en) * | 1976-01-15 | 1981-03-24 | Westinghouse Electric Corp. | Phase coherent tracker of an arbitrary number of signals |
| US4070710A (en) * | 1976-01-19 | 1978-01-24 | Nugraphics, Inc. | Raster scan display apparatus for dynamically viewing image elements stored in a random access memory array |
| NL179417C (en) * | 1976-06-22 | 1986-09-01 | Hollandse Signaalapparaten Bv | BRIGHTNESS CONTROL DEVICE FOR DISPLAYING VIDEO SIGNALS ON A GRID SCAN DISPLAY. |
| JPS5399826A (en) * | 1977-02-14 | 1978-08-31 | Hitachi Ltd | Controller for data display |
| US4136359A (en) * | 1977-04-11 | 1979-01-23 | Apple Computer, Inc. | Microcomputer for use with video display |
| US4146879A (en) * | 1977-04-12 | 1979-03-27 | International Business Machines Corporation | Visual display with column separators |
| US4149148A (en) * | 1977-04-19 | 1979-04-10 | Sperry Rand Corporation | Aircraft flight instrument display system |
| US4247843A (en) * | 1978-08-23 | 1981-01-27 | Sperry Corporation | Aircraft flight instrument display system |
| IT1107869B (en) * | 1978-09-20 | 1985-12-02 | Olivetti & Co Spa | DEVICE AND METHOD OF VISUALIZING IMAGES FOR A PROGRAMMABLE CALCULATOR |
| JPS5588129A (en) * | 1978-12-27 | 1980-07-03 | Fuji Photo Film Co Ltd | Form synthesizer-recorder |
| US4317114A (en) * | 1980-05-12 | 1982-02-23 | Cromemco Inc. | Composite display device for combining image data and method |
| JPS57144589A (en) * | 1981-03-04 | 1982-09-07 | Nissan Motor | Picture display unit |
| US4454593A (en) * | 1981-05-19 | 1984-06-12 | Bell Telephone Laboratories, Incorporated | Pictorial information processing technique |
| US4498079A (en) * | 1981-08-20 | 1985-02-05 | Bally Manufacturing Corporation | Prioritized overlay of foreground objects line buffer system for a video display system |
| US4542376A (en) * | 1983-11-03 | 1985-09-17 | Burroughs Corporation | System for electronically displaying portions of several different images on a CRT screen through respective prioritized viewports |
-
1984
- 1984-03-21 US US06/591,760 patent/US4599610A/en not_active Expired - Fee Related
-
1985
- 1985-02-26 CA CA000475192A patent/CA1240081A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4599610A (en) | 1986-07-08 |
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Legal Events
| Date | Code | Title | Description |
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| MKEX | Expiry | ||
| MKEX | Expiry |
Effective date: 20050802 |