CA1244139A - Microwave waveform receiver - Google Patents
Microwave waveform receiverInfo
- Publication number
- CA1244139A CA1244139A CA000497407A CA497407A CA1244139A CA 1244139 A CA1244139 A CA 1244139A CA 000497407 A CA000497407 A CA 000497407A CA 497407 A CA497407 A CA 497407A CA 1244139 A CA1244139 A CA 1244139A
- Authority
- CA
- Canada
- Prior art keywords
- signal
- sampling
- digital
- samples
- delay line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
- G01R19/2506—Arrangements for conditioning or analysing measured signals, e.g. for indicating peak values ; Details concerning sampling, digitizing or waveform capturing
- G01R19/2509—Details concerning sampling, digitizing or waveform capturing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/16—Spectrum analysis; Fourier analysis
- G01R23/175—Spectrum analysis; Fourier analysis by delay means, e.g. tapped delay lines
Abstract
ABSTRACT OF THE DISCLOSURE
A microwave signal receiving apparatus comprises a delay line for distributing a microwave signal, samplers for sampling the signal spatially along the delay line and producing analog samples, analog-to-digital converters for converting the analog samples to digital samples, and digital memories associated with each converter for storing the digital samples.
A microwave signal receiving apparatus comprises a delay line for distributing a microwave signal, samplers for sampling the signal spatially along the delay line and producing analog samples, analog-to-digital converters for converting the analog samples to digital samples, and digital memories associated with each converter for storing the digital samples.
Description
` ~2~3~9 The present invention relates to a method and an apparatus for acquiring, storing and analyzing single or multiple simultaneous wideband complex radio frequency (RF) signals.
BACKGROUND OF THE INVENTION
A present method of acquiring, storing and analyzing RF
signals is to down-convert an RF signal to an intermediate frequency (IF) by local oscillator mixing for sampling and digitization using existing technology. The digital words generated by the analog to digital conversion process are stored in a digital memory. Once stored the con-tents may be accessed by a processor unit and analyzed. The drawback of this method is a limitation on the maximum instantaneous bandwidth. Since the process involves down conversion and serial digitization, -the maximum instantaneous bandwidth is set by the speed of the current digitization, analog-to-digital (A/D) conversion and digital memory processes. This limits the instantaneous bandwidth to several hundred MHz.
Another method of acquiring, storing and analyzing RF
signals employs the strobe principle as employed in sampling oscilloscopes. In sampling oscilloscopes, a voltage sample is taken at a discrete point on an input signal. Subsequent waveforms are sampled at later discrete points in order to obtain the overall waveforms. A drawback of this method is that, although it is capable of handling extremely wide instantaneous bandwidths, the technique is restricted to repetitive signals.
It cannot handle transient signals or complex waveforms which vary continuously.
SUMMARY OF THE INVENTION
The present invention employs a distributed sampling technique to acquire RF signals over wide RF bands to allow complex signal analysis, including analysis either at near real-time or at some time after acquisition, to be performed on the acquired signals.
i3~
In accordance wi-th one aspect of the present invention, there is provided a method of acquiri.ng a signal to be analyzed, comprising distributing the signal along a delay line, simultaneously sampling the delay line at a plurality of discrete points therealong to produce a plurality of analog samples;
converting each of the analog samples to a digital sample, and storing each of the digital samples in a predetermined memory location.
In accordance with another aspect of the present invention, there is provided a microwave signal receiving apparatus comprising delay line means for distributing a microwave signal, means for sampling the signal spatially along the delay line means and producing analog samples, means for converting the analog samples to digital sa~ples, means for storing the digital samples, and means for analyziny the digital samples.
BRIEF DESCRIPTION OF THE DRAWINGS
: These and other features of the invention will become more apparent from the description which follows in which reference is made to the appended drawings wherein:
FIGURE 1 is a block diagram of the basic components oE
the present invention;
FIGURE 2 is a block diagram of a preferred embodiment of the invention; and FIGURES 3a and 3b respectively illustrate a waveform to be sampled and a reconstructed waveform after undersampling.
31.2443L3~D
DETAILED DESCRIPTION
FIGURE 1 illustrates a basic block diagram of the microwave receiving apparatus, generally designated by the reference numeral 10, of the present invention. The apparatus is generally comprised of delay line means 12, having an input terminal 14, for distributing an input microwave signal, means 16 for sampling the signal at discrete points along the delay line means and producing parallel analog samples, means 18 for converting the analog samples to digital samples, means 20 for storing the digital samples and means 22 for analyzing the digital samples. The sampling means, converting means and storing means are responsive to a controller 24 which in turn is controlled by a processor 26 which is adapted to access storing means 20, control analyzer 22 and appropriate peripheral devices 28, such as mass storage devices, printers, video display devices and the like.
The delay line means is of the form of a meander delay line connected to a load or termination resistor 30, as shown, while the sampling means are a plurality of sampling gates 16a to 16n connected at discrete points or taps 32a to 32n respectively along the delay line. The converting means 18 are a plurality of analog-to-digital converters 18a to 18n corresponding in number to -the number of sampling gates and each being connected to an associated sampling gate. The storing means 20 includes a plurality oE buffers 20a to 20n corresponding in number to the number of analog-to-digital converters and each being connected to an associated analog-to-digital converter. Each buffer has a plurality of storage locations for storing in predetermined sequence the digital outputs of its associated converter. Thus it will be seen that the sampling means, converting means and storing means provide a plurality of parallel signal flow paths between the delay line and the analyzer.
The analyzer 22 may be a hardware dedicated device or a mixed hardware-software device. The construction and operation of the analyzer is well known to those skilled in this art and ~29L4~
accordingly it is not described in detail herein. Possible analyzer functions may include FFT algorithms, correlation routines and the like to analyze the input signal in terms of measurements such as frequency, pulse width, pulse repetition 5 rate, signal structure and the like, reconstruct the signal from the digital samples. The signal may then be displayed as desired on an appropriate display device and/or it may be stored indefinitely on a mass storage device for later analysis. The display, storage and other such output devices are generally 10 referred to by reference numeral 28.
The controller may be a pulse train generator connected to the sampling gates, converters and buffers as shown.
Thus, a signal received at input terminal 14 propagates along the meander delay line to termination resistor 24. Upon receipt of an appropriate trigger signal from the processor 26, sampling pulse train generator 24 generates a sampling pulse to allow the voltage distributed along the meander line to be 20 simultaneously sampled by samplers 16a to 16n. The parallel sampled analog voltages are transmitted to and subsequently transformed into digital words or samples by analog-to-digital converters 18a to 18n. The digital words corresponding to the sampled analog voltages are stored in memory locations specified 25 by processor 26 of digital memories 20a to 20n.
Thus, n samples, taken spatially along the input delay line, of the input waveform are stored in the digital memories.
If the input signal is longer in time than the delay in the input 30 delay line, the process of sampling, analog-to-digital converting and digital storing is repeated with the digital words corresponding to the subsequent set of n samples being stored in the next available location oE each of the memories. The process of sampling, converting and storing is repeated until all of the 35 input waveform has been sampled or until the processor halts the operation.
4~g Once stored the signal is retrieved from memory and passed to analyzer 22 for signal parameter measurements. To do this, the processor sequentially transmits the digital sample in the first memory location of each of memory units 20a to 20n beginning with memory 20n and ending with ending with memory 20a.
It then sequentially transmits the digital sample in the second memory location of each of memory units 20a to 20n beginning with memory 20n and ending with ending with memory 20a. This process is repeated until all required samples have been retrieved from memory and delivered to the analyzer. The analyzer then performs the required analysis and outputs the result(s), desired parameter(s) or actual stored signal, on an appropriate peripheral device 28.
FIGURE 2 illustrates a preferred embodiment which provides time and/or frequency preselection in order to reduce the processing requirements. The embodiment is similar to that of FIGURE 1 and, accordingly, like parts have been designated by like reference numerals.
An RF input signal arriving at terminal 50 is divided by a power splitter 52 into two paths 54 and 56. A signal in path 54 is detected by an RF detector 58 which transmits an appropriate signal to processor 26. Path 56 includes a delay unit 60, a PIN switch 62, a tunable filter 64. The output of the filter is connected to circuitry which is substantially as illustrated in FIGURE 1 including input terminal 14 of delay line 12. Pin switch 62 is controlled by processor 26 along line 70 and has two output terminals 66 and 68. Terminal 66 is connected to terminal 14 of the delay line and therefore bypasses the filter while terminal 68 is connected to the input of the filter.
Filter 64 is controlled by the processor along line 72 to provide bandwidth preselection.
BACKGROUND OF THE INVENTION
A present method of acquiring, storing and analyzing RF
signals is to down-convert an RF signal to an intermediate frequency (IF) by local oscillator mixing for sampling and digitization using existing technology. The digital words generated by the analog to digital conversion process are stored in a digital memory. Once stored the con-tents may be accessed by a processor unit and analyzed. The drawback of this method is a limitation on the maximum instantaneous bandwidth. Since the process involves down conversion and serial digitization, -the maximum instantaneous bandwidth is set by the speed of the current digitization, analog-to-digital (A/D) conversion and digital memory processes. This limits the instantaneous bandwidth to several hundred MHz.
Another method of acquiring, storing and analyzing RF
signals employs the strobe principle as employed in sampling oscilloscopes. In sampling oscilloscopes, a voltage sample is taken at a discrete point on an input signal. Subsequent waveforms are sampled at later discrete points in order to obtain the overall waveforms. A drawback of this method is that, although it is capable of handling extremely wide instantaneous bandwidths, the technique is restricted to repetitive signals.
It cannot handle transient signals or complex waveforms which vary continuously.
SUMMARY OF THE INVENTION
The present invention employs a distributed sampling technique to acquire RF signals over wide RF bands to allow complex signal analysis, including analysis either at near real-time or at some time after acquisition, to be performed on the acquired signals.
i3~
In accordance wi-th one aspect of the present invention, there is provided a method of acquiri.ng a signal to be analyzed, comprising distributing the signal along a delay line, simultaneously sampling the delay line at a plurality of discrete points therealong to produce a plurality of analog samples;
converting each of the analog samples to a digital sample, and storing each of the digital samples in a predetermined memory location.
In accordance with another aspect of the present invention, there is provided a microwave signal receiving apparatus comprising delay line means for distributing a microwave signal, means for sampling the signal spatially along the delay line means and producing analog samples, means for converting the analog samples to digital sa~ples, means for storing the digital samples, and means for analyziny the digital samples.
BRIEF DESCRIPTION OF THE DRAWINGS
: These and other features of the invention will become more apparent from the description which follows in which reference is made to the appended drawings wherein:
FIGURE 1 is a block diagram of the basic components oE
the present invention;
FIGURE 2 is a block diagram of a preferred embodiment of the invention; and FIGURES 3a and 3b respectively illustrate a waveform to be sampled and a reconstructed waveform after undersampling.
31.2443L3~D
DETAILED DESCRIPTION
FIGURE 1 illustrates a basic block diagram of the microwave receiving apparatus, generally designated by the reference numeral 10, of the present invention. The apparatus is generally comprised of delay line means 12, having an input terminal 14, for distributing an input microwave signal, means 16 for sampling the signal at discrete points along the delay line means and producing parallel analog samples, means 18 for converting the analog samples to digital samples, means 20 for storing the digital samples and means 22 for analyzing the digital samples. The sampling means, converting means and storing means are responsive to a controller 24 which in turn is controlled by a processor 26 which is adapted to access storing means 20, control analyzer 22 and appropriate peripheral devices 28, such as mass storage devices, printers, video display devices and the like.
The delay line means is of the form of a meander delay line connected to a load or termination resistor 30, as shown, while the sampling means are a plurality of sampling gates 16a to 16n connected at discrete points or taps 32a to 32n respectively along the delay line. The converting means 18 are a plurality of analog-to-digital converters 18a to 18n corresponding in number to -the number of sampling gates and each being connected to an associated sampling gate. The storing means 20 includes a plurality oE buffers 20a to 20n corresponding in number to the number of analog-to-digital converters and each being connected to an associated analog-to-digital converter. Each buffer has a plurality of storage locations for storing in predetermined sequence the digital outputs of its associated converter. Thus it will be seen that the sampling means, converting means and storing means provide a plurality of parallel signal flow paths between the delay line and the analyzer.
The analyzer 22 may be a hardware dedicated device or a mixed hardware-software device. The construction and operation of the analyzer is well known to those skilled in this art and ~29L4~
accordingly it is not described in detail herein. Possible analyzer functions may include FFT algorithms, correlation routines and the like to analyze the input signal in terms of measurements such as frequency, pulse width, pulse repetition 5 rate, signal structure and the like, reconstruct the signal from the digital samples. The signal may then be displayed as desired on an appropriate display device and/or it may be stored indefinitely on a mass storage device for later analysis. The display, storage and other such output devices are generally 10 referred to by reference numeral 28.
The controller may be a pulse train generator connected to the sampling gates, converters and buffers as shown.
Thus, a signal received at input terminal 14 propagates along the meander delay line to termination resistor 24. Upon receipt of an appropriate trigger signal from the processor 26, sampling pulse train generator 24 generates a sampling pulse to allow the voltage distributed along the meander line to be 20 simultaneously sampled by samplers 16a to 16n. The parallel sampled analog voltages are transmitted to and subsequently transformed into digital words or samples by analog-to-digital converters 18a to 18n. The digital words corresponding to the sampled analog voltages are stored in memory locations specified 25 by processor 26 of digital memories 20a to 20n.
Thus, n samples, taken spatially along the input delay line, of the input waveform are stored in the digital memories.
If the input signal is longer in time than the delay in the input 30 delay line, the process of sampling, analog-to-digital converting and digital storing is repeated with the digital words corresponding to the subsequent set of n samples being stored in the next available location oE each of the memories. The process of sampling, converting and storing is repeated until all of the 35 input waveform has been sampled or until the processor halts the operation.
4~g Once stored the signal is retrieved from memory and passed to analyzer 22 for signal parameter measurements. To do this, the processor sequentially transmits the digital sample in the first memory location of each of memory units 20a to 20n beginning with memory 20n and ending with ending with memory 20a.
It then sequentially transmits the digital sample in the second memory location of each of memory units 20a to 20n beginning with memory 20n and ending with ending with memory 20a. This process is repeated until all required samples have been retrieved from memory and delivered to the analyzer. The analyzer then performs the required analysis and outputs the result(s), desired parameter(s) or actual stored signal, on an appropriate peripheral device 28.
FIGURE 2 illustrates a preferred embodiment which provides time and/or frequency preselection in order to reduce the processing requirements. The embodiment is similar to that of FIGURE 1 and, accordingly, like parts have been designated by like reference numerals.
An RF input signal arriving at terminal 50 is divided by a power splitter 52 into two paths 54 and 56. A signal in path 54 is detected by an RF detector 58 which transmits an appropriate signal to processor 26. Path 56 includes a delay unit 60, a PIN switch 62, a tunable filter 64. The output of the filter is connected to circuitry which is substantially as illustrated in FIGURE 1 including input terminal 14 of delay line 12. Pin switch 62 is controlled by processor 26 along line 70 and has two output terminals 66 and 68. Terminal 66 is connected to terminal 14 of the delay line and therefore bypasses the filter while terminal 68 is connected to the input of the filter.
Filter 64 is controlled by the processor along line 72 to provide bandwidth preselection.
2~4~9 Thus, the processor may con-trol PIN switch 62 and tunable filter 64 to provide frequency preselection and pulse train generator 24 to provide time preselection. Delay circuit 60 is inserted in path 56 to delay the incoming RF signal in order to permit the processor, switch, filter, and pulse generator to respond to the desired time and/or frequency format.
~owever, the delay unit is not essential since the processor may be arranged to set bounds on time and frequency windows after an initial full look at the environment.
Essentially, four basic modes of operation are possible. The first basic mode is a wide open receiver analyzer where there is no time or frequency preselection. In this mode, the incoming RF signal enters terminal 50, passes throuyh delay 15 unit 60 and PIN switch 62 and is routed to terminal 14 via terminal 66. The signal is then distributed, sampled, converted, stored, analyzed and displayed as desired. The pulse train generator is activated from the outset.
The second basic mode entails only frequency preselection. In this mode, the incoming signal enters terminal 50, passes through delay unit 60 and is routed to terminal 14 via terminal 68 and filter 64 by PIN switch 62 under the control of the processor. The pulse train generator is activated from the outset.
The third basic mode of operation allows time preselection only. In this case, the incoming RF signal enters terminal 50, passes through delay unit 60 and is routed to 30 terminal 14 via terminal 66 by PIN switch 62 under the control of the processor. The signal is distributed but is only sampled when the pulse train generator is activated under the control of the processor. Once activated, the signal is sampled, converted, stored, analyzed and displayed as desired.
:~2~L39 The fourth and final basic mode of operation provides both time and frequency preselection. In this mode, the incoming RF signal enters terminal 50, passes through delay unit 60 is routed to terminal 14 via terminal 68 and filter 64 by PIN switch 62 under the control of the processor. The signal is distributed but is only sampled when the pulse train generator is activated by the processor.
Clearly the versatility offered by this approach allows any number of time and/or frequency windows to be implemented in real-time. Equally, it is evident that other types of circuitry are possible (i.e. mixers) to provide either time or frequency preselection and possible configurations are not limited to those discussed above.
Although the description thus far has assumed that the actual signal has been over-sampled, thereby storing the RF
signal itself, it is possible to under-sample the incoming signal to obtain an IF signal. obtaining an IF signal allows a reduction of the processing and analyzing time~
FIGURES 3a and 3b illustrate the effect of undersampling a waveform. FIGURE 3a illustrates a waveform prior to samplirlg and sampling periods while FIGURE 3b illustrates illustrates a waveform as reconstructed following undersampling.
As shown in FIGURE 3a, the waveform is sampled at a rate Sr = l/T
and is a sinusoid of frequency fl where fl< Sr < 2fl and T is the sampling period. The reconstructed waveform is also a sinusoid with a frequency less than fl. It can be shown that, given a sampling interval of T seconds, frequency components at fl and fl + n/T Hz, n being an integer, are indistinguishable, i.e. they have the same sampling values. In the case where Sr >2fl (greater than the Nyquist sampling rate), filtering of frequency components above fl will allow recovery of the sampled signal. However, for Sr < 2fl, the frequency domain is in effect "folded" by the sampling process.
-" ~24~3~
The process of undersampling may be used to effectively down~convert a signal over a limited frequency band. This process is related to the aliasing phenomenon. For example, given an effective sampling rate, Sr, of 200 MHz, an input signal having frequency components in the range of 200 MHz to 399 MHz, an output signal having Erequency components from 0 to 199 MHz is created thereby achieving down conversion. Since the spectrum is "folded" it is necessary to filter out any frequency components below 200 MHz and above 400 MHz in order to avoid possible ambiguities.
This process can be employed to down convert the carrier frequency without removing or destroying the modulation as long as the modulation is below Sr/2, 100 MHz in this case.
In effect, the actual "IF bandwidth" is equal to one-half of the sampling rate. In terms of -the embodiment illustrated in FIGURE 2, the filtering process may be undertaken by tunable filter 64 and the effective sampling rate may be controlled by processor 26 by selectively addressing the individual sampler or memory locations. The analyzer 22 in turn would adaptively read from the memory locations as specified by processor 26 to obtain the desired IF signal. The process therefore allows adaptive down-conversion of microwave signals to any desired IF.
Moreover, the process may be adaptively tailored for any given response. Although the analysis may be done immediately, it may be desirable to store the contents of the memories in a mass storage memory for analysis at some period after acquisition.
The above described approach offers several advantages.
It can store very complex RF signals over wide bandwidths extending from ~C to the GHz regime and the s-torage capability allows the contents to be recovered and analyzed either at RF or a-t IF.
Thus, the novel aspects of this invention is to use a distributed sampling technique to acquire the RF signal (by oversampling) or the IF signal (by undersampling) to convert the ~2~ 9 analog signal to digital fo:rm for digital storage and to retrieve the stored signal to perform complex signal analysis over wide RF
bands. This includes the analysis of complex signals in either near real-time or at some time after acquisition. Moreover, the system may be adaptively tailored to optimize its response to any received signal, including CW signals.
~owever, the delay unit is not essential since the processor may be arranged to set bounds on time and frequency windows after an initial full look at the environment.
Essentially, four basic modes of operation are possible. The first basic mode is a wide open receiver analyzer where there is no time or frequency preselection. In this mode, the incoming RF signal enters terminal 50, passes throuyh delay 15 unit 60 and PIN switch 62 and is routed to terminal 14 via terminal 66. The signal is then distributed, sampled, converted, stored, analyzed and displayed as desired. The pulse train generator is activated from the outset.
The second basic mode entails only frequency preselection. In this mode, the incoming signal enters terminal 50, passes through delay unit 60 and is routed to terminal 14 via terminal 68 and filter 64 by PIN switch 62 under the control of the processor. The pulse train generator is activated from the outset.
The third basic mode of operation allows time preselection only. In this case, the incoming RF signal enters terminal 50, passes through delay unit 60 and is routed to 30 terminal 14 via terminal 66 by PIN switch 62 under the control of the processor. The signal is distributed but is only sampled when the pulse train generator is activated under the control of the processor. Once activated, the signal is sampled, converted, stored, analyzed and displayed as desired.
:~2~L39 The fourth and final basic mode of operation provides both time and frequency preselection. In this mode, the incoming RF signal enters terminal 50, passes through delay unit 60 is routed to terminal 14 via terminal 68 and filter 64 by PIN switch 62 under the control of the processor. The signal is distributed but is only sampled when the pulse train generator is activated by the processor.
Clearly the versatility offered by this approach allows any number of time and/or frequency windows to be implemented in real-time. Equally, it is evident that other types of circuitry are possible (i.e. mixers) to provide either time or frequency preselection and possible configurations are not limited to those discussed above.
Although the description thus far has assumed that the actual signal has been over-sampled, thereby storing the RF
signal itself, it is possible to under-sample the incoming signal to obtain an IF signal. obtaining an IF signal allows a reduction of the processing and analyzing time~
FIGURES 3a and 3b illustrate the effect of undersampling a waveform. FIGURE 3a illustrates a waveform prior to samplirlg and sampling periods while FIGURE 3b illustrates illustrates a waveform as reconstructed following undersampling.
As shown in FIGURE 3a, the waveform is sampled at a rate Sr = l/T
and is a sinusoid of frequency fl where fl< Sr < 2fl and T is the sampling period. The reconstructed waveform is also a sinusoid with a frequency less than fl. It can be shown that, given a sampling interval of T seconds, frequency components at fl and fl + n/T Hz, n being an integer, are indistinguishable, i.e. they have the same sampling values. In the case where Sr >2fl (greater than the Nyquist sampling rate), filtering of frequency components above fl will allow recovery of the sampled signal. However, for Sr < 2fl, the frequency domain is in effect "folded" by the sampling process.
-" ~24~3~
The process of undersampling may be used to effectively down~convert a signal over a limited frequency band. This process is related to the aliasing phenomenon. For example, given an effective sampling rate, Sr, of 200 MHz, an input signal having frequency components in the range of 200 MHz to 399 MHz, an output signal having Erequency components from 0 to 199 MHz is created thereby achieving down conversion. Since the spectrum is "folded" it is necessary to filter out any frequency components below 200 MHz and above 400 MHz in order to avoid possible ambiguities.
This process can be employed to down convert the carrier frequency without removing or destroying the modulation as long as the modulation is below Sr/2, 100 MHz in this case.
In effect, the actual "IF bandwidth" is equal to one-half of the sampling rate. In terms of -the embodiment illustrated in FIGURE 2, the filtering process may be undertaken by tunable filter 64 and the effective sampling rate may be controlled by processor 26 by selectively addressing the individual sampler or memory locations. The analyzer 22 in turn would adaptively read from the memory locations as specified by processor 26 to obtain the desired IF signal. The process therefore allows adaptive down-conversion of microwave signals to any desired IF.
Moreover, the process may be adaptively tailored for any given response. Although the analysis may be done immediately, it may be desirable to store the contents of the memories in a mass storage memory for analysis at some period after acquisition.
The above described approach offers several advantages.
It can store very complex RF signals over wide bandwidths extending from ~C to the GHz regime and the s-torage capability allows the contents to be recovered and analyzed either at RF or a-t IF.
Thus, the novel aspects of this invention is to use a distributed sampling technique to acquire the RF signal (by oversampling) or the IF signal (by undersampling) to convert the ~2~ 9 analog signal to digital fo:rm for digital storage and to retrieve the stored signal to perform complex signal analysis over wide RF
bands. This includes the analysis of complex signals in either near real-time or at some time after acquisition. Moreover, the system may be adaptively tailored to optimize its response to any received signal, including CW signals.
Claims (25)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A microwave signal receiving apparatus comprising:
delay line means for distributing a microwave signal;
means for sampling the signal spatially along said delay line means and producing analog samples;
means for converting the analog samples to digital samples;
means for storing the digital samples;
means for analyzing said digital samples.
delay line means for distributing a microwave signal;
means for sampling the signal spatially along said delay line means and producing analog samples;
means for converting the analog samples to digital samples;
means for storing the digital samples;
means for analyzing said digital samples.
2. A microwave signal receiving apparatus as defined in claim 1, said sampling means including a plurality of sampling gate means.
3. A microwave signal receiving apparatus as defined in claim 2, further including controller means for simultaneously activating said sampling gate means at predetermined timed intervals.
4. A microwave signal receiving apparatus as defined in claim 3, said controller means including a pulse train generator and a microprocessor, said microprocessor being arranged to provide a trigger signal at predetermined timed intervals, said pulse train generator being responsive to said trigger signal to enable said gate means.
5. A microwave signal receiving apparatus as defined in claim 2, said converter means being a plurality of analog-to-digital converters corresponding in number to the number of said sampling gate means, each said analog-to-digital converters being associated with one of said sampling gate means.
6. A microwave signal receiving apparatus as defined in claim 5, said storing means including a memory means associated with each said converters, each said memory means having a plurality of storage locations for storing a plurality of sequential outputs of its associated converter.
7. A microwave signal receiving apparatus as defined in claim 4, said converter means being a plurality of analog-to-digital converters corresponding in number to the number of said sampling gate means, each said analog-to-digital converters being associated with one of said sampling gate means and being responsive to an enable signal from said pulse train generator for converting the current analog sample output of its associated gate means to a digital sample output.
8. A microwave signal receiving apparatus as defined in claim 7, said storing means including a memory means associated with each said converter, each said memory means having a plurality of storage locations for storing a plurality of sequential outputs of its associated converter and being responsive to an enable signal from said pulse train generator for storing the current digital sample output of its associated converter in one of said storage locations.
9. A microwave signal receiving apparatus as defined in claim 8, said storing means being responsive to said processor means for transferring digital samples in said storage locations to said analyzing means in predetermined sequence.
10. A microwave signal receiving apparatus as defined in claim 1. further including filter means connected to the input of said delay line means for filtering out signals of predetermined frequency.
11. A microwave signal receiving apparatus as defined in claim 10. further including means for selectively bypassing said filter means.
12. A microwave signal receiving apparatus as defined in claim 11. further including delay means for delaying an incoming signal.
13. A microwave signal receiving apparatus as defined in claim 1. further including means for detecting the presence of RF energy at an input terminal.
14. A microwave signal receiving apparatus as defined in claim 1. further including means responsive to an indication of RF energy at said input terminal for transmitting said energy to said delay line means.
15. A microwave signal receiving apparatus comprising:
an input terminal for applying an input signal to said apparatus;
means for directing said signal along first and second paths;
said first path including:
processor means and means for detecting the presence of RF energy at said input terminal;
said second path including:
signal delay means for delaying an input signal for a predetermined timed interval;
delay line means for distributing a signal, said delay line means having an input terminal;
filter means for filtering out of said input signal signals of predetermined frequency and producing a filtered input signal, said filter means having an output connected to said delay line means input terminal;
switch means responsive to said processor for selectively bypassing said filter means and applying said input signal to said delay line means input terminal or applying said input signal to filter means;
a plurality of sampling gates spatially connected to said delay line means for sampling the signal and producing a plurality of analog samples;
a plurality of analog-to-digital converters corresponding in number to the number of said sampling gate means, each said analog-to-digital converters being associated with one of said sampling gate means for converting the analog samples output by its associated gate means to digital samples;
means for storing the digital samples, said storing means including a memory means associated with each said converter, each said memory means having a plurality of storage locations for storing a plurality of sequential outputs of its associated converter;
controller means responsive to said processor for activating said gate means, analog-to-digital converters and said storing means;
analyzing means for analyzing digital samples stored in said memory means and storing a digital representation and other predetermined parameters of said input signal, said processor means being adapted to transfer said digital samples from said memory means to said analyzer at predetermined sequence; and display means responsive to said processor and said analyzing means for displaying said input signal and/or one or more parameters of said signal.
an input terminal for applying an input signal to said apparatus;
means for directing said signal along first and second paths;
said first path including:
processor means and means for detecting the presence of RF energy at said input terminal;
said second path including:
signal delay means for delaying an input signal for a predetermined timed interval;
delay line means for distributing a signal, said delay line means having an input terminal;
filter means for filtering out of said input signal signals of predetermined frequency and producing a filtered input signal, said filter means having an output connected to said delay line means input terminal;
switch means responsive to said processor for selectively bypassing said filter means and applying said input signal to said delay line means input terminal or applying said input signal to filter means;
a plurality of sampling gates spatially connected to said delay line means for sampling the signal and producing a plurality of analog samples;
a plurality of analog-to-digital converters corresponding in number to the number of said sampling gate means, each said analog-to-digital converters being associated with one of said sampling gate means for converting the analog samples output by its associated gate means to digital samples;
means for storing the digital samples, said storing means including a memory means associated with each said converter, each said memory means having a plurality of storage locations for storing a plurality of sequential outputs of its associated converter;
controller means responsive to said processor for activating said gate means, analog-to-digital converters and said storing means;
analyzing means for analyzing digital samples stored in said memory means and storing a digital representation and other predetermined parameters of said input signal, said processor means being adapted to transfer said digital samples from said memory means to said analyzer at predetermined sequence; and display means responsive to said processor and said analyzing means for displaying said input signal and/or one or more parameters of said signal.
16. A method of acquiring a signal to be analyzed, comprising:
distributing the signal along a delay line;
simultaneously sampling the delay line at a plurality of discrete points therealong to produce a plurality of analog samples;
converting each of the analog samples to a digital sample;
storing each of the digital samples in a predetermined memory location.
distributing the signal along a delay line;
simultaneously sampling the delay line at a plurality of discrete points therealong to produce a plurality of analog samples;
converting each of the analog samples to a digital sample;
storing each of the digital samples in a predetermined memory location.
17. A method as defined in claim 16, further including the step of accessing and analyzing each digital sample in a predetermined sequence.
18. A method as defined in claim 17, further including the step storing all of the digital samples in a mass storage device.
19. A method as defined in claim 17, further including the step repeating said sampling, converting and storing steps before commencing said accessing and analyzing steps.
20. A method as defined in claim 16, wherein said sampling step is effected at a rate which results in oversampling of said signal.
21. A method as defined in claim 16, wherein said sampling step is effected at a rate which results in undersampling sampling of said signal.
22. A method as defined in claim 21, wherein the sampling rate, Sr, is f1 < Sr < 2f1, where f1 is the frequency of the signal.
23. A method of acquiring a signal to be analyzed, comprising:
(a) selecting a frequency range within which signals are to be acquired;
(b) distributing signals within said range along a delay line;
(c) simultaneously sampling the delay line at a plurality of discrete points therealong to produce a group of analog samples;
(d) simultaneously converting each of the analog samples to a digital sample;
(d) simultaneously storing each of the digital samples of the group of samples in predetermined memory locations;
(e) repeating steps (c), (d) and (e).
(a) selecting a frequency range within which signals are to be acquired;
(b) distributing signals within said range along a delay line;
(c) simultaneously sampling the delay line at a plurality of discrete points therealong to produce a group of analog samples;
(d) simultaneously converting each of the analog samples to a digital sample;
(d) simultaneously storing each of the digital samples of the group of samples in predetermined memory locations;
(e) repeating steps (c), (d) and (e).
24. A method of down-converting an RF signal having frequency components between f1 and f2. where f2 is greater than f2 to an IF signal. comprising:
(a) filtering said RF signal to remove frequency components below f1 and above f2:
(b) distributing the RF signal along a delay line:
(c) simultaneously sampling the delay line at a sampling rate Sr which is greater than f1 and less than f2 and at a plurality of discrete points along said delay line to produce a group of analog samples:
(d) simultaneously converting each of the analog samples to a digital sample;
(e) simultaneously storing each of the digital samples in predetermined memory locations:
(f) repeating steps (c), (d) and (e) until all of the RF signal has been sampled:
(g) constructing a new signal by sequentially accessing the digital samples in said memory locations.
(a) filtering said RF signal to remove frequency components below f1 and above f2:
(b) distributing the RF signal along a delay line:
(c) simultaneously sampling the delay line at a sampling rate Sr which is greater than f1 and less than f2 and at a plurality of discrete points along said delay line to produce a group of analog samples:
(d) simultaneously converting each of the analog samples to a digital sample;
(e) simultaneously storing each of the digital samples in predetermined memory locations:
(f) repeating steps (c), (d) and (e) until all of the RF signal has been sampled:
(g) constructing a new signal by sequentially accessing the digital samples in said memory locations.
25. A method of down-converting an RF signal having frequency components between f1 and f2. where f2 is greater than f1. to an IF signal. comprising:
(a) filtering said RF signal to remove frequency components below f1 and above f2:
(b) distributing the RF signal along a delay line:
(c) simultaneously sampling the delay line at a sampling rate Sr which is greater than the Nyquist sampling rate and at a plurality of discrete points along said delay line to produce a group of analog samples:
(d) simultaneously converting each of the analog samples to a digital sample:
(e) simultaneously storing each of the digital samples in predetermined memory locations:
(f) repeating steps (c). (d) and (e) until all of the RF signal has been sampled:
(g) constructing a new signal by sequentially accessing only predetermined ones of the digital samples in said memory locations.
(a) filtering said RF signal to remove frequency components below f1 and above f2:
(b) distributing the RF signal along a delay line:
(c) simultaneously sampling the delay line at a sampling rate Sr which is greater than the Nyquist sampling rate and at a plurality of discrete points along said delay line to produce a group of analog samples:
(d) simultaneously converting each of the analog samples to a digital sample:
(e) simultaneously storing each of the digital samples in predetermined memory locations:
(f) repeating steps (c). (d) and (e) until all of the RF signal has been sampled:
(g) constructing a new signal by sequentially accessing only predetermined ones of the digital samples in said memory locations.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000497407A CA1244139A (en) | 1985-12-11 | 1985-12-11 | Microwave waveform receiver |
| US06/924,782 US4866441A (en) | 1985-12-11 | 1986-10-30 | Wide band, complex microwave waveform receiver and analyzer, using distributed sampling techniques |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000497407A CA1244139A (en) | 1985-12-11 | 1985-12-11 | Microwave waveform receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1244139A true CA1244139A (en) | 1988-11-01 |
Family
ID=4132064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000497407A Expired CA1244139A (en) | 1985-12-11 | 1985-12-11 | Microwave waveform receiver |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4866441A (en) |
| CA (1) | CA1244139A (en) |
Families Citing this family (28)
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| US5208545A (en) * | 1991-03-27 | 1993-05-04 | Schweitzer Engineering Laboratories Inc. | Apparatus and method for eliminating phase skew in a multi-channel data acquisition system |
| US5539402A (en) * | 1992-08-03 | 1996-07-23 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | System for memorizing maximum values |
| US5471162A (en) * | 1992-09-08 | 1995-11-28 | The Regents Of The University Of California | High speed transient sampler |
| US5532925A (en) * | 1994-08-12 | 1996-07-02 | Fisher Controls International, Inc. | Current-to-pressure transducer with selectable, adjustable input filter |
| FR2764070B1 (en) * | 1997-05-28 | 1999-07-02 | Commissariat Energie Atomique | SINGLE SHOT ELECTRIC SAMPLER FOR SHORT PULSES |
| US7515896B1 (en) | 1998-10-21 | 2009-04-07 | Parkervision, Inc. | Method and system for down-converting an electromagnetic signal, and transforms for same, and aperture relationships |
| US6061551A (en) | 1998-10-21 | 2000-05-09 | Parkervision, Inc. | Method and system for down-converting electromagnetic signals |
| US6166673A (en) * | 1998-09-29 | 2000-12-26 | National Instruments Corporation | Data acquisition system and method with a selectable sampling rate |
| US7236754B2 (en) | 1999-08-23 | 2007-06-26 | Parkervision, Inc. | Method and system for frequency up-conversion |
| US6813485B2 (en) * | 1998-10-21 | 2004-11-02 | Parkervision, Inc. | Method and system for down-converting and up-converting an electromagnetic signal, and transforms for same |
| US7039372B1 (en) | 1998-10-21 | 2006-05-02 | Parkervision, Inc. | Method and system for frequency up-conversion with modulation embodiments |
| US6370371B1 (en) * | 1998-10-21 | 2002-04-09 | Parkervision, Inc. | Applications of universal frequency translation |
| US6853690B1 (en) | 1999-04-16 | 2005-02-08 | Parkervision, Inc. | Method, system and apparatus for balanced frequency up-conversion of a baseband signal and 4-phase receiver and transceiver embodiments |
| US6879817B1 (en) | 1999-04-16 | 2005-04-12 | Parkervision, Inc. | DC offset, re-radiation, and I/Q solutions using universal frequency translation technology |
| US7110435B1 (en) * | 1999-03-15 | 2006-09-19 | Parkervision, Inc. | Spread spectrum applications of universal frequency translation |
| US7693230B2 (en) | 1999-04-16 | 2010-04-06 | Parkervision, Inc. | Apparatus and method of differential IQ frequency up-conversion |
| US7065162B1 (en) * | 1999-04-16 | 2006-06-20 | Parkervision, Inc. | Method and system for down-converting an electromagnetic signal, and transforms for same |
| US7110444B1 (en) | 1999-08-04 | 2006-09-19 | Parkervision, Inc. | Wireless local area network (WLAN) using universal frequency translation technology including multi-phase embodiments and circuit implementations |
| US8295406B1 (en) | 1999-08-04 | 2012-10-23 | Parkervision, Inc. | Universal platform module for a plurality of communication protocols |
| US6225935B1 (en) * | 2000-03-16 | 2001-05-01 | Mmtc, Inc. | Biphase-encoded signal processing employing passive and/or semi-passive transistor circuits |
| US7010286B2 (en) | 2000-04-14 | 2006-03-07 | Parkervision, Inc. | Apparatus, system, and method for down-converting and up-converting electromagnetic signals |
| US7454453B2 (en) | 2000-11-14 | 2008-11-18 | Parkervision, Inc. | Methods, systems, and computer program products for parallel correlation and applications thereof |
| GB0109518D0 (en) * | 2001-04-18 | 2001-06-06 | Mclean Reuben F | Signal analysis and synthesis |
| US7072427B2 (en) | 2001-11-09 | 2006-07-04 | Parkervision, Inc. | Method and apparatus for reducing DC offsets in a communication system |
| US7570189B2 (en) * | 2002-06-27 | 2009-08-04 | Nxp B.V. | Radio frequency data capture |
| US7460584B2 (en) | 2002-07-18 | 2008-12-02 | Parkervision, Inc. | Networking methods and systems |
| US7379883B2 (en) | 2002-07-18 | 2008-05-27 | Parkervision, Inc. | Networking methods and systems |
| US20060068556A1 (en) * | 2004-09-27 | 2006-03-30 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3484591A (en) * | 1966-07-18 | 1969-12-16 | Hewlett Packard Co | Extended bandwidth signal-to-noise ratio enhancement methods and means |
| US3597761A (en) * | 1969-11-14 | 1971-08-03 | American Astronics Inc | High-speed analog-to-digital converter and method therefor |
| US3872387A (en) * | 1972-09-29 | 1975-03-18 | Zenith Radio Corp | Frequency response modifier for fixed-tuned IF amplifiers |
| US3820112A (en) * | 1973-10-01 | 1974-06-25 | A Roth | High speed analog-to-digital conversion system |
| FR2428945A1 (en) * | 1978-06-13 | 1980-01-11 | Thomson Csf | TRANSITIONAL SIGNALING DEVICE |
| CA1135342A (en) * | 1979-12-21 | 1982-11-09 | Trevor W. Tucker | Microwave storage device |
| JPS56115026A (en) * | 1980-02-18 | 1981-09-10 | Sony Tektronix Corp | Analog-digital converter |
| US4611194A (en) * | 1985-08-16 | 1986-09-09 | The United States Of America As Represented By The Secretary Of The Army | Analog-to-digital converter |
-
1985
- 1985-12-11 CA CA000497407A patent/CA1244139A/en not_active Expired
-
1986
- 1986-10-30 US US06/924,782 patent/US4866441A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US4866441A (en) | 1989-09-12 |
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