CA1244538A - Dtmf receiver sense and control arrangement - Google Patents
Dtmf receiver sense and control arrangementInfo
- Publication number
- CA1244538A CA1244538A CA000496967A CA496967A CA1244538A CA 1244538 A CA1244538 A CA 1244538A CA 000496967 A CA000496967 A CA 000496967A CA 496967 A CA496967 A CA 496967A CA 1244538 A CA1244538 A CA 1244538A
- Authority
- CA
- Canada
- Prior art keywords
- dtmf
- dtmf receiver
- data
- operated
- response
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/18—Electrical details
- H04Q1/30—Signalling arrangements; Manipulation of signalling currents
- H04Q1/44—Signalling arrangements; Manipulation of signalling currents using alternate current
- H04Q1/444—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies
- H04Q1/45—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling
- H04Q1/457—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling with conversion of multifrequency signals into digital signals
- H04Q1/4575—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling with conversion of multifrequency signals into digital signals which are transmitted in digital form
Abstract
DTMF RECEIVER SENSE AND CONTROL ARRANGEMENT
ABSTRACT OF THE INVENTION
The DTMF receiver sense and control arrangement collects and stores multiple customer originated data for determination of customer identification, validity and billing purposes. This arrangement is part of a telecommunications switching office and monitors up to 24 DTMF receivers (channels) to determine whether each channel contains valid data. This data is stored in temporary storage for subsequent transmission to a processor of the switching office. Each of the DTMF receivers asynchronously presents data for collection by this arrangement.
This arrangement provides the proper timing required to operate up to 24 receivers to obtain their data, while it is stable at the receiver. Once a receiver transmits data, this arrangement then synchronizes its operation to that receiver so that, sequential monitoring of each of the 24 channels is guaranteed and no loss of valid data will result. In addition, each DTMF receiver may be enabled selectively for special monitoring.
ABSTRACT OF THE INVENTION
The DTMF receiver sense and control arrangement collects and stores multiple customer originated data for determination of customer identification, validity and billing purposes. This arrangement is part of a telecommunications switching office and monitors up to 24 DTMF receivers (channels) to determine whether each channel contains valid data. This data is stored in temporary storage for subsequent transmission to a processor of the switching office. Each of the DTMF receivers asynchronously presents data for collection by this arrangement.
This arrangement provides the proper timing required to operate up to 24 receivers to obtain their data, while it is stable at the receiver. Once a receiver transmits data, this arrangement then synchronizes its operation to that receiver so that, sequential monitoring of each of the 24 channels is guaranteed and no loss of valid data will result. In addition, each DTMF receiver may be enabled selectively for special monitoring.
Description
~DMF REOE IVFR SENSE AND CONTROL ARRANGEMENl' ~CKGROUND OF THE INVENTION
The present inven-tlon pertains to a data acquisi-tion arrangement for a telecommunications switching system and more particularly to an arrangement for collec-ting and transmittiny customer data for identification, validation and billing of special features such as calling card sel~ices.
With the popularization of placing telephone calls via credit cards, exis-ting telecammunication switching systems require m~difications to provide -this function to custom~rs. Cus-tomer identification is required for billing purposes. Further, a validity code is re~uired to insure that the credit card is being pro~erly used.
This data must be collected in an on-line fashion.
m at is, before the switching system may complete the call, the customer must transmit the required informatlon to the switching system via his station equiE~ent. The customer is supplied with a request signal mdicating that the switching system requires this information. The customer then responds with a series of numbers via the DTMF keypad with the required identification, billing and validity data. The switching system must then collect this information; transmitted to its central processing unit; and, analyzes the in~orn~ation for proper handling of the telephone call. If a valid call has been ~nitiated by the cust~mer, the system will respond by connecting his caLl.
Accordingly, systems which were previously designed and did not originally incorporate this feature, must be supplemented to provide this capability. The present invention is a mcdular addition for such a telecGmmNnications system which provides the data acquisition and transmission for special features such as calling card service.
SUMM~RY OF THE INVENTION
In a teleccmmunications switching system which has a network clock, a DTMF receiver arrangement is connected to a number of DTMF receivers. mese DTMF receivers interface between ~ 'f ~kS~38 custamers and the switching system for transmitting data to the switching system. The DTMF receiver arrangement is also connected to a processor of the switching system.
The DTMF receiver arrangement includes control points which are connected to the processor and operate to store and transmit DTMF receiver data to and frQm the processor. Sense points are connected to the processor and operate to store data for transmission to the processor.
A sequencing circuit is connected to the network clock.
m e sequencing circuit operates in response to the network clock to produce a number of regularly defined time slots for samplin~
DIMF receivers during a complete DIMF receiver sampling cycle.
The D~ receiver c~rrangement also includes last look circuitry. The last look circuitry is connected to the DTMF
receivers, to the seq~encing circuit and to the netw~rk clwk.
The last look circuit cyclically operates during each time slot in response to the sequencing circuit to produce and to store an indication of whether a particular DTMF receiver has been previously sa~led for valid data during the current DTMF receiver sampling cycle.
A generating circuit is connected to the control points, to the last loo~ circuit and to the sequencing circuit.
me generating circuit operates in response to an indication of said last look circuit that the particular DTME' receiver has previously been sampled during the current sampling cycle. As a result, the generatIng circuit operates to inhibit production of a write signal which all~s valid data to be stored. The generating circuit also operates in response to an indication that of the last look circuit, that the particular DTMF receiver of this ti~e slot has not been previously sampled during the current DTMF
receiver sampling cycle. In response to this indication, the generating circuit produces a write signal which enables valid data to be stored. The last look circuitry also stores ~he new sampling indication.
53~3 A storage device is connected to the DTMF receivers for storing valid receiver data. In addition, the storage device is also connected to the se~uencing circuit, to the generating circuit and to the sense points. me storage device operates in response to the write signal of the generating circuit to store data frcm a particular ~IMF receiver during the corresponding time slot. me storage device also operates to transmit the stored data of each DTMF receiver to the sense point for retransmission to the processor of the switching system.
A B~IEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram of a DTMF receiver sense and control arrangement for a telecommunications switching system.
Figure 2 is a schematic diagram of the control logic for the DTMF receiver sense and control arrangement of the present invention.
DESCRIPTION OF I~E PREFER~ED EMBODIMENT
Referring to Figure 1, a block diasratn of the DTMF
receiver sense and control ærangement is shown. m e DTMF
receiver sense and control (DRSC) arrangement is connected to the switching system's processor via a tri-state bus. The processor interfaces to the DRSC by operating three control pomt words ~50, 51, 53) and one sense point word (52). Word 52 is a sense word.
Words 50, 51 and 53 æe control words. Sense words may onl~ be read from by the processor, whereas control words may be written to or read from by the processor. The DRSC may read and write both sense and control words. Each of the sense and control words and the corresponding tri-state bus is 32 bits wide however, this design is not limlted to a 32 bit implementation.
DTMF receivers 1 through 24 are connected between and the timing, synchronization and control logic 99. m is DRSC
arrangement may monitor up to 24 such DTMF receivers. me timing, synchronization and control logic 99 is also connected to a network clock ~not shown) which operates at a frequency 8 khz.
Logic 99 is connected to the network clcck via the LTS 192 lead.
DTMF receivers 1 through 24 are connected to the logic 99 via the ~Z~S38 data/flags bus. The data/fLags bus is 4 bits wide. Logic 99 selectively exa~ines each of ~le 24 DIMF receivers. In order to connect the logic 99 to one of the Dq~ receivers. I`he MMF
receivers are accessed by a 5 bit address bus.
In addition, channel initiali~ation hardware is connected between each of the 24 DTMF receivers and control word 50. The channel initialization hardware 30 is also connected to the logic 99 via INITCOMP lead.
Control words 50, 51 and 53 are connected to logic sense word 52 is connected to FIFO 40 which is turn connected to logic 99. m e fact that the DTMF receivers 1 through 24 are packaged four per printed wiring card is important to further understanding of the present invention. The processor transmits an indication via the tri-state bus to control ~ord 50. mis indication determines which group of 4 DIME' receivers on a particular printed wiring card is to be initialized. mese indications are stored and control word 50 and transmitted to the channel initialization hardware 30 in response to this transfer.
Channel initialization hardware 30 addresses the particular printed wiring card of DqMF receivers indicated by control word 50 and initializes these receivers for a transmission of customer data to the logic 99. When the initialization of the DIMF
receivers is ccmplete, a signal is transmitted from the channel initialization hardware 30 via the INITCCMP lead to the logic 99.
Next, the processor indicates to the logic 99 which of the 24 DTMF receivers have been initiali~ed and are ready for use by the call processing function. To acccmplish this, the processor sets bits and control word 51 which correspond to those DTMF receivers which have been initialized. The purpose of the DRSC circuitry is to provide a means for collecting customer data, so that, this data may be processed by an off-line data processing system for validating and billing custcmers for special service such as, credit card calls. m e data is taken by the logic 99 at a particular rate. m e DrDMF ch.~nnel will hold customer data valid for approximately 45 milliseconds. m e logic 99 access each Dl~
53~3 channel once every 24 milliseconds to guarantee that the customer data is accessecl while the data is .stcible. Each one millisecond access interval of a receiver is broken up into two intervals each of 0.5 milliseconds. Duriny the first interval, ]ogic 99 examines a flag to determine whether the particular receiver is transmitting a valid digit. During the second interval, logic 99 removes the data digit from the receiver and stores it in FIFO 40.
Each data word stored in FIFO 40 will also contain a corresponding 5 hit address of the particular DTMF receiver from which the data originated.
When the processor requires the customer data FIFO 40 has unlocked one data word containing the channel address and the DTMF data into sense word 52. me processor will read this word from sense word 52 and store it in the processors memory.
In addition, the processor may indicate to logic 99 that it is to receive a particular data word via control word 53 for maintenance purposes. The processor will transmit this data word via the tri-state bus to control word 53. Logic 99 will remove this data word from the control word 53 and insert it into the data being sent back to the processor through FIFO 40 at the appropriate ti~e. The processor will read this data via the sense word 52 and determine whether the word read compares to the word the processor transmitted, thereby indicating a fault in the DRSC
circuitry.
The DTMF receivers or channels are connected to FIFO 40 via the data/flags 4 bit bus. Control word 51 of Figure 1 is connected to AND gate 161 via the RCVR ON lead. On each cycle of the DRSC clock, an indication is transmitted via this lead. This indication determines whether the particular receiver to be examined in this time slot is active. me processor sets bits in ~rd 51 corresponding to each one of the 24 receivers which is active. Therefore, the DRSC will send data to the processor ~or only those receivers which are active.
The L~S192 signal, which is an 8 ~h~ frequency, and the MCLK2 signal are transmitted from the net~Drk clock of the 3~3 switching system to AND gate 100 via corresponding leads. AND
gate 100 is comlected to clivide by four circuit 101. Divide by four circuit 101 is connected to selector 105, which is a modulo 48 circuit, providing for a set of output signals which indicate 48 equal time periods. In addition, divide by four circuit 101 is connected to D-type flip-flop 125 and to N~ND gate 146.
Selector 105 is connected via a number of output leads to decoder 110. Decocler 110 provides a plurality of signals via the CEN O through CEN 5 leads. These leads are connected to the six DTMF receiver printed wiring cards. Each DTMF receiver printed wiring card contains Pour DTMF receiver circuits.
Selector 105 produces three other signals on the A, B
and C leads. The A and B leads along with the three other signals, which produce the DqMF receiver printed wiring card enables, represent the identity of the particular DTMF channel for which the DRSC is currently processing data. These leads containing the chalmel number are connected to comparator 180 and to FIFO 40. When a digit of custcmer data is transmitted to the processor of the switching system, the channel number (DTMF
receiver identity) which produced this digit is also simultaneously transmitted.
The data/flags bus is connected to the D input of flip-flops 141 through 144. Inverted copies of the A, B and C
signals are prcduced by gates 112, 113 and 111 respectively.
Gates 112 and 113 are connected to decoder 130~ Since the A and B
signals are the lcw to order bits of the channel nu~ber, their deccde by decoder 130 produces an indication of which one of the four DTMF receivers on a particular printed wiring card is currently being interrogated for data.
Decoder 130 is connected to NOR gates 131 through 134.
~OR gates 131 through 134 are connected to the clock input of D-type latches 141 through 144, respectively. N~ND gate 126 is connected to D-type latch 125 and to gate 111. The output of N~ND
gate 126 is connected as an enabling signal to NOR gates 131 throl~gh 134. ~AND gate 146 and decoder 130 are each connected to 53~3 NOR gate 147. NOR gate 147 and the network clock via the l.~S192 lead are connected to NOR gate 149. NOR gate 1~9 is connected to the ~rite enable of the last look memory 150.
D-type flip-^flop 125 and gate 111 are connected to NAND
gate 127, which is also connected to AND gate 128. Demultiplexer 160 and gate 161 are connected to OR gate 162, which in turn is connected to AND gate 128. AND gate 128 is connected via the WRITE FIFO lead to FIFO 40. The slgnal on this lead enables FIFO
40 to receiver and store valid data digits frcm each of the receivers at the appropriate time intervals.
The outputs of selector 105, which are decoded for the DTMF receiver prin~ed wiring cards, are connected to last look memory 150 as an address. m e outputs of D-type latches 141 through 144 are connected as the data inputs to last look memory 150. mese four inputs represent the four DTMF receivers on a particular printed wiring card. Onlv one of the four DTMF
receivers on a particular printed wiring card will be responding during a particular DRSC clock interval. The outputs of last look memory 150 are connected to AND gates 151 through 154. In addition, the output of D~type flip-flops 141 through 144 æe respectively connected to AND gates 151 through 154. m e output of AND gates 151 through 154 æe connected to demultiplexer 160.
Demultiplexer 160 is also connected to gates 112 and li3. The RCVR ON lead fxom word 51 of Figure 1 is connected as an enabling signal to demultiplexer 160.
The output of FIFO 40 is connect~d via a 9 bit bus to sense word 52 fGr transmission to the processor of the custcmer digits.
For a maintenance access of the DRSC circuitry, the processor sets an indication in control word 53 of Figure 1.
Control word 53 is connected via the MAINT ACOE SS lead to D-type latch 170. NPND gate 166 is connected to the clock input of latch 170. The maintenance function of the processor inserts a particular digit word into the stream of digits transmitted from the DRSC to the processor. The processor then reads back the appropriate receiver digit and determines, whether the digit receivecl corresponds to the digit transmitted. The processor transmits the maintenance digit to control word 53 of Figure 1.
Control word 53 is connected via a 4 bit bus to latch 185.
Flip-flop 170 is connected to comparator 180.
Comparator 180 is also connected to word 53 of Figure 1 via the MPINT REG CHANNEL # lead for receiving the maiNtenance channel identity nu~ber. Cc~p æ ator 180 is connected to N~ND gate 181.
NPND gate 181 is also connected to gate 111. The output of N~ND
gate 181 is connected to the enable of decoder 110 and to the enable of latch 185. me output of latch 185 is coNnected via the 4 bit input DATA bus to FIFO 40. In addition, ccmparator 180 is connected to the input of AND ga-te 161.
Two clock signals from the network elock (LTS192 and MCLK2) are ccmbined by AND gate 100 and transmitted to divide by four cireuit 101. Divide by four cireuit 101 produces a signal on the CRY lead which is transmitted to selector 105. Selector 105 produces all the timing signals necessary for operation of the DRSC logic. The DRSC counts modulo 48 and produces a numker of signals during each one of the 48 intervals. m ree of the signals produced by selector 105 are the high order 3 bits of the channel number, which is the identity of the current DTMF receiver to be processed by the DRSC cireuitry. These signals are transmitted to deeoder 110. Decoder 110 produces card enables CEN 0 through CEN
5. The A and B signals of selector 105 are the two low order bits of the channel number. me opposite sense of the A and B signals is produced by NAND gates 112 and 113, respectively. Both senses of these signals are used throughout the circuit.
me signal procluced on the C lead indicates which half cycle of 48 cycles of selector 105 is currently in progress.
During the first half of each selector cycle, the C lead is at logic 0 and flags from a particular printed wiring card of receivers are gated to latches 141 through 144 for determination of whether a valid digit e~ists for the corresponding receivers.
Although, during this selector cycle, one of the card enables CEN
~Z~3~3 signals enables one particular printed wiring card containing four DTMF receivers, only one of the receivers has me~mingful data.
D~lring the selector half cycle when the C signal is at logic 1, valid data appears on the data/flag bus from the particular receiver. This data is gated into FIFO 40.
A total of 4~ selector cycles was chosen because data is available and stable at the receiver for 45 milliseconds. It takes approximately 1 millisecond to process each receiver therefore, 24 receivers may be processed in 24 milliseconds. The 24 millisecond co~mt of selector 105 guarantees that each receiver will be serviced while it has valid and stable data. Also, each receiver may be examined a second time.
When the CRY signal is clocked, flip flop 125 latches this signal and provides and enabling signal to NOR gates 131 through 134 via gate 126. m e two low order bits of the channel address IA and B) are decoded by decoder 30 to select which one of the four receivers on a particular printed wiring card is currently operating in this clock cycle. Decoder 130 then operates the corresponding gate 131 through 134, which latches a flag in one of the flip-flops 141 through 144, corresponding to the particular one of four receivers which is enabled during this clock cycle. When a flag is set in last look memory 150, it indicates that on the previous examination of that receiver, a valid digit was collected from that receiver.
Since each receiver is examined twice within a 48 millisecond time period, the same digit may be seen twice. In order to circumwent this problem, the value of the flag stored in flip-flops 141 through 144 is anded with the value contained for that receiver in the last look m~mory 150, by AND gates 151 through 154, respectively. This produces the CHOK 0 through CHOK
3 signals. The CHOK 0 - CHOK 3 signals are then input to demultiplexer 160. Demultiplexer 160 is enabled as a function of the RCVR ON signal, whenever a particular receiver is active. In addition, demultiplexer 160 decodes the two low order bits of the channel address A and B in order to select the appropriate one of t L?~ 3 ~B
four last look values. Demultiplexer 160 then procluces a signal, which it transmits to gate 128 to produce the WRITE FIFO signal, which causes FIFO 40 to store the presellt value of the data/flags bus. The data on the data/flag bus will be stored, if the value of the last look for that particular receiver is 0, however, if the last look value for that particular receiver was 1, indicating that it had been sampled within the previous 24 millisecond interval, the WRITE FIFO signal will be inhibited and data will not be stored into FIFO 40. When this cycle has been repeated for the other three receivers on the printed wiring card currently being examined, the contents of latches 141 through 144 are stored in the last look memory 150 via the signal from gate 149, which occurs once every four clock cycles of selector 105, transmitted to the WE input of last book memory 150. me flags are wl-itten into last look memory 150 as a function of the high three order bits of the channel address produced by selector 105.
FIFO 40 continuously presents the first data which it received and transmits this data to sense word 52 of Figure 1.
When the processor initiates a read of sense word 52, the next oldest word contained in FIFO 40 is transmitted to sense word 52.
In this way, the processor may cyclically retrieve a data dlgit for each of the 24 DTMF receivers.
For a maintenance access, the processor transmits to control word 53 a bit (MAINT ACOESS), which indicates that a maintenance access is requested, and the identity of the DTMF
chamlel ~channel number~ in which to insert a predefined data digit. In addition, the processor transmits the maintenance digit to control word 53. Control word 53 writes the maintenance digit into latch 185 via the MAINT DATA bus, which is a 4 bit bus.
Latch 185 stores the maintenance digit, until such time as it is required for insertion into the digit stream transmitted to the processor via sense word 52. me data input to flip-flop 170 is permanently set at logic 1 and the M~INT ACOE SS signal causes flip-flop 170 to produce a signal for operating comparator 180.
53!3 Comparator 180 compares the maintenance channe] num~er transmitted by the processor w:ith the current ehannel number produced by selector 105. Ebr comparlson of the two channel numbers, the SEL MAINT signal is produced by eomparator 180, which indicates that the eurrent ehannel cycle is the one for which the maintenanee digit is to be transmitted. The SEL MAINT signal is transmitted to gate 161 which causes gate 166 to reset the maintenance request to eamparator 180 for the next selector cyele.
In addition, the SEL MAINT signal operates NAND gate 181 to disable deeoder 110 fro~ produeing eard enables CEN O through CEN
5, while simultaneously enabling lateh 185. Lateh 185, when enabled, transmits the 4 bit digit via the DATA lea~1 to FIFO 40 during the partieular seleetor eycle requested for maintenanee by the processor. T~lis data diyit is then transmitted via sense word 52 to the proeessor, as if it was colleeted fram the eorresponding reeeiver. The proeessor then analyzes the digit to determine whether a fault in the DRSC logie exists and the nature of a fault for any bit failure in the pattern transmitted. As a result, the transmission operation of data for each DTMF receiver channel may be tested. I'he ne~t seleetor eyele will oeeur as a typieal aeeess to a reeeiver.
Although the preferred embodiment of the in~ention has been illustrated, and that form described in detail, it will be readily apparent to those skilled in the art that various modifieations may be made therein without departing from ~he spirit of the invention or fram the scope of the appended elaims.
The present inven-tlon pertains to a data acquisi-tion arrangement for a telecommunications switching system and more particularly to an arrangement for collec-ting and transmittiny customer data for identification, validation and billing of special features such as calling card sel~ices.
With the popularization of placing telephone calls via credit cards, exis-ting telecammunication switching systems require m~difications to provide -this function to custom~rs. Cus-tomer identification is required for billing purposes. Further, a validity code is re~uired to insure that the credit card is being pro~erly used.
This data must be collected in an on-line fashion.
m at is, before the switching system may complete the call, the customer must transmit the required informatlon to the switching system via his station equiE~ent. The customer is supplied with a request signal mdicating that the switching system requires this information. The customer then responds with a series of numbers via the DTMF keypad with the required identification, billing and validity data. The switching system must then collect this information; transmitted to its central processing unit; and, analyzes the in~orn~ation for proper handling of the telephone call. If a valid call has been ~nitiated by the cust~mer, the system will respond by connecting his caLl.
Accordingly, systems which were previously designed and did not originally incorporate this feature, must be supplemented to provide this capability. The present invention is a mcdular addition for such a telecGmmNnications system which provides the data acquisition and transmission for special features such as calling card service.
SUMM~RY OF THE INVENTION
In a teleccmmunications switching system which has a network clock, a DTMF receiver arrangement is connected to a number of DTMF receivers. mese DTMF receivers interface between ~ 'f ~kS~38 custamers and the switching system for transmitting data to the switching system. The DTMF receiver arrangement is also connected to a processor of the switching system.
The DTMF receiver arrangement includes control points which are connected to the processor and operate to store and transmit DTMF receiver data to and frQm the processor. Sense points are connected to the processor and operate to store data for transmission to the processor.
A sequencing circuit is connected to the network clock.
m e sequencing circuit operates in response to the network clock to produce a number of regularly defined time slots for samplin~
DIMF receivers during a complete DIMF receiver sampling cycle.
The D~ receiver c~rrangement also includes last look circuitry. The last look circuitry is connected to the DTMF
receivers, to the seq~encing circuit and to the netw~rk clwk.
The last look circuit cyclically operates during each time slot in response to the sequencing circuit to produce and to store an indication of whether a particular DTMF receiver has been previously sa~led for valid data during the current DTMF receiver sampling cycle.
A generating circuit is connected to the control points, to the last loo~ circuit and to the sequencing circuit.
me generating circuit operates in response to an indication of said last look circuit that the particular DTME' receiver has previously been sampled during the current sampling cycle. As a result, the generatIng circuit operates to inhibit production of a write signal which all~s valid data to be stored. The generating circuit also operates in response to an indication that of the last look circuit, that the particular DTMF receiver of this ti~e slot has not been previously sampled during the current DTMF
receiver sampling cycle. In response to this indication, the generating circuit produces a write signal which enables valid data to be stored. The last look circuitry also stores ~he new sampling indication.
53~3 A storage device is connected to the DTMF receivers for storing valid receiver data. In addition, the storage device is also connected to the se~uencing circuit, to the generating circuit and to the sense points. me storage device operates in response to the write signal of the generating circuit to store data frcm a particular ~IMF receiver during the corresponding time slot. me storage device also operates to transmit the stored data of each DTMF receiver to the sense point for retransmission to the processor of the switching system.
A B~IEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram of a DTMF receiver sense and control arrangement for a telecommunications switching system.
Figure 2 is a schematic diagram of the control logic for the DTMF receiver sense and control arrangement of the present invention.
DESCRIPTION OF I~E PREFER~ED EMBODIMENT
Referring to Figure 1, a block diasratn of the DTMF
receiver sense and control ærangement is shown. m e DTMF
receiver sense and control (DRSC) arrangement is connected to the switching system's processor via a tri-state bus. The processor interfaces to the DRSC by operating three control pomt words ~50, 51, 53) and one sense point word (52). Word 52 is a sense word.
Words 50, 51 and 53 æe control words. Sense words may onl~ be read from by the processor, whereas control words may be written to or read from by the processor. The DRSC may read and write both sense and control words. Each of the sense and control words and the corresponding tri-state bus is 32 bits wide however, this design is not limlted to a 32 bit implementation.
DTMF receivers 1 through 24 are connected between and the timing, synchronization and control logic 99. m is DRSC
arrangement may monitor up to 24 such DTMF receivers. me timing, synchronization and control logic 99 is also connected to a network clock ~not shown) which operates at a frequency 8 khz.
Logic 99 is connected to the network clcck via the LTS 192 lead.
DTMF receivers 1 through 24 are connected to the logic 99 via the ~Z~S38 data/flags bus. The data/fLags bus is 4 bits wide. Logic 99 selectively exa~ines each of ~le 24 DIMF receivers. In order to connect the logic 99 to one of the Dq~ receivers. I`he MMF
receivers are accessed by a 5 bit address bus.
In addition, channel initiali~ation hardware is connected between each of the 24 DTMF receivers and control word 50. The channel initialization hardware 30 is also connected to the logic 99 via INITCOMP lead.
Control words 50, 51 and 53 are connected to logic sense word 52 is connected to FIFO 40 which is turn connected to logic 99. m e fact that the DTMF receivers 1 through 24 are packaged four per printed wiring card is important to further understanding of the present invention. The processor transmits an indication via the tri-state bus to control ~ord 50. mis indication determines which group of 4 DIME' receivers on a particular printed wiring card is to be initialized. mese indications are stored and control word 50 and transmitted to the channel initialization hardware 30 in response to this transfer.
Channel initialization hardware 30 addresses the particular printed wiring card of DqMF receivers indicated by control word 50 and initializes these receivers for a transmission of customer data to the logic 99. When the initialization of the DIMF
receivers is ccmplete, a signal is transmitted from the channel initialization hardware 30 via the INITCCMP lead to the logic 99.
Next, the processor indicates to the logic 99 which of the 24 DTMF receivers have been initiali~ed and are ready for use by the call processing function. To acccmplish this, the processor sets bits and control word 51 which correspond to those DTMF receivers which have been initialized. The purpose of the DRSC circuitry is to provide a means for collecting customer data, so that, this data may be processed by an off-line data processing system for validating and billing custcmers for special service such as, credit card calls. m e data is taken by the logic 99 at a particular rate. m e DrDMF ch.~nnel will hold customer data valid for approximately 45 milliseconds. m e logic 99 access each Dl~
53~3 channel once every 24 milliseconds to guarantee that the customer data is accessecl while the data is .stcible. Each one millisecond access interval of a receiver is broken up into two intervals each of 0.5 milliseconds. Duriny the first interval, ]ogic 99 examines a flag to determine whether the particular receiver is transmitting a valid digit. During the second interval, logic 99 removes the data digit from the receiver and stores it in FIFO 40.
Each data word stored in FIFO 40 will also contain a corresponding 5 hit address of the particular DTMF receiver from which the data originated.
When the processor requires the customer data FIFO 40 has unlocked one data word containing the channel address and the DTMF data into sense word 52. me processor will read this word from sense word 52 and store it in the processors memory.
In addition, the processor may indicate to logic 99 that it is to receive a particular data word via control word 53 for maintenance purposes. The processor will transmit this data word via the tri-state bus to control word 53. Logic 99 will remove this data word from the control word 53 and insert it into the data being sent back to the processor through FIFO 40 at the appropriate ti~e. The processor will read this data via the sense word 52 and determine whether the word read compares to the word the processor transmitted, thereby indicating a fault in the DRSC
circuitry.
The DTMF receivers or channels are connected to FIFO 40 via the data/flags 4 bit bus. Control word 51 of Figure 1 is connected to AND gate 161 via the RCVR ON lead. On each cycle of the DRSC clock, an indication is transmitted via this lead. This indication determines whether the particular receiver to be examined in this time slot is active. me processor sets bits in ~rd 51 corresponding to each one of the 24 receivers which is active. Therefore, the DRSC will send data to the processor ~or only those receivers which are active.
The L~S192 signal, which is an 8 ~h~ frequency, and the MCLK2 signal are transmitted from the net~Drk clock of the 3~3 switching system to AND gate 100 via corresponding leads. AND
gate 100 is comlected to clivide by four circuit 101. Divide by four circuit 101 is connected to selector 105, which is a modulo 48 circuit, providing for a set of output signals which indicate 48 equal time periods. In addition, divide by four circuit 101 is connected to D-type flip-flop 125 and to N~ND gate 146.
Selector 105 is connected via a number of output leads to decoder 110. Decocler 110 provides a plurality of signals via the CEN O through CEN 5 leads. These leads are connected to the six DTMF receiver printed wiring cards. Each DTMF receiver printed wiring card contains Pour DTMF receiver circuits.
Selector 105 produces three other signals on the A, B
and C leads. The A and B leads along with the three other signals, which produce the DqMF receiver printed wiring card enables, represent the identity of the particular DTMF channel for which the DRSC is currently processing data. These leads containing the chalmel number are connected to comparator 180 and to FIFO 40. When a digit of custcmer data is transmitted to the processor of the switching system, the channel number (DTMF
receiver identity) which produced this digit is also simultaneously transmitted.
The data/flags bus is connected to the D input of flip-flops 141 through 144. Inverted copies of the A, B and C
signals are prcduced by gates 112, 113 and 111 respectively.
Gates 112 and 113 are connected to decoder 130~ Since the A and B
signals are the lcw to order bits of the channel nu~ber, their deccde by decoder 130 produces an indication of which one of the four DTMF receivers on a particular printed wiring card is currently being interrogated for data.
Decoder 130 is connected to NOR gates 131 through 134.
~OR gates 131 through 134 are connected to the clock input of D-type latches 141 through 144, respectively. N~ND gate 126 is connected to D-type latch 125 and to gate 111. The output of N~ND
gate 126 is connected as an enabling signal to NOR gates 131 throl~gh 134. ~AND gate 146 and decoder 130 are each connected to 53~3 NOR gate 147. NOR gate 147 and the network clock via the l.~S192 lead are connected to NOR gate 149. NOR gate 1~9 is connected to the ~rite enable of the last look memory 150.
D-type flip-^flop 125 and gate 111 are connected to NAND
gate 127, which is also connected to AND gate 128. Demultiplexer 160 and gate 161 are connected to OR gate 162, which in turn is connected to AND gate 128. AND gate 128 is connected via the WRITE FIFO lead to FIFO 40. The slgnal on this lead enables FIFO
40 to receiver and store valid data digits frcm each of the receivers at the appropriate time intervals.
The outputs of selector 105, which are decoded for the DTMF receiver prin~ed wiring cards, are connected to last look memory 150 as an address. m e outputs of D-type latches 141 through 144 are connected as the data inputs to last look memory 150. mese four inputs represent the four DTMF receivers on a particular printed wiring card. Onlv one of the four DTMF
receivers on a particular printed wiring card will be responding during a particular DRSC clock interval. The outputs of last look memory 150 are connected to AND gates 151 through 154. In addition, the output of D~type flip-flops 141 through 144 æe respectively connected to AND gates 151 through 154. m e output of AND gates 151 through 154 æe connected to demultiplexer 160.
Demultiplexer 160 is also connected to gates 112 and li3. The RCVR ON lead fxom word 51 of Figure 1 is connected as an enabling signal to demultiplexer 160.
The output of FIFO 40 is connect~d via a 9 bit bus to sense word 52 fGr transmission to the processor of the custcmer digits.
For a maintenance access of the DRSC circuitry, the processor sets an indication in control word 53 of Figure 1.
Control word 53 is connected via the MAINT ACOE SS lead to D-type latch 170. NPND gate 166 is connected to the clock input of latch 170. The maintenance function of the processor inserts a particular digit word into the stream of digits transmitted from the DRSC to the processor. The processor then reads back the appropriate receiver digit and determines, whether the digit receivecl corresponds to the digit transmitted. The processor transmits the maintenance digit to control word 53 of Figure 1.
Control word 53 is connected via a 4 bit bus to latch 185.
Flip-flop 170 is connected to comparator 180.
Comparator 180 is also connected to word 53 of Figure 1 via the MPINT REG CHANNEL # lead for receiving the maiNtenance channel identity nu~ber. Cc~p æ ator 180 is connected to N~ND gate 181.
NPND gate 181 is also connected to gate 111. The output of N~ND
gate 181 is connected to the enable of decoder 110 and to the enable of latch 185. me output of latch 185 is coNnected via the 4 bit input DATA bus to FIFO 40. In addition, ccmparator 180 is connected to the input of AND ga-te 161.
Two clock signals from the network elock (LTS192 and MCLK2) are ccmbined by AND gate 100 and transmitted to divide by four cireuit 101. Divide by four cireuit 101 produces a signal on the CRY lead which is transmitted to selector 105. Selector 105 produces all the timing signals necessary for operation of the DRSC logic. The DRSC counts modulo 48 and produces a numker of signals during each one of the 48 intervals. m ree of the signals produced by selector 105 are the high order 3 bits of the channel number, which is the identity of the current DTMF receiver to be processed by the DRSC cireuitry. These signals are transmitted to deeoder 110. Decoder 110 produces card enables CEN 0 through CEN
5. The A and B signals of selector 105 are the two low order bits of the channel number. me opposite sense of the A and B signals is produced by NAND gates 112 and 113, respectively. Both senses of these signals are used throughout the circuit.
me signal procluced on the C lead indicates which half cycle of 48 cycles of selector 105 is currently in progress.
During the first half of each selector cycle, the C lead is at logic 0 and flags from a particular printed wiring card of receivers are gated to latches 141 through 144 for determination of whether a valid digit e~ists for the corresponding receivers.
Although, during this selector cycle, one of the card enables CEN
~Z~3~3 signals enables one particular printed wiring card containing four DTMF receivers, only one of the receivers has me~mingful data.
D~lring the selector half cycle when the C signal is at logic 1, valid data appears on the data/flag bus from the particular receiver. This data is gated into FIFO 40.
A total of 4~ selector cycles was chosen because data is available and stable at the receiver for 45 milliseconds. It takes approximately 1 millisecond to process each receiver therefore, 24 receivers may be processed in 24 milliseconds. The 24 millisecond co~mt of selector 105 guarantees that each receiver will be serviced while it has valid and stable data. Also, each receiver may be examined a second time.
When the CRY signal is clocked, flip flop 125 latches this signal and provides and enabling signal to NOR gates 131 through 134 via gate 126. m e two low order bits of the channel address IA and B) are decoded by decoder 30 to select which one of the four receivers on a particular printed wiring card is currently operating in this clock cycle. Decoder 130 then operates the corresponding gate 131 through 134, which latches a flag in one of the flip-flops 141 through 144, corresponding to the particular one of four receivers which is enabled during this clock cycle. When a flag is set in last look memory 150, it indicates that on the previous examination of that receiver, a valid digit was collected from that receiver.
Since each receiver is examined twice within a 48 millisecond time period, the same digit may be seen twice. In order to circumwent this problem, the value of the flag stored in flip-flops 141 through 144 is anded with the value contained for that receiver in the last look m~mory 150, by AND gates 151 through 154, respectively. This produces the CHOK 0 through CHOK
3 signals. The CHOK 0 - CHOK 3 signals are then input to demultiplexer 160. Demultiplexer 160 is enabled as a function of the RCVR ON signal, whenever a particular receiver is active. In addition, demultiplexer 160 decodes the two low order bits of the channel address A and B in order to select the appropriate one of t L?~ 3 ~B
four last look values. Demultiplexer 160 then procluces a signal, which it transmits to gate 128 to produce the WRITE FIFO signal, which causes FIFO 40 to store the presellt value of the data/flags bus. The data on the data/flag bus will be stored, if the value of the last look for that particular receiver is 0, however, if the last look value for that particular receiver was 1, indicating that it had been sampled within the previous 24 millisecond interval, the WRITE FIFO signal will be inhibited and data will not be stored into FIFO 40. When this cycle has been repeated for the other three receivers on the printed wiring card currently being examined, the contents of latches 141 through 144 are stored in the last look memory 150 via the signal from gate 149, which occurs once every four clock cycles of selector 105, transmitted to the WE input of last book memory 150. me flags are wl-itten into last look memory 150 as a function of the high three order bits of the channel address produced by selector 105.
FIFO 40 continuously presents the first data which it received and transmits this data to sense word 52 of Figure 1.
When the processor initiates a read of sense word 52, the next oldest word contained in FIFO 40 is transmitted to sense word 52.
In this way, the processor may cyclically retrieve a data dlgit for each of the 24 DTMF receivers.
For a maintenance access, the processor transmits to control word 53 a bit (MAINT ACOESS), which indicates that a maintenance access is requested, and the identity of the DTMF
chamlel ~channel number~ in which to insert a predefined data digit. In addition, the processor transmits the maintenance digit to control word 53. Control word 53 writes the maintenance digit into latch 185 via the MAINT DATA bus, which is a 4 bit bus.
Latch 185 stores the maintenance digit, until such time as it is required for insertion into the digit stream transmitted to the processor via sense word 52. me data input to flip-flop 170 is permanently set at logic 1 and the M~INT ACOE SS signal causes flip-flop 170 to produce a signal for operating comparator 180.
53!3 Comparator 180 compares the maintenance channe] num~er transmitted by the processor w:ith the current ehannel number produced by selector 105. Ebr comparlson of the two channel numbers, the SEL MAINT signal is produced by eomparator 180, which indicates that the eurrent ehannel cycle is the one for which the maintenanee digit is to be transmitted. The SEL MAINT signal is transmitted to gate 161 which causes gate 166 to reset the maintenance request to eamparator 180 for the next selector cyele.
In addition, the SEL MAINT signal operates NAND gate 181 to disable deeoder 110 fro~ produeing eard enables CEN O through CEN
5, while simultaneously enabling lateh 185. Lateh 185, when enabled, transmits the 4 bit digit via the DATA lea~1 to FIFO 40 during the partieular seleetor eycle requested for maintenanee by the processor. T~lis data diyit is then transmitted via sense word 52 to the proeessor, as if it was colleeted fram the eorresponding reeeiver. The proeessor then analyzes the digit to determine whether a fault in the DRSC logie exists and the nature of a fault for any bit failure in the pattern transmitted. As a result, the transmission operation of data for each DTMF receiver channel may be tested. I'he ne~t seleetor eyele will oeeur as a typieal aeeess to a reeeiver.
Although the preferred embodiment of the in~ention has been illustrated, and that form described in detail, it will be readily apparent to those skilled in the art that various modifieations may be made therein without departing from ~he spirit of the invention or fram the scope of the appended elaims.
Claims (19)
1. In a telecommunications switching system having a network clock, a DTMF receiver arrangement is connected between a plurality of DTMF receivers, which transmit customer data to said switching system, and a processor of said switching system, said DTMF receiver arrangement comprising:
control means connected to said processor, said control means being operated to store and to transmit data from said processor and to said processor;
sense means connected to said processor, said sense means being operated to store data and to transmit said stored data to said processor;
sequencing means connected to said network clock, said sequencing means being operated in response to said network clock to produce a plurality of regularly defined time slots during a DTMF receiver sampling cycle;
last look means connected to said plurality of DTMF
receivers, to said sequencing means and to said network clock, said last look means being cyclically operated during each said time slot in response to said sequencing means cyclically to produce and to store an indication of whether a particular DTMF
receiver has been previously sampled for valid data during a current DTMF receiver sampling cycle;
generating means connected to said control means, to said last look means and to said sequencing means, said generating means being operated in response to said indication of said last look means that said particular DTMF receiver has been previously sampled during said current DTMF receiver sampling cycle, to inhibit production of a write signal and said generating means being further operated in response to an indication of said last look means that said particular DTMF receiver is to be sampled during a corresponding time slot of said current DTMF receiver sampling cycle, to produce said write signal; and storage means connected to said plurality of DTMF
receivers, to said sequencing means, to said generating means and to sense means, said storage means being operated in response to said write signal to store said data from a particular DTMF
receiver during said corresponding time slot and said storage means being further operated to transmit said stored data of each DTMF receiver to said sense means for retransmission to said processor.
control means connected to said processor, said control means being operated to store and to transmit data from said processor and to said processor;
sense means connected to said processor, said sense means being operated to store data and to transmit said stored data to said processor;
sequencing means connected to said network clock, said sequencing means being operated in response to said network clock to produce a plurality of regularly defined time slots during a DTMF receiver sampling cycle;
last look means connected to said plurality of DTMF
receivers, to said sequencing means and to said network clock, said last look means being cyclically operated during each said time slot in response to said sequencing means cyclically to produce and to store an indication of whether a particular DTMF
receiver has been previously sampled for valid data during a current DTMF receiver sampling cycle;
generating means connected to said control means, to said last look means and to said sequencing means, said generating means being operated in response to said indication of said last look means that said particular DTMF receiver has been previously sampled during said current DTMF receiver sampling cycle, to inhibit production of a write signal and said generating means being further operated in response to an indication of said last look means that said particular DTMF receiver is to be sampled during a corresponding time slot of said current DTMF receiver sampling cycle, to produce said write signal; and storage means connected to said plurality of DTMF
receivers, to said sequencing means, to said generating means and to sense means, said storage means being operated in response to said write signal to store said data from a particular DTMF
receiver during said corresponding time slot and said storage means being further operated to transmit said stored data of each DTMF receiver to said sense means for retransmission to said processor.
2. A DTMF receiver arrangement as claimed in claim 1, wherein there is further included initialization means connected to said control means and to each of said plurality of DTMF
receivers, said initialization means being operated to reset each of said DTMF receivers in response to an indication from said processor via said control means.
receivers, said initialization means being operated to reset each of said DTMF receivers in response to an indication from said processor via said control means.
3. A DTMF receiver arrangement as claimed in claim 2, said control means including a plurality of control point words; a first control point word is connected to said initialization means and operates to transmit the identity of each DTMF receiver to be reset to said initialization means; and a second control point word is connected to generating means and operates to indicate whether a particular receiver is operative.
4. A DTMF receiver arrangement as claimed in claim 3, said sense means including at least one sense point word connected between said processor and said storage means.
5. A DTMF receiver arrangement as claimed in claim 4, said sequencing means including:
first gating means connected to said network clock;
dividing means connected to said first gating and being operated in response to signals of said network clock to produce a counted down signal; and selecting means connected to said dividing means and to said first gating means and said selecting means being operated in response to said counted down signal to cyclically produce a plurality of channel number output signals and a half cycle output signal during each of a predefined number of regular time slots.
first gating means connected to said network clock;
dividing means connected to said first gating and being operated in response to signals of said network clock to produce a counted down signal; and selecting means connected to said dividing means and to said first gating means and said selecting means being operated in response to said counted down signal to cyclically produce a plurality of channel number output signals and a half cycle output signal during each of a predefined number of regular time slots.
6. A DTMF receiver arrangement as claimed in claim 5, said sequencing means further including:
second gating means connected to said selecting means and being operated in response to said half cycle output signal and certain of said plurality of channel number output signals to produce an inverted sense of said half cycle and of said certain output signals; and first decoding means connected to said selecting means and to said plurality of DTMF receivers, said first decoding means being operating in response to another group of said plurality of channel number output signals to selectively enable certain groups of said DTMF receivers to transmit said data.
second gating means connected to said selecting means and being operated in response to said half cycle output signal and certain of said plurality of channel number output signals to produce an inverted sense of said half cycle and of said certain output signals; and first decoding means connected to said selecting means and to said plurality of DTMF receivers, said first decoding means being operating in response to another group of said plurality of channel number output signals to selectively enable certain groups of said DTMF receivers to transmit said data.
7. A DTMF receiver arrangement as claimed in claim 6, said last look means including:
second decoding means connected to said selecting means via said certain ones of said plurality of channel number output signals, said second decoding means being operated in response to said certain channel number signals to produce an indication of for sampling one of a plurality of DTMF receivers during a particular time slot;
third gating means connected to said decoding means and to said selecting means, said third gating means being operated in response to said half cycle signal to produce an enable flag signal for said one DTMF receiver of said particular time slot;
and first latching means connected to said plurality of DTMF receivers and to said third gating means and being operated in response to said enable flag signal to store a flag signal of said particular DTMF receiver indicating whether said DTMF
receiver has valid data to transmit.
second decoding means connected to said selecting means via said certain ones of said plurality of channel number output signals, said second decoding means being operated in response to said certain channel number signals to produce an indication of for sampling one of a plurality of DTMF receivers during a particular time slot;
third gating means connected to said decoding means and to said selecting means, said third gating means being operated in response to said half cycle signal to produce an enable flag signal for said one DTMF receiver of said particular time slot;
and first latching means connected to said plurality of DTMF receivers and to said third gating means and being operated in response to said enable flag signal to store a flag signal of said particular DTMF receiver indicating whether said DTMF
receiver has valid data to transmit.
8. A DTMF receiver arrangement as claimed in claim 7, said last look means further including:
second latching means connected to said dividing means;
and fourth gating means connected to said selecting means, to said third gating means and to said second latching means, said fourth gating means being operated in response to said half cycle signal to enable said third gating means.
second latching means connected to said dividing means;
and fourth gating means connected to said selecting means, to said third gating means and to said second latching means, said fourth gating means being operated in response to said half cycle signal to enable said third gating means.
9. A DTMF receiver arrangement as claimed in claim 8, said last look means further including fifth gating means connected to said dividing means, to said selecting means, to said second decoding means and to said network clock, said fifth gating means being operated to produce a memory write enable signal during each fourth time slot.
10. A DTMF receiver arrangement as claimed in claim 9, said last look means further including memory means connected to said selecting means, to said fifth gating means and to first latching means, said memory means being operated in response to said memory write enable signal to store said DTMF receiver flag signals for a predefined number of DTMF receivers.
11. A DTMF receiver arrangement as claimed in claim 10, said last look means further including sixth gating means connected to said memory means and to said first latching means, said sixth gating means being operated to produce channel data stored signals for each of said predefined number of DTMF
receivers, indicating whether valid data has been processed for a particular DTMF receiver during a time slot of a preceding DTMF
receiver sampling cycle.
receivers, indicating whether valid data has been processed for a particular DTMF receiver during a time slot of a preceding DTMF
receiver sampling cycle.
12. A DTMF receiver arrangement as claimed in claim 11, said generating means including demultiplexing means connected to said sixth gating means, to said DTMF receiver being sampled during the current time slot and to said selecting means, said demultiplexing means being operated in response to said channel data stored signal to produce a storage enable signal.
13. A DTMF receiver arrangement as claimed in claim 12, said generating means including seventh gating means connected to said demultiplexing means, to said selecting means, to said second latching means and to said second control point word and being operated in response to said storage enable signal to produce a write FIFO signal.
14. A DTMF receiver arrangement as claimed in claim 13, said storage means including buffering means connected between said particular DTMF receiver of said current time slot and said sense point word and said seventh gating means, said buffering means being operated in response to said write FIFO signal to store said DTMF received data during said time slot and said buffering means being further operated to transmit a first data of said data stored to said sense point word.
15. A DTMF receiver arrangement as claimed in claim 14, said buffering means further connected to said selecting means and being operated in response to said channel number signals to store said channel number signals corresponding to each said DTMF
receiver data and said buffering means being further operated to transmit said stored channel number signals with said transmitted receiver data to said sense point word.
receiver data and said buffering means being further operated to transmit said stored channel number signals with said transmitted receiver data to said sense point word.
16. A DTMF receiver arrangement as claimed in claim 15, said buffering means including a first in first out device for transmitting said data received to said processor in an order in which said first in first out device received said data.
17. A DTMF receiver arrangement as claimed in claim 16, said dividing means including a divide by four circuit.
18. A DTMF receiver arrangement as claimed in claim 17. said selecting means including a modulo forty-eight selector circuit.
19. A DTMF receiver arrangement as claimed in claim 18, said memory means including random access memory means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/685,198 US4611325A (en) | 1984-12-21 | 1984-12-21 | DTMF receiver sense and control arrangement |
| US685,198 | 1984-12-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1244538A true CA1244538A (en) | 1988-11-08 |
Family
ID=24751146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000496967A Expired CA1244538A (en) | 1984-12-21 | 1985-12-05 | Dtmf receiver sense and control arrangement |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4611325A (en) |
| CA (1) | CA1244538A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4757508A (en) * | 1987-12-07 | 1988-07-12 | The Grass Valley Group, Inc. | Tracking modulation limiter for lasers |
| SE501156C2 (en) * | 1993-04-21 | 1994-11-28 | Ellemtel Utvecklings Ab | Reference signal composed of clock signal and synchronization signal, synchronization device and method, etc. reference signal |
| DE19609233B4 (en) * | 1996-03-09 | 2005-09-01 | Deutsche Telekom Ag | Method for generating a control signal in a pulse dialing method for a public exchange |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4219699A (en) * | 1978-10-13 | 1980-08-26 | Wescom, Inc. | Telephone supervision system using DTMF signals |
| US4203008A (en) * | 1979-02-26 | 1980-05-13 | Northern Telecom Limited | Digital signalling receiver for receiving PCM tones |
| IT1154048B (en) * | 1981-06-09 | 1987-01-21 | Urmet Sud Costr Elett Telefon | IMPROVEMENT OF SYSTEMS AND EQUIPMENT FOR PUBLIC TELEPHONE USING INTER-URBAN URBAN EQUIPMENT EQUIPPED WITH SELECTOR |
| IL63707A (en) * | 1981-09-01 | 1984-05-31 | Israel Electronics Corp | Tasi apparatus for use with systems having interregister multifrequency signalling |
| US4439636A (en) * | 1982-03-09 | 1984-03-27 | Martha Newkirk | Credit card actuated telecommunication access network |
-
1984
- 1984-12-21 US US06/685,198 patent/US4611325A/en not_active Expired - Fee Related
-
1985
- 1985-12-05 CA CA000496967A patent/CA1244538A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4611325A (en) | 1986-09-09 |
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