CA1246232A - Intermeshed resistor network for analog to digital conversion - Google Patents
Intermeshed resistor network for analog to digital conversionInfo
- Publication number
- CA1246232A CA1246232A CA000501607A CA501607A CA1246232A CA 1246232 A CA1246232 A CA 1246232A CA 000501607 A CA000501607 A CA 000501607A CA 501607 A CA501607 A CA 501607A CA 1246232 A CA1246232 A CA 1246232A
- Authority
- CA
- Canada
- Prior art keywords
- coarse
- fine
- network
- segments
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/145—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages
- H03M1/146—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages all stages being simultaneous converters
- H03M1/147—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages all stages being simultaneous converters at least two of which share a common reference generator
- H03M1/148—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages all stages being simultaneous converters at least two of which share a common reference generator the reference generator being arranged in a two-dimensional array
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
- H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
- H03M1/365—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string
Abstract
INTERMESHED RESISTOR NETWORK FOR ANALOG
TO DIGITAL CONVERSION
Abstract of the Disclosure In an A/D converter a resistive network produces 2n different voltage steps. The resistive network includes a coarse relatively low impedance resistive string which is subdivided into 2x coarse segments. The resistive network also includes a fine relativley high impedance resistive string comprised of one fine resistive element per each coarse segment. Each fine resistive element in the string is then subdivided into 2(n-x) fine sub-segments. In determining the value of an input voltage being sensed, all the coarse segments are used to sense which coarse segments brackets the input voltage. However, only that one fine segment, which is in parallel with the ''bracketing'' coarse resistor, is then coupled to comparator means to sense which of the fine element sub-segments brackets the input voltage.
TO DIGITAL CONVERSION
Abstract of the Disclosure In an A/D converter a resistive network produces 2n different voltage steps. The resistive network includes a coarse relatively low impedance resistive string which is subdivided into 2x coarse segments. The resistive network also includes a fine relativley high impedance resistive string comprised of one fine resistive element per each coarse segment. Each fine resistive element in the string is then subdivided into 2(n-x) fine sub-segments. In determining the value of an input voltage being sensed, all the coarse segments are used to sense which coarse segments brackets the input voltage. However, only that one fine segment, which is in parallel with the ''bracketing'' coarse resistor, is then coupled to comparator means to sense which of the fine element sub-segments brackets the input voltage.
Description
12~ 3~
-1- RCA 81,842 INTERMESHED RESISTOR NETWORK FOR ANALOG
TO DIGITAL CONVERSION
This invention relates to analog-to-digital (A/D) converters and, in particular, to means for generating a wide range of reference voltage steps particularly useful in A/D converters.
In the following description, reference is made to the accompanying drawings, in which like reference characters denote like components, and in which:
FIGURE 1 is a partial schematic, partial block diagram of a prior art analog-to-digital converter;
FIGURE 2 is a partial schematic, partial block, diagram of an analog-to-digital converter embodying the invention;
FIGURE 3 is a detailed schematic diagram of a course resistor segment connected in parallel with a fine resistive element in accordance with the invention;
FIGURE 4 is a top view of an elongated diffusion region used to form a "fine" resistive element in accordance with the invention;
FIGURE 5 is a detailed schematic diagram of an integrated "fine" resistive element embodying the invention;
FIGURE 6 is a schematic diagram of a comparator circuit useful in practicing the invention; and FIGURE 7 is a schematic diagram of a section of a resistor network for prGducing fractional values of the voltages being sensed.
In a prior art 8-bit "flash" A/D converter, shown in FIGURE l, a wide range of reference voltage steps is obtained by connecting a tapped resis-tive network across a reference voltage and by making contacts ~taps) at known ohmic increments along the resistive network. The number of increments, or steps, and hence the number of taps along the resisti.ve network is a function of the number of bits of resolution re~uired. In general, for an "n"-bit system 2n sub-reference steps are generated. Thus, in an "8-bit"
3~
-1- RCA 81,842 INTERMESHED RESISTOR NETWORK FOR ANALOG
TO DIGITAL CONVERSION
This invention relates to analog-to-digital (A/D) converters and, in particular, to means for generating a wide range of reference voltage steps particularly useful in A/D converters.
In the following description, reference is made to the accompanying drawings, in which like reference characters denote like components, and in which:
FIGURE 1 is a partial schematic, partial block diagram of a prior art analog-to-digital converter;
FIGURE 2 is a partial schematic, partial block, diagram of an analog-to-digital converter embodying the invention;
FIGURE 3 is a detailed schematic diagram of a course resistor segment connected in parallel with a fine resistive element in accordance with the invention;
FIGURE 4 is a top view of an elongated diffusion region used to form a "fine" resistive element in accordance with the invention;
FIGURE 5 is a detailed schematic diagram of an integrated "fine" resistive element embodying the invention;
FIGURE 6 is a schematic diagram of a comparator circuit useful in practicing the invention; and FIGURE 7 is a schematic diagram of a section of a resistor network for prGducing fractional values of the voltages being sensed.
In a prior art 8-bit "flash" A/D converter, shown in FIGURE l, a wide range of reference voltage steps is obtained by connecting a tapped resis-tive network across a reference voltage and by making contacts ~taps) at known ohmic increments along the resistive network. The number of increments, or steps, and hence the number of taps along the resisti.ve network is a function of the number of bits of resolution re~uired. In general, for an "n"-bit system 2n sub-reference steps are generated. Thus, in an "8-bit"
3~
-2- RCA 81,842 A/D converter system -- i.e., where "n" is equal to 8 --the reference voltage of the system is subdivided lnto 256 substantially equal voltage steps by taps connected at e~ual ohmic increments along a resistive network connected between VREF~ and VRE -. Each tap is coupled via a corresponding transmission gate, which is selectively enabled by means of a reference clock (CLREF) to a corresponding comparator. Thus, in the circuit of FIGURE
l, 256 comparators are needed. This large number of comparators requires much space and dissipates considerable power. In circuits embodying the present invention, the number of comparators is significantly reduced.
The manufacture of the prior art resistive network with a large number of taps presents several problems.
A first such problem is that, for proper operation, the total impedance of the resistive network must be made relatively small to prevent significant changes of the reference voltages at the various taps, when the taps are coupled via their associated transmission gates to the inputs of their associated comparators. Where the resistive network is formed on an integrated circuit, the need to make the resistive network a low impedance results in the resistive network being very large in area and occupying a substantial portion of the chip area.
A second problem is that the large number (e.g. 256) of subdivisions of a relatively small impedance re~uires that each subdivision be a proportionately smaller impedance. Where these small ohmic increments are in the range of several ohms or less, their values cannot be accurately controlled.
A further problem is that coupling the taps of the resistive network to the capacitive input of -the comparators causes significant loading and shifting of the reference voltages which is not uniform along the resistive network. The loading effect varies along the length of the resistive network being, typically, most pronounced at the extreme ends of the resistive network and least pronounced ~2~3~
_3_ RCA 81,842 at the center of the network. For example, when the input voltage (VIN) ls being sampled, the 256 comparator inputs are charged to the value of VIN. When the reference voltage taps are subsequently coupled to the comparator inputs, the 256 capacitive compartor inputs either discharge into the resistive network or draw charge from the resistive network. The greatest disparity occurs, of course, when VIN is at the extreme of its range, i.e. at, or close to, zero volts or at, or close to, 5 volts, and the perturbation on the resistive network is most pronounced at the top end of the resistive network for VIN
close to zero and at the bottom end of the resistive network for VIN close to VREF~.
The problems discussed above are aggravated when the circuit is operated at relatively high speeds. In this connection, a capacitor at the input of each comparator must be charged quickly to its associated reference voltage step (e.g. within 25 nanoseconds). To charge or discharge the capacitances quickly, the impedance of the resistive network must be kept low.
The difficulties discussed above are significantly reduced or overcome in circuits embodying the invention.
In an n-blt A/D converter embodying the invention, the tapped resistive network is comprised of a coarse, relatively low impedance resistive network connected to first and second terminals across which a source of reference voltage is connected. The coarse network is divided into 2x coarse segments for producing substantially equal ohmic increments. Accordingly, substantially equal 2x coarse steps of the reference voltage appear across respective coarse segmen-ts. The tapped resistive network also includes relatively high impedance network comprising 2x resistive fine elements.
Each fine network element is connected in parallel with a respective coarse segment, and is subdivided into 2(n x) fine sub~segments. The subsegments of each fine network element subdivide each of the 2x coarse voltage steps into -3a- RCA 81,8~2 2(n x) fine voltage steps. Within the A/D converter, the value of an input voltage may be determined by first sensing which of the coarse network segments brackets the input voltage and then comparing the input voltage with the fine reference voltage steps in the fine resistive element connected in parallel with that particular bracketing coarse network segment.
FIGURE 2 illustrates a configuration of an 8-bit "flash" A/D converter embodying the invention. The term "flash" normally refers to the fact that the analog-to-digital conversion or comparison is done in one step during one clock cycle. However, as detailed below, the circuit of FIGURE 2 may be termed a two-step "flash"
converter, with one step being used to determine the . _ . _ _ . .
:L2~6~3~
- 4 - RCA 81,842 1 "coarse" value of an input voltage (VIN) to its 4 most significant bits (MSB) and the second step being used to determine the "fine" value of VIN to its 4 least significant bits (LSB). The converter has been divided 5 into two 4-bit sections whose outputs are subsequently recombined to produce the desired 8-bits o~ inormation.
One 4-bit section is denoted as the "coarse" section and the other 4-bit section is denoted as the "fine"
section. The "coarse" section includes means for 10 subdividing the reference voltage into 24 "coarse"
reference segments and to sense which coarse segment brackets the unknown input voltage being sampled (or - measured). The "fine" section includes means for subdividing each 24 coarse segments into 2~ fine 15 sub-segments and to sense which fine sub-segment brackets the unknown input voltage being sampled. The coarse section includes a coarse resistor string 22 with 24 coarse taps (TCi) located at equal increments along the string, 24 transmission gates (TGCi) for coupling the 24 20 taps to 24 "coarse" comparators and a coarse logic array encoder 28. The "fine" section includes a fine resistor string 24 comprised of 24 segments with each segment further subdivided into 24 sub-segments with (24-1) fine taps formed between the 24 fine sub-segments. The fine 25 segment also includes (24-1) transmission gates per segment for coupling the (2~ -1) taps of a segment to the corresponding (24-1) fine comparators and a "fine" logic array encoder 30.
The coarse resistor element 22 may be formed by 30 connecting discrete resistive elements of equal value, connected-in series between VREF+ and VREF- with taps formed or connected at the junctions between the resistors. Also, a tap (e.g. TC16~ may be connected to the end of the resistor (e.g. R16) connected to VREF+.
35 Alternatively, the coarse resistor network 22 may be formed of a single resistor element connected between the negative reference voltage VREF- and the positive reference voltage VRE~+. Taps are formed or connected, at substantially equal ohmic increments along the coarse ~2~ 3~
- 5 - RCA 81,842 1 resistor element 22 to produce substantially equal voltage increments across the coarse segments located between each coarse tap. Consequently, the voltage increasing monotonically along the coarse resistor goes from the tap 5 closest to VREF- to the tap closest to VREF+.
The coarse resistor network 22 is a relatively low impedance resistance. By way of example, in the embodiment of FIGURE 2, the total impedance of network 22 REF and VREF- is approximately 500 ohms 10 Network 22 is divided into 16 (i.e. 24) coarse segments of substantially equal ohmic (e.g. approximately 30 ohms each) increments to produce 16 substantially equal reference voltage steps, which can be represented by 4 bits. In the discussion to follow, it is assumed, for 15 ease of illustration, that VREF- is ground and VREF~
is 6.4 volts. Thus, the volt3ge drop (~VC) across each coarse segment is 400 millivolts, with the voltage at a succeeding tap along the stack being 400 millivolts greater than the voltage at a preceding tap.
There are 16 "coarse" comparators (CCi), one comparator for each coarse tap along resistor network 22 including a sixteenth comparator for the tap to which VREF~ is applied. The sixteenth comparator senses an overflow condition, i.e. when VIN is greater than 25 VREE,I. In applications where it is not necessary to sense the overflow condition, the sixteenth comparator may be eliminated.
Corresponding to each coarse tap (TCi) on coarse resistor network 22 there is a coarse transmission gate (TGCi) for selectively coupling the coarse tap (TCi) to the reference input of its corresponding coarse comparator (CCi). The coarse comparators and the fine comparators may be of the same type as the comparator shown in FIGURE
6. However, other suitable comparators may be used 35 instead.
The outputs (OCCi) of the coarse comparators are applied to the coarse logic array decoder/encoder 28 which produces: 1) a coarse indication of the value of VIN;
and 2) control signals indicative of which coarse segment ., 12~23~
- 6 - RCA 81,842 1 brackets the input voltage being sampled. Logic arr3y decoder/encoder 28 may be of the type used in the ~A3300 and CA3308 integrated circuits manufactured by RCA Corp.
and described in dat3 sheet published by RCA Corp.
5 Alternatively, the decoder/encoder 28 may be any one of a number of known decoder/encoder arrangements capable of producing functions l and 2 noted above.
The fine resistor network 24 includes a relatively hi~h impedance resistance connected in parallel with the relatively low impedance coarse resistor 22 between VREF- and VREF+. Resistor network 24 is divided into 16 (e.g. 24) fine resistive elements (or fine segments) with each fine resistive element being connected in parallel with a corresponding coarse segment as shown in 15 FIGURE 3. Each fine resistive element is further subdivided into 24 (or 16) sub-segments to provide 24 (or 16) fine`reference voltage steps between each pair of "coarse" taps [TCi and TCi~l]. A fine tap ~Tfi) is connected, or formed, at the junctions of every two fine sub-segments of each resistive element resulting in 15 fine taps (Tfl through Tfl5) at which are produced 15 different fine reference voltage levels (Vfl throu~h Vfl5) between each pair of coarse taps. Thus, as shown in FIGURE 3, for each coarse segment there is a set of 15 fine reference taps (Tfi's) which are given an ascending order goin~ from Tfl to Tfl5 as the resistor network is ascended from node i to the next higher succeeding node (i+l). As for the case of the coarse resistor, each fine resistive element may be a single resistor string 30 connected between two coarse taps with fine taps connected, or formed, at substantially equal ohmic increments along the string. Alternatively, the fine resistive element may be formed of substantially equal "discrete" resistors connected in series.
The total ohmic value of the fine resistive element between a pair of coarse taps is typically lO0 times the ohmic value of the coarse resistor (Rc) connected between those two taps. By way of example, where the coarse value is approximately 30 ohms, the ohmic value of the fine ~z~
~ 7 - RCA 81,842 1 resistive element is 3200 ohms and the impedance between any two fine taps is approximately 200 ohms. Hence the voltage level at each coarse tap is primarily determined by the coarse resistance.
A signi~icant advantage of the circuit of the invention is that the fine resistor network 24 may be formed with relatively high impedance sections. The fine resistor network may thus be formed on an integrated circuit using relatively little space and dissipates considerable less power than the prior art circuitry.
A layout of a portion of a fine resistive element is shown in FIGURE 4. In the circuit of the invention, each fine resistive element is formed of an elongated N
diffusion and an elongated P diffusion which are essentially connected in parallel and which provide the required ohmic drops with extremely high packing density.
P and N transistors are formed along the elongated diffusion to divide the diffusion into substantially equal ohmic increments. The layout shows tabs extending from the diffusions. These tabs provide the taps along the diffusions and these tabs/taps also function as the source/drain regions of the fine transmission gate transistors coupling their respective taps to the reference input of their corresponding fine comparator.
The use of N and P diffusions connected in parallel provides some significant advantages. The input voltage, VIN, covers a dynamic range assumed, by way of example, to range between 0 and 6.4 volts. If a single MOS
transmission gate were used to connect a tap to a comparator, the transmission gate transistor in several instances would conduct in the source follower mode--producing an offset. Also since the gates are driven by oppositely phased clock signals, switching charge injection is approximately neutralized resulting in faster settling.
Therefore, were a single N diffusion or a single P
diffusion used to form the resistive element, a full (i.e.
complementary) transmission gate would have to be used to couple the full fine tap voltages to the comparators.
~, ~2~23~
- 8 - RCA 81,842 1 This would add another metal connection between the transmission gate and the N or the P-diffusion. This would make the wiring very difficult~ By parallelin~
equal N and P diffusions, the source/drain regions of the transmission gate transistors are at the same potential at each respective tap. As a result, the wiring is minimized and the full dynamic range of the reference voltage and the input voltage can be fully utilized.
The N and P elongated diffusions forming the fine resistive element also form the source/drain regions of the transmission gate transistors used to couple the "tapped" points on the fine resistive element to the corresponding fine comparators.
The schematic circuit representation of the layout of FIGURE 4 is shown in FIGURE 5. Note that when fscl goes low and fsci goes high that each sub-segment (e.g. RFNl) from the N-diffusion and its corresponding sub-segment from the P-diffusion (e.g. RFpl) are connected in parallel via their respective transmission gate transistors (TGfNl and TGfPl) to their corresponding fine comparator input (e.g. Fcl). Evidently analysis of the layout and the resulting schematic indicates that a very compact, low parasitic, and efficient layout has been produced.
There are 16 sets (TGfi) of fine transmission gates, each set being comprised of 15 transmission gates. Each set of fine tran~mission gates is enabled by a control signal (fsci) produced by coarse logic array 28. During operation of the A/D converter only one set of fine
l, 256 comparators are needed. This large number of comparators requires much space and dissipates considerable power. In circuits embodying the present invention, the number of comparators is significantly reduced.
The manufacture of the prior art resistive network with a large number of taps presents several problems.
A first such problem is that, for proper operation, the total impedance of the resistive network must be made relatively small to prevent significant changes of the reference voltages at the various taps, when the taps are coupled via their associated transmission gates to the inputs of their associated comparators. Where the resistive network is formed on an integrated circuit, the need to make the resistive network a low impedance results in the resistive network being very large in area and occupying a substantial portion of the chip area.
A second problem is that the large number (e.g. 256) of subdivisions of a relatively small impedance re~uires that each subdivision be a proportionately smaller impedance. Where these small ohmic increments are in the range of several ohms or less, their values cannot be accurately controlled.
A further problem is that coupling the taps of the resistive network to the capacitive input of -the comparators causes significant loading and shifting of the reference voltages which is not uniform along the resistive network. The loading effect varies along the length of the resistive network being, typically, most pronounced at the extreme ends of the resistive network and least pronounced ~2~3~
_3_ RCA 81,842 at the center of the network. For example, when the input voltage (VIN) ls being sampled, the 256 comparator inputs are charged to the value of VIN. When the reference voltage taps are subsequently coupled to the comparator inputs, the 256 capacitive compartor inputs either discharge into the resistive network or draw charge from the resistive network. The greatest disparity occurs, of course, when VIN is at the extreme of its range, i.e. at, or close to, zero volts or at, or close to, 5 volts, and the perturbation on the resistive network is most pronounced at the top end of the resistive network for VIN
close to zero and at the bottom end of the resistive network for VIN close to VREF~.
The problems discussed above are aggravated when the circuit is operated at relatively high speeds. In this connection, a capacitor at the input of each comparator must be charged quickly to its associated reference voltage step (e.g. within 25 nanoseconds). To charge or discharge the capacitances quickly, the impedance of the resistive network must be kept low.
The difficulties discussed above are significantly reduced or overcome in circuits embodying the invention.
In an n-blt A/D converter embodying the invention, the tapped resistive network is comprised of a coarse, relatively low impedance resistive network connected to first and second terminals across which a source of reference voltage is connected. The coarse network is divided into 2x coarse segments for producing substantially equal ohmic increments. Accordingly, substantially equal 2x coarse steps of the reference voltage appear across respective coarse segmen-ts. The tapped resistive network also includes relatively high impedance network comprising 2x resistive fine elements.
Each fine network element is connected in parallel with a respective coarse segment, and is subdivided into 2(n x) fine sub~segments. The subsegments of each fine network element subdivide each of the 2x coarse voltage steps into -3a- RCA 81,8~2 2(n x) fine voltage steps. Within the A/D converter, the value of an input voltage may be determined by first sensing which of the coarse network segments brackets the input voltage and then comparing the input voltage with the fine reference voltage steps in the fine resistive element connected in parallel with that particular bracketing coarse network segment.
FIGURE 2 illustrates a configuration of an 8-bit "flash" A/D converter embodying the invention. The term "flash" normally refers to the fact that the analog-to-digital conversion or comparison is done in one step during one clock cycle. However, as detailed below, the circuit of FIGURE 2 may be termed a two-step "flash"
converter, with one step being used to determine the . _ . _ _ . .
:L2~6~3~
- 4 - RCA 81,842 1 "coarse" value of an input voltage (VIN) to its 4 most significant bits (MSB) and the second step being used to determine the "fine" value of VIN to its 4 least significant bits (LSB). The converter has been divided 5 into two 4-bit sections whose outputs are subsequently recombined to produce the desired 8-bits o~ inormation.
One 4-bit section is denoted as the "coarse" section and the other 4-bit section is denoted as the "fine"
section. The "coarse" section includes means for 10 subdividing the reference voltage into 24 "coarse"
reference segments and to sense which coarse segment brackets the unknown input voltage being sampled (or - measured). The "fine" section includes means for subdividing each 24 coarse segments into 2~ fine 15 sub-segments and to sense which fine sub-segment brackets the unknown input voltage being sampled. The coarse section includes a coarse resistor string 22 with 24 coarse taps (TCi) located at equal increments along the string, 24 transmission gates (TGCi) for coupling the 24 20 taps to 24 "coarse" comparators and a coarse logic array encoder 28. The "fine" section includes a fine resistor string 24 comprised of 24 segments with each segment further subdivided into 24 sub-segments with (24-1) fine taps formed between the 24 fine sub-segments. The fine 25 segment also includes (24-1) transmission gates per segment for coupling the (2~ -1) taps of a segment to the corresponding (24-1) fine comparators and a "fine" logic array encoder 30.
The coarse resistor element 22 may be formed by 30 connecting discrete resistive elements of equal value, connected-in series between VREF+ and VREF- with taps formed or connected at the junctions between the resistors. Also, a tap (e.g. TC16~ may be connected to the end of the resistor (e.g. R16) connected to VREF+.
35 Alternatively, the coarse resistor network 22 may be formed of a single resistor element connected between the negative reference voltage VREF- and the positive reference voltage VRE~+. Taps are formed or connected, at substantially equal ohmic increments along the coarse ~2~ 3~
- 5 - RCA 81,842 1 resistor element 22 to produce substantially equal voltage increments across the coarse segments located between each coarse tap. Consequently, the voltage increasing monotonically along the coarse resistor goes from the tap 5 closest to VREF- to the tap closest to VREF+.
The coarse resistor network 22 is a relatively low impedance resistance. By way of example, in the embodiment of FIGURE 2, the total impedance of network 22 REF and VREF- is approximately 500 ohms 10 Network 22 is divided into 16 (i.e. 24) coarse segments of substantially equal ohmic (e.g. approximately 30 ohms each) increments to produce 16 substantially equal reference voltage steps, which can be represented by 4 bits. In the discussion to follow, it is assumed, for 15 ease of illustration, that VREF- is ground and VREF~
is 6.4 volts. Thus, the volt3ge drop (~VC) across each coarse segment is 400 millivolts, with the voltage at a succeeding tap along the stack being 400 millivolts greater than the voltage at a preceding tap.
There are 16 "coarse" comparators (CCi), one comparator for each coarse tap along resistor network 22 including a sixteenth comparator for the tap to which VREF~ is applied. The sixteenth comparator senses an overflow condition, i.e. when VIN is greater than 25 VREE,I. In applications where it is not necessary to sense the overflow condition, the sixteenth comparator may be eliminated.
Corresponding to each coarse tap (TCi) on coarse resistor network 22 there is a coarse transmission gate (TGCi) for selectively coupling the coarse tap (TCi) to the reference input of its corresponding coarse comparator (CCi). The coarse comparators and the fine comparators may be of the same type as the comparator shown in FIGURE
6. However, other suitable comparators may be used 35 instead.
The outputs (OCCi) of the coarse comparators are applied to the coarse logic array decoder/encoder 28 which produces: 1) a coarse indication of the value of VIN;
and 2) control signals indicative of which coarse segment ., 12~23~
- 6 - RCA 81,842 1 brackets the input voltage being sampled. Logic arr3y decoder/encoder 28 may be of the type used in the ~A3300 and CA3308 integrated circuits manufactured by RCA Corp.
and described in dat3 sheet published by RCA Corp.
5 Alternatively, the decoder/encoder 28 may be any one of a number of known decoder/encoder arrangements capable of producing functions l and 2 noted above.
The fine resistor network 24 includes a relatively hi~h impedance resistance connected in parallel with the relatively low impedance coarse resistor 22 between VREF- and VREF+. Resistor network 24 is divided into 16 (e.g. 24) fine resistive elements (or fine segments) with each fine resistive element being connected in parallel with a corresponding coarse segment as shown in 15 FIGURE 3. Each fine resistive element is further subdivided into 24 (or 16) sub-segments to provide 24 (or 16) fine`reference voltage steps between each pair of "coarse" taps [TCi and TCi~l]. A fine tap ~Tfi) is connected, or formed, at the junctions of every two fine sub-segments of each resistive element resulting in 15 fine taps (Tfl through Tfl5) at which are produced 15 different fine reference voltage levels (Vfl throu~h Vfl5) between each pair of coarse taps. Thus, as shown in FIGURE 3, for each coarse segment there is a set of 15 fine reference taps (Tfi's) which are given an ascending order goin~ from Tfl to Tfl5 as the resistor network is ascended from node i to the next higher succeeding node (i+l). As for the case of the coarse resistor, each fine resistive element may be a single resistor string 30 connected between two coarse taps with fine taps connected, or formed, at substantially equal ohmic increments along the string. Alternatively, the fine resistive element may be formed of substantially equal "discrete" resistors connected in series.
The total ohmic value of the fine resistive element between a pair of coarse taps is typically lO0 times the ohmic value of the coarse resistor (Rc) connected between those two taps. By way of example, where the coarse value is approximately 30 ohms, the ohmic value of the fine ~z~
~ 7 - RCA 81,842 1 resistive element is 3200 ohms and the impedance between any two fine taps is approximately 200 ohms. Hence the voltage level at each coarse tap is primarily determined by the coarse resistance.
A signi~icant advantage of the circuit of the invention is that the fine resistor network 24 may be formed with relatively high impedance sections. The fine resistor network may thus be formed on an integrated circuit using relatively little space and dissipates considerable less power than the prior art circuitry.
A layout of a portion of a fine resistive element is shown in FIGURE 4. In the circuit of the invention, each fine resistive element is formed of an elongated N
diffusion and an elongated P diffusion which are essentially connected in parallel and which provide the required ohmic drops with extremely high packing density.
P and N transistors are formed along the elongated diffusion to divide the diffusion into substantially equal ohmic increments. The layout shows tabs extending from the diffusions. These tabs provide the taps along the diffusions and these tabs/taps also function as the source/drain regions of the fine transmission gate transistors coupling their respective taps to the reference input of their corresponding fine comparator.
The use of N and P diffusions connected in parallel provides some significant advantages. The input voltage, VIN, covers a dynamic range assumed, by way of example, to range between 0 and 6.4 volts. If a single MOS
transmission gate were used to connect a tap to a comparator, the transmission gate transistor in several instances would conduct in the source follower mode--producing an offset. Also since the gates are driven by oppositely phased clock signals, switching charge injection is approximately neutralized resulting in faster settling.
Therefore, were a single N diffusion or a single P
diffusion used to form the resistive element, a full (i.e.
complementary) transmission gate would have to be used to couple the full fine tap voltages to the comparators.
~, ~2~23~
- 8 - RCA 81,842 1 This would add another metal connection between the transmission gate and the N or the P-diffusion. This would make the wiring very difficult~ By parallelin~
equal N and P diffusions, the source/drain regions of the transmission gate transistors are at the same potential at each respective tap. As a result, the wiring is minimized and the full dynamic range of the reference voltage and the input voltage can be fully utilized.
The N and P elongated diffusions forming the fine resistive element also form the source/drain regions of the transmission gate transistors used to couple the "tapped" points on the fine resistive element to the corresponding fine comparators.
The schematic circuit representation of the layout of FIGURE 4 is shown in FIGURE 5. Note that when fscl goes low and fsci goes high that each sub-segment (e.g. RFNl) from the N-diffusion and its corresponding sub-segment from the P-diffusion (e.g. RFpl) are connected in parallel via their respective transmission gate transistors (TGfNl and TGfPl) to their corresponding fine comparator input (e.g. Fcl). Evidently analysis of the layout and the resulting schematic indicates that a very compact, low parasitic, and efficient layout has been produced.
There are 16 sets (TGfi) of fine transmission gates, each set being comprised of 15 transmission gates. Each set of fine tran~mission gates is enabled by a control signal (fsci) produced by coarse logic array 28. During operation of the A/D converter only one set of fine
3~ transmission gates is enabled at any one time. When the set of fine transmission gates is enabled the 15 fine taps associated with that set are coupled to their corresponding fine comparator inputs.
FIGURES 2 and 3 are intended to show that whenever a "coarse" segment "brackets" an input voltage, the 15 fine taps (Tfi) contained within the "bracketing" coarse segment are coupled in accordance with their ordered arrangement via 15 transmission gates TGfj (1-15) to the reference input of like ordered comparators.
~L2~623~
- 9 - RCA 81,842 1 There are fifteen fine comparators (FCl through FC15) which may be of the comparator type shown in FIGURE 6 or which may be any one of a number of known comparator circuits whose outputs may be coupled to a storage device for latching and storage. The fine comparators have two inputs. One input is VIN--the input signal being sampled. The other input is a "selected" fine reference voltage input. As shown in FIGURE 6, the reference input tQ a comparator (i) is any one of 16 fine voltages Vfi.
10 For example, the fine voltage (Vfl) from the first fine tap (T~l) from each one of the 16 coarse segments are multiplexed via their corresponding fine transmission gate TGfj, 1 to the first fine comparator FCl. Likewise the fine voltage (Vfl5) from the 15th fine tap (Tfl5) from each one of the 16 coarse segments are applied via their corresponding fine transmission gates T~fj, 15 to FC15.
The signal and reference inputs are applied via their respective transmission gates (TGR or TGS) to an input capacitor Cl, where their levels are compared. Their difference, if any, is amplified via inverters Il and I2 which provide two stages of amplifications. The amplified output of I2 is applied to a latch which stores the signal for subsequent processing by logic array decoder/encoder 30.
The outputs (Ofci) of the comparators are applied to a fine logic array decoder/encoder circuit 30 (Figure 2).
Circuit 30 produces an output which indicates the value of an input voltage being sampled within its 4 least significant bits (LSB).
The operation of the A/D converter embodying the invention is best explained by reference to FIGURES 2 and 3. As before, it is assumed that:
a) VREF~ is at 6.4 volts;
b) that VREF- is at ground; and c) the voltage across each coarse segment is then 400 millivolts and increases in increments of ~00 millivolts along the coarse network 22; and d) the voltage across each fine sub-segment is then 25 millivolts and increases in increments o 25 millivolts . "
12~3~
10 - RCA 81,842 1 along the fine network.
An input voltage (VIN) to be sampled is applied Vi3 sampling transmission gates, TGS, which are mo~entarily enabled, to the inputs of the 16 coarse and 15 fine 5 comparators. This contrasts to the prior art circuit where 256 comparators have to be charged or discharged.
After the input signal is "inputted" the sampling transmission gates are disabled. However, the value of VIN remains stored at the inputs of the comparators.
10 After sampling VIN, a reference control signal CLRE~
is applied to enable all the coarse transmission gates (TGCi) concurrently.
The reference voltages present at each coarse tap (TCi) is then applied via its corresponding coarse 15 transmission gate (TGCi) to the reference input of its corresponding coarse comparator (CCi).
The outputs (OCi) of each coarse comparator then produce a signal indicative of whether the coarse reference voltage (VCi) applied to the comparator is 20 greater or less than the value of VIN previously applied to the comparator input.
For ease of description, assume that when VIN is greater than the local reference VCi, the outp~t OCi of that comparator is driven "low" or logic "0" and that, 25 when VIN is less than VCi, the output OCi goes high or logic "1".
Assume, by way of example, that a VIN having an amplitude of 612.5 millivolts is applied to the comparators. Subsequently, when the local reference 30 voltages (VCi), are applied, OCl goes low while the remaining coarse comparator outputs go high. All the coarse comparator outputs are applied to logic array decoder/encoder 28 which produces an enabling signal on signal line fsc2 and maintains a disabling signal on all 35 the remaining fsci lines. That is, array 28 is designed to produce an enabling signal on fsc2 and a disabling signal on the other fsci's, when OCl is low and OC2 (and the remaining OCi's) i5 high. Enabling fsc2 indicates that VIN lies in a range between VCl and VC2 and that :~2~3~
RCA 81, 8 4 2 1 the fine sections across coarse segment R2 are to be selected. Decoder 28 also encodes the information received f~om the coarse comparators and produces the 4 most significant bits (MSB) of information regarding 5 VIN. Assuming that the voltage range between 0 volts and VCl (or TCl) is assigned a binary value of 0000, the - output lying between VCl and VC2 will be read out as 0001 (i.e. greater than 0.4 volt and less than 0.8 volt).
The second step in determining the value of VIN
10 follows. The enabling fsc2 signal enables the 15 fine transmission gates TGf 2 (1-15) coupling all the fine reference voltages (Vfi's) produced across coarse segment R2 to their corresponding fine comparators FCl through FC15.
Assume, as before, that the output (Ofi) of a fine comparator goes low when VIN is greater than the local reference voltage (Vfi) applied to the comparator input and Ofi goes high when VIN is less than Vfi.
For an assumed value of 612.5 millivolts, the fine 20 comparators FCl through FC8 will sense a VIN which is greater than the local Vfi's. Accordingly, the outputs (Ofl through Of8) of comparators FC1 through FC8 will be driven low.
The outputs, Of9 through Ofl5, of comparators FC9 25 through FC15 will have a "high" value indicating that VIN is less than V9 through V15. The outputs of the fine comparators are applied to fine logic array encoder 30. Encoder 30 is designed to respond to Ofl through Of8 being low and to Of9 through Of15 being high by producing 30 a 4 bit code which represents the value of VIN within its 4 least significant bits (LSB).
The 4 LSB values generated would be 1000. Thus, combining the most significant bits produced during the first step with the least significant bits generated 35 during the second step produces a binary read out for a VIN of 612.5 millivolts of:
MSB LSB
In the discussion above, the coarse and fine resistor ~2~ 3Z
- 12 - RCA 81,842 1 networks were divided into equal increments. It should be appreciated that another advantage of using a coarse and a fine resistor network is that it enables the generation of reference voltages other than those discussed above, 5 rather easily. For example, as shown in FIGURE 7, the first tap (Tfl) along the fine network may be set a point which will produce a voltage Vl which is equal to one-half (1/2) the value of each fine increment (~Vf). The succeeding taps along the fine network may be located a 10 full fine increment apart. However the voltages at a tap (Tfi) may then be expressed as:
[ i av - 1/2 ~Vf]
where i is the number of the tap along the fine network. This feature enables a comparator point to be 15 set at 1/2 the least significant bit, which is a desirable feature in this art.
The voltage across a particular coarse segment may also be controlled or varied easily. For example, in FIGURE 7, a resistor Rx connected in parallel with Rc and 20 having an ohmic value of 16 times Rc may be used to set the voltage at node TCl, to be one sixteenth less than the value of TCl when Rx is removed from the circuit. This feature may be used in conjunction with the setting of the first fine tap at 1/2 LSB to provide reference voltage 25 comparisons at points which are one half the least significant bit levels.
In the discussion above the invention was illustrated when embodied in an 8-bit converter. Obviously, the invention is equally applicable to converters having 30 greater or less bits of resolution. As a general proposition, the "n" bits will be divided into two sections. In the discussion above, the "n" bit were divided into two sections, each section for producing a like number of bits. However, the division need not be 35 equal, although normally that would be most advantageous.
Thus, one section may include X bits and the other section n-x bits. The one section (assume it to be the coarse section) then needs 2x coarse segments and the other section (e.g. the fine section) needs 2(n x~ fine 12~6~3~ -- 13 - RCA 81,842 1 sub-segmentsper coarse segment. Furthermore, the one (e.g. coarse) section will generally have up to 2x taps while the other (e.g. fine) section will generally have 2(n~X)-l taps Dividing the resistive network into two sections provides the following significant advantages:
1) The total impedance is comparable to prior art, but l/16th the number of comparators need to be charged or discharged.
2) The speed/comparator is faster because there is less capacitance on the decoded LSB intermeshed ladder and the switching path is through only one transmission gate.
Although the total impedance of the coarse resistor network is comparable to the total impedance of the prlor 15 art networks, there are fewer metal contacts along the coarse resistor. As to the fine or high impedance network, the resistance between taps is significantly higher than in the prior art minimizing contact resistance variables. The total resistance is thus more favorably 20 distributed.
The comparator count is down from 256 to 31, thus the charge injected into the resistor ladder is reduced 8 times.
FIGURES 2 and 3 are intended to show that whenever a "coarse" segment "brackets" an input voltage, the 15 fine taps (Tfi) contained within the "bracketing" coarse segment are coupled in accordance with their ordered arrangement via 15 transmission gates TGfj (1-15) to the reference input of like ordered comparators.
~L2~623~
- 9 - RCA 81,842 1 There are fifteen fine comparators (FCl through FC15) which may be of the comparator type shown in FIGURE 6 or which may be any one of a number of known comparator circuits whose outputs may be coupled to a storage device for latching and storage. The fine comparators have two inputs. One input is VIN--the input signal being sampled. The other input is a "selected" fine reference voltage input. As shown in FIGURE 6, the reference input tQ a comparator (i) is any one of 16 fine voltages Vfi.
10 For example, the fine voltage (Vfl) from the first fine tap (T~l) from each one of the 16 coarse segments are multiplexed via their corresponding fine transmission gate TGfj, 1 to the first fine comparator FCl. Likewise the fine voltage (Vfl5) from the 15th fine tap (Tfl5) from each one of the 16 coarse segments are applied via their corresponding fine transmission gates T~fj, 15 to FC15.
The signal and reference inputs are applied via their respective transmission gates (TGR or TGS) to an input capacitor Cl, where their levels are compared. Their difference, if any, is amplified via inverters Il and I2 which provide two stages of amplifications. The amplified output of I2 is applied to a latch which stores the signal for subsequent processing by logic array decoder/encoder 30.
The outputs (Ofci) of the comparators are applied to a fine logic array decoder/encoder circuit 30 (Figure 2).
Circuit 30 produces an output which indicates the value of an input voltage being sampled within its 4 least significant bits (LSB).
The operation of the A/D converter embodying the invention is best explained by reference to FIGURES 2 and 3. As before, it is assumed that:
a) VREF~ is at 6.4 volts;
b) that VREF- is at ground; and c) the voltage across each coarse segment is then 400 millivolts and increases in increments of ~00 millivolts along the coarse network 22; and d) the voltage across each fine sub-segment is then 25 millivolts and increases in increments o 25 millivolts . "
12~3~
10 - RCA 81,842 1 along the fine network.
An input voltage (VIN) to be sampled is applied Vi3 sampling transmission gates, TGS, which are mo~entarily enabled, to the inputs of the 16 coarse and 15 fine 5 comparators. This contrasts to the prior art circuit where 256 comparators have to be charged or discharged.
After the input signal is "inputted" the sampling transmission gates are disabled. However, the value of VIN remains stored at the inputs of the comparators.
10 After sampling VIN, a reference control signal CLRE~
is applied to enable all the coarse transmission gates (TGCi) concurrently.
The reference voltages present at each coarse tap (TCi) is then applied via its corresponding coarse 15 transmission gate (TGCi) to the reference input of its corresponding coarse comparator (CCi).
The outputs (OCi) of each coarse comparator then produce a signal indicative of whether the coarse reference voltage (VCi) applied to the comparator is 20 greater or less than the value of VIN previously applied to the comparator input.
For ease of description, assume that when VIN is greater than the local reference VCi, the outp~t OCi of that comparator is driven "low" or logic "0" and that, 25 when VIN is less than VCi, the output OCi goes high or logic "1".
Assume, by way of example, that a VIN having an amplitude of 612.5 millivolts is applied to the comparators. Subsequently, when the local reference 30 voltages (VCi), are applied, OCl goes low while the remaining coarse comparator outputs go high. All the coarse comparator outputs are applied to logic array decoder/encoder 28 which produces an enabling signal on signal line fsc2 and maintains a disabling signal on all 35 the remaining fsci lines. That is, array 28 is designed to produce an enabling signal on fsc2 and a disabling signal on the other fsci's, when OCl is low and OC2 (and the remaining OCi's) i5 high. Enabling fsc2 indicates that VIN lies in a range between VCl and VC2 and that :~2~3~
RCA 81, 8 4 2 1 the fine sections across coarse segment R2 are to be selected. Decoder 28 also encodes the information received f~om the coarse comparators and produces the 4 most significant bits (MSB) of information regarding 5 VIN. Assuming that the voltage range between 0 volts and VCl (or TCl) is assigned a binary value of 0000, the - output lying between VCl and VC2 will be read out as 0001 (i.e. greater than 0.4 volt and less than 0.8 volt).
The second step in determining the value of VIN
10 follows. The enabling fsc2 signal enables the 15 fine transmission gates TGf 2 (1-15) coupling all the fine reference voltages (Vfi's) produced across coarse segment R2 to their corresponding fine comparators FCl through FC15.
Assume, as before, that the output (Ofi) of a fine comparator goes low when VIN is greater than the local reference voltage (Vfi) applied to the comparator input and Ofi goes high when VIN is less than Vfi.
For an assumed value of 612.5 millivolts, the fine 20 comparators FCl through FC8 will sense a VIN which is greater than the local Vfi's. Accordingly, the outputs (Ofl through Of8) of comparators FC1 through FC8 will be driven low.
The outputs, Of9 through Ofl5, of comparators FC9 25 through FC15 will have a "high" value indicating that VIN is less than V9 through V15. The outputs of the fine comparators are applied to fine logic array encoder 30. Encoder 30 is designed to respond to Ofl through Of8 being low and to Of9 through Of15 being high by producing 30 a 4 bit code which represents the value of VIN within its 4 least significant bits (LSB).
The 4 LSB values generated would be 1000. Thus, combining the most significant bits produced during the first step with the least significant bits generated 35 during the second step produces a binary read out for a VIN of 612.5 millivolts of:
MSB LSB
In the discussion above, the coarse and fine resistor ~2~ 3Z
- 12 - RCA 81,842 1 networks were divided into equal increments. It should be appreciated that another advantage of using a coarse and a fine resistor network is that it enables the generation of reference voltages other than those discussed above, 5 rather easily. For example, as shown in FIGURE 7, the first tap (Tfl) along the fine network may be set a point which will produce a voltage Vl which is equal to one-half (1/2) the value of each fine increment (~Vf). The succeeding taps along the fine network may be located a 10 full fine increment apart. However the voltages at a tap (Tfi) may then be expressed as:
[ i av - 1/2 ~Vf]
where i is the number of the tap along the fine network. This feature enables a comparator point to be 15 set at 1/2 the least significant bit, which is a desirable feature in this art.
The voltage across a particular coarse segment may also be controlled or varied easily. For example, in FIGURE 7, a resistor Rx connected in parallel with Rc and 20 having an ohmic value of 16 times Rc may be used to set the voltage at node TCl, to be one sixteenth less than the value of TCl when Rx is removed from the circuit. This feature may be used in conjunction with the setting of the first fine tap at 1/2 LSB to provide reference voltage 25 comparisons at points which are one half the least significant bit levels.
In the discussion above the invention was illustrated when embodied in an 8-bit converter. Obviously, the invention is equally applicable to converters having 30 greater or less bits of resolution. As a general proposition, the "n" bits will be divided into two sections. In the discussion above, the "n" bit were divided into two sections, each section for producing a like number of bits. However, the division need not be 35 equal, although normally that would be most advantageous.
Thus, one section may include X bits and the other section n-x bits. The one section (assume it to be the coarse section) then needs 2x coarse segments and the other section (e.g. the fine section) needs 2(n x~ fine 12~6~3~ -- 13 - RCA 81,842 1 sub-segmentsper coarse segment. Furthermore, the one (e.g. coarse) section will generally have up to 2x taps while the other (e.g. fine) section will generally have 2(n~X)-l taps Dividing the resistive network into two sections provides the following significant advantages:
1) The total impedance is comparable to prior art, but l/16th the number of comparators need to be charged or discharged.
2) The speed/comparator is faster because there is less capacitance on the decoded LSB intermeshed ladder and the switching path is through only one transmission gate.
Although the total impedance of the coarse resistor network is comparable to the total impedance of the prlor 15 art networks, there are fewer metal contacts along the coarse resistor. As to the fine or high impedance network, the resistance between taps is significantly higher than in the prior art minimizing contact resistance variables. The total resistance is thus more favorably 20 distributed.
The comparator count is down from 256 to 31, thus the charge injected into the resistor ladder is reduced 8 times.
Claims (10)
1. In an ''n''-bit analog-to-digital converter where ''n'' is an integer greater than 2: a tapped resistive network connected between first and second terminals for producing at taps thereof any one of 2n increments of a reference potential applied to said terminals;
where said network comprises:
a coarse, relatively low impedance resistive network connected between said first and second terminals;
said coarse network being divided into 2x coarse segments for producing 2x substantially equal ohmic increments, x being an integer less than n; and a fine relatively high impedance network comprising 2x resistive elements, each one of said fine network elements being connected in parallel with a respective coarse segment and being subdivided into 2(n-x) fine sub-segments.
where said network comprises:
a coarse, relatively low impedance resistive network connected between said first and second terminals;
said coarse network being divided into 2x coarse segments for producing 2x substantially equal ohmic increments, x being an integer less than n; and a fine relatively high impedance network comprising 2x resistive elements, each one of said fine network elements being connected in parallel with a respective coarse segment and being subdivided into 2(n-x) fine sub-segments.
2. The converter network as claimed in claim 1, each one of said fine elements having impedance significantly greater than the impedance of the respective one of said coarse segments connected thereto.
3. The converter network as claimed in claim 1, said 2x coarse taps being formed along said coarse network, 2x-1 of said coarse tap being formed at respective junctions between adjacent coarse network segments and the remaining coarse tap being formed at one end of said coarse network.
4. The converter network as claimed in claim 3, wherein there are formed along each of said fine resistive elements [2(n-x)-1] fine taps.
5. The combination as claimed in claim 4 wherein the first fine sub-segment is of different ohmic value than the other fine sub-segments.
14 .
14 .
6. In the converter network as claimed in claim 4 wherein: each one of said fine resistive elements includes first and second diffused regions;
each diffused region is subdivided into said 2(n-x) fine sub-segments; and an end of each fine sub-segment in each diffused region is connected to a respective one of a set of terminals which are common to all of said fine resistive elements, by the conduction path of a transistor, each transistor connected to said first region being of conductivity type opposite to the conductivity type of a transistor connected to said second region;
so that a pair of complementary transistors connected to each terminal of said set form a transmission gate.
each diffused region is subdivided into said 2(n-x) fine sub-segments; and an end of each fine sub-segment in each diffused region is connected to a respective one of a set of terminals which are common to all of said fine resistive elements, by the conduction path of a transistor, each transistor connected to said first region being of conductivity type opposite to the conductivity type of a transistor connected to said second region;
so that a pair of complementary transistors connected to each terminal of said set form a transmission gate.
7. In the analog-to-digital converter of claim 1, which produces 2n bits of resolution, and which further includes: signal input terminal for receiving an input voltage whose amplitude is to be determined; and comparator means for comparing voltage at said input terminal to voltages produced by said tapped resistive network;
wherein said comparator means includes:
first comparator means for comparing said input voltage with said coarse voltage segments for ascertaining the coarse value range of the input voltage and for producing a control signal indicative of the coarse segment bracketing the input voltage;
and second comparator means responsive to said control signal for comparing the voltage at said input terminal with only the 2(n-x) fine voltage sub-segments produced by the one of said fine network elements connected in parallel with the coarse segment ascertained as producing voltages bracketing said input voltage.
wherein said comparator means includes:
first comparator means for comparing said input voltage with said coarse voltage segments for ascertaining the coarse value range of the input voltage and for producing a control signal indicative of the coarse segment bracketing the input voltage;
and second comparator means responsive to said control signal for comparing the voltage at said input terminal with only the 2(n-x) fine voltage sub-segments produced by the one of said fine network elements connected in parallel with the coarse segment ascertained as producing voltages bracketing said input voltage.
8. In the converter as claimed in claim 7:
said first comparator means including: no more than 2x comparators and transmission gate means for coupling each one of said comparators to a respective one of the 2x segments along said coarse resistive network; and said second comparator means including no more than [2(n x)-1] comparators;
whereby the total number of comparators to produce 2n bits of information does not exceed 2x + 2(n-x)-1 comparators.
said first comparator means including: no more than 2x comparators and transmission gate means for coupling each one of said comparators to a respective one of the 2x segments along said coarse resistive network; and said second comparator means including no more than [2(n x)-1] comparators;
whereby the total number of comparators to produce 2n bits of information does not exceed 2x + 2(n-x)-1 comparators.
9. In the analog-to-digital converter of claim 6, which produces 2n bits of resolution, and which further includes: signal input terminal for receiving an input voltage whose amplitude is to be determined; and comparator means for comparing voltage at said input terminal to voltages produced by said tapped resistive network;
wherein said comparator means includes:
first comparator means for comparing said input voltage with said coarse voltage segments for ascertaining the coarse value range of the input voltage and for producing a control signal indicative of the coarse segment bracketing the input voltage;
and second comparator means responsive to said control signal for comparing the voltage at said input terminal with only the 2(n-x) fine voltage sub-segments produced by the one of said fine network elements connected in parallel with the coarse segment ascertained as producing voltages bracketing said input voltage.
10. In the converter as claimed in claim 9:
said first comparator means including: no more than 2x comparators and transmission gate means
wherein said comparator means includes:
first comparator means for comparing said input voltage with said coarse voltage segments for ascertaining the coarse value range of the input voltage and for producing a control signal indicative of the coarse segment bracketing the input voltage;
and second comparator means responsive to said control signal for comparing the voltage at said input terminal with only the 2(n-x) fine voltage sub-segments produced by the one of said fine network elements connected in parallel with the coarse segment ascertained as producing voltages bracketing said input voltage.
10. In the converter as claimed in claim 9:
said first comparator means including: no more than 2x comparators and transmission gate means
Claim 10 continued:
for coupling each one of said comparators to a respective one of the 2x segments along said coarse resistive network; and said second comparator means including no more than [2(n-x)-1] comparators;
whereby the total number of comparators to produce 2n bits of information does not exceed 2x + 2(n-x)-1 comparators.
for coupling each one of said comparators to a respective one of the 2x segments along said coarse resistive network; and said second comparator means including no more than [2(n-x)-1] comparators;
whereby the total number of comparators to produce 2n bits of information does not exceed 2x + 2(n-x)-1 comparators.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/700,866 US4612531A (en) | 1985-02-12 | 1985-02-12 | Intermeshed resistor network for analog to digital conversion |
| US700,866 | 1985-02-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1246232A true CA1246232A (en) | 1988-12-06 |
Family
ID=24815196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000501607A Expired CA1246232A (en) | 1985-02-12 | 1986-02-11 | Intermeshed resistor network for analog to digital conversion |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4612531A (en) |
| JP (1) | JPS61189022A (en) |
| KR (1) | KR900000997B1 (en) |
| CA (1) | CA1246232A (en) |
| DE (1) | DE3604158A1 (en) |
| FR (1) | FR2577366A1 (en) |
| GB (1) | GB2170968B (en) |
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| CN110048719B (en) * | 2019-03-25 | 2023-04-28 | 湖州师范学院 | Segmented parallel comparison type ADC |
| US11742843B2 (en) * | 2020-04-23 | 2023-08-29 | Silicon Laboratories Inc. | Apparatus for offset cancellation in comparators and associated methods |
| US11764759B2 (en) | 2020-04-23 | 2023-09-19 | Silicon Laboratories Inc. | Apparatus for offset cancellation in comparators and associated methods |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IE38230B1 (en) * | 1972-09-15 | 1978-01-18 | Ind Des Telecommunications Com | Improvements in digital coders |
| FR2264432B1 (en) * | 1974-03-15 | 1976-12-17 | Thomson Csf | |
| US4016555A (en) * | 1975-04-07 | 1977-04-05 | Tyrrel Sylvan F | Signal converter |
| US4099173A (en) * | 1976-08-06 | 1978-07-04 | Gte Laboratories Incorporated | Digitally sampled high speed analog to digital converter |
| DE2905116A1 (en) * | 1978-02-21 | 1979-08-30 | Nat Semiconductor Corp | Double D=A converter with reduced number of switches - has series resistor chain divided into two groups with switching networks responding to highest and lowest position digits |
| JPS5623026A (en) * | 1979-08-03 | 1981-03-04 | Nec Corp | Analog-digital conversion unit |
| NL8006995A (en) * | 1980-12-23 | 1982-07-16 | Philips Nv | ANALOG-DIGITAL CONVERTION SWITCH. |
| US4447747A (en) * | 1981-03-02 | 1984-05-08 | Gte Laboratories Incorporated | Waveform generating apparatus |
| JPS589426A (en) * | 1981-07-10 | 1983-01-19 | Sony Corp | Analog-to-digital converter |
| US4542370A (en) * | 1981-10-20 | 1985-09-17 | Tokyo Shibaura Denki Kabushiki Kaisha | Cascade-comparator A/D converter |
| JPS5869111A (en) * | 1981-10-20 | 1983-04-25 | Toshiba Corp | Analog-to-digital converter |
-
1985
- 1985-02-12 US US06/700,866 patent/US4612531A/en not_active Expired - Lifetime
-
1986
- 1986-02-06 GB GB08603003A patent/GB2170968B/en not_active Expired
- 1986-02-10 DE DE19863604158 patent/DE3604158A1/en active Granted
- 1986-02-11 KR KR1019860000924A patent/KR900000997B1/en not_active IP Right Cessation
- 1986-02-11 CA CA000501607A patent/CA1246232A/en not_active Expired
- 1986-02-12 JP JP61029855A patent/JPS61189022A/en active Pending
- 1986-02-12 FR FR8601911A patent/FR2577366A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61189022A (en) | 1986-08-22 |
| US4612531A (en) | 1986-09-16 |
| GB2170968B (en) | 1988-06-15 |
| KR860006878A (en) | 1986-09-15 |
| GB2170968A (en) | 1986-08-13 |
| GB8603003D0 (en) | 1986-03-12 |
| FR2577366A1 (en) | 1986-08-14 |
| DE3604158A1 (en) | 1986-08-21 |
| DE3604158C2 (en) | 1990-02-22 |
| KR900000997B1 (en) | 1990-02-23 |
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