CA1248623A - Video signal processing circuit for processing an interlaced video signal - Google Patents

Abstract

ABSTRACT:
"Video signal processing circuit for processing an interlaced video signal."

A movement-adaptive processing circuit for an interlaced video signal has a selection circuit (5) which passes on to its output (21) one of the three video signals applied to its inputs (3, 9, 11) and which signals substantially correspond to three position-sequential lines of two consecutive fields when this signal has an amplitude which is closest to the mean amplitude of these three video signals (Figure 1). The processing circuit may be used in many types of circuits such as, for example, in line or field number conversion circuits, noise suppression circuits, DPCM decoding circuits, vertical contour correction circuits and in still-picture display circuits of video record players.

Description

~2~
P~ 11 613 l 28-1-1986 "Video signal processing circuit for processing an interlaced video signal."

The invention relates to a video signal processing circuit for processing an in-terlaced video signal, comprising a motion-adaptive selection circuit operable by means of a decision circuit, which selection circuit has three inputs coupled to a video signal source for applying video signals thereto corresponding substantially to three position-sequential lines of two fields, and an output.
A video signal processing circuit of the type described above designed as a line number doubler is known from Radio Mentor Elektronik, No. 5, 1975, page 196. In this circuit a first input of the selection circuit is coupled directly to the video signal source, a second input is coupled to the video source through a delay circuit having a delay of one line period and a third input is coupled to the video source through a delay circuit having a delay of one field period minus half a line period. The output of the selection circuit is coupled through a line num~er doubler to an input combina-tion of a change over switch a further input combination of which is coupled to the video signal source through a further line num~er doubler. The selection circuit includes an adder circuit coupled to the first and second inputs thereof, whilst an output of this adder circuit is connected to an input of a change-over switch a further input of which is coupled to the third input of the selection circuit and an output is coupled to the output of the selection circuit. The change-over switch of the selection circuit is operated by means of a m.ove-ment detector circuit serving as a decision circuit, which de-tection circuit compares -the video signals of two sequential pictures supplied by the video signal source. The selection circuit which can only be used for the said application serves to obtain lines to be added from the previous field, which lines are located between the original lines of a field in the case of still pictures, or from the same field from the adder circuit serving as an interpolation circuit in the case of noving pictures.
It is an object of the invention to provide a video signal processing circuit having a different type of selection and decislon ~ 3~ ~ 3 PHN 11 613 -2- 2~-1-1986 circuit and resulting ir. a better picture with fewer disturbing phenomena, which circuit can also be applied for many other types of video signal processing operations.
To thi.s end a video signal processing circui-t of the type described in the opening paragraph according to the invention is characterized in that the decision circuit has three inputs each coupled to an input of the selection circuit and is arranged for determining at any moment at which input of the selection circuit the amplitude of the video signal applied thereto is closest to the mean value of the amplitudes of -the three inpu-ts, whilst the selection circuit includes a circuit for coupling said input to its output under the influence of the decision circuit.
As a result of -this rneasure the video signal processing circuit is found to yield a considerable reduction in disturbing phenomena occurring as a result of interlacing, both in rr.oving and in still pictures, and is suitable for all kinds of movement-adaptive signal video processing operations such as, for example, inter alia in line number doubling or halving per field and other line nurr~er conversions, field num~er conversions, noise suppression, decoding of differential pulse-rncdulated signals, still-picture display by rneans of a video record player and vertical contour correction.
Furthermore a picture memory is no longer required for the rnovement adaptation.
The invention will now be described with reference to the drawing.
In the draw.ing:
Figure 1 illustrates with a block diagram a video signal processing circuit according to the invention for use in still-picture display by means of a video record player, Fi~ure 2 with a block diagram a further video signal pro-cessing circuit according to the invention for use in still-picture display by rneans of a video record player, Figure 3 with a block diagram a video signal processsing circuit according to the invention in which a nurn~er of lines is doubled per field, Figure 4 with a block diagram a second possible ernbcd:Lment of a video sigrlal processing circuit according to the invention with which a line nurr~er doubling per field is obtained, ~2~$6;~3 PHN 11 613 -3- 2~-1-19~6 Figure 5 wl~h a block diagram a third possible embcdiment of a video slgnal processing circuit according to the invention ~or a line num~er doubling per field, Figure 6 with a block diagram a fourth possible emkcdiment of a video signal processing circuit according to the invention for obtaining a line number doubling per field, Figure 7 with a block diagram a video signal processing circuit according to the .invention for field number doubling, Figure 8 wlth a block diagram of a fur-ther video signal o processing circuit according to the invention for field number doubling, Figure 9 with a block diagram a video signal processing circuit according to the invention for obtaining noise suppression, Figure 10 with a block diagram of a video signal proeessing circuit according to the invention for differential pulse code mcdula-tion and dem~dulation, Figure 11 with a block diagram a video signal processing circuit according to the invention for obtaining vertical contour correction, Figure 12 with a block diagram a further video slgnal processing circuit according to the invention for vertical contour correetion, Figure 13 with a block diagram a possible em~cdiment of a video signal proeessing cireuit according to the invention for 25 halving the numl~er of lines per field, Figure 14 with a bloek diagram a further possible em-bcdiment of a v.ideo signal proeessing cireuit according to the in-vention for halving the numl~er of lines per field, Figure 15 with a bloek diagram a possible embcdiment of 30 a second comb filter circui.t for use in the line number doubler of Figure 6 r Figure 16 with a bloek diagram a possible emkcdiment of a video signal processiny eircuit according to the invention, arranged as a movement deteetor, Figure 17 with a bloek diagram a possible embcd.iment of a video signal proeessing eireuit according to the invention including a line number doubler, a non-linear filter circuit and a vertical contour correction cireuit, 6~3 Pi~ 11 613 -4- 2~ 19~6 Figure 18 with a block circuit diagram a video signal processing circuit according to the invention, in which a comb fllter circuit is included subsequent to a non-linear filter circuit and a line num~er doubler, Figure 19 with a block diagram a video signal processing circuit according to the inverltion having a control circuit arranged between the output and the input circuit of a non-linear filter circuit, Figure 20 with a block diagram a video signal processing circuit according to the invention including a different possible embcdiment of a control circuit arranged between the output and the input circuit of a non-linear filter circuit and Figure 21 with a block diagram a video signal processing circuit according to the invention, including a direction correction circuit preceding the input circuit of a non-linear filter circuit.
In Figure 1 a video s.ignal originating from an interlaced still television picture such as, for example,in still-picture dis~lay by means of a video record player is applied to an input 1. This video signal is the same from picture to picture, but may differ from field to field. The two ~ields of a picture are referred to as A and B.
The input 1 is connected to an input 3 of a selection circuit 5 and via a delay circuit 7 having a delay of one field period minus half a line period to an input 9 of the selection circuit 5. An input 11 of the selection circuit 5 is connected to the input 1 via a delay circuit 13 having a delay of one line period and the delay circuit 7.
The inputs 3, 9 and 11 of the selec-tion clrcuit 5 are connected to an output 21 of the selection circui-t 5 via switches 15, 17 and 19, respectively. The switches 15, 17, 19 have operation signal inputs 23, 25 and 27, respectively, constit.uting an operation si.gnal input comb.ination of the selection circuit 5 and being con-nectecl to an operati~n signal output ccmbination of a decisi.on circuit 29, which operation signal output combination has OlltpUtS 31, 33, 35 respectively, of a logic circuit 37.
I'he logic circuit 37, which may be, for example, a gating circuit or a read-only nemory, has three inputs 39, 41, 43 which are also the outputs of three comparison circuits 45, 47, 49. Inputs 51 , . .

PHN 11 613 -5~ 3 2~-1-1986 and 53 of the comparison circuit 45 are connected to the inputs 11 and 3, respectively, of the selection circuit 5. Inputs 55 ard 57 of the comparison circuit 47 are connected to the inputs 11 and 9, respectively, of the selection circuit 5 and inputs 59 and 61 of the comparison circuit 49 are connected to the inputs 9 and 3, respec-tively of the selection circuit 5.
The output 21 of the selection circuit 5 is connected to an input 63 of a chanye-over switch 6S a further input 67 of which is connected to the input 1 and an output 68 of which con-lo stitutes the output of the video signal processing circuit. Anoperation signal input 69 of the change-over switch 65 receives a switching signal of half the field frequency so that the change-over switch 65 is in the position shown during processing of a video signal from the fields B and is in the position not shown during processing of a video signal from the fields A. A switching signal having the opposite phase yields a comparable result.
The selection circuit 5 and the decision circuit 29 to-gether constitute a non~linear filter circuit 71 by which the signal at one of the inputs 3, 9 or 11 of the selection circuit 5 which is closest to the mean value of the signals at these inputs 3, 9 and 11 is passed on to the output 21.
Signasls p, q and r originating from three superjacent pixels of two consecutive fields are present at the inputs 3, 9 and 11 of the selection circuit 5, in this case with the signal p repre-sen-ting the central pixel from the present field, the signal q representing the lower pixel and the signal r representing the upper pixel from the previc~ls field. When the signals at the inputs 43, 41, 39 of the lo~ic circuit 37 are referred to as x, y and z, respec-tively, the following Table applies in which x = 0 for p ~q and x = 1 for p~ q y = 0 for q ~ r and y = 1 for q~ r z = 0 for r ~ p and z = 1 for r~ p and I, II and III denote the desired position of the switches 15, ~7 and 19 respectively, of the selection circuit 5 brought a~out by the signals at the outputs 31, 33 and 35, respectively, of the decision circuit 37 and in which the digit O represents the non-closed position and the digit 1 represents the closed position.

~;~4~i$;~3 PHN 1 1 6 1 3 -6- 28-1 -1 9~6 x y z I II III
O O O d d d O 0 1 0 'I O

1 1 1 d d d lO The character d indicates that it does not matter which switch is closed. If a read-only memory is used for the logic circuit 37, it is possible to choose, for example, the switch I for this purpose. When using a gating circuit it is possible to choose the switch I, for example, for x = y = z = O and the switch III may be chosen for x = y = z = 1, which results in the following logical formulas.
I = x'z' + xy'z II = x'y'z -~ xyz' III = yz + xy'z' in which a single dash mark denotes an inversion.
When the non-linear filter circuit 71 is used in this manner, flickering effects occurring at the picture frequency are avoided without reducing the num~er of lines per field period.
It is found that a better picture impression is obtained in still-picture display than with any other known circuit.
It will be evident that a single delay circuit having adelay of one field perio~ plus half a line pericd may alternatively be applied instead of the series arrangement of the delay circuits 7 and 13 between the input 1 and the input 11 of the selection circuit 5.
When the delay circuits 7 and 13 are interchanged, the above-descri~ed video signal processing circuit may be used for a reduction in line flicker in the case of conversion of an interlacec1 to a non-interlaced picture by means oE an adaptation oE the vertical deflection of the picture display tube from field to field such that an extra vertical deflection over half a line distance of the original field, hence over one picture line dis-tance oE the original picture is effected when the change-over switch 65 is in the position ..

P~ 11 613 _7_ ~ 6 ~ ~ 28-1-1986 B sh~n.
In Figure 2 in which corresponding parts have the same reference numerals as in Figure 1 and to which reference is made for its description, the input 1 is connected to an input 73 of a parallel fi]ter circuit 75. The same signal as in Figure 1 is applied to the input 1. The input 73 of the parallel filter circuit 75 is also an input of a comb filter circuit 77 forming part of the parallel filter circuit 75. A further input 79 of the parallel filter circuit 75, which is also a further input of the comb filter circuit 77, can be connected through a change-over switch 81 to the input 1 or to an output of a delay circuit 83 having a delay tume of one field period minus half a line period whose input is connected to the input 1. The change-over switch 81 is operated by a switching signal of half the field frequency applied to an input 85 thereof, so that the change-over switch 81 assumes the position not shcwn when a signal from an A field occurs at the input 1 and assumes the position shown when a signal from a B field occurs.
A series arrangement of delay elements 87, 89, 91, 93 and 95, 97, 99, 101 each having a delay of one line period is connected 2D to the inputs 73 and 7g, respectively, of the comb filter circuit 77.
The outputs of the delay elements 87, ~9, 91, 93 and 95, 97, 99, 101 are connected via c oefficient circuits 103, 105, 107, 109 and 111, 113, 115, 117 to adder circuits 119 and 121, respectively, and via coefficient circuits 123, 125, 127, 129 and 131, 133, 135, 137 to adder circuits 139 and 141, respectively. Furthermore the inputs of the delay circuits ~7 and 95 are connected through c oe fficient circuits 143 and 145 to the adder circuits 139 and 141, respectively.
Outpu-ts 147 and 149 of the adder circuits 139 and 121 are connected to inputs 151 and 153, respectively, of an adder cir-cuit 155 an output 157 of which is also an output of the c~b filtercircuit 77 which is connected to the input 3 of the noh-linear filter circuit 71 and to an inverting input 159 of a subtractor circuit 161 a non-inverting input 163 of which is connected to the ou-tput of the dek~y element ~9 and an output 165 of which constitutes an output of the ccmb filter circuit 77.
Cutputs 167 and 169 of the adder circuits 119 and 141 are connected to inputs 171 and 173, respec-tively, of an adder circuit 175 an output 177 of which constitutes an output of the comb filter P~ 11 613 -8~ 28-1-1986 circuit 77 which is directly connectecl to -the input 9 of the non-linear filter circuit 71 and to the input 11 of the non-linear filter circuit 71 through a delay circuit 179 having a delay of one line period.
An output 181 of the comb filter circuit 77, which is also an output of the parallel filter circuit 75, is connected to the output of the delay element 97 and to the input 67 of the change-over switch 65 the input 63 of which is connected to an output 183 of an adder circuit 185, which output 183 is also an output of the lO parallel filter circuit 77. An input 187 of the adder circui-t 185 is connected to the output 21 of the non-linear filter circuit 71 and an input 189 is connected to the output 165 of the subtractor circuit 161.
During the occurrence of the A fields the change-over switches 81 and 65 assume, for example, the position not shown. A
signal which is delayed over two line periods relative to the signal at the input 1 is then applied to the output 68 of the change~over switch 65, which signal is further unprocessed.
During the occurrence of the B fields the change-over switches 81 and 65 are in that case in the position shc~n. The comb filter circuit 77 and the non-linear filter circuit 71 are then operative.
A cc~nb-filtered signal substantially corresponding to a signal from the present field which is delayed over two line periods then appears at the output 157 of the comb filter circuit 77. Simul-taneously a comkrfiltered signal substantially corresponding to a signal delayed over two line periods from a line of the previous field located just below the line of the present field to which the signal at the outpu-t 157 corresponds then appears at the output 177 of the comb filter circuit 77.
Comb~filtexed signals substantially corresponding to signals originating from three vertically sequential lines oE two consecutive fields are then applied to the inputs 3, 9 and 11 of the non-linear filtex circuit 71. In conformity with the description of Fig~re 1 these cc~b-filtered signals are selected by the non-linear filter circuit 71 and applied to the input 187 of the adder circuit 185 the other input 189 of which receives a complementary cc~rfiltexed signal comprising the signal components which have been processed P~ 11 613 -9 28-1-1986 by the non-linear filter circuit 71 and which originate from the output 165 of the subtractc)r circuit 161.
The follcwing considerations apply for dimensioning the c oefficient circuits of the comb filter circuit 77.
When the comb filter circuit 77 is operative, signals from an A and a B field are simultaneously present at its inputs 79 and 73. These two signals may have eclually much influence on the signals at the outputs 157 and 177 of the eomb filter eircuit 77. The coefEicient circuits 103, 105, 107, 109 may therefore be o chosen to be ec~al to the e oe ff:Lcient circuits 111, 113, 115, 117, respectively, and the coefficient circuits 143, 123, 125, 127, 129 may be chosen to be eclual to the coeffieient eircuits 145, 131, 133, 135, 137, respectively.
Signal components having a periodicity in the ver-tical direction corresponding to two picture lines ~lst be passecl, signal components having a periodicity in the vertical direetion corresponcling to three picture lines must be suppressed and signal cc~?onents having a periodicity in the vertical direetion corresponding to more than four picture lines must be passed.
Furthermore possible signal transients in the vertical direetion may not show ringing.
For a comb filter circuit having eight delay elements per dek~y circuit instead of the four shcwn for the sake of elarity, the follcwing values are, for example, chosen for the e oefficient circuits 143 0.0083 111 0.0014 123 0.0148 113 0.0089 125 0.0313 115 -0.1120 127 0.132~ 117 0.1155 30 129 0.6815 n.d. 0.1155 n.d 0.1325 n.d. -0.1120 n.d. 0.313 n.d. O.OOCI9 n.d. -0.014~ n.d. 0.0014 n.d. 0.0083 The c oefficient eireuits that have not been drawn are denoted by n.d. The order from left to right in the circuit corres-ponds to that from top to bottom in the Table. The input 163 of the subtractor circuit 161 and the input 67 of the change-over switch 65 must now be conr.ecte~ to the output of the delay element 93 and ~ 3~ 3 P~ 11 613 -lO- 28-1-19~6 the output of the delay element 101, respectively. In this case the adder circuit 175 supplies a signal substantially corresponding to a slgnal from the previous field and the adder circuit 155 supplies a signal substantially corresponding to a signal Erom the present field.
The video signal processing circui-t of Figure 2, likewise as that of Figure 1, may be used for a reduction in line Elicker when the change-over switch 81 is omitted, the input 79 of the parallel filter circuit 75 is connec-ted to the input 1 and the input 73 of the parallel circuit 75 is connected to the ou-tput of the delay circui-t 83 instead of to the input 1 and when the vertical deflection is corrected in the sane manner as is described with reference to Figure 1.
In Figure 3 in which corresponding parts have the same reference numerals as in Figure 1 to which reference is n~de for a further description, the video signal applied to the input 1 is to be doubled in line number. To eliminate remaining line flicker pheno-mena in a picture with a video signal doubled in line number, the video signal is first passed through a comb filter 201. An cutput 203 of the comb filter 201 then supplies a video signal in which an attenu-ation occ~s for a 625-line picture system at frequencies which are (n + 1/3) times the field frequency and (m + 1/3) times the line frequency (m = 0, 1, 2, ...) (n = 0, 1, 2, ...) and particularly at frequencies in the proximity of (m + 1/3)ti~es the line frequency of the video signal which is applied to the comb filter. For systems having a different line number per picture this is the same, apart from the addition to n, which may then be different.
The same considerations as for the comb filter circuit of Figure 2 apply to the assembly of the comb filter 201. The data 30 mentioned can also be used in this case. The video signal at the output 203 of the comb filter 201 is subsequently applied to -the input 3 oE the non-linear filter circuit 71 and to the input 9 of the non-linear filter circuit 71 through the delay circuit 13 having a delay of one line period, and furthermore to the input 11 of the non-linear filter circuit 71 through the delay circuit 7 having a delayof one field period minus half a line period. The output 21 of the non-linear filter circuit 71 then supplies a con~filtered video signal which is cleared from movenent-depenclent interferences by -the P~ 11 613 ~ 28-1-1986 the non-linear filter circuit. This videc- signal is applied to an input 205 of an adder circuit 207, whilst a complementary ccmk-filtered video signal is applied to its input 209.
The cornplementary ccmb~filtered video signal originates 5 from an output 211 of a subtractor circuit 213 of which an input 215 is connected to the outpu-t 203 of the comb filter 201 and an input 217 is connected via an all-pass circuit 219 to the input 1. The all-pass circuit 219 has the sarne delay t.ime as the comb filter 201.
The combination of the ccmh filter 201, the all-pass circuit 219 and the subtractor circui-t 213 will hereinafter be referred to as second cGmb filter circuit 220.
The adder circuit 207 applies a filtered video signal to an input 221 of a line number doubler 223, which signal represents at any moment from a group of three lines constitutedby the two lines fr:om the present field and an interlocated line, that line of which the value of the video signal is closest to the ~ean value of the video sig-nals of the three lines of said group, whilst an unfiltered video signal originating from the output of the all-pass circuit 219 is appli.ed to a further input 225 of the line number doubler 223 through a delay circuit 226 having a delay of one field period plus one picture line period.
The line number doubler 223, which is only sho~n concisely has write switches 227 and 229 connected to the inputs 221 and 225, respectively, four line mernories 231, 233, 235, 237 and read switches 243 and 245 connected to outputs 239 and 241, respectively. In the position shown of the switches 227, 229, 243, 245 the line memories 233, 237 are written during a line period of the video signal to be con-verted and the line memories 231 and 235 are read twice at the double rate. In the subsequent line period of the video signal to be converted the switches 227, 229, 243, 245 assume the position not shown and line rnemories 231 and 235 are written and line rnernories 233 and 237 are read twice at the double rate.
Consec~ently, a video signal of the double l.ine frequency is continuously present at the output 239 of the line nurr~er doubler 223, the signal value of the said video signal in a line pair being substantially equal to that signal value of three superjacent lines of two consecutive Eields ~f the video signal at the input 1 which approximates the mean signal value of these three lines as closely as ~%~
P HN11 613 -12- 28-1-19~6 possible, whilst a video slgnal whose signal value in a line pair is equal to that in a line of the converted unprocessed video signal is continuously present at the output 241.
The outputs 239 and 241 of the line num~er doubler 223 are alternately connected through a change-over switch 244 to an output 246. To this end the change-over switch 243 receives an operation signal of half the line frequency of the converted video signal at an inpu-t 247 so that the output 246 alternately supplies during a line pericd a converted video signal whose signal value is substan-tially equal to that signal value of three position sequential linesof the video signal to be converted, which approximates the mean signal value of these three lines as closely as possible, and during a fol-lowing line pericd an unprocessed converted video signal. As a result a video signal of double the line frequency having a very great freedom of interference is obtained without using a vement detector.
The circuit of Figure 2 will generally be preferred because in the comb filter 201 not only a nurn~er of delay circuits having a delay of one line pericd, but also a delay circuit having a delay oE one field period must be used because the signals of the even and cdd fields follcw the same signal path and signal components pro-ducing a picture pattern having a periodicity of three picture lines and having a frequency of (n + 1/3) times the field frequency must also be suppressed.
The circuit of Figure 3 may ke simplified by omitting the comb filter 201, the all-pass circuit 219, the subtraetor circuit 213, the delay eircuit 226 and the adder circuit 207. The input 3 of the non-linear filter circuit 71 and the input of the delay circuit 13 are then conneeted to the input 1, and the output 21 of the non-linear filter circuit 71 is connected to the input 221 of the line number doubler 223. For a seldom cee~lrring picture pattern having a periodieity in the vertieal direetion of three pieture lines an ex-tremely slight interferenee oeeurring at the pieture frequency must then be toleratecl.
Figure 4 shows a different possible embcdiment of a circuit for obtaining a video signal doubled in line numker per field, using the parallel filter circuit 75 described in Figure 2 and the line number doubler 223 described in Figure 3. Corresponding parts have the same reference numerals as in the foregoing Figures.

P~ 11 613 -13- 28-1-1986 In this case the input 1 is directly connected to the input 79 of the parallel filter circuit 75 and through a delay circuit 251 having a delay of one field pericd plus half a line period to the input 73 of the parallel filter circuit 75. The outputs 183 and 181 of the parallel filter circuit 75 are connected to the inputs 221 and 225, respectively, of the line num~er doubler 223. ~ switching signal of half the line frequency of the converted video signal is then applied to the operation signal input 247 of the change-over switch 246.
Figure 5 shcws a possible ernbodiment of a circuit for ok-taining a substantially interference-free video signal dcubled in line nurnker, incorporating a non linear fil.-ter circuit 71 as descriked in Figure 1 after a line number doubler 223 as descri~ed in Figure 3.
The input 1 is directly connected to the input 225 and to the input 221 of the line numker doubler 223 through a delay circuit 253 having a delay of one field period plus half a line period.
The output 239 of the line number dcubler 223 is connected to the input 11 of the non-linear filter circuit 71 and the output 241 fof the line nurr~er doubler 223 is connected to the input 3 and through a delay circuit 255 having a delay tirne of one line period of the converted signal to the input 9 of the non-linear filter circuit It is found that a change-over switch as in the circuits of Figures 3 and 4 is not required ~ecause the non-linear filter circuit 71 auto~atically selects the correct signal to be, reproduced.
When a second change-over switch operating with a phase opposed to that of the change-over switch 245 is provided at the outputs of the memories 235, 237 of the line nurrker doubler 223, a signaldelayed over two line periods can ke derived from this switch.
The input of the delay circuit 253 may then receive this signal delayed over two line periods instead of the signal from the input 1 and the delay time of the delay circuit 253 may be decreasedby two line periods.
The memories 235, 237 may ke serial memories which are written with their output signal during the accel.erated reading.
Figure 6 shows a variant of the circuit of Figure 3 in which a line numker doubler is incorporated in frcnt of the second comb filter circuit 220 instec~d of kehind the adder circuit 207.
Corresponding parts have the same reference numerals as in Figure 3.
The change-over switch 244 now swi-tches ketween the output of the adder PHN 11 613 -14- 28 1-19~6 circuit 207 and a delay circuit 256 having a delay of cne line period of the converted signal connected to the outFut 217 of the all-pass circuit 219 of the seeond comb filter circuit 220. The input 11 of the non-linear filter circult 71 now is eonnected v.ia a delay circuit 257 having a delay of one line period of the eonverted signal to the output of the delay circuit 13 which in this ease has a delay of one line Feriod of the eonverted signal, whils-t the input 209 of the adder eireuit 207 is connected via a delay circui.t 259 having a delay of line period of the converted signal is conneeted to the output 211 of the second ecmb filter cireuit 220.
The input 1 of the eircuit is eonnected to an input 261 of a line numker doubler 263 and to an input 267 thereof via a delay eireui-t 265 having a delay of one field period.
The line numker doubler 263 has three line memories 269, lS 271, 273, whose inputs ean be connected through two write switches 275, 277 to the input 267 or 261 and whose outputs ean be conneeted through a read switeh 279 to an output 281 of the line num~er doubler 263. The output 281 of the line numker doubler 263 is eonnected to the input of the second comb filter circuit 220.
In this case the seeond eomb filter cireuit 220 only com-prises delay elem~nts having a delay of one line period, and if desired, it may alternatively be designed as a recursive filter, for example, as a digital wave filter having only two delay elements.
An example of such a comb filter circuit designed as a transversal filter is shown in Figure 15.
The write and read switches 275, 277, 279 are operated in such a rhythm that lines of the signal at the input 261 and of the signal at the input 267 are alternately written in a different line memory, whilst between two write periods each memory is read at the double rate during half a line pericd of the signal to be converted.
A line from the present field, a line Erom the previous field, a second line from the present field, a second line from the previous field, a th.ird line from the present field and so forth then suceessive-ly occur at the output 281.
As a result video signals substantially originating from a line from the present field and from the previous field are alter-nately available at the outputs 203 oE the second eomb filter circuit 220, and this in the order in whieh they are positicned in a pieture .: -Pr~ 11 613 ~15 28-1-1986 so that substantially the video signals from three position-sequential lines from two fields are presented at the inputs 3, 9 and 11 of the non-linear fllter circuit 71.
A switching signal of half the line frequency of the con-verted video signal is ncw applied to the change-over signal input 247 of the change-over switch 244 so that alternately a video signal of a line from the present field and substantially of a non-linear filtered signal of three consecutive lines of two fields is obtained at the output 246 of the change-over switch 244.
If desired, the second comb fi.l-ter cjrcuit 220 may ~e omitted. The adder circuit 207 and the delay circuits 256 and 259 are then also omitted, whilst the input 3 of the non-linear filter circuit.
71 and that of the delay circuit 13 are then connected to the output 281 of the line number doubler 263 and the change-over switch 244 is then to swi.tch between the c~tput 21 and the input 9 of the non-linear fil.ter circuit 71.
The delay circuit 265 ard the line numker doubler 263 can be replaced by the circuit shcwn in Figure 4 in which the comb filter circuit 75 iS omitted and the input 221 of the line number doubler 223 iS connected to the output of the delay circuit 251 and the input 225 of the line doubler circuit 223 iS connected to the input 1.
In the video signal processing circuit o~ Figure 7 in which the same reference numerals have been used for corresponding parts as in the previcus Figures, a non-linear filter circuit 71 described in Figure 1 is used in an interpolation circuit incorporated after a field number dcubler 283.
An interl.aced video signal whose fields have been mentioned A, B, C, D, E, ..., is applied to the input 1 which is also the input of the field :numker doubler 283. The fields A, C, ... cover one field period plus halE a line period during doubling, the fields B, D, ...
cover one field period minus half a line period. A video signal whose field frequency is doubled and in which each field oE the input signal occurs twice in succession is then available at an output 285 of the field number doubler 283. This video signal is here referred to as A, A, B, B, C, C, D, D. This video signal is applied to the input 3 of the non-linear filter circuit 71~ to a change-over switch 287 and to a first input of a change-over switch 289.
:, ..

;23 The output of the ehange-over switeh 237 is conneeted through a series arrangement of delay circuits 291, 293, 295 to the input 11 of -the non-linear filter circuit 71. The other input of the change-over switch 287 is connected to the canneetion ketween the 5 delay cireuits 293 and 295. The delay eireuits 291, 293 and 295 have delay times of one line perlod, one field period minus one and a hald line periods of one line period respectively of the convertecl video signal.
The input g of the non-linear filter eireuit 71 ean ke connected via a ehange-over switeh 297 to the eonneetion ketween the delay cireuits 291, 293 or to that ketween the delay eireuits 293, 295.
Furthermore the input 11 of the non-linear filter cireuit 71 is eon-neeted to a second input of the change-over switch 289 a third input of whieh is connected to the output 21 of the non-linear filter lS eircuit 71. The output 298 of the ehange-over switeh 289 eonstitutes the output of the eireuit.
The circuit including the change-over switches 287, 289, 297, the delay cireuits 291, 293, 295 and -the non-linear filter cir-cuit 71 replaces an interpolation circuit and provides a ~eiter inter-ference suppression than the kncwn interpolation circuits.
The ehange-over switehes are to ke operated as follcws.
When the group of fields A, B, B, C is referred to as a switching cyclewhich is periodically repeatecl for the suksequent groups of fcur fields C, D, D, E; E, F, F, G and so forth and in which four switching intervals referred to as cne, two, three and four oeeur every time, the change-over switch 287 is to ke in the position shcwn in the intervals two and four, the ehange-over switeh 297 is -to ~e in the upper position shown in the interval two. Furthermore the ehange-over switeh 289 is to ke in the eentral position not shown in the inter-vals two and three, in the upper position shcwn in the in-terval four and in the lower position not shown in the interval one. In the inter-vals one and three the ehange-over switeh 287 is to ke in the position not shown and the ehange-over switch 297 is to ke in the position not shcwn in theinterval three. During the intervals one and four the position of the change-over switch 297 is not important beeause the ehange~over switeh 289 is then in its upper or lower position and the output signal of the eircuit is not obtained from the non-linear filter cireuit 71.

Due to the operation of the change-over switch 287 a cycle A, A, B, B which is thus delayed over approximately one field ~eriod of the original signal relative to the cycle B, B, C, C ~ecomes available in this cycle B, B, C, C at the input 11 of the non-linear filter circuit 71.
The change-over switch 297 ensures that a s.ignal is avail-able at the input 9 of the non-linear filter circuit 71 , which s.ignal is delayed over one line ~eriod during the interval three with respect to the signal at the input 3 and which occurs one l.ine perio~ earlier during the interval two with respect to the signal at the input 11.
As a result three pos.ition-sequential lines from two consecutive fields become available at the inputs 3, 9 and 11 of the non-linear filter circuit 71 during the intervals two and three, two lines from the field A and an interlocated line from the field B occur in the interval -two and two lines from the field B and an interlccated line from the field A occur in the interval three. In these intervals two and three the non~linear filter circuit 71 is therefore oeprative in the output signal kecause the change-over switch 289 is then in its central position.
In a first cycle a signal from the field A in the interval one, a non-linear filtered signal from three consecutive lines from the fields A and B in the intervals two and three and a signal from the field B in the interval four beccme available at the output 298. In the further cycle A is replaced by C and B by D and so forth.
The change-over switch 289 may be omitted when the change-over switch 297 is extended by two positions so that the input 9 of the non-linear filter circuit 71 is interconnected to the input 11 of the non-linear filter circuit 71 during the interval four and to the input 3 of the non-linear filter c.ircui.t 71 during the interval one.
E`igure 8 shcws hcw the video signal processing circui.t of Figure 7 is to be adapted when a parallel filter circuit 75 as des-cribed in Figure 2 is used. Corresponding parts have the sa~e reference numerals as in the previous Figures.
In this case the change-over switch 289 has only two positions and its inputs are connected to the outputs 183 and 181 of the parallel :Eilter circuit 75. In the intervals one and four the change-over switch 289 is in the lcwer positi.on not shcwn and the P~ l1 613 -18- 28 1~1986 output 29~ is connected to the output 181 of the parallel filter eircuit 75 from which it receives a non-proeessed delayed signal. In the upper position shown of the change-over switch 289, which position is to be assumed in intervals two and three, the output 298 is connected to the output 183 of the parallel filter eircuit 75 and receives a comb-filtered signal processed by the non-linear filter circuit 71 of the parallel fil-ter circuit 75.
The input 73 of the parallel filter eireui-t 75 is connected -through a change-over switch 301, which is in -the position not shc~n in the interval three, to the output 285 of the field number doubler 283 in this interval three and in the interval two, in which the ehange-over switch 301 is in the position shewn, it is eonneeted -to the output of delay eireuit 293. Since the signal at the input 73 crf t~e parallel filter cireuit 75 is not proeessed in the output signal during the intervals one and four, the position of the change-over switch 301 in these intervals one and four is not important.
The input 79 of the parallel filter circuit 75 is conneeted thrcugh a change-over switch 303 in the intervals one and two, in which the position not shown is assumed, to the output 285 of the field num~er doubler 283 and in the intervals three and four, in which the position shown oeeurs, it is conneeted to the output of the delay cireuit 295.
Figure 9 shows a noise suppression eireuit for a video signal applied to an input 1 in whieh a non-linear filter circuit 71 as described in Figure 1 is used. The output 21 of this non-linear filter circuit 71 is connected to an inverting input 305 of a subtractor cireuit 307 whose non-inverting input 309 reeeives the video signal originating from the input 1. An output 311 of the su~tractor cireui-t 307 is connected through a transfer cireuit 313 having a transfer faetor of k which may be, for example, movement dependent in known manner to an input 315 oE an adder eireuit 317 a further input 319 of whieh is also eonneeted to the output 21 of the non-linear filter eireuit 71.
An output 321 whieh also eonstitutes the output of -the eircuit is eonneeted through a delay eircuit 323 having a clelay of one field period minus half a line period to the input 3 of the non-linear filter eircuit 71 and to an input of a delay eircuit 325 having a delay of one line period and whose output is eonneeted to .

P~ 11 613 -19- 2~ 1986 the input 9 of the ncrl-linear filter cireuit 71 and to the input of a delay eireuit 327. The delay circuit 327 has a delay of one field pericd minus half a line pericd and an output thereof is ecnneeted to the input 11 of the non-linear filter circuit 71.
The non-linear filter circuit 71 then automatieally passes one of its three input signals that is most suitable for the most favourable noise suppression.
If so desired, a ec~b filter cireuit 220 and an adder cireuit 207 may be ineludecl, as shcwn in Figure 3, between the output lO of the delay circuit 323 and the intereonneeted inputs 305 and 319 of the subtraeting eireuit 307 and the adder eireuit 317.
In Figure 10 the non-linear filter eircuit 71 is used in a DP~ deccder 331 an input 333 of whieh is ec,nneeted to an output 335 of a quantising subtractor eireuit 337, a non-inverting input 339 oE which is connected to the input 1 and an inverting input 341 is eonneeted to an cutput 343 of the deecder 331 so that a DPCM eneoder is eonstituted. Corresponding parts have the same reference numerals as in the previous Figures.
The output 343 of the deecder 331 is connected to the out-put 21 of the non-linear filter circuit 71 whieh applies its output signal also to an input 345 of a dequantising adder eircuit 347 a further input 349 of which is conneeted to the input 333 of the de-ccder 331.
An output 350 of the dequantising adder cireuit 347 is eonneeted through a delay eireuit 351 having a delay of one field pericd minus half a line pericd to the input 3 of the non-linear filter eireuit 71 and to the input of a delay eireuit 353 having a delay of one line period whose output is eonneetecl tothe input 9 of the non-linear filter eireuit 71 and to the input of a delay eireuit 355.
The delay cireuit 355 has a delay of one field period ~inus half a line pericd and its cutput is eonneeted to the input 11 of the non-linear filter eireuit 71.
The quantising subtraetor eireuit 337 supplies a ecde for eaeh ineoming sample c~f the video signal, whieh ecde eorresponds to a value dependent on the differenee in amplitude between the video signal at the output 343 of the deecder 331 and the amplitude of the video signal sample at the input 1.
Tho deeoder 333 is an integrator eireuit in which the valne -~8~

of thecode is added to a value of a video signal sample whose position in the pict.ure substantially c~rresponds to the posi.tion in the pic-ture of the sample at the input 1. The most suitable position yielding the most accurate result for integration is then determined ~y the non-linear filter circuit 71.
In Figure11 the same reference numerals have been used as in the previous Figures for corresponding parts. The input 1 is con-nected to the input 3 of the non-linear filter circuit 71 whose input 9 is connected through a delay circuit 359 to the input 1 and the input 11 is connected through a delay circuit 361 to the output of the delay circuit 359. The delay circuit 359 has a delay of one line period, the delay circuit 361 has a delay of one field period minus half a line period. The non-linear filter circuit 71 therefore re-ceives a video signal of two lines from the present field and an interlocated line from the previous field and passes on at any moment the value closest to the mean value of these three video signals to its output 21. The output 21 of the non-linear filter circuit 71 is con-nected to an input 363 of an adder and subtractor circuit 365 and to a further input 369 thereof through a delay circuit 367 having a delay Of one line period. A third input 371 of the adder and subtractor cir-cuit 365 is connected to the output of the delay circuit 359 which is furthermore connected to an input 373 of an adder circuit 375. A fur-ther input 377 of this adder circuit 375 is connected to an output 381 of the adder and subtractor circuit 365, through a transfer cir-cuit 379 having a, possibly controllable, transfer factor of k. Anoutput 383 of the adder circuit 375 constit.utes the C~1tpUt of the circuit serving as a vertical contour correction circuit.
Of the video signals applied to the inputs of the adder and subtractor circuit 365 half the sum of the signals at the inputs 363 and 369 is subtracted from the signal at the input 371 and thi.s difference is passed on to the output 381. This half sum is the~ean value of the values closest to the mean values in the two conse-cutive line periods of the video signals of three vertically sequential line, the signal corresponding to the central line being applied to the input 371 of the adder and subtractor circuit 365. The signal at the output 381 of the adder and subtractor circuit 365 produces a transient correction signal through the transfer circuit 379 at the input 377 of the adder circuit 375, which signal is added to the signal

2~
PHN 11 6~3 -21- 28-1-1986 of the said central line applied to the input 373 so that a contcur correction which is as favcurable as possible at any mc,ment is ob-tained.
Figure 12 shows how the vertical contour correction cir-cuit of Figure 11 is to be adapted when the parallel filter circuit75 of Figure 4 and Figure 2 is used. Corresponding parts have the same reference numerals as in the previous F'igures to which reference is made for their further description.
The input 363 of -the adder and subtractor circuit 365 con-nected to the input of the delay circuit 367 is now connected to theoutput 183 of the parallel filter circuit 75, whilst the input 373 of the adder circuit 375 connected to the input 371 of the adder and sub-tractor circuit 365 is connected to the output 181 of the parallel filter circuit 75 through a delay circuit 385 having a delay of one lS line period. The latter delay circuit 385 may be omitted, if desired, when the branch to the output 181 on the relevant comb filter in the parallel filter circuit 75 is taken one line period later.
In Figure 13 in which corresponding parts have the same reference numerals as in the previous Figures to which reference is made for their further description, an interlaced video signal whose line number per field is to be virtually halved, fcr exarnple, fram 624.5 to 312.5 is applied to the input 1. This signal is applied through a delay circuit 401 having a delay of one field period plus half a line period of the video signal to be converted to the input 2s 73 of the parallel filter circuit 75 described with reference to Figure 2.
The output 183 of the parallel filter circuit 75 applies a filtered video signal to an input 403 of an interpolation circuit 405. The output 181 of the parallel filter circuit 75 applies a non-processed video signal to an input 407 of the interpolation circuit405, which signal has a delay adapted to the delay of the video signal at the input 403.
The interpolation circuit 405 is structurally e~ual to the comb filter circuit 77 of Figure 2 without the subtractor circuit lhl 3s and the outputs 165 and 181 and has for its object to suppress fre-quency components of more than 312 pericds per picture height. The coefficients of the coefficient circuits 143, 111, 123, 113, 125, 115, 127, 117 and 129 may have, for example, the values 0, 0, -1/8, P~LN 11 613 -22- 28-1-1986 1/4, 3/4, 1/4, -1/~, 0 and 0, respectively. The values of the coeffi-cients of the c oefficient circuits 145, 103, 131, 105, 133, 107, 135, 109 and 137 are equal thereto.
The interpolaticn circuit ~05 has cutputs 409 and 411 ccrresponding to the outputs 157 and 177, respectively, of the ccmb fil-ter circuit 77 of Figure 2. Each of these cutputs 409 and 411 is connected to an input of an adder circuit 413 an output of which is connected to an input 415 of, for example, a kn~wn line number halving circuit 417 an output of which supplies the desired signal with a great freedcm from interference.
Figure 14, in which corresponding parts have the same reference numerals as in the previous Figures and to which reference is made for their further description, shcws a simplified embcdiment of the circuit of Figure 13. The input 407 of the interpolation circuit 405 in this case is connected tc the input 1 of the circuit which is also connected to the input 3 of the ncn-linear filter circuit 71 described with reference to Figure 1. The input 9 of the non-linear filter circuit 71 is connected to an cutput of a delay circuit 431 having a delay of cne line period and to which also an input of a delay circuit 433 having a delay of one field pexiod minus half a line pericd is connected whose cutput is connected to the input 11 of the non-linear filter circuit 71.
Fig~re 15 shows a possible embcdiment of the second comb filter circuit 220 for use in the circuit of Figure 6. A series ar-rangement of delay elements 421, 423, 425, 427, 429 and 431 eachhaving a delay of one line period is connected to the input 281. The inputs and outputs thereof are connected through coefficient circuits 433, 435, 437, 439, 441, 443 and 445 to an adder circuit 447 an outpu-t 44~ of which is connected to the cutput 203 and to an :inverting input 451 of a subtractor circuit 453, a non-inverting inpl1t 455 of which is connected to the output of the delay element 425 which is further connected to the C~ltpUt 217. The cutput of the subtractor c.ircuit 453 is connected to the cutput 211 of the comb filter circuit.
In Figure 16, in which compcnents ccrresponding to those of the preceding Figures, have been given the same reference nu~erals, the output 21 of the ncn-linear filter circuit 71 is connected to an input 501 of a subtracting circuit 503 a further input 505 cf which is con-nected to the input 11 of the non-linear filter circuit 71.

An output 507 of the subtraeting cireuit 503 then applies a movement indication signal to an input 509 of a high-pass filter 511 from an output 513 of whieh a signal is obtained which is motlon-dependent but has substantially zero value when a stationary vertical 5 transient occurs in the picture, so that this transient is not detected as movement.
If the circuit is used subsequent to a line num~er doubler, for example the doubler shcwn in Eigure 6, then the delay circuit 7, which in the Figure prcduces a delay of one field period minus half a line period is replaced by a delay eireuit produeing a delay of a line pericd and the input 505 of the subtraeting eircuit 503 is connected to the input 9 of the non-linear filter eireuit 71.
In Figure 17 ecmponents corresponding to those in the preceding Figures have been given the same reference numerals. A line 15 number doubler circuit 265, 263 is follcwed by a non-linear filter eir-euit 13, 257, 71 as deseribed with reference to Figure 6. That input of the change-over switch 244 not eonnected to the output of the non-linear filter eireuit 71 is ~ere eonnected to the input 9 of the non-linear filter circuit 71.
The output 246 of the change-over circuit 244 is ccnnected to the input 363 of the adder - and - subtracting eireuit 365 and to an input of a delay circuit 515 prolucing a delay of one line pericd, whose output is eonneeted to the input of the delay circuit 367, to the input 371 of the adder-and-subtracting circuit 365 and to -the 26 input 373 of the adder circuit 375.
The line n~un~er dcubler and filter eireuits preeeding the input of the delay eireuit 515 and the input 363 of the adder-and-sub-traetling eireuit 365 may, if so desired be replaeed by those of F`igures

3, 4, 5 or 6.
In Figure 18, in whieh eomponents eorresponding to those of -the preeeding Figures have been given the same reference numerals, i-t is shewn hcw in a ecmbination of a line num~er dcubler 265, 263 a ncn-linear filter cireuit 71 and a comb filter circuit 517, this ecmb filter eireuit ean be arranged subsequent~to the non-linear filter circuit. This renders it possible to design the eomb filter eireuit sueh that, independently of eaeh cther, the transient response and the suppression of the unwanted signal ecmporlents resulting from the non-linear cperation, ean be rendered as advantageous as possible.

P~ 11 613 -24- 28-1-1986 The ccmb filter circuit 517 is a complementary circuit and has two complementarily filtering signal paths from two inputs 519, 521 to a combining circuit 523 which in this case is in the form of an adder circuit, an output 525 of which is connected to one of the inputs of the change-over switch 244. The respective inpu-ts 519 and 521 of the complementary comb filter circuit 517 are connected to -the output 21 and the inpu-t 9, respectively of the non-linear filter circuit 71.
For clarity's sake -the drawing shcws the complementary comb filter circuit 517 with two comb filters 527, 529. Each of these filters may be implemented as shcwn in Figure 15, the subtracting circuit 453 and the output 217 then being omitted.
For an advantageous structure the coefficients can be chosen as follcws:
Coefficient Filter 527 Filter 529 433 +0.0625 -0.0625 435 -0.1975 +0.1875 437 -~0.1875 -0.1875 439 +0.8750 +0.1250 441 +0.1875 -0.1875 443 -0.1875 +0.1875 445 +0.0625 -0.0625 Thus, the requirements to be imposed on the comb filter 529 are satisfied. These requirements are: the attenuation of the fre-quencies of a number of periods per picture height in the region of25 one third of the num~er of picture lines, caused by the non-linear filter 71, must be corrected, as must also the 180 phase shift then occurring, the phase characteristic must be linear, at frequencies of a num~er of periods per picture height equal to half the num~er of picture lines the attenuation must be at its mc~ximum, the d.c.
current transfer must ke equal to unity and the frequency characteris-tic for frequencies near zero periods per picture height must be as flat as possible.
If the number of delay lines and coefficients of the comb filter 529 are increased, then the frequency characteristic can be kept flatter to near the frequency corresponding to half the num~er of picture lines per picture height and the attenuation at that fre-quency can be increased, which is advantageous for still pictures.

. .

For moving pic-tures the described composition is an advantageous composition.
One of the comb filters 527 or 529 can be replaced by a delay circuit when the relevant, respective, inputs 521 and 519 of the complementary comb filter circuit and the further, respective, inputs 519 and 521 are connected to the input of the ccmb filters 529 and 527, respectively, vla a subtracting circuit. Depending on the sign of the transfer from each input to the output of the relevant sub-tracting circuit, the combining circuit 523 must be either an adder or a subtracting circuit.
The line doubler and non-linear filter circuit 2~5, 263, 13, 257, 71 can be replaced by the line numker doubler and non-linear filter circuit 253, 223, 255, 71 of Figure 5. The input 521 of the complementary comb filter circuit 517, connected to the relevant input of the change-over switch 244 must then be connected to the input 3 of the non-linear filter circuit 71.
When the complementary comb filter circuit 517 is of the structure as shcwn in the Figure, the comb filter 527 may, if so desired, be structured such that in addition a vertical contour cor-rection is obtained. The lower input of the change-over switch 244 must then ~e connected to the output of the comb filter 527.
In Figure 19, in which components corresponding to those shown in the preceding Figures have been given the same reference numerals, it is shown that a control circuit 530 can be substituted for the complementary comb filter 517 of Figure 18.
A video signal is applied from the output 21 of the non-linear filter circuit 71 to an input 533 of an amplitude ratio control circuit 535 via an input 531 of the control circuit 530. The video signal at the input 9 of the non-linear filter circuit 71 is applied via an input 537 of the control circuit 530 to a further input 539 of the amplitude ratio control circuit 535. An output 541 of the amplitude ratio control circuit 535 is connected to the upper input of the change-over switch 244.
A control signal input 543 of the amplitude ratio control circuit 535 is connected to an output of a function generator 545, which may ~e in the form of a programmable read-only memory (PROM). The function generator 545 receives a signal from an output of an absolute-difference value determining circuit 547 whose inputs are connected , PHN 11 613 -26- 28~ 1986 to the outputs of two absolute-difference value determin.ing circuits 549 and 551, which determine the absolute difference value ketween the slgnals at the input 531 and 537, respectively of -the control circuit 530 and the output signal of an averaging circuit 552 whose inputs 553, 555, 557 are connected to the respective inputs 11 and 9, 3 of the non-linear filter circuit 71~
Obtaining the control signal for the amplitude ratio control circuit 535 is k~sed on the following considerations. The non-linear filter circuit 71 attenuates freq~lencies whose num~er of periods per picture height is approximately equal to one third of the num~er of lines per picture to the highest possible extent and then prcduces the highest degree of distortion. The energy transfer is at its lowest at those frequencies. A measure of this frequency transfer can ke obtained using the absolute-difference value determining circuits 549, 551 and 547. When the energy transfer from the non-linear filter 71 is low, the transfer factor k from the input 539 to the cutput 541 of the amplitude ratio control circuit 535 must be made large by the control signal at the input 543 thereof, so that a non-distorted signal transfer is effected. When the energy transfer is great, then the transfer factor k is made small and the transfer 1-k from the input 533 to the cutput 541 of the amplitude ratio control circuit 535 becomes large, so that the non-linear filter 71 is thus made operative.
If so desired, a change-over switch can be used instead of a continuously controllable amplitude ratio control circuit 535.
The f~mction generatcr 545 can provide a control behaviour adapted to the users's wishes and a threshold action.
The remarks made in the description with reference to Figure 18 on the possible use of a different line numker doubler circuit al.so hold here.
The control circuit 530 can also be used in other applica-tions of the non-linear filter 71 when invariably the video signal corresponding to the central line of three consecutive picture lines is applied to the input 555 of the averaging circuit 552 cmd to the input 537 of the control circuit 530. The averaging circuit 552 has, as is shc~n in the picture, a transfer factor equal to one fourth from its inputs 553 and 557 to its output and equal to one half fram its input 535 to its cutput.
In Figure 20, in which components corresponding to those of PHN 11 613 -27- 28~1~1986 the preceding pictures have been given the sa~e reference numerals, it is shown how the control signal-producing portion of the control circuit 530 of Figure 19 can be structured in a different manner.
To that end, delay circuits 561 and 563, respeetively, producing a delay equal to one line period, are arranged between the output 281 of the line doubler circuit 263 and the input of the delay circuit 13 and after the ou-tput of the delay circuit 257.
Inputs 565 and 567, 569, respectively and 571, 573, 575 oE
the control circuit 530 are connectecl to, respectively, the CltpUt 281 of the line numker doubler and the output oE the respective delay circuits 561, 13, ~57, 563. The inputs 573, 569 and 575, 567 and 571, 565, respectively of the control circuit 530 are connected to the inputs of an absolute-difference value determining circuit 575 and 577, 579, respectively, whose outputs are corm-ected to an input oE respective 15 absolute-difference value determining circuits 581, 583 and 585, whose Eurther inputs are connected to an output of a threshold value generating circuit 587. The outputs of the absolute-diEference determin-ing circuits 581, 583, 585 are connected to inputs of the function generator 545.
Video signals obtained from iive directly superjacent lines of two fields are ncw present at the output 281 of -the line doubler 263 and at the outputs of the delay circuits 561, 13, 257, 563. Frequencies having numkers of periods in the region of one third of the numker of picture lines per picture height can now be detected with the aid of the 25 absolute~diEference value determining circuits 575, 577, 579, 581, 583, 585 and the function generator 5~5. When these frequencies are indeed present, then the non-linear filter 71 is switched-off by the amplitude ratio control eireuit 535, as deseribed with reference to Figure 19.
These frequencies are present when continuously at least two oE the output voltages of the absolute difEerence value determining cireuits 575, 577, 579 exceed the threshold value applied to the absolute-cliEEerence value determining circuits 581, 583, 585.
Also here it holds that the use in other video signa1.
proeessing eireuits including a non-linear filter is possible when video signals from five directly superjacent lines oE two fields are applied to the inputs of the absolute-difference value determining circuits and video signals from the three centre lines of these lines are applied to the non-linear filter circuit 71.

P~ 11 613 -28- 28-1-1986 In Figure 21, in which cornponents corresponding to those of preceding picture have been given the sarne reference nurr.erals, the non-linear filter circuit 71 is preceded by a direction correction circuit 601.
Three inputs 603, 609, 611 of this correction circuit receive video signals which correspond to three ver-tically in-line pic-ture elerrents of three position-sequential lines from two consecu-t.ive interlaced fields of a picture to be displayed. The video signal corresponding to the central picture element is, for example, applied to the input 609 and via a delay circwit 613 producing a time delay correspcnding, for example, to the duration of a picture element and an output 615 of the direction correction circuit 601 to the input 9 of the non-linear circuit 71.
The input 603 of the direction correction circuit 601 is ccnnected to a series arrangement of two delay eireuits 617, 618, each prcducing the sarne time delay as the delay circuit 613, and to the lcwest of three inputs of the upper change-over switch of a direction selection circuit 621. The upper and central inpwt, respectively of these three inputs is connected to the output of the delay circuit 619 and 617, respecti~7ely.
The input 611 of the direction correction circuit 601 is connected to a series arrangemen-t of two delay circuits 623, 625 which each!! also produee the same time delay as the delay circuit 613, and to the highest input of the three inputs of the low~r change-over switch of the direction selection circuit 621. The lcwest and central input, respectively of these three inputs is connected to the cutput of the respective delay circuits 625 and 623.
The output of the highest and lcwest change-over sw.itch, respectively of the direction selection switch 621 is co~nected to the input 3 and 11, respectively of the non-linear :Eilter circuit vla an output 627 and 629, respectively of the direction correction circuit 601. It will be obvious that the direction selection circuit 621 is an elec-tronic circuit. It is operated by a direction selectionsignal combination applied to its input c~nbination 631 and received from an output combination 633 o:E a function generator 635 which is in the form of, for exarnple, a pro~rammable read-only memory (PROMj.
The f~mction generator 635 has five .inputs 637 and 639, 641, 643, 645, respectively, which are connected to an ou-tput of the respec-P~ 11 613 -29- 2~-1-1g~6 t.ive comparator circuits 647 and 649, 651, 653, 655. The canparator circuit 647 and 649, respectlvely cc~pares the signal value pro~uced by an absolute-difference value determining circuit 657 and 659, res-pec-tively to a threshold value received from a thre.hold value generator 661.
An input of the absolute-difference value deter~uning cir-cuit 647 and 649, respectively is connected to the output of an absolute-difference value determining circuit 663, 665. A further inFu-t of the absolute-difference value determining circuit 657 and 659, respectively is connected to the output of an absolute-difference value determining circuit 665 and 667, respectively. The output of the absolute-difference value determining circuit 663 is hlrther connected to an input of the canparator circuits 651 and 655, the cutput oE the absolute-difference determining circuit 665 to an input of the c~nparator circuits 651 and 653 and the output of the absolute-difference value determining circuit 667 to an input of the canparator circuits 653 and 655.
If the upper, the central and the lcwer position, respective-ly of the direction selection circuit 621 is denoted I, II and III, respectively and the signals at the respective inputs 637 and 639, 641, 643 and 645 of the function generator 635 are denoted A and B, C, D, E, respectively, then the follcwing Table holds for the positions I and III. In all the other cases the position II is assumed.
A B C D E position 621 o 0 0 O

In this situation it is assumsd that C and D, E, respectively have logic one value when the output value of the circuit 663 exceeds the. output value of -the circuit 665, the output value of circuit 667 , P~ 11 613 -30- 28-1-1936 exceeds that of -the circuit 665 and the output value of the circuit 667 exceeds that of the circuit 663, respectively.
This implies that the non-linear filter circuit 71 receives video signals from picture elements which, depending on the direction of a contcur, are on top of each other in a direction corresponding to tha direc-tion of that contour ~s ~ result of which an improved noise suppression by -the non-linear filter circuit 71 is obtained.
The direction correction circuit can be used in all the described cases, but the delay equal to one pic-ture element this correction circuit produces, must be -taken account of. With the excep-tion of the delay circuits, a]l the further circuits connected to the inputs 3, 9 and 11 of the non-linear circuits then remain connected thereto.
If so desired, the direction correction circuit 601 can be extended such that in the signal paths from the inputs 603 and 611 to the direction selection circuit 621 and the function generator 635 video signals corresponding to rnore picture elements can be used for selecting more contcur directions.

Claims (16)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PRO-PERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A video signal processing circuit for processing an interlaced video signal, comprising a motion-adaptive selection circuit operable by means of a decision circuit, which selection circuit has three inputs coupled to a video signal source for applying video signals thereto substan-tially corresponding to three position-sequential lines of two fields, and an output characterized in that the decision circuit has three inputs each being coupled to an input of the selection circuit and is arranged for determining at any moment at which input of the selection circuit the amplitude of the video signal applied thereto is closest to the mean value of the amplitudes at the three inputs, whilst the selection circuit includes a circuit for coupling said input to its output under the influence of the decision circuit.

2. A video signal processing circuit as claimed in Claim 1, characterized in that it includes a comb filter circuit for applying video signals to the inputs of the selection circuit being comb-filtered in such a manner that signal components having a periodicity in the vertical direction corresponding to three picture lines are suppressed therein, when corresponding to two picture lines, are passed when corresponding to more than four picture lines are likewise passed and that signal transients sub-stantially do not show ringing in the vertical direction.

3. A video signal processing circuit as claimed in Claim 1 or 2, characterized in that the decision circuit includes three comparison circuits each having an input pair which is coupled to another pair of the inputs of the selection circuit and whose outputs are coupled to an address input combination of a read-only memory, whilst the read-only memory has an output combination which is coupled to an operation signal input combination of the selection

4. A video signal processing circuit as claimed in Claim 1 or 2, characterized in that it includes a line number doubling circuit one input of which is coupled at least through the selection circuit and another input is coupled through a delay circuit to the video signal source.

5. A video signal processing circuit as claimed in Claim 1 or 2, characterized in that the video signal pro-cessing circuit includes a line number doubling circuit one input of which is connected at least through a delay cir-cuit having a delay of one field period plus half a line period and another input of which is directly coupled to the video signal source.

6. A video signal processing circuit as claimed in Claim 1 or 2, characterized in that it includes a line number doubler having three line memories with writing cycli partially overlapping each other.

7. A video signal processing circuit as claimed in Claim 1 or 2, characterized in that the video signal source includes a field number doubler of the A, A, B, B, type.

8. A video signal processing circuit as claimed in Claim 1, characterized in that it is a recursive noise reduction circuit having a feedback path incorporating the selection circuit.

9. A video signal processing circuit as claimed in Claim 1, characterized in that it is a DPCM decoder an input of which is coupled to an input of an adder circuit a further input of which is connected through a delay circuit to an output of the adder circuit, which delay cir-cuit includes the selection circuit.

10. A video signal processing circuit as claimed in Claim 1, characterized in that an output of the selection circuit is coupled to an input of an adder an subtractor circuit forming a vertical contour correction signal and to a further input thereof through a delay circuit having a delay of one line period, said adder and subtractor cir-cuit having a third input which is coupled to an input of the selection circuit.

11. A video signal processing circuit as claimed in Claim 2, characterized in that the comb filter circuit has two outputs which through a delay circuit and directly with a delay of one line period with respect to each other can apply comb-filtered signals to two inputs of an adder and subtractor circuit a third input of which is coupled through a delay circuit having a delay of one line period to one of the said outputs of the comb filter circuit, said adder and subtractor circuit being able to supply a contour correction signal.

12. A video signal processing circuit as claimed in Claim 1 or 2, characterized in that it includes a line number halving circuit which is coupled at least through an interpolation circuit to the selection circuit.

13. A video signal processing circuit as claimed in Claim 1, characterized in that connected to the output of the selection circuit is an input of a subtracting circuit a further input of which is connected to the input of the decision circuit to which a video signal from a previous field is applied so that at an output of the subtracting circuit a movement indication signal is obtained.

14. A video signal processing circuit as claimed in Claim 1, characterized in that it includes a line number doubler circuit whose output circuit is coupled to the input circuit of the decision and selection circuit serving as a non-linear filter circuit and that the output and an input of the decision and selection circuit are coupled to the inputs of a change-over switch via a complementary comb fil-ter circuit.

15. A video signal processing circuit as claimed in Claim 1, characterized in that it includes a control cir-cuit coupled to the output and to the input circuit of the decision and selection circuit serving as a non-linear fil-ter circuit.

16. A video signal processing circuit as claimed in Claim 1, 2 or 8, characterized in that a direction correc-tion circuit is coupled to the input circuit of the decision and selection circuit which serves as a non-linear filter circuit.