CA1252912A - Semiconductor package with high density i/o lead connection - Google Patents

Semiconductor package with high density i/o lead connection

Info

Publication number
CA1252912A
CA1252912A CA000537983A CA537983A CA1252912A CA 1252912 A CA1252912 A CA 1252912A CA 000537983 A CA000537983 A CA 000537983A CA 537983 A CA537983 A CA 537983A CA 1252912 A CA1252912 A CA 1252912A
Authority
CA
Canada
Prior art keywords
fingers
conductive fingers
paddle
package according
mils
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000537983A
Other languages
French (fr)
Inventor
Lawrence A. Greenberg
David J. Lando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Application granted granted Critical
Publication of CA1252912A publication Critical patent/CA1252912A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Abstract

SEMICONDUCTOR PACKAGE WITH HIGH DENSITY
I/O LEAD CONNECTION

Abstract Disclosed is a semiconductor package which permits coupling of semiconductor bond pads to I/O leads where a high density of connections is needed. Conductive fingers backed by an insulating tape are bonded to the ends of the fingers on a lead frame. The tape fingers are electrically coupled to the bond pads on one major surface of the semiconductor chip by wire bonding.
In one embodiment, the opposite major surface of the chip is bonded to a paddle on the lead frame through an aperture in the tape for maximum heat dissipation.

Description

~2,~

SEMICONDUCTOR PACKAGE WIT~I HIG~ DENSITY
I/O LEAD CONNECTION

Psack~round Q~
This invention relates to semiconductor device packages, and in 5 particular to a package requiring a high density of connections from the semiconductor to external leads.
In standard semiconductor device packaging, the semiconductor chip is electrically connected to outside circuitry by means of a lead frame. The lead frame may be thought of as a solid metal picture frame with fingers radiating 10 inward from either two opposing sides or from all four sides toward the geometric center of the frame. Also radiating inward from each of the four corners of the fralne is a ~lnger which terminates on a square or rectangular piece of metal, typically referred to as a paddle, which occupies a portion of the geometric center. One major surface of the chip is bonded to the paddle, and 15 contact pads on the opposite surface are electrically coupled to the lead frame fingers by bonding conductive wires to the pads and fingers. The chip and a portion of the lead frame fingers are then encapsulated or molded in a material such as an epoxy or plastic molding compound, and the molded package body and lead frame fingers are cut from the frame. The lead frame fingers are then 20 formed to provide a means of electrically connecting the package to the second level interconnection board, which is typically a printed circuit board. The severed fingers therefore constitute the I/O (Input/Output) leads for the semiconductor chip.
This standard packaging scheme generally has been satisfactory.
25 However, a problem exists where a high density of connections is required between the chip contact pads and the lead frame fingers due to a great number of such contacts and/or smaller than standard chip sizes. In such cases, it is difficult to fabricate the fingers sufficiently close together to accommodate the high denslty of interconnections. For example, lead frame fingers cannot 30 usually be made with less than a 16 mil ~.4 mm) pitch (the distance between the center of two adjacent fingers). In order to provide connection to a chip with 50 pads on a chip side having standard dimensions (320 mils or 8 mm), the ends of the fingers can only be brought to within approximately 2~0 mils ~6.1 mm) of
- 2-the chip due to the limit on pitch. This tends to cause sagging and shorting of the wires between the pads and fingers.
One solution to the problem of high density I/O connections involves use of multi-level ceramic or glass packages ~see, e.g., U. S. Patent 4,49~,122). While adequate, such packages are fairly expensive. One possible alternative which has been proposed recently is to provide a multi-level lead frame structure for connecting the chip. It is desirable to provide a further alternative package for high density connections.
A further problem which exists in many semiconductor packages is 10 inadequate heat removal from the chip during operation. This is more troublesome as chips become more complex and are required to do more functions. It is, therefore, also desirable to provide a semiconductor package with efficient heat dissipation.
~smm~ ~ the I~e~i~
The invention is a semiconductor device package comprising a mounting pad and a plurality of first conductive fingers with one end of each in close proximity to the pad and defining a first gap therebetween. A plurality of second conductive fingers, which are formed on an insulating film, extend over the gap with one end of said second conductive fingers bonded to corresponding i~lrst conductive fingers and the opposite end of the second conductive fingers terminating in close lateral proximity to the pad to dei~lne a second gap therebetween which is less than the first gap.
~12~i~ Q~ ~h~ nrawing, In the drawing:
FIG.lis a plan view of a semiconductor device package at one stage of fabrication in accordance with one embodiment of the invention;
FIGS.2 and 3 are magni~led portions of a package, partially broken away, during further stages of fabrication in accordance with the same embodiment;
FIG. ~i is a perspective view of a portion o~ a semiconductor package in accordance with a further embodiment of the invention; and FIG.5is a perspective view of the semiconductor package in a final stage of manufacture.

~2,~
- 3 -It will be appreciated that for purposes of illustration, there figures are not necessarily drawn to scale.
Detailed l~cription Packaging of a semiconductor device starts with a standard type of lead 5 frame such as illustrated in FIG. 1. The lead frame, 10~ includes a first plurality of conductive fingers, such as 11, radiating inward from the solid picture-frame-like perimeter, 12. In this example, the fingers are present on all four sides of the perimeter, but may also be present on any lesser number of sides. The lead frame also includes a paddle, 13, located at the center, with a second plurality10 of conductive fingers, such as 1~, coupled to the paddle and extending to thefour corners of the perimeter. A gap, such as 15, is formed between the first plurality of conductive fingers (11) and the paddle on all four sides of the paddle. The paddle, fingers and perimeter are typically formed from a sheet of metal such as alloyed copper.
For a typical high-density interconnection package, the frame includes a total of 200 fingers, such as 11, extending to each side of the paddle (50 on each side). ~t their narrowest point, the fingers are approximately 8 mils (.2 mm) wide with a spacing of 8 mils (.2 mm) between each finger on a side (thus producing a 16 mil (.4 mm) pitch). The paddle is typically approximately 20 350 mils x 350 mils (8.9 x 8.9 mm). The gap, 15, between the paddle and the fingers is approximately 10 mils (.25 mm). It would be desirable to bring the conductive fingers closer to the semiconductor device to be bonded to the paddle, but it is difficult to do this since the fingers cannot generally be made narrower than 8 mils (.2 mm). This width limitation is due primarily to the fact25 that a lead frame is e-tched from a sheet of metal approximately 8 mils (.2 mm) thick and the etching features are limited to the thickness. (The lead frame can also be stamped from sheet metal, but similar dimensional limitations apply.) Therefore, in orde~r to provide for the high density interconnection, an 30 additional element is provided to bridge the gap between the lead frame and paddle. As illustrated in FIG. 2, which is a magnified view of the central portions of the lead frame, this element comprises a third plurality of conductive fingers, such as 16, formed on an insulating layer 17 mounted on the paddle 13. These conductive fingers correspond in number and position to the
- 4 -conductive fingers of the lead frame and have their outer ends (23) extending approximately 10 mils (.25 mm) beyond the insulating layer and bonded to the upper surface of an associated conductive finger, while their inner ends (24) form a gap, 40, extencling approximately 10 mils (.25mm) from the sides of a
5 hole, 18, formed in the insulating layer. The insulating layer, 17, could extend all the way out to the outer ends, 23, of the fingers 16, in which case the flngers 16 would be bonded to the underside of the lead frame fingers 11. The inner ends, 24, of the conductive fingers 16 could also extend right up to the sides of the hole, 18. ~lso, although the outer dimension of the insulating layer, 17, islO shown as slightly smaller than the paddle, it could be equal to or greater than the size of the paddle). The portion of the paddle, 13, exposed by the hole, 18,forms a mounting pad 41 for a semiconductor chip to be described. The f~lngers 16 form a gap 40 with the pad which is less than the gap 42 between the lead frame fingers 11 and the pad.
In this example, the additional element was formed from a wire-bondable tape which was supplied by 3M Company for Tape Automated Bonding (TAB) packages. The conductive f~lngers were made of 99.9% copper plated to a thickness of approximately 2 mils (.05 mm) and each had a width of 8 mils (.2 mm) and a separation between fingers of approximately ~ mils (.05 mm) to 20 produce a pitch of 10 mils (.25 mm). The fingers, 16, can be placed closer together than the lead frame fingers 11, since the former are fabricatecl by plating rather than etching or stamping. Further, even if ïingers 16 were etched, they are thinner and so can be placed closer together. The insulating layer, 17, which provided mechanical backing for the fingers, was made of 25 polyimide and was approximately 3 mils (.08 mm) thick. The standard tape was modified by punching the hole, 18, in the insulator 17 at the center. The hole measured approximately 250 mils x 250 mils (6.4 x B.4 mm).
The insulating layer, 17, was bonded to the underlying paddle, 13, and the conductive fingers on the insulator (e.g., 16) were bonded to their 30 corresponding fingers of the lead frame (e.g., 11) by thermocompression bonding. This typically involves heating the structure at a temperature of approximately 550 degrees C for .2 seconds while applying pressure of approximately 4û PSI (.28 M Pa).

As illustrated in FI(~. 3, which is also a magnified view of the central portion of the lead frame, the semiconductor chip, 20, was placed in the hole 18of the insulating layer 17 so that the back surface of the chip was in mechanical contact with the mounting portion of the underlying paddle, 13. The chip was 5 bonded to the paddle by conductive epoxy. The paddle and connected fingers, 14, therefore provided a ground connection to the back surface of the chip.
Further, the paddle provided an excellent heat sink during the operation of the chip. In particular, the calculated heat dissipation for a 148 pin package assuming natural convection cooling was approximately 32 degrees per watt for 10 this embodiment, which was approximately 3 degrees per watt better than when the chip was bonded to a conductive pad on the tape (FIG. 4). The chip measured approximately 190 mils x 200 mils (4.8 x 5.1 mm).
As also illustrated in FIG. 3, the front surface of the chip, 20, included a plurality of bonding pads, such as 21, on its periphery. These pads were made lS of aluminum with a thickness of approximately 1 micron and measured approximately 4 mils x ~ mils (.1 x .1 mm). The pads were also spaced approximately 4 mils (.1 mm) apart. Electrical connection between each of these pads and their corresponding conduct;ve fingers on the insulating layer was provided by wires (e.g., 22) attached to the pad and finger by standard wire20 bonding techniques. This involved ball bonding one end of a wire to a pad andthen wedge bonding the other end of the wire to the conductive fïnger while heating to a temperature of 200 degrees C.
It will be appreciated, therefore, that the smaller pitch o~ the conductive fingers (e.g., 16) formed on the insulating layer 17 permits the fingers to be 25 brought closer to the semiconductor device, 20, than is practical for the lead frame fingers for a high density interconnect package. This allows a relatively short span for the wires (e.g., 22) to traverse and thereby reduces the possibility of failures in the wi.e connections. In general, it is desirable to have wires spanning less than 150 mils (3.8 mm) distance. In this example, the wires were 30 approximately 70 mils (1.8 mm) long. Further, since the device is bonded directly to the underlying paddle, 13, heat dissipation is maximizecl.
While the embodiment of FIG. 3 appears preferable in terms of ma~imum heat dissipation, the embodiment illustrated in FIG. 4, where corresponding elements are similarly numbered, may also be useful. ~For the sake of clarity, . ~ , . .

- B -the lead frame is not shown in FIG. 4.) It will be noted that the major distinction in the embodiment of FIG. 4 is that the device, 20, is bonded to a conductive material pad, 30, which is formed on the insulating layer 17 at the center of the conductive finger pattern. Tabs 32-35 also extend from the 5 corners of the pad 30 out beyond the ends of the insulator 17. The layer 17 isbonded to the paddle (13 of FIG. 2) and the fingers, 16, are bonded to the lead frame fingers (11 of Fig. 2) as before. In addition, the Tabs 32-35 are thermocompression bonded to corresponding fingers (14 of FIG. 2) coupled to the paddle. Ground connection to the device is, therefore, provided through 10 pad 30 and tabs 32-35 rather than through the paddle 13. In fact, in this embodiment the paddle can be dispensed with and ground connections made by wire-bonding or thermocompression bonding the tabs 32-35 to appropriate conductors of the lead frame. In this example, the pad 30 was made of copper, with a thin layer (approximately 30 micro-inches or .75 micros) of gold on the 15 surface. The pad was approximately 220 mils (5.6 mm) long, 220 mils (5.6 mm) wide and 2 mils (.05 mm) thick.
In the final fabrication steps, the structure of FIGS. 3 or 4 is encapsulated with a standard material, such as room temparature vulcanizing silicone rubber, which covered the device, conductive fingers on the insulator, 20 the paddle, and at least a portion of the conductive fingers of the lead frame.
The ~mgers of the lead frame are then cut from the perimeter 12 and appropriately formed so that each would comprise an I/O lead for the package suitable for connection to printed circuit boards or the like. A typical final package is shown in a perspective view in FIG. 5 with the encapsulant shown as 25 element 31.
The package described herein appears most advantageous for semiconductor devices requiring a high number of ItO leads, i.e., at least 15 ona side. The invention is also advantageous where it is desired to reduce the size of the chip, for example to less than 100 mils (2.5 mm) on a side, so that a 30 higher density of interconnection is required. In general, the invention is most advantageous where a pitch of less than 16 mils (.4 mm) is desirable for the ends of the conductive fingers nearest the chip so that wire spans of less than 150 mils (3.8 mm) can be achieved.

Claims (10)

Claims
1. A semiconductor device package characterized by a mounting pad;
a plurality of first conductive fingers with one end of each in close lateral proximity to the pad and defining a first gap therebetween;
a plurality of second conductive fingers formed on an insulating layer and extending over the gap, one end of said second conductive fingers being bonded to corresponding first conductive fingers and the opposite end of the second conductive fingers terminating in close lateral proximity to the pad to define asecond gap therebetween which is less than the first gap.
2. The package according to claim 1 further comprising a semiconductor device with two major surfaces, said device having one major surface bonded to the mounting pad and the opposite major surface including a plurality of bonding pads.
3. The package according to claim 2 further comprising electrical wire connections between the bonding pads on the device and corresponding second conductive fingers.
4. The package according to claim 3 wherein the length of the wire is less than 150 mils.
5. The package according to claim 3 wherein the number of electrical connections between the pads and second conductive fingers is at least 15 per side.
6. The package according to claim 1 wherein the pitch of the second conductive fingers is less than 16 mils.
7. The package according to claim 1 wherein a conductive paddle is formed on a plane with the first conductive fingers and the insulating layer is mounted on the paddle.
8. The package according to claim 7 wherein the insulating layer includes a hole therein so that the mounting pad is defined by the portion of the underlying paddle exposed by said hole.
9. The package according to claim 1 wherein the mounting pad is formed on the same surface of the insulating layer as the second conductive fingers.
10. The package according to claim 1 wherein the mounting pad has four sides and there are at least 15 conductive fingers in close proximity to each side.
CA000537983A 1986-05-27 1987-05-26 Semiconductor package with high density i/o lead connection Expired CA1252912A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/866,931 US4774635A (en) 1986-05-27 1986-05-27 Semiconductor package with high density I/O lead connection
US866,931 1992-04-10

Publications (1)

Publication Number Publication Date
CA1252912A true CA1252912A (en) 1989-04-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CA000537983A Expired CA1252912A (en) 1986-05-27 1987-05-26 Semiconductor package with high density i/o lead connection

Country Status (7)

Country Link
US (1) US4774635A (en)
EP (1) EP0247775B1 (en)
JP (1) JP2671922B2 (en)
KR (1) KR960004562B1 (en)
AT (1) ATE95631T1 (en)
CA (1) CA1252912A (en)
DE (1) DE3787671T2 (en)

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EP0247775A2 (en) 1987-12-02
DE3787671T2 (en) 1994-02-03
JP2671922B2 (en) 1997-11-05
KR870011692A (en) 1987-12-26
ATE95631T1 (en) 1993-10-15
JPS6324647A (en) 1988-02-02
EP0247775A3 (en) 1988-01-20
KR960004562B1 (en) 1996-04-09
EP0247775B1 (en) 1993-10-06
DE3787671D1 (en) 1993-11-11
US4774635A (en) 1988-09-27

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