CA1254981A - Communications switching system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A communication switching system for routing digital voice and data signals and message signals between a plurality of peripheral circuits disposed in one or more peripheral subsystems and a main controller. Each peripheral subsystem is comprised of a peripheral switch matrix controlled by a peripheral control processor for switching the voice and data signals between predetermined peripheral circuits and the circuit switch matrix. The voice, data and message signals are transmitted through a circuit switch matrix of the main controller on predetermined time slot channels. The message signals are transmitted via communication controllers associated with the main controller and each of the peripheral subsystems according to a bit oriented data link protocol. The message signals are transmitted asynchronously during a predetermined one or more dynamically allocated time slot channels of the circuit switch matrix. The data link protocol guarantees error free transmission of a plurality of message signals. The communication system is inexpensive and efficient since both voice and data transmission as well as messaging is effected through use of a single circuit switch matrix.

Description

~l2~
01 This invention relates in general to 02 communication switching systems, and in particular 03 to a system for switching and routing digitized 04 voice, data and message signals between a plurality 05 of peripherals, and a main controller.
06 Switching systems, such as PABXs, have 07 been used in the past to route voice and data 08 signals between local and remote peripherals such as 09 subscriber sets, terminals and data sets, and to generate and receive message or supervisory signals 11 to and from the peripherals. Message signals are 12 typically tran~mitted between the peripherals and 13 one or more control circuits of a PABX in order to 14 indicate real time events such as a subscriber set going off-hook or ringing etc.
16 Peripherals are typically interfaced to 17 the PABX via dedicated peripheral circuits which 18 frequently include analog-to-digital and 19 digital-to-analog converters for digitizing voice signals into pulse code modulated signals (PCM).
21 Various conventions or standards have 22 been adop-ted by PABX manufacturers to facilitate 23 digital voice and da-ta signal switching and 24 messaging. One such convention was developed by the Bell System Cornpanies, and is known in the art as 26 the Tl carrier. According to the Tl carrier 27 convent:ion, digital signals are arranged in 28 "frames" consisting of twenty-four channels of PCM
29 and clata signals. Each channel is comprised of an 8 bit data or PCM signal, and the signal transmission 31 rate is approximately 1.54~ megabits per second.
32 Hence, one "frame" of digi-tal signals is comprised 33 of 193 bits configured as twenty-four 8-bi~ channels 34 and one framing or synchroniziny bit.
3~ Message signals are sen-t between a main 36 control circuit of the PABX and a peripheral by 37 replacing the least significant bit of a transmitted 01 PCM voice signal on a predetermined channe]. with a 02 control bit. PCM signals are received by -the PABX
03 or peripheral and the control bits are ex-tracted 0~-L ~rom successive ones of the PCM signals and 05 assembled or reconstructed to ~orm digital message 06 signals which are applied to one or more control 07 circuits for implementing real time events, such as 08 generating dial tone to an off-hook line~ etc.
09 The Tl carrier convention suE~ers from the disadvan-tage that random noise is injected into 11 -the PCM voice signal as a result o~ the least 12 signi-ficant bi-t -thereof being replaced by a control 13 bit. Also, while a PCM voice channel can be used to 14 transmit a control bit, a data carrying channel cannot be used in this manner since corrup-tion o~
16 the da-ta signal and loss of data integrity would 17 typically resultO A further disadvantage of -the Tl 18 carrier conven-tion is that since the control bi-ts 19 are incorporated into -the PCM signals, message signals cannot be transmit-ted independently of PCM
21 voice signals.
22 Another prior art system, described in 23 Canadian ~atent Application serial number ~31,426, 24 ~iled on June 29, 1983 by Conrad Lewis and assigned to Mitel Corporation, utilizes separate circuits ~or 26 switching voice and data signals on the one hand, 27 and message signals on the other. According -to the 28 Mitel invention, main and peripheral digital 29 switching circuits or switches, are utilized to transmit and route PCM voice and data signals 31 between various peripherals, and a separate message 32 switch is util.ized to transmit message signals 33 between a main control circuit and one or more 34 peripheral control processors o~ the peripherals.
By using a dedicated switch Eor 36 transmitting the message signals, the Mitel system 37 overcomes the disadvantage o~ the Tl carrier 01 convention ~herein random nolse is injected into the 02 voice signal. Also, the dedicated message switch is 03 capable of transmitting a large number of message 04 signals in a short amount of time during periods of 05 high message signal traffic, such as during a system 06 reset or bootstrap, etc.
07 However, considerable additional 08 circuitry and wiring was required in order to 09 implement t~e dedicated message switch. Such additional circuitry and wiring was found to be 11 undesirable in that it was costly and occupied 12 considerable circuit board area. Also, the main 13 control circui-t and peripheral control processors 14 were required to perform error checking routines on received message signals, and in response generate 16 acXnowledgements for each received message signal.
17 These operations significantly detract from system 18 performance since they require a substantial number 19 o processor cycles to implement.
A further prior art circuit is described 21 in U.S. patent number 4,322,843 of Beuscher et al, 22 issued March 30, 1982 to Bell Telephone LaboratorieS
23 and entitled CONTROL INFORMATION COMMUNICATION
24 ARRANGEMENT FOR A TIME DIVISION SWITCHING SYSTEM.
The Beuscher patent teaches a time division 26 switching system having distributed control 27 processors for exchanging control messages and 28 completing talking paths between subscribers. Each 29 control message includes an address portion de~ining -the destination o~ the control message and is 31 transmitted ~o a time shared space division switch 32 during predetermined time slot channels on an 33 associated pair of incoming and outgoing time 34 multiplexed lines connected -to a corresponding one of the dis-tributed control processors. Speech 36 representations are transmitted along the same pair 37 of lines as the control message. A central control 01 unit and a plurality of peripheral control units 02 exchange control messages utilizing selected ones of 03 the time multiplexed channels, the remainder of the 04 channels being used to carry the voice signals.
05 Each control message comprises a plurality of 06 control words and each control channel can transmit 07 one word per frame.
08 According to Beuscher et al, a given 09 channel is defined as a control channel for only one pair of time multiplex lines. For example, if 11 channel 1 is defined as a control channel on a 12 predetermined pair of time multiplexed lines, no 13 other pairs o time multiplexed lines will use 14 channel 1 as a control channel. During each time slot having the same numerical designation as a 16 predetermined defined con-trol channel, a main time 17 multiplex switching unit receives and applies the 18 control message carried by the predetermined control 19 channel on the outgoing one of the -time multiplexed lines (relative to the peripheral control unit) to a 21 dedicated output port of the switching unit 22 connected to an input of a main control distribution 23 unit. Similarly, during the same time slot, the 24 time multiplexed switching unit connects an output of the main control distribution unit to a 26 corresponding predetermined dedicated input port of 27 the time multiplexed switching unit Eor transmitting 28 a further control message to the other of the pair 29 of time multiplexed lines for reception by the peripheral control unit. The control distribution 31 unit determines -the proper destination for the 32 received control message and retransmits the message 33 to the aforementioned input port of the time 3~ multiplexed switching unit in a channel having the same numerical designation as the control channel 36 associated with the destination unit.
37 Since each peripheral control unit has a 01 unique control channel associa-ted therewith, the 02 number of peripheral control units is restricted by 03 -the number of channels per frame, thereby limi-ting 04 the expandabili-ty of the system.
05 ~ccording to the pxesent inven-tion, a 06 communication system is provided for switching PCM
07 voice and data signals via a circuit switch matrix, 08 for linking a plurality of peripherals connected to 09 peripheral subsystems, and also for providing transmission and reception of message signals on one 11 or more allocated channels of the circuit switch 12 matrix. According to a preferred embodiment of the 13 present inven-~ion, the channels are dynamically 14 allocated for accommodating various amounts of message signal traffic. The allocated channels are 16 multiplexed via the circuit switch matrix to provide 17 time sharing of the same messaging channels for each 18 peripheral subsystem, contrary to Beuscher et al 19 wherein each periperal con-trol unit has a dedicated messaging channel. Time multiplexing of the 21 allocated channels allows for simple expansion of 22 the number of peripheral subsystems connected to the 23 system. Thus, the number of subsystems which can be

2~ connected to the system is not limited to the number of channels in a frame, unlike the system disclosed 26 in the Beuscher et al patent.
27 The message signals are transmitted 28 according to a protocol which incorporates error 29 detection and handshaking features for guaranteeing error-free transmission of the message signals, 31 thereby overcoming the disadvantages of the prior 32 art MITEL~ device which required substantial 33 processor time for implementing error checking

3~ routines. Also, according -to the protocol used in the present invention, a plurality of message 36 signals can be concatenated in a single message 37 packe-t, requiring a single acknowledgement from the 3~3 - 5 -01 main controller or processor, thereby alleviating 0~ time consuming multiple acknowledgements as required 03 in the prior art MITEL device.
04 As a result o-f alloca-ting en-tire circuit 05 switch channels for the transmission of message 06 signals, the present invention overcomes the 07 disadvantages of the prior ar-t Tl carrier convention 08 which required replacing PCM bits with message 09 signal bits, resulting in extraneous noise. Yet, according to the present invention no additional 11 circui-try and wiring is required for implementing a 12 dedicated message switch, as in the prior art Mitel 13 device.
1~ In addition, because the number of channels per frame allocated for the transmission of 16 message signals can be varied dynamically under 17 processor control according to the preferred 18 embodiment, the present invention can efficiently 19 transmit a large number of message signals per frame during periods of high message signal traffic, such 21 as during a system reset or bootstrap, etc.
22 In general, the invention is a 23 communication system, comprised of a main controller 24 for controlling time multiplex switching of voice and data signals, one or more peripheral subsystems 26 for transmitting and receiving the voice and data 27 signals to and from a plurality of peripherals 28 connected thereto on predetermined time slot 29 channels, under control of respective peripheral control processors and a circuit switch matrix 31 connected to the main con-troller and the peripheral 32 subsystems, for performing time and space multiplex 33 switching of the voice and data signals between the 34 subsystems under control of the main controller.
~he invention is further comprised of a plurality of 36 communication controllers connected to respective 37 ones of -the peripheral con-t~ processors on the ~1 circuit switch matrix, first predetermined ones of 02 the communication controllers also being connected 03 to peripheral control processors, and a further one 04 of the communication controllers also being 05 connected to the main controller, for exchanging 06 message signals between the respective ones of the 07 peripheral control processors and the main 08 controller via the circuit switch matrix in 09 accordance with a bit-oriented data link protocol during predetermined time shared ones of the time 11 slot channels for each of the peripheral subsystems, 12 whereby error free transmission and reception of 13 message signals is effected simultaneously with 14 voice and data signal transmission and reception.
More particularly, the invention is a 16 message system for use in a communication system 17 comprised of a main controller, one or more 18 peripheral subsystems, and a circuit switch matrix 19 for performing time and space multiplex switching of time slot channels carrying digital voice and data 21 signals between the peripheral subsystems under 22 control of the main controller. The system is 23 comprised o-f one or more communication controllers 24 connected -to the one or more peripheral subsystems and the circuit switch matrix, for transmitting and 26 receiving network layer message signals in 27 accordance with a bit oriented data link protocol to 28 and from the subsystems and in response -transmitting 29 and receiving link layer message signals to and from the circuit switch matrix during a predetermined 31 one of the time slot channels. The inven-tion 32 preferably includes a further communication 33 controller connected to the main controller and the 34 circuit switch matrix, for transmitting and receiving the link layer message signals received 36 and transmitted by the one or more communication 37 controllers via the circuit switch matrix, and in 01 response transmitting and receiving network layer 02 message signals in accordance with the 03 aforemen-tioned bit-oriented data link protocol to 04 and from the main controller, and circuitry 05 connected to each of the communication controllers 06 for detecting errors in transmission of the message 07 signal and causing retransmission of the message 08 signals in response thereto, whereby error free 09 transmission and reception of message signals is effected simultaneously with voice and data signal 11 transmission and reception.
12 It is assumed that a person skilled in 13 the art to whom this description is directed, would 1~ understand digital telephone and switching concepts, programming of microprocessors, the structure and 16 operation of peripherals such as analog trunks, 17 analog line circuits, digital trunksl tone 18 generators and receivers, recorded announcement 19 circuits, etc., which interface via peripheral circuits to the peripheral subsystems. It is 21 intended that the terms 'icircuit switch" and 22 "peripheral switch" refer to apparatus which switch 23 a plurality of lines carrying time divided digital 24 signal channels to others of the same or other types. The term "message signal" denotes a control 26 or other supervisory or instructional signal.
27 A better unders-tanding of the invention 28 will be obtained by reference to the detailed 29 description below in conjunction with the following drawings, in which:
31 Figure 1 is a block diagram of the 32 invention in its broadest form, 33 Figure 2 is a block schematic diagram of 34 a circuit switch matrix portion of a preferred 01 embodiment of the present invention, 02 Figures 3A and 3B are block diagrams of 03 a peripheral switch matrix portion of -the preEerred 04 embodiment, 05 Figures 4A and 4B are block diagrams of 06 the basic switching element used in the present 07 invention, 08 Figure 5 is a schematic diagram o~
09 balanced driver/receiver and peripheral switch circuitry according to the preEerred embodiment of 11 the invention, 12 Figure 6 is a schematic diagram of 13 microprocessor, DMA, DRAM, communication controller 14 and channel allocation circuitry of a peripheral subsystem according to the preferred embodiment, and 16 Figure 7 is a schematic diagram of 17 microprocessor, DMA, DRAM, cornmunication controller 18 and channel allocation circuitry of the main 19 controller according to the pre~erred embodiment.
With reference to Figure 1, a main 21 con~rol processor MCP 1 is shown connected via a 22 control bus 3 to a circuit switch matrix CSM 5, a 23 communication controller circuit 7, a direct memory 24 access control circuit DMAC 9 and a dynamic random access memory circuit DRAM 11.
26 MCP 1 is typically comprised of a 27 microprocessor and associated decoding and control 28 circuitry, described in greater detail below with 29 reference to Figure 7. Circuit switch matrix CSM 5 is typically cornprised of a plurality of digital 31 crosspoint switches for implementing time and space 32 switching of digital signals between respeckive 33 input and output links thereof, as discussed in 34 greater detail below with reference to Figures 2, 4A
and 4Bo 36 Circuit switch matrix CSM 5 is also 37 _ 9 _ 01 connected to communication controller circui-t 7 02 which converts network layer message signals 03 received from DRAM 11 via DMAC 9, under control of 04 MCP 1, into data link layer message signals for 05 transmission through CSM 5 on one or more 06 dynamically allocated channels thereof to a 07 predetermined one or more peripheral subsystems, 08 denoted as BAY l...BAY ~, as described in greater 09 detail below. Also, controller circuit 7 converts data link layer message signals received from the 11 subsystems via CSM 5 to network layer message 12 signals ~or storage in DRAM 11 via DMAC 9, under 13 control of MCP 1, as described in detail below. The 14 network and data link layer message signals refer to the second and third lowest layers of what has 16 become known in the art as the Open System 17 Interconnection model of communication protocol 18 established by the International Organization for 19 Standardization, ISO. The ISO reference model for Open Systems Interconnection is a seven layer 21 architecture for the interconnection of systems 22 having different manufacturers and being of 23 different design. While the primary application of 24 the reference model to date has been in the field of local area networks, according to the present 26 invention the reference model has been applied to 27 telecommunication systems.
28 Peripheral subsystems BAY 1 .... BAY N, 29 are connected to CSM 5 via dedicated circuit switch links. For instance, BAY 1 is shown comprised of a 31 peripheral control processor PCP 13 connected via a 32 control bus 15 to a plurality of peripheral circuits 33 17 to 19, peripheral circuit switch 21, 34 communica-tion controller 23, DMAC 25 and DRAM 27.
Peripheral switch 21 is connec-tedvia 36 predetermined dedica-ted circuit switch links to CSM
37 5, and has a further predetermined number of ~L2~

^l bidirectional links connected to peripheral circui-ts 02 17 to 19.
03 According to -the present invention, the 04 number of links connected between the peripheral 05 circuits 17 to 19 and peripheral switch 21 is 06 greater than the number of links connec-ting 07 peripheral switch 21 to circuit switch matrix CS~
08 5. Hence, while CSM 5 performs a local matrix 09 function, peripheral switch 21 typically performs a channel assignment or concentration function for 11 connecting predetermined ones of the peripheral 12 circuits to the dedicated links connected to CSM 5.
13 A further plurality of peripheral 14 subsystems, (such as BAY ~), are typically connected via dedicated links to circuit switch matrix CSM 5.
16 For instance, BAY N is comprised of a peripheral 17 control processor PCP 29 connected via control bus 18 31 to peripheral circuits 33 to 35, and to 19 peripheral switch 37, conver-ter 39, DMAC 41 and ~RAM
43.
21 Each of the con-trollers 23 and 39 shares 22 a dedicated link with the corresponding peripheral 23 switch 21 and 37. Thus message signals are received 24 directly by the controllers 23 and 39 without first passing through the corresponding swi-tch 21 or 37.
26 Peripherals such as data sets and 27 subscriber sets, etc., are typically connected -to 28 -the peripheral circuits 17 to 19 (33 to 35~ via 29 balanced telephone lines, for carrying voice, data and line s-tatus signals. As discussed above, 31 peripheral circuits 17 to 19 (33 to 35) are 32 typically comprised of circuitry for converting 33 analog voice signals to PC~ digital signals and vice 34 versa, and line status circuits for detecting status signals and genera-ting control signals on the 36 control bus 15 (31) in response thereto. PCP 13(29) 37 detects the control signals generated by the 38 peripheral circuits, indicative of real time events 39 ~

01 such as off--hook, ringing, etc.
02 For the purposes of explanation, a 03 scenario will be considered in which a peripheral 04 such as a data set connected to peripheral circuit 05 17, (BAY 1), goes off hook and transmits data 06 signals (such as electronic mail signals) to a 07 Eurther da-~a set connected to peripheral circuit 33, 08 (BAY N).
09 Initially, an oEf-hook status signal is generated by the data set followed by dialling (or 11 DTMF) signals which are detected in a line status 12 circuit of peripheral circuit 17. Peripheral 13 circui-t 17 generates a first control signal for 14 appliction to PCP 13 via control bus 15 in response to receiving the status and dialling signals.
16 Next, a message signal is formatted in 17 DRAM 27 under control of PCP 13. Message formatting 18 in DRAM 27 is executed at the network layer of the 19 ISO reference model. Communication controller 23 then begins transmitting flag signals to circuit 21 switch matrix CSM 5. CSM 5 scans the PCM links in 22 order to detect such flag signals under control of 23 MCP 1, as described in detail below. Upon detection 24 of the flag signal, CSM 5 establishes a link therethrough between controllers 7 and 23 and sends 26 a go ahead f'ag signal to controller 23. Upon 27 reception of the go ahead flag signal, controller 23 28 begins receiving the network layer message signals 29 from DRAM 27 via DMAC 25 and conver-ts them into data link layer message signals for transmission during 31 predetermined dynamically allocated channels to 32 controller 7 via CSM 5.
33 In a preferred embodiment, the data link 34 message signals were formatted in controllers 7 and 35 2339 according to a variation of the High-Level 36 Data Link Control (HDLC) protocol but could 37 alternatively be format-ted according to any bit ~ 2~

01 oriented data link protocol, such as -the X.25 02 protocol recom~ended by CCITT. A useful description 03 of the HDLC protocol is found in an ar~icle entitled 04 `'IS0 High-Level Data Link Control (HDLC)", published 05 in September 1982 by Datapro Research Corporation.
06 A characteris-tic of the data link protocol is that 07 once the message signals have been transmitted from 08 the network layer (i.e. DR~M 27) to the link layer 09 (i.e. controllers 23 and 7), error-~ree transmission to and reception by MCP 1 is guaranteed. The data 11 link protocol incorporates a number of features, 12 such as cyclic redundancy check, packet numbering, 13 and retransmit timers for ensuring retransmission of 14 message signals between the controllers 17 and 23 until such time as the signal has been correctly 1~ received, without requiring additional servicing by 17 either of PCP 13 or MCP 1.
18 Communication controller 7 receives the 19 link layer message signal from circui-t swi-tch matrix CSM 5 and reconverts the link layer signal to a 21 network layer signal, for storage in DRAM 11 in 22 parallel form via DMAC 9. ~CP 1 then reads the 23 message signal stored in DRAM 11 and in response 24 generates a control si~nal on control bus 3 for configuring CSM 5 to establish a transmission path 26 between peripheral circuits 17 and 33. MCP 1 also 27 typically sends an acknowledgement message signal 28 via controller 7, and CSM 5 to PCP 13, in order to 29 acknowiedge receipt of the message signal.
As discussed above, a plurality of such 31 message signals can be concatenated in a single link 32 layer message packet for transmission to MCP 1 via 33 controller 7, requiring only a single 34 acknowledgement of the messages having been received, thereby overcoming the disadvantage of the 36 prior art MITEL system, which required individual 37 message signals to be transmitted through the 01 message switch circuit, each signal requiring an 02 acknowledgement signal upon reception.
03 According to the aforemen-tioned prior 04 art T1 system, considerable time was required in 05 order to transmit a message signal since only one 06 bit could be transmitted with each transmitted PCM
07 voice byte. In the present system however, PCM
08 channels are dynamically allocated for transmit-ting 09 message signals such that the amounts oE voice, data and message signal traffic are dynamically 11 controlled, as described in greater detai] below.
12 Data signals received from the 13 peripheral (i.e., data set) via peripheral circuit 14 17 are transmitted through peripheral switch 21 and CSM 5 to peripheral switch 37, and therefrom to 16 peripheral circuit 33, for display on a screen or 17 storage in a memory of the peripheral, which can be 18 a data set connected to circuit 33.
19 Alternatively, in the event the peripheral connected to circuit 33 is busy, or the 21 memory associated therewith is full, the 22 aforemen-tioned da-ta signals (eg. electronic mail) 23 can be stored in a non-volatile storage medium such 24 as a ~loppy disk, associated wi~h the peripheral control processor PCP 29.
26 During power up or system bootstrap, 27 data signals such as operating system data signals 28 are typically required to be downloaded Erom the 29 main control processor MCP 1 to the one or more 30 peripheraL subsystems, (BAY 1 BAY ~). According 31 to the present invention the data signals stored in 32 DRAM 11 are bulk transferred on dynamically 33 allocated channels to the controllers 23 and 39, 34 circumventing the peripheral switches 21 and 37 which typically are in undefined states prior to 36 powering-up or resetting the system.
37 A block schematic diagram of circuit 3~ - 14 -01 switch matrix CSM 5 is illustrated in Figure 2. As 02 discussed above, CSM 5 provides time and space 03 crosspoint connections for linking various ones of 04 the peripheral circuits which have been assigned 05 predetermined PCM channels, via peripheral switches 06 21 or 37. In the preferred embodiment, ~SM 5 is 07 comprised of Mitel digital time and space crosspoint 08 switching circuits, (abbreviated as DX circuits) 09 which provide time slot and space assignment of at least eight 32-channel input links to eight 11 32-channel output links. A four-by-four square 12 matrix of DX circuits is formed having four 8-link 13 input terminals and four 8-link output terminals.
14 The matrix thus provides 32 bidirectional links for implementing PCM voice and data switching, as well 16 as messaging and bulk data transfer as discussed 17 above with reference to Figure 1.
18 Mitel DX circuits are well known in the 19 art and a full description of their operation may be found in Canadian Patent number 1,171,946 issued 21 July 31, 1984 to Mitel Corporation.
22 According to the preferred embodiment 23 illustrated in ~igure 2, DX circuits DXl, DX2, 24 DX3 .... DX16 (denoted by numerals 5A, 5B, 5C .... 5P, 25 respectively) are connected to respective input and 26 output links via the aforementioned input and output 27 terminals. For instance, DXl (5A) has 8 input links 2~ connected to terminals LIOA, LIlA LI7A and 8 29 ou-tput links connected to terminals LOOA, LOlA
LO7A thereof. The remaining DX circuits 5B, 5C
31 5P are connected in a similar manner to respective 32 input and output links.
33 In a successful prototype of -the 3~ invention, ten peripheral subsystems were connected to the main control board, although for the purposes 36 of explaining operation of the invention only two 37 such subsystems (BAY 1 and BAY N) were described ~l2~

01 with reference to Figure 1.
02 In the successful pro-totype of the 03 invention an external processor in the form of a 04 digital signal processor was also connected to CSM 5 05 for performing tone conferencing, DTMF tone 06 generation and progress tone detection. The 07 external processor does not form part of the present 08 invention but the opera-tion and connection thereof 09 to CSM 5 would be well known to a person skilled in the art. TABLE 1 illustrates link connections 11 between -the circuit switch matrix CSM 5 and the 12 aforementioned ten peripheral subsystems according 13 to the preferred embodiment.

I6 LINK (IN) CONNECTION INK (OUT) CONNECTION
18 LIOA From LOOA To 19 communication communication controller 7 controller 7 21 LIl-3A From ex-ternal LO1-3A To external 22 processor processor 23 LI4-6A PCM from Bay 1 LO4-6A PCM to Bay 1 24 LI7A PCM from Bay 2 LO7A PCM to Bay 2 26 LIO-lB PCM from Bay 2 LOO-lB PCM to Bay 2 27 LI2-4B PCM from Bay 3 LO2-4B PCM to Bay 3 28 LI5-7B PCM from Bay 4 LO5-7B PCM to Bay 4 LIO-2C PCM from Bay 5 LOO-2C PCM to Bay 5 31 LI3-5C PCM from Bay 6 LO3-5C PCM to Bay 6 32 LI6-7C PCM from Bay 7 LO6-7C PCM -to Bay 7 34 LIOD PCM from Bay 7 LOOD PCM to Bay 7 LIl-3D PCM from Bay 8 LO1-3D PCM to Bay 8 36 LI4-5D PCM from Bay 9 LO4-5D PCM to Bay 9 37 LI6-7D PCM from Bay 10 Lo6-7D PCM to Bay 10 01 With reference to Figures 2, 3A and 3B, 02 peripheral switch 21 of Figure 1 is shown as being 03 comprised of two DX circuits 45 and 47. Input 0~ terminals SI0 of circuits 45 and 47 are connected to 05 the LO4A and LO6A output terminals respectively of 06 CSM 5, and the SIO input to DX circuit 47 is further 07 connected to communication controller 23. The SIl 08 input terminals of circuits 45 and 47 are both 09 connected to the LO5A output terminal of CSM 5.
Hence, the link connected to the LO5A terminal of 11 CSM 5 is shared between the two circuits, and the 12 LO6A link from CSM 5 is shared between DX circuit 47 13 and controller 23.
14 According to the preferred embodiment, a link carries 32 time slot channels per frame.
16 Hence, 15 channels are applied to the SIl input 17 terminal of circuit 45 and the other 15 channels are 18 applied to the SIl input terminal of circuit 47.
19 The SOO output -terminal of DX circuit 45 is connected to the LI~A input terminal of CSM 5.
21 Output terminal SOO of circuit 47 is connected to 22 the LI6A input -terminal of CSM 5, and the output of 23 controller 23 which is put in a high impedance mode 24 when not transmitting. The lin~ connected to the LI5A input terminal of CSM 5 is shared between the 26 SOl output -terminals of circuits 45 and 47.
27 With reference to Figure 3A, four 28 peripheral circuits 17, 51, 53 and 19 are shown.
29 Each of the peripheral circuits typically has a plurality of balanced telephone lines comprised of 31 tip and ring leads connected thereto for receiving 32 voice and data signals from peripherals such as 33 telephone sets~ data sets and data terminals.
34 According to the preferred embodiment, twenty-four balanced lines are connected to each of the 36 peripheral circuits 17, 51, 53 and 19. As discussed 37 above, voice signals received from the balanced ~L2~

01 lines are conver-ted via analog-to-digital conversion 02 circuitry o:E the peripheral circuits to PCM
03 signals. The PCM voice signals are then applied to 04 the DX circuit 45 for transmission to CSM 5, as 05 discussed above with reference to Figure 1.
06 Peripheral circuits 17 and 53 each have 07 one and one-half links extending therefrom to DX
08 circuit 45, one half link being shared with half 09 link outputs of peripheral circuits 51 and 19 respectively. Likewise, 6 output link terminals 11 So2-S07 of DX circuit 45 are connected to respective 12 input terminals of the peripheral circuits 17, 51, 13 53 and 19. Thus, a total of 12 links extend between 14 the DX circuit 45 and the peripheral circuits 17, 51, 53 and 19, comprised of 6 input links and 6 16 output links.
17 With reference to Figure 3B, individual 18 links between the DX circui~ 47 and individual ones 19 of the four peripheral circuits are not i~lustrated, in order to simplify the description, yet are 21 connected in an identical manner as shown in Figure 22 3A. The four peripheral circuits are represented by 23 the block 57. Further balanced llnes numbered 24 97~672 are connected to respective terminals of the peripheral circuits 57.
26 DX circuits 45 and 47 are configured in 27 order to connect predetermined incoming and outgoing 28 links, and channels thereof between CSM 5 and 29 predetermined peripheral circuits 17, 51, 53, 19 and 57, in response to receiving control signals from 31 PCP 13 (Figure 1).
32 DX circuits 45 and 47 are representative 33 of the connection of peripheral circuits to CSM 5 in 34 each of the additional subsystems which, in the preferred embodiment, numbered ten.
36 As discussed above, the basic time and 37 space division switch used in the present invention ~25~

01 is preferably a MITEL ~X circuit. The circuit is 02 fully described in the aforenoted Mitel patent, to 03 which the reader is referred.
04 Turning to Figure 4A, illustrating 05 internal circuitry of one of the DX circuits, such 06 as 5A in Figure 2, a plurality of input lines 07 carrying time division multiplexed input signals, 08 typically 8 lines referred to as SI0-SI7, are 09 connected to an input data manipulator, shown in two sections lOlA and lOlB. The da-ta carried by each 11 input line is received in serial format whereby the 12 time sequence of data is divided into frames, each 13 frame being divided into 32 channels, and each 14 channel being divided by 8 bits comprising a data word. In the manipulators lOlA and lOlB, the input 16 signals are converted from serial into parallel 17 form. The resulting sequences of signals are 18 applied via an 8 bit parallel link from each 19 manipulator to ~he data D input of the two coxresponding portions of a data memory 102A and 21 102B, referred to below as memory 102. The timing 22 of the storage of this data in data memory 102A and 23 102B is controlled by write control logic circuits 24 103A and 103B which are controlled via a pair of leads SDMW and clock source C244, both carrying 26 timing waveforms generated in a timing waveform 27 generator 118 (Figure 4B). The memory portions 28 could of course be combined, as could the input data 29 manipulator portions and write con-trol logic circuits. The data memory for the example shown is 31 organized as 256x8 bits for storing one frame Erom 32 each of the 8 input lines, each of which carries a 33 2.048MHz serial data stream.
34 The output port Q of data memory 102 is carried via an 8 bit parallel link through circui-try 36 to be described later to an output data manipulator 37 104, which provides parallel to serial conversion.

~2~

01 Manipulator 104 is operated under control of input 02 and output cloc~ signals and output lead timing 03 signals on its I/P CLK, O/P CLK and O/P LD ports 04 respectively.
05 8 bit parallel output leads 105 are 0~ connected to a corresponding number of tri-s-tate 07 drivers 106, the outputs of which are connected to a 08 group of 8 output leads SOO-S07 eac~ for carrying 09 time division multiplexed output signals.
A 256xll bit connection memory organiz~d 11 into an 8 bit portion 107A and a 3 bit portion 107B
12 has its 8 bit parallel data inpu-~ terminals D
13 connected via line CD (7-0) to a controller 14 interface 117 (Figure 4B) for providing a source of data, which is kypically connected in a circuit to 16 the MCP 1 (or PCP 13 or 39). The 8 bit parallel 17 address inputs AD of the connection memory are 18 connected to the output of a 2:1 multiplexer 108, 19 which has two 8 bit parallel inputs. One of the 2Q inputs is divided into two groups, one for receiving 21 addresses on 5 parallel lines A(~-0) and one for 22 receiving addresses on 3 parallel lines C~R(2-0), 23 for connec-tion to the MCP 1, PCP 13 or 39, etc., via 2~ controller interface 117. The other 8 bit parallel input is connected to a timing waveform source via 26 leads CMRAC(7-0~. Write control logic circuits 109A
27 and 109B have their outputs connected to the write 28 leads W of the respective connection memory portions 3209 107A and 107B, and have as inputs -timing signals on 31 leads CCMLBW, SCR/W, and C24~.
32 The 8 and 3 parallel output leads 33 respective]y from outputs Q of connection memory 3~ portions 107A and 107B are connected to the data inputs of a pair of correspond~ng connection memory 36 data registers 110A and 110B. The output leads of 37 connection memory portions 107A and 107B are also 01 connected to the CMD(7-0) and CMD(10-8) inputs of 02 controller lnterface 117 (Flgure 4B) which is 03 connected to the MCP l, PCP 13 or 39, etc.
04 The leads connected to the outputs Q of 05 data memory portions 102A and 102B are connected to 06 the DMD(7-0) inputs of the controller interface 117 07 which is connected to the MCP l, PCP 13 or 39, etc.
08 ~n 8 bit output of the connection memory 09 data register 110A is applied to corresponding 8 bit parallel inputs of multiplexers 110 and lll. The ll second 8 bit input of multiplexer 110 is connected 12 to the output of the data memory (referred to below 13 as 102), and the 8 bit parallel output of 14 multiplexer 110 i9 connected to the input of serial to parallel converter output data manipulator 104.
16 Seven of the 8 parallel output bits of multiplexer 17 lll are applied to the address AD input of data 18 memory 102, while the eighth bit is applied to its l9 output enable input through an inverter 119. An 8 bit parallel second input of multiplexer 111 is 21 connected to the address A(4-0) output and -the 22 memory address output CAR(2-0) of controller 23 interface 117. In addition, a third 7 bit parallel 24 input is connec-ted to timing waveform generator 118 via leads DMWAC~6-0).
26 Output bits 8-10 of the connec-tion memory 27 data register 110B are applied -to a three bit 28 parallel input CMDR10 of OR gate 112. A second 29 input of OR gate 112 is connected to a CAR7 lead Erom the controller interface 117. The output of OR
31 ga-te 112 is connected to the input selection port of 32 multiplexer 110, ~hereby either of the two inputs to 33 the multiplexer can be selected.
34 The output leads from the connection memory da-~a register por-tion 110B carrying bits 8 36 and 9 are connected to -the input of a retiming 37 register 113. The bits are passed through to logic 01 circuit 120, and a single bit output lead is 02 connected to the input of serial to parallel 03 converter 114. The bit 9 output lead of retiming 04 register 113, referred to as XC, is made available 05 for control of an external circui-t, not shown.
06 Leads CAR~ and CAR5 from the controller interface 07 117 are connected to logic circuit 120.
08 Serial bits of the output lead from the 09 connection memory data register 110 are converted to parallel format in serial to parallel converter 114, 11 and are applied in 8 bit parallel form from the 12 output Q of converter 114 to an output driver 13 control register 115. The output leads CDC(7-0) 14 from register 115, which carry output driver control signals, are connected to corresponding inputs of an 16 output enable control logic circuit 116, with an 17 output driver enable input lead ODE, which can be 1~ connected from external circuitry for forcing the 19 output tri-state driver to a particular state from an ex-ternal circuit. The output leads of output 21 enable control logic 116 are connected to the 22 control inputs of the output tri state drivers 106.
23 A microprocessor controller interface 24 circuit 117 (Figure 4B) interfaces the above ~ described circuit with -the MCP 1, PCP 13 or 39 via 27 leads E, R/W, MR, CE, address bus leads A(5-0) and 28 data bus leads D(7-0), referred to in Figure 1 as 29 the control bus 3 (or in the case of a peripheral subsystem, control buses 15 or 31). The inputs to 31 the controller interface 117 are the 8 data memory 32 read data leads DMD(7-0), and the 11 connec-tion 33 memory read data leads CMD(7-0) and CMD(10-8). The 34 outputs from controller interface 117 are the single individual controller connection memory low and high 36 write enable leads CCMLBW and CCMHBW, 5 address bit 37 leads A(4-0) controller address register bits 01 CAR(2-0~, controller address registe.r bits (7-5 3 for 02 specifying data and connection memory addresses, and 03 8 leads specifying connection memory input data 04 CD ( 7 -0 ) .
05 In operation, input signals are received 06 on leads SI0-SI7 and are conver~.ed from serial to 07 parallel in the serial to parallel converter of 08 input data manipulator, portions lOlA and lOlB. The 09 parallel data is then writ-ten into a speech memory corresponding to data memory 102. An address 11 memory, constituted by connection memory 107, stores 12 addresses of data words to be read out to a parallel 13 to serial converter corresponding to data 14 manipulator 104, from where it is applied directly to the output lines S00-S07.
1~ Thus the circuit performs the 17 combination of time division swi~ching and space 18 division switching as noted above.
19 MCP 1 (or PCP 13 or 29) has read access to the data memory 102 and both read and write 21 access to the connection memory 107. Consequently, 22 while the data memory 102 stores one frame of 8 bit 23 words received on the 8 serial input links, any of 24 this data can be read by the MCP 1 (or PCP 13 or 29) via the control bus. This is effected by the output 2~ of da-ta memory 102 being connected via output leads 27 DMD(7-0) from memory 102 to the input of controller 28 interface 117. Thus data signals transmitted on the 29 input PCM lines can be read by MCP 1.
MCP 1 (or PCP 13 or 29) writes into the 31 connec-tion memory 107 via data leads CD(7-0) at 32 addresses specified on leads A(4-0) and CAR(2-0) 33 which are connected to multiplexer 108, and reads 34 the contents of the connection memory via leads CMD(7-0) which are connected from khe output of 36 connection memory 107A to corresponding inpu-ts of 37 controller interface 117.

01 MCP 1 (or PCP 13 or 29) can also write 02 directly to -the output leads SOo S07 in the 03 following manner. Signals Erom the connection 04 memory are temporarily stored in the data register 05 portions llOA and llOB. The most significant 8 bits 06 output -from the connection memory data register llOA
07 (CMDR(7-0) ) are applied to one of the parallel input 08 ports of multiple~er 110, while the output bits of 09 data memory 102 are applied to the other input port. Since bit 10 from data register llOB in 11 conjunction with the bi-t on lead CAR7 from the MCP 1 12 (or PCP 13 or 29) controls which oE the two groups 13 of inputs of multiplexer 110 are output therefrom to 14 output data manipulator 104 and to the PCM output leads, it is apparent that MCP 1 (or PCP 13 or 29) 16 can substitute its own signals on -the output leads 17 instead oE the PCM words from data memory 102.
18 As noted earlier, when such signals are 19 stored in clata memory 102 from a preceding similar switching matrix these signals can be read via leads 21 DMD(7-03 Erom the output of data memory 102 directly 22 to the MCP 1 (or PCP 13 or 29) through the 23 con-troller interface 117. Controller to controller 24 communication is thus facilitated.
The signals stored in data memory 102 26 are normally designated to output PCM links and time 27 slots by addresses specified by signals stored in 28 the connec-tion memory 107A, and which are input to 29 multiplexer 111 via connection memory data register llOA and 8 bit parallel leads CMDR(7-0). In 31 addition, the MCP 1 (or PCP 13 or 29) can direct 32 specific substitute words to be outpu-i: from data 33 memory 102 through memory address leads CAR(2-0) and 34 A(4-0) w~ich are inpu-t to multiplexer 111. A -third source of signals to multiplexer 111 is timing 36 signal lead DMWAC(6-0) which is connected from a 01 timin~ waveform generator 118 (Figure 4B).
02 The MCP 1 (or PCP 13 or 29) writes 11 03 bit words (bits 0-10) in~o connection memory 04 portions 107A and 107B at addresses specified on 05 leads CAR(2-0) and A(4-0), at times specified by the 06 write control logic circuits 109A and 109B, which 07 generates write command signals to the associated 08 memory. Bit 10 of the connection memory is used to 09 select either the data memory or bits 7-0 of the connection memory as the source of 8 bit words to be 11 sent out on the serial output links. Depending on 12 the state of bit 10, bits 7-0 ei~her form the word 13 to be transmitted via leads CMDR(7-0) and 14 multiplexer 110 to the output data manipulator, or select one of the 256 8 bit words stored in the data 16 memory to be transmitted on the corresponding output 17 links during the corresponding channel time. As 18 described earlier, bit 10 is passed through OR gate 19 112, which alters the state of multiplexer 110, de~ining the particular source of data which is 21 enabled to pass therethrough to output data 22 manipulator 104.
23 Bit 9 of the connection memory is used 24 to control an external circuit. This bit is received from connection memory data register 26 portion 110B, is corrected for phase in retiming 27 register 113 with clock timing signal C488 and is 28 made available on lead XC for control of an external 29 circuit, not shown.
Bit 8 passes from connection memory data 31 register portion 110B through retiming register 113, 32 through logic circuit 120 to a serial to parallel 33 converter 114, sequential bits being converted by 34 serial to parallel converter 114 into 8 bit parallel form, and stored in output driver control register 36 115. The output signal is applied to output enable 37 control logic 116, from which it is applied to the 01 gates of output tri-state drivers 106. The 02 transmission and output impedance states of the 03 tri-state drivers for corresponding output links are 04 -thereby specified.
05 When bit 10 is 0, bits 7-0 o~ the 06 connection memory specify which one of the data 07 memory words is to be sent out on the serial output 08 link which corresponds to the connec~ion memory 09 location, during the channel time which corresponds to the connection memory location. Thus when bit 10 11 is 0, bi-ts 7-0 are an address signal, which is 12 applied from lead CMDR(7-0) through multiplexer 111 13 to the AD input of data memory 102.
14 When bit 10 is 1, bits 7-0 of the connection memory consti-tute -the data word which is 16 to be sent out on the serial output link which 17 corresponds to the connection memory location, 18 during the channel time which corresponds to the 19 connection memory location. This word is passed through multiplexer 110 as described earlier.
21 MCP 1 (or PCP 13 or 29) thereby reads 22 -the serial input links from the data memory without 23 interpreting frame, channel, and bit timing and 24 serial to parallel conversion. By writing to the connection memory, MCP 1 (or PCP 13 or 29) can 26 transmit data words via the serial output links such 27 that timing and parallel-serial conversion are 28 automatically controlled.
29 The DX circuit can switch signals between incoming and outgoing channels on any of the 31 incoming and outgoing lines, and can also transmit 32 data to MCP 1 (or PCP 13 or 29) or receive data Erom 33 MCP 1 ~or PCP 13 or 29) and transmit the data to 34 any of the outgoing lines or predetermined time slot channels. In addition, MCP 1 (or PCP 13 or 29) can 36 control the switching paths within the DX circuit.
37 The DX circui-t can also control or send data to 01 another external device. The DX circuit has been 02 integrated into a single chip. The present 03 invention is enhanced in one aspect by the ability 04 to transmit data via the DX circuit in various 05 ways.
06 With reference to Figure 5, balanced 07 receivers 201 and 203 are shown for receiving 08 signals from CSM 5 on the L04A, L05A and L06A
09 links. An additional link labelled SPARE is provided for connection to a further link of CSM 5.
11 Timing signals FP and C244 are received from a 12 backplane timing and control bus ~not shown), and 13 are generated on the main control board as described 14 in greater detail below with reference to Figure 7.
A further input link is provided on receiver 203, 16 which is not connected. Signals received from the 17 backplane are pre~erably balanced differential 18 signals, and are received on inverting and 19 non-inverting inputs of the receivers 201 and 203.
Pull-up resistors Rpu are connected to non-inverting 21 inputs of receivers 201 and 203 and to a +5 volt 22 power source. Receivers 201 and 203 convert the 23 received signals to unbalanced signals for 24 application to DX circuits 45 and 47, as discussed above with reference to Figures 3A and B.
26 In particular, a first output of 27 receiver 201 is connected to the SIO input of DX
28 circuit 45, a second output of receiver 201 is 29 connected to the SIO input of DX circuit 47 and to an HDLCRX terminal for transmission to controller 31 23. A third output of receiver 201 is connected to 32 the SIl input of DX circuits 45 and 47. First and 33 second outputs of receiver 203, carrying the frame 34 pulse FP and clock C244 signals respectively, are connected to control inputs of DX circui-ts 45 and 47 36 and further transmitted to channel selection logic 37 circuitry, discussed in greater detail below with 01 reference to Figure 6.
02 The SOO output of DX circuit 45 is 03 connected to balanced output driver 205 for 04 connection to the LI4A link of CSM5. The S00 output 05 of DX circuit 47 is connected a second inpu-t of 06 driver 205, to which an HDLCDX terminal is also 07 connected, discussed in greater detail below with 08 reference to Figure 6. A third input of driver 205 09 is connected to the SOl out.puts of DX circuits 45 and 47. A fourth input of driver 205 is left 11 unconnected, for use as a spare to accommodate 12 future expansion.
13 The S02-S07 outputs of DX circuit 45 are 14 connected to COl-CO6 inputs respec-tively of bidirectional buffer circuit 207. The S02-S07 16 ou-tputs of DX circui-t 47 are connected to the 17 C07-C012 inputs of circuit 207. The CIl-CI6 outputs 18 of bu:Efer circui-t 207 are connected to -the SI2-SI7 19 inputs respectively of DX circuit 45, and the CI7-CI12 ou-tputs of circuit 207 are connected to the 21 SI2-SI7 inputs respectively of DX clrcui-t 47.
22 Address inputs AO-A5 of DX circuit 45 and 47 are 23 connected to the microprocessor address bus, 24 discussed below with refexence to F'igure 6, and the DO~D7 data terminals oE DX circui-ts 45 and 47 are 26 connected to a data bus also discussed with 27 reference to Figure 6.
28 Buffer circuit 207 has been shown for 29 convenience as being a single bidirectional bu~fer circuit having 24 inpu-t terminals and 24 output 31 terminals, but can alternatively be any number (for 32 example, -three) bidirectional buffer circuits having 33 a predetermined number oF inpu-ts and ou-tputs, (for 34 example, eight).
Referring now to the peripheral 36 subsystem schematic diagram of Figure 6, a 37 microprocessor 300 is shown having address inputs 01 A0-Al9 thereof connected -to an address bus 301.
02 Data inputs D0-D7 of microprocessor 300 are 03 connected to a data bus 303, and con-trol inputs of 04 microprocessor 300 are connected to a control bus 05 305. Address lines A0-A5 of address bus 301 are 06 connected to address inputs of controller interfaces 07 (such as interface 117 discussed above with 08 reference to Figure ~B) of DX circuits 45 and 47 09 (Figure 5). Likewise, the data bus 303 is connected ~ to data inputs of the control interfaces and the FP, 12 C244, E, R/W, MR and CE signals of control bus 305 13 are also connected to further inputs of controller 14 interfaces.
According to a successful embodiment, 16 microprocessor 300 was a Motorola~ model MC68008 17 eight bit microprocessor clocked at 8.192 megahertz.
18 DRAM 27, discussed above with reference 19 -to Figure 1, is connected to the data, address and control buses, and is preEerably a 64k byte memory 21 which in the successful embodimen-t, was configured 22 as eight 64k-by-1 bit DRAM chips. According to the 23 successful embodiment, the chips were disposed in 24 sockets on a peripheral circuit board and prewired to accommodate 9 multiplexed addresses, thereby 26 enabling replacement by 256k by-l bit DRAM chips, 27 for the purpose of future memory expansion. Row 28 selec-t and column select signal generation was 29 implemented in a well known manner.
An enable decoder circuit 307 is 31 illustrated having A, B and C inputs connected to 32 the A14, A15 and A16 address lines of address bus 33 301. Also, negative enable inputs Gl and G2A of 34 decoder 307 are connected to an output of NOR gate 309 and the A17 address line of address bus 301.
36 The inputs of NOR gate 309 are connected to the A18 37 and Al9 address lines. A G2B enable input of 38 decoder 307 is connected via a pull-up resistor Pu 01 to a logic high +5 volt potential source.
02 First, fourth and sixth ou-tpu-ts of 03 decoder 307 are not connec-ted. The second output 04 thereof being connec-ted to a Eirst input of a ~A~D
8~ gate 311, and the third output of decoder 307 is 07 connected to a chip select CS input of DMAC 25, 08 discussed above with reference to Figure 1. DMAC 25 09 is further connected to PCP 13 via the address, data and control buses; 301, 303 and 30 respectively.
11 DMAC 25 has DMA request and acknowledge 12 terminals connected in circuit paths to 13 communication controller 23 which, as discussed 14 above, is preferably an HDLC controller.
In particular, DMA channel 1 request 16 (REQl) is connected to an RXDA output of controller 17 23, DMA channel 2 request (REQ2) is connected to a 18 Transmi-t Bu-f~er Empty terminal TXBE of controller 2~ 23, and DMA channels 1 and 2 acknowledge outputs 21 ACKl and ACK2 are connected to second and third 22 inputs of NA~D gate 311, the output of which is 23 connected to a chip enable input CE of controller ~45 23. The channel 0 request and acknowledge terminals 26 REQ0 and ACK0 are not connected.
27 According to the preferred embodiment, 28 controller 23 was a Motorola 68652-2 MDLC controller 29 circuit, clocked at 2.048 megahertz per second, and DMAC 25 was an Intel~ 8257-5 DMA controller circuit, 31 also clocked at 2.048 megahertz.
32 An enable decoder circuit 315 is 33 illustrated having A, B, C and D inputs connected to 34 the Al, A2, A3 and A0 lines of address bus 301 respectively. An enable input G is connected to the 36 fifth output of decoder 307, and the Q0-Q4 outputs 01 of enable circuit 315 are not connected. The Q5, Q6 02 and Q7 outputs of circuit 315 are connected to 03 Transmit Enable (TXE), Receive Enable (RXE), and 04 Maintenance Mode MM inputs, respectively, of 05 controller 23.
06 Serial input RXSI of con-troller 23 07 carries the HDLCRX signal received from receiver 201 08 (Figure 5). The transmit serial output TXSO o 09 controller 23 is connected via tri-state gate 317 to the HDLCDX -terminal of balanced driver 205. As 11 discussed above, the ~IDLCTX terminal is required to 12 be placed in a high impedance state in the event 13 controller 23 is not transmitting valid data, since 14 link LI 5A of CSM 5 i5 also shared with the SOO
output of DX circuit 47.
16 A three bit channel size register 319 17 having three inputs, is connected to the DO, Dl and 18 D2 lines of data bus 303. QO, Ql and Q2 outputs of 19 register 319 are connected to first inputs of NAND
gates 321, 323 and 325, respectively.
21 A flip-flop 327 is illustrated having a 22 J input thereof connected to the ~5 volt source, a K
23 input connected to the FP output of receiver 203 and ~a5 a clock input thereof connected to the C244 output 26 of receiver 203. A Q output of flip-flop 327 is 27 connected ~o the clock inputs of cascadad counters 28 329 and 331. A counter overflow output CO of 29 coun-ter 329 is connected to an enable input P of counter 331. A Q4 output of counter 329 is 31 connected to a first input of NOR gate 333 and a Ql 32 output of counter 331 is connected to a second input 33 of NOR gate 333. The Q2, Q3 and Q4 outputs of 34 counter 331 are connected to the second inputs of NAND gates 325, 323 and 321 respectivel~.
36 The outputs of NOR gate 333 and NAND
37 gates 321, 323 and 325 are connected to four 01 respective inputs of ~AND gate 335. The output of 02 NAND gate 335 is connected to a tri-state enable 03 input of gate 317 and to a first input of NOR gate 8~ 337. A second input of NOR gate 337 is connected to 06 the Q output of flip-flop 327.
07 An output of NOR gate 337 is connected 08 to a D input of flip-flop 339 and to a transmit 09 clock input (TXC) of controller 23. A clock input of flip-flop 339 is connected to the C244 output of 11 receiver 203, and a Q output of flip-flop 339 is 12 connected to a receive clock input (RXC) of 13 controller 23. Hence, the receive clock signal 14 applied to the RXC input of controller 23 is time shifted by 1 clock cycle from the transmit clock 16 signal applied to the transmit input TXC. The 17 receive clock signal is shif~ed in ~his manner for 18 reasons of system timing, and results in -the 19 controller 23 having timing characteristics of a DX
circuit, thus facilitating straight forward 21 interfacing with CSM 5.
22 Receive status and receive data outputs 23 RXSA and RXDA of con-troller 23 are connected to 24 first and second inputs respectively of a priority encoder circuit 3~1, the output of which is 26 co-nnected -to an interrupt input INT of PCP 13.
27 Also, the TXBE output of controller 23 is connected 28 to a further input oE priority encoder circuit 341.
29 In operation, a predetermined three bit data word is loaded into channel size regis-ter 319 31 for causinc3 generation of transmit and receive clock 32 burs-ts to the TXC and RXC inputs respectively of 33 contxoller 23, in order to effect transmission and 3~ reception of message signals during predetermined 3~ time slot channels. The Q output of flip-flop 327 37 generates a 488 kilohertz signal for application to 01 OR ga-te 337 and counters 329 and 331. In response, 02 the Q4 output of counter 329 generates a 7.8 03 kilohertz signal. The Q1, Q2, Q3 and Q4 outputs of 04 counter 331 carry 16, 32, 64 and 128 kilohertz clock 05 signals for application to the NOR gate 333 and NAND
06 gates 325, 323 and 321. These clock signals are 07 gated through respective ones of NAND gates 321, 323 08 and 325 in response to various logic signals 09 appearing on the Q0, Ql and Q2 outputs of channel size register 319. In particular, with reference to 11 T~BLE 2 below, message signal channel allocation and 12 consequently message signal transmission/reception 13 rate is illustrated for various values of D0, Dl and 14 D2 applied to channel size register 319.

16 TRANSMISSIO~/
17 D0 Dl D2 Channel Allocated RECEPTIO~ RATE

19 1 1 1 0 64kbs 0 1 1 0,16 12~kbs 21 0 0 1 0,8,16,24 256kbs 22 0 0 0 0,4,8,12,16,20,24,28 512kbs 24 With reference to Figure 7, main control processor 1 is shown connected to DMAC 9 via address 26 lines Al-A7 of address bus 400, and also via control bus 401. In addition, an interrupt reques-t terminal j2~ IRQ is connected to an interrupt input INT oE MCP
31 1. Also, DTACK terminals of each of MCP 1 and DMAC
32 9 are connected together. The A8-A23 address lines 33 of address bus 400 are connected to a buffered latch 34 402. Data terminals D0-D15 of MCP 1 are connected via a data bus 403 to a buffered latch 404. Outputs 36 of latches 402 and 404 are connected to mul-tiplexed 37 inputs A8/D0-A23/D15 of DMAC 9. Latch control 01 output lines LCTRL of ~MAC 9 are connected to 02control inputs of the la~ches 402 and 404 for 03 effecting multiplexing of the address and data 04 lines.
05MCP 1 ls connected to DRAM 11 via data 06bus 403, address bus 400 and control bus ~01, and to 07 individual DX circuits of CSM 5 via corresponding 08 controller interfaces, not shown, for read and 09 writing directly to the DX circuits via the address, data and control buses.
11Communication controller 7 is 12 illustrated having control inputs thereof connected 13to control bus 401, and data inputs DO-D15 thereof 14 connected to data bus 403. In addition, a number of handshaking signals are transmi-tted between DMAC 9 16 and controller 7. In particular, a DMA channel 2 17 request signal is generated by an HDLC Receive Data Available output. (R~DA) of con-troller 7, and inverted in inverter 402 and applied to the REQ2 21 input of DMAC 9. The Transmit Buffer Emp-ty terminal 2~ (TXBE) of controller 7 is connected via inverter 403 24 to the PCL3 input of DMAC 9. The Receive Status ~2~ Available (RXSA) output of control 7 is connec~ed ~8 via inverter 404 to the PCL2 input of DMAC 9. DONE
29 and channel acknowledge ACK3 outputs of DMAC 9 are 30connected via OR gate 405 and inverter 406 to one of 31 the control inputs of controller 7.
32Address lines AO-A2 o address bus 400 33 are connected to an input of a decoder 407, 34 providing further control and enable signals ~o controller 7. In particular, the QO output of 36 decoder 407 is connected to the Receiver Enable 37 input (RXEN) of controller 7, and the Ql output of ~ ~ 5 ~3~

01 decoder 407 is connected to the Transmit Enable 02 inpu~ TXEN of controller 7. The Q2 output of 03 decoder 407 carries a signal denoted as ST~RT TX for 04 application to a Eirst input of OR gate 408, the 05 second input of which is connected to the output of 87 inverter 403, and the output of which is connec-ted 08 to the DMA channel 3 request input REQ3 of DMAC 9.
09 The Q3 output of decoder 407 is connected to the maintenance mode input MM of controller 7, and the 11 Q4 ou~put oE decoder 407 is connected to channel 12 select circuitry of the main controller, described 13 in detail below.
14 Timing circuitry is illustrated for generating the aforementioned frame pulse signal FP
16 and clock signal C244, for synchronizing PCM data 17 transmission between the main con-troller and the 18 peripheral subsystems. An oscillator 10 preferably 19 running at 16.384 megahertz drives a clock input of a counter 412 for producing submultiple clock 21 frequencies. The counter 412 can alternatively be a 22 series o cascaded counters connected in a well 23 known manner.
24 The C244 output of counter 412 is connected to a balanced transmit driver (not shown), 26 ~or transmission to the peripheral subsys-tems via a 27 backplane connection, in order to synchronize timing 28 between the subsystems and main controller. The 29 C48s3 output oE counter 412 is connected to a clock input of flip~flop 414. The C926, C1952 and C3904 31 counter outputs are connected to three inputs of a 32 NAND gate 416. The output of which is connected to 33 an inverter 418. The C926, C1952 and C3904 counter 34 outputs are also connected to three inputs oE a N~ND
gate 420, and C7808, C15625, C31250, C62500 and 36 C125000 counter outputs are connected to Eur-ther 37 inputs oE the NAND gate 420. The C125000 output is ~1 also connected -to a firs~ input of NOR gate 422, a 02 second input of which is connected to -the Q4 output 8~ of decoder 407, which 05 generates a channel allocation signal 128/64 as 06 described in detail below.
07 The output of NAND gate 420 is connected 08 -to an inverter 424 and to a first input of NOR gate 09 426. The output of inverter 424 is connected to a first input of NAND gate 428, a second input of 11 which is connected to the C125000 output of counter 12 412. The output of NAND gate 428 is connected to a 13 first input of OR gate 430, a second input of which 14 is connected to the C48B output of counter 412. The output of OR gate 430 carries the aforementioned 16 frame pulse signal FP.
17 The output of NOR gate 422 is connected 18 to a second input of NOR gate 426, the output of 19 which is connected to a J input of flip-flop 414.
The output of inverter 418 is connected -to the 21 input of flip-flop 414.
22 The inverted output from NAND gate 416 23 generates a signal which has a logic high value 24 during the first bit (i.e. bit 0), of any of the thirty-two eight bit tirne slot channels. The output 26 of NAND gate 420 generates a signal having a logic 27 high value except during the first bit of the 28 sixteenth and thirty-second time slot channels.
29 The output of NOR gate 422 generates a logic low value in the event a logic high value is 31 applied to the second input -thereof from the Q4 32 output of decoder 407, and alternates be-tween logic 33 high and low values for each half frame (i.e.
34 sixteen channels) in the event a logic low signal is applied thereto from the Q4 output of decoder 407.
36 The output of NAND gate 420 is high excep-t during 37 t'ne first bi-t of the sixteenth and -thirty-second ~2~

01 channels. Thus, the Q output of flip-flop ~1~ is at 02 a logic low value except during channels 1~ and 32 03 in the event the Q4 output of decoder 407 is at a 04 logic high value, and the Q output of flip-flop 414 05 is at a logic high value during only the 06 thirty-second time channel.
07 The Q output of flip-flop ~1~ is applied 08 to a first input of ~AND gate 432, the second input 09 of which is connected to the source of C488 clock signal, (i.e. counter 412). Hence, NAND gate ~32 11 generates a bursty 488 kilohertz clock signal on the 12 output thereof, which is gated on the sixteenth and 13 thirty-second channels in the event the Q4 output of 14 decoder 407 i5 at a logic value, and the C~88 clock signal is gated only in the thirty-second channel in 16 the event the Q4 output is at a logic low value.
17 In order -to better understand the 18 operation and construction of the present invention, 19 it will be helpful to discuss the theory and features of HDLC protocol. As discussed above, the 21 link layer provides error-free point-to-point 22 transmission of signals passed to it from ~he 23 network layer. The term error-free means that the 24 link layer guarantees correct delivery of signals that are passed to it, regardless of errors that may 26 occur during actual transmission on the physical 27 medium interconnecting a transmitting and a 28 receiving HDLC controller. The physical medium is 29 designated by the term "physical layer" and according to the present inven-tion comprises the 31 communication~links interconnecting the HDLC
32 controllers. A message signal frame (i.e. comprised 33 of one or more message signals) is no-t considered to 3~ have been clelivered until the link layer at the receiving end passes it up to the corresponding 36 network layer. Thus, the link layers in both the 37 main controller and peripheral subsystem must ~2~

01 cooperate to ensure correct delivery.
02 According -to a successful prototype of the 03 present invention, the HDLC protocol is es-tablished 04 partially by the communication controllers themselves 05 (controllers 7, 23,.. 29) which generate and detect 06 Cyclic Redundancy Code (C~C), and partially by the 07 associated one of the processors 08 (MCP 1, PCP 12,.. PCP 29) which assign predetermined 09 sequence numbers to the message signal frames for detecting whether a received frame is out of sequence, 11 and thereby request retransmission.
12 The structure of an HDLC message signal 13 frame is illustrated below in TABLE 3.

16 FLAG ADD~ESS CO~TROL I~FORMATION FC5 FLAG

18 01111110 8 bits 8 bits 8 bits 16 bits 01111110 All frames start and end with a flag 21 consisting of bit sequence 01111110. The flag is used 22 for synchronization between the receiving and 23 transmitting controllers. When in an idle state the 24 communication controllers generate and transmit a sequence o~ contiguous "1" bits between successive 2~ frames, which is ~nown as per-forming inter-frame time 27 fill.
28 Since it is possible Eor six or more 29 one bits to be found contiguous elsewhere in the frame (i.e~ as part of the message signal), HDLC provides 31 means for achieving transparency of these non-Elag 32 related sequences of one bits. The transmit~ing 33 controller examines the frame content including the 34 address, control and cyclic redundancy check (FCS) portions and inserts a zero bit aEter all sequences of 36 five contiguous one bits thereby ensuring that a flag 37 sequence is not ina~vertently simulated. At the 01 receiving controller, the incom:ing frames are examined 02 and any O bit directly following five one bits is 03 ignored.
0~ The 1ag is followed by an address field, 05 which, according to the present invention, is unused.
06 The purpose of the information frame is to 07 effect -the actual -transfer of data from one controller 08 to ano-ther. All information frames are crea-ted Erom 09 data packets crossing the ne-twork/link layer boundary. Once -the network layer passes inEormation 11 to the link layer, correct delivery is guaranteed.
12 Thus, the linX layers buffers information frames until 13 correct delivery of each has taken place. The data 14 contained in the information frames is the only data that is passed between the link and network layer 16 boundaries. The ~lags, control byte and FCS bytes 17 being utilized by the communication controllers to 18 ensure correct delivery of the information frames.
19 The Frame Check Sequence or FCS portion of the frame is a sixteen bit sequence sent prior to the 21 closing flag. The function of the FCS bits is to 22 detect errors in the bits following the opening flag 23 but before the FCS bits, excluding zero bits inserted 24 for transparency, as discussed above. The receiving con-troller per-forms a Cyclic Redundancy Check (CRC) on 26 the FCS bits in a well known manner, in order to 27 determine whether errors have been generated during 28 transmission, and the associated processor initiates 29 recovery or retransmission procedures in response thereto.
31 A control byte identifies frame type, 32 frame sequence number and/or acknowledge sequence 33 number, as described in greater detail below. The 34 format of -the control byte depends on ~he type of frame being transmitted; information, supervisory or 36 unnumbered, as defined in TABLE ~ below.

~2~

05 _ = = CONTROL FI~LD TYPE
o67 7 61 5 ~ 3 2 1 0 08 0 ~(S) 0 N(R) INFORMATION

1 0 S(N) 0 ~(R) SUPERVISORY
1 1 _ __ _ _ 13 1 1 F(N) 0 F(N) UNNUMBERED

A "send sequence number" N(S) is assigned 16 to the information frame by the associated processor.
17 A "receive sequence number" N(R) is also assigned and 18 designates the sequence number of -the next frame 19 expec-ted by the receiving controller, which serves to acknowledge all frames with sequence numbers up to but 21 not including N(R).
22 The purpose of the supervisory frame is to 23 control the transfer of information frames. They are 24 used to acknowledge the reception o, or to request retransmission of specific information frames, based 26 on the sequence number N(~). Supervisory bits 4 and 5 27 of the control field (labelled S(N)) are encoded as 28 either 00, which indicates that the receiving 29 controller is ready, or as 01 to indicate rejection of a received infromation frame.
31 Unnumbered frames provide a metaprotocol 32 for link layer control. They are used to set up, tear 33 down and reset links between various ones of the 34 communication controllers. The designation "unnumbered" refers to the act that these frames do 36 not contain sequence numbers, since they are not 37 directly involved in the transfer of information L

01 frames. Modifier bits 5~ 4, 2, 1 and 0 tdenoted as 02 ~(N)) are assigned values for facilitating two primary 03 functions: an unnumbered acknowledgement (00-110) 04 discussed below, and to set asynchronous balanced mode 05 of operation (11-100). The asynchronous balance mode 06 of operation defines the protocol as being 07 bidirectional and asynchronous, wherein each 08 controller sends both commands and responses and also 09 receives bo-th commands and responses.
As discussed above, sequence numbers N(S) 11 are assigned to each of -the HDLC frames which are sent 12 in order to distinguish inormation frames from each 13 other. They allow the receiving controller and 14 associated processor -to identify incoming information frames, and they allow a transmitting controller and 16 associated processor to interpre-t acknowledgements or 17 rejects correctly.
18 As discussed above, message signals are 19 bu~fered by the link layer. According to the present invention, up to three such message signals can be 21 buffered prior to receiving an acknowledgement.
22 Sequence numbers are assigned sequentially starting 23 with 000 and incremented by one thereafter.
24 The next send sequence number to be assigned -to an outgoing information frame by the 26 processor associated with the transmi-tting controller 27 is designated as the send state variable V(S).
28 Subsequent to link set up or link reset, the value of 29 V(S) is zero. V(S) represents the upper bound of a sliding window for the transmitting con-troller and 31 associated processor, as described in greater detail 32 below.
33 At -the receiving end of the link, the 34 processor associated wi-th -the receiving controller maintains a received state variable, designated as 36 V(R) which specifies the next send sequence number 37 N(S) that is expected to be received in an incoming 01 information frame. Subsequent to link set up or link 02 reset, its value is also zero. When the expected 03 sequence number is received, V(R) is incremented by Q4 one. For each transmitted information or supervisory 05 frame, the current value of V(R) is assigned to the 06 receive sequence number N(R) in the control field.
07 The processor associated with the 08 transmitting controller maintains an expected 09 acknowledgernent variable, ~(S), equal to the sequence number of the information frame that has been 11 outstanding for the longest time. A(S) represen-ts a 12 lower bound for the aforementioned sliding window of 13 the transmitting controller. After link set up or 14 link reset, its value is zero.
The value ~(R) serves as an 16 acknowledgement of reception of all frames between 17 A(S) and ~(R)-l. A(S) is incremented in response to 18 receiving acknowledgements from the receiving 19 controller until it is equal to N(R), at which time the next acknowledgement received is the same as the 21 next frame expected by the receiving controller. It 22 will be noted that acknowledging frames that have 23 already been acknowledged by a previous N(R) has no 24 effect since A(S) and N(R) will be equal.
As discussed above, the purpose of using 26 HDLC protocol in -the present invention is to provide 27 guaranteed delivery of message signal packets. Hence, 28 recovery from errors is the most important aspect of 29 the protocol. The protocol employs a retransmission strategy for error recovery. After transmitting an 31 information frarne while there are no outstanding 32 frames (i.e. A(S)=V(S)), the processor associated with 33 the transmit~ing controller executes a subroutine for 34 implementing an internal retransmission -timer, designated as Tl. In the event an acknowledgemen-t is 36 received for all currently outstanding frames, the 37 timer is stopped. If an acknowledgement is received 3~ - 42 -01 processor associated with the transmi-tting controller 02 detects that one or all of the transmitted frames have 03 been lost or damaged during transmission, and were not 04 received by the receiving controller. The processor 05 therefore halts the Tl timer and causes -the 06 transmitting controller to retransmit a]l outstanding 07 frames numbered from A(S) to V(S~-l, in sequential 08 order. Timer Tl is then restarted. The -transmitting 09 controller internally bu~fers all transmitted frames until -they have been acknowledged by the receiving 11 controller and associated processor. Upon 12 retransmission, the values of N(R) are updated to the 13 current value of V(R) but the values oE N(S) are 14 maintained at their originally transmitted values.
The processor associated with the transmitting 16 controller maintains a count of the number of -times 17 the controller has had to retransmit a particular 18 window of frames. If -the count exceeds a 19 predetermined value, the processor will take recovery action usually in -the form of attempting to reset the 21 link.
22 In the event the receiving controller 23 receives a frame having an N(S) value equivalen-t to 24 the current value of V(R), the processor associated therewith executes a subroutine for starting an 26 acknowledgement timer, designated as T2. If the timer 27 is already running, it is no-t affected. In the event 28 the transmit-ting controller sends an information frame 29 while T2 is running, the value N(R) in the control field of -the frame is assigned the current value of 31 V~R) and -the processor associated with the receiving 32 controller, upon detecting this, stops the T2 timer.
33 In the even-t -the T2 timer expires before any 34 information Erames are transmitted in the reverse direction, then a supervisory frame is sent having 36 S(N)=00 indicating that the receiver is ready , and 37 the value of N(R) is sent equal to V(R). Thus, the 01 purpose of the T2 timer is twofold. Firstly, i-t 02 allows -the receiving controller to receive several 03 frames before generating an acknowledgement, in order 04 -that the number of receiver ready frames that must be 05 -transmitted and received is minimized, and secondly, 06 it gives the receiving controller -the opportunity of 07 eliminating generation and transmission of a receiver 08 ready supervisory frame by simply transmitting an 09 information frame in the reverse direction (i.e. to the previous transmitting controller), wi-th the 11 current value of N(R) made equal to V(S), which serves 12 to acknowledge all previously received frames. This 13 procedure is known in the art as "piggy-backing"
14 acknowledgements.
The T2 timer ensures that the receiving 16 controller waits only a predetermined amount of time 17 before generating an acknowledgement, ei-ther by 18 transmitting a receiver ready supervisory signal or by 19 piggy-backing acknowledgements. Ideally, the T2 timer is set such that the receiving controller provides 21 acknowledgements -to the -transmit-ting controller before 22 the Tl timer elapses.
23 In the event the receiving controller and 24 associated processor encounter an information ~rame with N(S) not equal to V(R), the frame is detected as 26 being out of sequence and therefore erroneous. This 27 situation can arise in the event the previous 28 informa-tion frame was damayed during transmission and 29 failed the CRC check at -the physical layer of -the frame, or because an acknowledgement was los-t or did 31 not arrive in sufficient time. The receiving 32 controller se-ts an internal flag indicating tha-t i-t is 33 in a reject condition. In the event the flag was no-t 34 already set, the receiving controller genera-tes a supervisory frame having S(N)=01 indicating a reject 36 condition and sets the value of N(R) equal to V(R)o 37 In the even-t the transmitting controller 3s3 - 44 -01 and associated processor receive a supervisory frame 02 indicating ~he reject condition, all outstanding 03 frames with sequence numbers up to but not including 04 N(R) are deemed to have been acXnowledged, and 05 alloutstanding frames with sequence numbers from ~R) 06 to V(S)-l are retransmitted.
07 Upon correctly receiving an informa-tion 08 frame with N(S)=V(R), the processor associated with 09 the receiving controller resets the internal reject condition flag. The purpose of the internal flag is ll -to ensure that only one reject function is transmitted 12 while the receiving controller is in a reject 13 condition. A proliferation of reject frames could 14 conceivably cause a large number of unnecessary retransmissions.
16 In the event the supervisory frame 17 transmitted by the receiving controller and including 18 the indication of a reject condition is lost, the Tl 19 timer ensures eventual retransmission of -the unacknowledged information frames.
21 Thus, the purpose of the supervisory bits 22 S(N) in the supervisory frame is twofold. Firstly, it 23 enables the processor associated with the receiving 24 controller to request retransrnission prior to the Tl timer running out, thereby speeding up the eventual 2~ reception of correct information frames, and secondly, 27 it prevents the transmitting controller from 28 transmitting further frames while the Tl timer is 29 still running and -the receiving controller is in a reject condition. These frames are only retransmitted 31 when the timer expires because -the Erame -that caused 32 the reject condition remains unacknowledged.
33 Supervisory frames containing an 34 indica-tion of frame rejection are only generated in the event an ou-t of sequence information frame is 36 received. They are not sent in the event a frame with 37 a failed CRC is detected at -the physical layerO

01 HDLC protocol i5 used primarily as a 02 point-to-point protocol between sta-tions having 03 dedicated links extending therebetween. According to 04 the present inven-tion, communication controller 7 is 05 multiplexed through CSM 5 for communication with a 06 plurality of sta-tions (i.e. individual ones of the 07 HDLC controller 2339, etc.).
08 During normal operation, each of the 09 controllers 23 and 39 receive "null" flags (i.e. a succession of at least 7 logic one bits from the main 11 controller). In order to accomplish this, MCP 1 12 writes null flags into a plurality of internal 13 registers of the connection memory data registers llOA
14 and B, as discussed above with reference to Figure 4A. The conten-ts of the connect:ion memory data 16 registers are transmitted to the individual controller 17 23 and 39 during the aforementioned dynamically 18 allocated time slot channels.
19 Similarly, each of -the controllecs 23 and 39 generate null flags for transmission and storage in 21 associated ones of the connection memory data 22 regis-ters llOA and B~ MCP 1 continually polls the 23 internal data registers in response to execution of an 24 interrupt subroutine, at a rate of approximately once per 5 milliseconds.
26 Considering operation of the invention, 27 in the event a subscriber's se-t connected to one of 28 the peripheral circuits 17... 19 of BAY 1 goes 29 off-hook, the associated line status circuit generates an off-hook signal. PCP 13 continually scans the line 31 status circuits in a well known manner and detects the 32 off-hook signal. In response, PCP 13 formats a 33 network layer message signal in DRAM 27 for 34 transmission to MCP 1. An internal send guarantee time (i.e. a program loop executed by PCP 13) is 36 initiated which regulates the amount of time elapsed 37 before DMAC 25 is activated in order to -transmit the 01 message signal via controller 23 to MCP 1. Thus, a 02 plurality oE message signals can be concatenated in 03 DRAM 27 during the elapsed time. As discussed above, 04 this alleviates the necessity of sending separa-te 05 message signals requiring separate acknowledgements.
06 Once the send guarantee timer runs out (i.e. aE-ter 07 approximately 5 milliseconds), the packet is assigned 08 a sequence number ~(S) by PCP 13, as discussed above.
09 The sequence number is unique between the transmi-tting and receiving controllers (23 and 7, respectively) for 11 the particular link (i.e. for the particular 12 subsystem). Thus, a difEerent one of the subsystems 13 (i.e. BAY N) may transmit a link layer message signal 14 packet on a different link, having the same sequence number, N(S). ~Iowever, controller 7 on the main 16 control board distinguishes between the separate links 17 via CSM 5, thereby keeping track oE the different 18 sequence numbers.
19 PCP 13 generates predetermined address signals on the A0, Al, A2 and A3 address lines for 21 application to decoder 315, with reference to Figure 22 6. In response, the Q5 output thereof goes high, 23 thereby enabling controller 23 via the TXE input.
24 Controller 23 then starts generating start flags (i.e. 01111110) during allocated time slo-t channels in 26 response to receiving clock bursts on ~he TXC inpu-t 27 thereof from ~AND gate 335, as discussed above.
28 Successive start flags are generated during the 29 allocated time slot channels for transmission along PCM link LI5A and storage in the associated in-ternal 31 register of connection memory data register 110A or B
32 of DX circuit 5A (Figure 2). As discussed above, MCP
33 1 continually polls the connection memory da-ta 34 registers 110A and B via the associated controller interface 117 (Figure 4B). Upon de-tection of a start 36 flag in the internal register, MCP 1 generates a "go 37 ahead" flag for storage in the internal register of ~5~

01 connection memory da-ta register llOA or B associated 02 with the allocated channel of the L05A data link 03 connected to con-troller 23, as discussed in further 04 detail below.
05 While awaiting reception of the "go ahead"
06 flag acknowledgement from MCP 1, PCP 13 initializes 07 DMAC 25 for transmission of message signals to 08 controller 23 from DRAM 27. In the interim, 09 additional message signals can be buffered into DRAM
27 for transmission in the message signal packet.
11 DMAC 25 directly transfers message signals 12 stored in DRAM 27 to controller 23 during the 13 allocated time slot channels. DMAC 25 is utilized in 1~ lieu of PCP 13 to transfer data from DRAM 27 to controller 23. At a 64 kilobit per second data rate, 16 a PCP 13 interrupt would be required to be serviced 17 each 125 microseconds in order to transfer data from 18 DRAM 27 to controller 23, via PCP 13. PCP 13 i5 19 unable to service the interrupt quickly enough resulting in an over run condition in controller 23, 21 wherein data is received after the transmit clock 22 signal applied to the TXC input has stopped running, 23 resulting in loss of data. DMAC 25 guarantees 24 efficient and rapid transfer of data from DRAM 27 to HDLC 23.
26 As discussed above, a transmit window is 27 defined for establishing the maximum number of 28 buffered untransmitted information frames. In the 29 preferred embodiment, sequence numbers N(S)=000, 001 and 010 were utilized. The number of packets 31 outstanding before an acknowledgement (i.e. the window 32 size) is dependent upon the size of DRAM 27.
33 As discussed above, the present invention utilizes 64k 34 bytes o~ DRAM 27 (expandable to 256k bytes).
Accordingly, in the event a larger DRAM 27 (i.e. 256k 36 bytes) is utilized to buffer a greater number of 37 message siynals, the window size could conceivably be 38 - ~8 --~L2~

01 made larger.
02 As discussed above, MCP 1 effectively 03 polls CS~ 5 for detection of the start flags. Upon 04 detection of a start flag generated by controller 23, 05 MCP 1 establishes a circuit switch link through CSM 5 0~ between controllers 23 and 7, (i.e. between links LI5A
07 and LOOA through DX circuit 5A). Also, ~CP 1 08 generates predetermined signals on address lines AO-A2 09 of address ~us ~00 for application to decoder 407. As a result, the QO outpu-t -thereof goes high, thereby 11 applying a logic high signal to the RXEN input of 12 controller 7, and enabling controller 7 to receive the 13 start flag on the RXSI input -thereof in response to a 14 clock burst being received on the RXCLK input from NAND gate 432, as discussed above. In response to 16 receiving the start flag and according to the bit 17 synchronous nature of the HDCL protocol, controller 7 18 synchronizes itself with controller 23. Controller 7 19 requires reception of at least 1 and up to 1 and 1/2 start 1ags in order to become synchronized. While it 21 is in the process of synchronizing, MCP 1 generates 22 the aforementioned "go ahead" flag to controller 23 23 along -the L05A link, via CSM 5. According to the 24 preferred embodiment, the "go ahead" flag was designated by the hexadecimal value 7F, and was 26 written into the outgoing connection memory data 27 register of DX circuit 5A and transmitted along the 28 L05A data link. Hence, one PC~ frame (i.e. 125 29 microseconds) is required to synchronize the transmitting and receiving controllers, and Eor the 31 receiving controller to generate and send the go ahead 32 flag. PCP 13 simultaneously configures controller 23 33 to operate in a receiver mode, in order to detect the 34 go ahead flag 7F, and generate an interrupt to priority encoder 3~1 from the RXDA output, when 36 received.
37 In response to receiving -the in-terrupt via 38 _ ~9 _ 01 priority encoder 3~1, PCP 13 enables DMAC 25 to start 02 sending message signals stored in DRA~ 27 to 03 controller 23. In particular, PCP 13 generates 04 predetermined signals on the address lines A1~, A15 05 and A16 applied to decoder 307, which in response 06 generates a logic low signal from the Q2 output 07 thereo~ for application to NAND gate 311. The message 08 signals are stored in 8 bit HDLC transmit buffers 09 internal to controller 23. The first 8 bit portion of the frame to be sent (after the start flag), is the 11 control by-te, as discussed above. The control byte 12 contains the aforementioned send and receive sequence 13 numbers N(S) and N(R) respectively. The control byte 14 is transmitted along the LI5A link in response to a burst of clock signal received on the TXC input of 16 controller 23 from NOR gate 337, and an enable signal 17 being applied to buffer 317 from NAND gate 335, as 18 discussed above.
19 DMAC 25 subsequently re-trieves and applies an 8 bit portion of the message signal stored in DRAM
21 27 to 8 bit transmit buffers internal to the 22 controller 23. The contents of the transmit buffer is 23 transmitted from the TXSO output of controller 23 in 2~ response to the enable signals being applied to buffer 317, and clock signals being applied to the TXC
26 input. Subsequently 8 bit portions are transmitted 27 in like manner. After each 8 bit portion of the 28 message signal has been transmitted, the transmit 29 buffer empty output ~TXBE), of controller 23 goes high, generating a channel 2 DMA request to retrieve a ~2 further 8 bits from DRAM 27. DMA requests are 33 acknowledged via the ACK2 output of DMAC 25 going low, 3~ causing the output of NAND gate 311 to go low, thereby enabling controller 23.
36 In response to a link layer message signal 37 packet being received on the RXSI input of controller 01 7 via CSM 5, the RXDA output thereof goes high, 02 generating a DMA channel 2 reques-t to DMAC 9O The 03 serial data received on -the RXSI input oE contr~ller 7 04 is synchronized and shiEted into an 8 bit con-trol 05 charac-ter shift register on the rising edge of the 06 clock signal applied to the RXCLK ~erminal. The 07 aforementioned zero dele-tion (after -five ones are 08 received) is implemented on the received serial data 09 so that a data character is not misinterpreted as a flag signal, as discussed above. Data bits received 11 subsequent to reception of the start flag and control 12 byte, are transmitted through a plurality of further 13 internal shift register and applied to the D0-D15 14 terminals of controller 7. The RXDA output then goes high, generating a DMA channel 2 interrupt request to 16 DMAC 9.
17 In response to the DMA channel 2 reques-t 18 DMAC 9 receives the network layer message signal 19 appearing on the D0 D15 terminals of controller 7 via data bus 403 and latch 404. The message signal is 21 latched from latch 404 to the mul-tiplexed input of 22 DMAC 9 in response to predetermined control signals 23 being generated on the LCTRL output of DMAC 9 for 24 application to latch 404 in a well known manner. DMAC
9 then stores the received message signal portion in a 26 predetermined address in DRAM 11.
27 Upon transmitting the last 8 bit portion 28 of the information frame, controller 23 generates the 29 aforementioned FCS portion of the frame, which is transmitted during the alloted time slot channels for 31 recep-tion by controller 7 through CSM 5, as discussed 32 above. Controller 7 performs a modulo-2 addition on 33 the 16 bit FCS portion, thereby implementing a CRC
34 check, in a well known manner.
In the event -the CRC check is successful, 36 a supervisor type frame is transmi-tted from con-troller 37 7 to controller 23, including the receiver ready 01 function, and the current value of N(R) indicating 02 ackno~ledgement of all frames with sequence numbers up 03 -to but not including N(~). As discussed above, the 04 supervisor type frame serves as an acknowledgement.
05 The receive status available output (RXSA) 8~ then goes high, thereby generating an interrupt on 08 Peripheral Control Line channel 2 (PCL2). This 09 indicates that the packet has been terminated, causing DMAC 9 to generate an interrupt request to MCP 1 via 11 the IRQ output thereof. In response MCP 1 disables 12 DMAC 9, and continues normal operation, (i.e. polling 13 the connec-tion memory data registers of the DX
14 circuits disposed in CSM 5 for detec-tion oE further start flags.
16 In the event the CRC error check fails, 17 the received message signal packet is discarded, 18 (i.e. no acknowledgement is sent from controller 7 to 19 controller 23), resulting in retransmission by controller 23, as discussed above. A~ter -the closing 21 flag is sen-t the TXBE output of controller 23 goes 22 high, interrupting PCP 13. PCP 13 services the 23 interrupt via decoder 315, thereby disabling the 24 transmitter of controller 23 by causing the TXE input to go low.
26 As discussed above, a number of strategies 27 are employed for ensuring correct transmission of 28 message signals. For example, in the event the Tl 29 retransmit timer runs out (after approximately 150 milliseconds), controller 23 will retransmi-t the 31 message signal packe-t. Alternatively, in the event 32 controller 23 sends a second packet before the timer 33 has run out, and controller 7 receives the packet but 34 detects an erroneous sequence number, an i.nternal reject flag is se-t and a supervisory frame is 36 genera-ted con-taining an indication of the reject 37 condition (i.e. S(N)=01). In response, controller 23 01 retransmits both message signal packets.
02 Thus, an information frame is passed up to 03 the network layer via DMAC 25 only in the event the 04 sequence number N(S) and FCS check are correct.
05 According to the present invention, the network layer 06 message signals (i.e. the contents of the information 07 frame) include an address header portion comprised of 08 a prede-termined number o-f bytes, for indicating the 09 destination o* the message. For example, the message can be utilized to initiate various subroutines of the 11 operating system program in order to implement various 12 Eeatures, such as call processing, etc.
13 In the event DRAM ll is ~ull and unable to 14 receive further message signals, controller 7 generates a further supervisory frame indicating that 16 the receiving controller is not ready (i.e. S(N)=10).
17 Once the data stored in DRAM 11 has been processed and 18 there i8 room to bu~er Eurther data, the receiver l9 ready supervisory control frame is -transmitted, (i.e.
S(~)=00).
21 Because the transmit and receive channels 22 on each communication controller are independent, each 23 controller is simultaneously "listening" for start 24 flags, and also transmitting idle or null flags.
In order to -transmi-t message signals from 26 controller 7 to one of the controllers in the 27 peripheral subsystems, (i.e. controller 23), MCP 1 28 formats the message signal in DRAM 11. The message 29 signal is assigned a sequence number N(S), as discussed above. MCP l generates predetermined 31 address signals on the A0-A2 address lines of address 32 bus 400 for application to decoder 407, with reEerence 33 to Figure 7. In response, the Ql output thereof goes 34 high, thereby enabling controller 7 via the TXEN
input. Controller 7 then starts generating start 36 flags (i.e. 01111110) during allocated time slot 37 channels in r~sponse to receiving clock bursts on the `` ~.2~

01 TXCLK input thereof from ~AND yate 4320 02 Communication controller 23 receives and 03 detects the HDLC flag signal on the RXSI input 04 thereof, received from the L05A outpu~ link of CSM 5, 05 and generated by controller 7. Controller 23 then 06 generates an interrupt signal via the RXSA and RXDA
07 outputs thereof through priority encoder 341.
8~ Controller 23 simultaneously requests mastership of DMA channel 1 via the REQl input thereof. Message 11 signals are subsequen-tly received by controller 23 in 12 an identical manner as discussed above. Once the 13 message signals have been received in their entirety, 14 an end flag signal is generated by controller 7 and received by con-troller 23 which, in response, 16 interrupts PCP 13 via encoder 341. PCP 13 then 17 disables controller 23 via the RXE input thereof 18 connected to the Q6 output of decoder 315.
19 Controller 7 receives message signals from DRAM 11 via DMAC 9 using DMA channel 3. In 21 particular, MCP 1 generates predetermined address 22 signals on the AO-A2 lines of address bus 400 for 23 causing the Q2 output oE decoder 407 to go low. The ~g output of NOR gate 40'3 thus goes low, causing a ~q channel 3 interrupt request on the REQ3 input of DMAC
28 9. DMAC 9 generates an acknowledge signal on the ACK3 29 output thereo~ for application to a predetermi~ed one of the control inputs o~ controller 7 via OR gate 405 31 and inverter 406. DMAC 9 begins transferring data 32 ~rom DRAM 11 via data bus 403 to the DO-D15 terminals 33 o~ controller 7. The message signal appeacing on the 34 DO-D15 terminals is loaded into an internal transmit buffer according to the link layer protocol, as 36 discussed above, and transmitted on the TXSO output.
37 Upon transmission of the link layer message signal, 3~ _ 5~ _ 01 the transmit buffer is emp-ty and the TXBE output of 02 controller 7 goes high generating a reques-t for 84 transer of urther data (i.e. message signals) Erom 05 DRAM 11, via the PCL3 and REQ3 inputs of DMAC 9. Upon 06 completion of the DMA transfer, a control signal is 07 generated on the DONE output of DMAC 9 for application 08 to the aforementioned predetermined control input of 09 con-troller 7, via OR gate 405 and converter 406.
In order to initially establish a 11 communication link between one of the controllers in 12 the peripheral subsystem (i.e. 23 or 39~, and 13 controller 7, the peripheral controller sends start 14 flags which are stored in the allocated internal connection memory data register of the associated DX
16 circuit in CSM 5, as discussed above. According to 17 the present invention, MCP 1 polls active links at a 18 rate of approximately once per 10 milliseconds and 19 polls inactive links at a somewhat slower rate of approximately once per 100 milliseconds. In the event 21 MCP 1 de-tects a start flag in an inactive link, it 22 generates and transmits the "go ahead" flag as 23 discussed above. In response to receiving the go 24 ahead flag~ the periphera] communication con~roller (i.e. 23 or 39) generates the aforementioned SABM flag 26 in an unnumbered frame, (i.e. bits 5, 4, 2, 1 and 0 27 are 1, 1, 1, 0 and 0 respectively). In response to 28 receiving the SABM flag, controller 7 generates an 29 unnumbered acknowledgemen-t signal (i.e. an unnumbered frame wherein bits 5, 4, 2, 1 and 0 are 0, 0, 1, 1 and 31 0 respectively).
32 ~ny of -the communication controllers in 33 the communication system of the presen-t inven-tion can 34 reset a link during normal operation by transmitting an SABM frame. Upon reception of the SABM frame, the 36 receiving controller replies with an unnumbered 37 acknowledgement frame and resets all o the ~L~$~

01 aforemention state variables to zero. Upon reception 02 of the unnumbered acknowledgement frame acknowledging 03 the SABM frame, the -transmitting station then resets 04 all state variables to zero. All information Erames 05 buffered internally by both sta-tions are discarded.
06 The link is then considered reset and informa-tion 07 transfer can resume.
08 In summary, the voice, data and message 09 switching requirements of a digital PABX are fulfilled in the present invention by implementing a combination 11 of circuit and packet switching techniques through use 12 of circuit switch and peripheral swi-tch matrices 13 comprised of digital crosspoint switches, such as 14 Mitel DX circuits.
The main and peripheral control 16 processors, MCP 1 and PCP 13 (or 29) respectively 17 share a portfolio of tasks which implement overall 18 system functionality. The main control processor MCP
19 1 has the highest level of authority and runs under call processing software in order to generate call 21 progress, DTMF tones, interface floppy disks, and 22 provide conferencing, etc. It also configures the 23 connection matrix of CSM 5, and provides message 24 signals to the one or more peripheral control processors, PCP 13 or PCP 29, etc.
26 The peripheral control processor (PCP 13 27 or 29) in turn buffers real time events (such as 28 off-hook and dialling signals), and communicates with 29 the main con-trol processor MCP 1 via high-level data link protocol message signals. In a successful 31 embodiment of the invention, up to two transmit 32 channels (channels 0 and 16) were used for 33 transmi-tting message signals from the main controller 34 to the peripheral controllers, and up to eight of transmit channels (0, 4, 8, 12, 16, 20, 24 and 28) 36 were used to send message signals from each of the one 37 or more peripheral processors (PCP 13 or 29, etc.,).

3B~

01 The plurali-ty of transmit channels are polled by the 02 main control processor MCP 1, in order to detect 03 message signals.
04 In addition, a dedicated DMA channel to 05 service the communication controllers (23 and 39) 06 provides bulk data transfer Erom the main controller 07 to the peripheral subsystems via the message system, 08 during power-up or reset.
09 Numerous other variations or alternative embodiments may now be conceived by a person skilled 11 in the art understanding the present invention and 12 using the principles disclosed herein. For 13 instance, whereas the preferred embodimen-t referred 14 to a communication system comprised of a main control board and ten peripheral subsystems, with 16 messaging signals being transmitted through the 17 circui-t and peripheral switches, it is contemplated 18 that a combination subsystem can be constructed 19 having the circuit switch and peripheral switch matrices disposed on a single board, and a 21 predetermined number of peripheral circuits 22 connected there-to. In this alternative embodiment, 23 message signals need not be transmitted via the 24 communication controller since the peripheral switch is located on the same board as -the main control 26 processor, MCP 1. Hence, both the circuit swi-tch 27 matrix and peripheral switch matrix can be 28 con~igured via the control buses.
29 Also, as discussed above, more than ten peripheral subsystems can be used, suitable 31 modifications being made to the circuit switch 32 matrix CSM 5 to accommodate the larger number o-f 33 links, since each subsystem is not required to have 3~ a separate dedicated time slot channel as in prior art systems. According to the present invention the 36 CSM 5 polls the message channels, thereby 37 effec-tively multiplexing the main commun:Lcations 01 con-troller 7.
02 In addition, since the peripheral 03 subsystems are capable of -transmitting message 04 signals on -Erom one to eight dynamically allocatable 05 channels of a PCM frame, it is apparent that 06 bay-to-bay (or subsystem-to-subsystem) communication 07 of message signals is possible through CSM 5.
08 Indeed, it is contemplated that with the advent of 09 digital telephones and data sets, message signals of the variety and type described herein can be 11 transmitted between peripheral subsystems, 12 intelligen-t peripherals (such as digital telephones~
13 and the main controller on dynamically allocated 1~ time slot channels.
Also, whereas the preferred embodiment 16 oE the invention utilizes a variation of HDLC
17 protocol, it will be understood that the system 18 according to the present invention could be 19 implemented according -to any well known bit-oriented data link protocol, such as the X.25 protocol 21 recommended by CCITT.
22 All such variations and alternative 23 embodiments are considered to be within -the sphere 2~ and scope of the invention as defined in the claims appended hereto.

2~ - 58 -~,

Claims (20)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A communication system, comprised of:
(a) a main controller, for controlling time and space multiplex switching of voice and data signals, (b) one or more peripheral subsystems for transmitting and receiving said voice and data signals to and from a plurality of peripherals connected thereto during predetermined time slot channels, under control of respective peripheral control processors, (c) a circuit switch matrix connected to said main controller and said peripheral subsystems, for performing time and space multiplex switching of said voice and data signals between said peripheral subsystems under control of said main controller, and (d) a plurality of communication controller means each connected to said circuit switch matrix, first predetermined ones of said communication controller means also being connected to respective ones of said peripheral control processors and a further one of said communication controller means also being connected to said main controller, for exchanging message signals between said respective ones of said peripheral control processors and said main controller via said circuit switch matrix in accordance with a bit-oriented data link protocol, during a further predetermined one of said time slot channels, wherein said message signals are exchanged according to a version of HDLC protocol and each of said communication controller means is comprised of a multi-protocol communications controller, whereby error-free transmission and reception of message signals is effected simultaneously with voice and data transmission and reception.

2. A communication system as defined in claim 1, further comprised of means for multiplexing said further communication controller means in order to accommodate simultaneous independent exchange of said message signals between individual ones of said peripheral control processors and said main controller.

3. A communication system as defined in claim 2, further including means for dynamically allocating additional predetermined ones of said time slot channels for exchanging said message signals, comprised of circuitry for generating transmit clock signal bursts during predetermined allocated time slot channels, the number of said predetermined allocated time slot channels being proportional to a desired volume of message signal traffic, and circuitry for applying said clock signal bursts to clock signal inputs of said plurality of communication controller means, whereby the amount of message signal traffic is made variable relative to voice and data signal traffic.

4. A communication system as defined in claim 1, wherein said main controller is comprised of:
(a) memory means for storing network layer message signals and one or more call processing programs, (b) main control processor means connected to said circuit switch matrix and said memory means for executing said programs and controlling said circuit switch matrix in response thereto, and (c) direct memory access means connected to said memory means and said further communication controller means, for translating said network layer message signals between said further communication controller means and said memory means.

5. A communication system as defined in claim 4, further including means for dynamically allocating additional predetermined ones of said time slot channels for exchanging said message signals, comprised of circuitry for generating and applying transmit and receive clock signal bursts to said further communication controller means.

6. A communication system as defined in claim 3, 4 or 5, wherein said message signals are transmitted and received according to a version of HDLC protocol and said further communication controller means is comprised of a multi-protocol communications controller circuit.

7. A communication system as defined in claim 1, 4 or 5, wherein said circuit switch matrix is comprised of a plurality of digital time/space crosspoint switching circuits.

8. A communication system as defined in claim 4 or 5, wherein said main control processor means is a microprocessor circuit.

9. A communication system as defined in claim 4 or 5, wherein said memory means is comprised of one or more dynamic random access memory circuits.

10. A communication system as defined in claim 1, wherein said one or more peripheral subsystems are each further comprised of:
(a) memory means for storing network layer message signals and one or more call processing programs, (b) said peripheral control processor being connected to said memory means, and being adapted for executing said programs and generating control signals in response thereto, (c) a peripheral switch matrix connected to said peripheral control processor, said circuit switch matrix, and via one or more circuit paths to said plurality of peripherals, for receiving said control signals and transmitting and receiving said voice and data signals between individual ones of said peripherals, and between said plurality of peripherals and the circuit switch matrix in response to reception of said control signals, and (d) direct memory access means connected to said memory means and a corresponding one of said communication controller means, for exchanging said network layer message signals between said corresponding one of said communication controller means and said memory means.

11. A communication system as defined in claim 10, further including means for dynamically allocating additional predetermined ones of said time slot channels for exchanging said message signals, comprised of circuitry for generating and applying transmit and receive clock signal bursts to said corresponding one of said communication controller means.

12. A communication system as defined in claim 10 or 11, wherein said peripheral switch matrix is comprised of a plurality of digital time/space crosspoint switching circuits.

13. A communication system as defined in claim 10 or 11, wherein said peripheral control processor means is a microprocessor circuit.

14. A communication system as defined in claim 10 or 11, wherein said memory means is comprised of one or more dynamic random access circuits.

15. In a communication system comprised of a main controller, one or more peripheral subsystems, and a circuit switch matrix for performing time and space multiplex switching of time slot channels carrying digital voice and data signals between said peripheral subsystems under control of said main controller, a message system comprised of:
(a) one or more communication controller means connected to said one or more subsystems and said circuit switch matrix, for transmitting and receiving network layer message signals in accordance with a bit-oriented data link protocol to and from said subsystems and in response transmitting and receiving link layer message signals to and from the circuit switch matrix during a predetermined one of said time slot channels, (b) a further communication controller means connected to said main controller and said circuit switch matrix, for transmitting and receiving said link layer message signals received and transmitted by said one or more communication controller means via said circuit switch matrix, and in response transmitting and receiving said network layer message signals in accordance with said bit-oriented data link protocol to and from the main controller, and (c) means included in each of said communication controller means for detecting errors in transmission of said link layer message signals and causing retransmission of said message signals in response thereto, whereby error free transmission and reception of message signals is effected simultaneously with voice and data signal transmission and reception.

16. A message system as defined in claim 15, further comprised of means for multiplexing said further communication controller means in order to accommodate simultaneous independent transmission and reception of said link layer message signals between individual ones of said one or more communication controller means and said further communication controller means.

17. A message system as defined in claim 16, wherein said link layer message signals are transmitted and received according to a bit-oriented data link protocol.

18. A message system as defined in claim 15, wherein said link layer message signals are transmitted and received according to a version of HDLC protocol.

19. A message system as defined in claim 15, further including means for dynamically allocating further predetermined ones of said time slot channels for transmitting and receiving said link layer message signals, comprised of circuitry for generating transmit clock signal bursts during predetermined allocated time slot channels for application to each of said communication controller means, the number of said predetermined allocated time slot channels being proportional to a desired volume of message signal traffic, whereby the amount of message signal traffic is variable relative to voice and data signal traffic in response to said channels being dynamically allocated.

20. A communication system, comprised of:

(a) a main controller, for controlling time and space multiplex switching of voice and data signals, (b) one or more peripheral subsystems for tansmitting and receiving said voice and data signals to and from a plurality of peripherals connected thereto during predetermined time slot channels, under control of respective peripheral control processors, (c) a circuit switch matrix connected to said main controller and said peripheral subsystems, for performing said time and space multiplex switching of said voice and data signals between said peripheral subsystems under control of said main controller, and (d) a plurality of communication controller means each connected to said circuit switch matrix, first predetermined ones of said communication controller means also being connected to respective ones of said peripheral control processors and a further one of said communication controller means also being connected to said main controller, for exchanging message signals between said respective ones of said peripheral control processors and said main controller via said circuit switch matrix in accordance with a bit-oriented data link protocol, during predetermined time shared ones of said time slot channels for each of said peripheral subsystems, whereby error-free transmission and reception of message signals is effected simultaneously with voice and data transmission and reception.