CA1259422A - Method and apparatus for performing variable length data read transactions - Google Patents
Method and apparatus for performing variable length data read transactionsInfo
- Publication number
- CA1259422A CA1259422A CA000511442A CA511442A CA1259422A CA 1259422 A CA1259422 A CA 1259422A CA 000511442 A CA000511442 A CA 000511442A CA 511442 A CA511442 A CA 511442A CA 1259422 A CA1259422 A CA 1259422A
- Authority
- CA
- Canada
- Prior art keywords
- data
- transferred
- system memory
- memory
- command
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 title claims abstract description 18
- 230000003139 buffering effect Effects 0.000 claims description 12
- 238000013479 data entry Methods 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 description 3
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
Abstract
Abstract A method and apparatus for performing variable length data read transactions is presented in accordance with a preferred embodiment of the present invention. An input/output (I/O) device which performs variable length data read transactions, such as one which includes a terminal, has associated with it a command linked list, located in system memory, in which a system processor or memory controller has placed command elements. For read transactions, each element typically specifies the place in system memory where data will be transferred, and the number of bytes of data to be transferred. The I/O device autonomously fetches elements on the linked list and executes them. As bytes are being transferred from the I/O device to system memory a residual byte count is kept by the I/O device. When the I/O
device has completed the data transfer, it may interrupt or otherwise provide the system processor with status information as to the data transfer. Additionally, the system processor may terminate a data transfer by sending a special flush command to the I/O device. Upon receipt of the flush command, the I/O
device stops the data transaction, and returns to the system processor the residual byte count. The residual byte count is used by the system processor to determine how many bytes of information were transferred to system memory.
device has completed the data transfer, it may interrupt or otherwise provide the system processor with status information as to the data transfer. Additionally, the system processor may terminate a data transfer by sending a special flush command to the I/O device. Upon receipt of the flush command, the I/O
device stops the data transaction, and returns to the system processor the residual byte count. The residual byte count is used by the system processor to determine how many bytes of information were transferred to system memory.
Description
I
1¦A METHOD AND APPARATUS FOR PERFORMING
21VARIABLE LENGTH DATA ~EAD TRANSACTIONS
3 Back~ d 4High performance computer peripherals US9 direct memory access (DMA) to efficiently transfer data from a peripheral 6 device to a computer memory. However, when the computer 7 peripheral is a terminal there are special problems involved in 8 the implementation of DMA transfers. Particularly, the amount of 9 data an operator of the terminal desires to transmit typically cannot be accurately predicted by a system pracessor.
11 In the prior art, various sche~ea have been used to 12 i~plement data transfers using ter~inals. For lnstance, a first-13 in-first-out (FIFO) buffer may be used to receive data from a 14 terminal. The system processor may then periodically poll the FIFO buf~er, and process any available data. This scheme, 16 however, requires memory space on the interface between the 17 terminal and the system processor. Also, thls polling 18 implementation is somewhat less ef~icient than DMA trans~ers.
19 A second scheme used in the prior art is for the terminal to interrupt the system processor to handle every character. This 21 scheme may be disadvantageous in that a large portion of system 22 processor time can be consumed if each character is individually 23 processed~ Interrupting per character can be especially 24 consumptive o~ processor time when a sys~em processor ls servicing several terminals simultaneously.
26 A third scheme used in the prior art is ~or a terminal to 27 transfer blocks of characters, which are delimited by special 28 characters (for instance, a carriage return). This scheme, 1~, however, may not be used in conjunction with certain operating systems, such as UMIX (Trade Mark), which allow application programs to process individual characters from a terminal as they are receivedO
~ r, ~ t~e IDVeDt;~n In accordance with the preferred embodiment of the present invention a method and apparatus for performing variable length data read transactions is presented. An input/output (I/O) device which performs variable length data read transactions, such as on~ which includes a terminal, has associated with it a command linked list, located in system memory, in which a system processor or memory controller has placed command elements. For read transactions, each element typically specifies the place in system memory where data will be transferred, and the number of bytes of data to be transferred.
The I/O device autonomously fetches elements on the linked list and executes them. As bytes are being transferred from the I/O device to system memory a residual byte count is kept by the I/O device. When the I/O device has completed the data transfer, it may interrupt or otherwise provide the system processor with status information as to the data transfer.
Additionally, the system processor may tPrminate a data transfer by sending a special flush command to the I/O device. Upon receipt of the flush command, the I/O
device stops the data transaction, and returns to the system processor the residual byte count. The residual byte count is used by the system processor to determine how many bytes of information were transferred to svstem memory. When the I/O device has finished respondiny to the flush command, it again starts up data transfers to system memory.
The above scheme for performing variable length data read transactions frees a system processor to specify the length of expected data transfer from an I/O
device and also gives the system processor flexi~ility to terminate the transfer if the amount of data is less than e~pected, or if the system processor wants to begin processing of data already collected.
Various aspects of this invention are as follows:
A method for receiving input from an input/output device comprising:
providing a plurality of consecutive memory locations for receiving data from the input/output device, providing to the input/output device an address of at least one of the plurality of memory locations;
providing to the input/output device a count which specifies the number of memory locations in the plurality of memory locations;
providing a command to the input/output ~evice to terminate transfer of data to the plurality of memory locations; and, receiving information as to how many of the plurality of consecutive mPmory locations received data from the input/output device.
A method utilizing a system processor to oversee a transfer of data from a first device to a system memory, the method comprising:
sending a command instruction from the system to the first device, the command instruction specifying a location in the system memory where data is to be transferred, and a unit count which indicates the amount of data to be transferred;
transferring data from the first device to the system memory;
sending a sec~nd command inctruction from the system to the first device, the command instruction instructing the first device to stop the transfer of data from the first device to the system memory; and ~2~
sending status information from the first device to the system processor, the status in~ormation indicating the amount of data transferred from the first device to the system memory.
A method utilizing a system processor to oversee a transfer of data from a first device to a system memory, the method comprising:
sending a command instruction from the system to the first device, the command instruction specifying a location in the system memory where data is to be transferred, and a unit count which indicates the amount of data to be transferred;
buffering data within the first device;
sending a second command instruction from the system to the first device, the command instruction instructing the first device to transfer the buffered data from the first device to the system memory; and sending status information from the first device to the system processor, the status information indicating the amount of data transferred from the first device to the system memory.
An apparatus for performing variable length data transactions from first device to a system memory, the apparatus comprising:
buffering means to receive data from the first device; command means for specifying to the buffering means a location in the system memory where data is to be transferred, and a unit count which indicates the amount of data to be transferred; and, flush means for specifying to the buPfering means to transfer data it has received from the first device;
and, status means for indicating the amount of data transferred from the first device to the buffering means in a period of time the period of time extending from a 3a ~25~2 point in time at which the command means specified to the bu~fering means the location and the unit count to a point in time when the flush means specified to the buffering means to transfer data.
Brief Description of the Drawinqs Figure 1 shows a system processor, system memory, and various I/0 devices coupled to a bus, in accordance with a preferred embodiment of the present invention.
Figure 2 shows a plurality of elements on a linked list in accordance with the preferred embodiment of the present invention.
Figures 3A, 3B, and 3C show a portion of system memory and an I/O device in accordance with the preferred embodiment of the present invention.
Figure 4 shows a portion of an I/0 device in accordance with a second preferred embodiment of the present invention.
Description of the Preferred ~mbodiment In Figure 1, a system processor 11, a system memory 14, an I/O device 12; an I/O device 13, and an I/0 device 15 are shown coupled to a bus 16. I/O device 15 includes a computer terminal 18 and a direct memory access terminal adaptor 17.
3b ~ 1 ~25~
1 ¦ In order for system processor 11 to obtaln data from
1¦A METHOD AND APPARATUS FOR PERFORMING
21VARIABLE LENGTH DATA ~EAD TRANSACTIONS
3 Back~ d 4High performance computer peripherals US9 direct memory access (DMA) to efficiently transfer data from a peripheral 6 device to a computer memory. However, when the computer 7 peripheral is a terminal there are special problems involved in 8 the implementation of DMA transfers. Particularly, the amount of 9 data an operator of the terminal desires to transmit typically cannot be accurately predicted by a system pracessor.
11 In the prior art, various sche~ea have been used to 12 i~plement data transfers using ter~inals. For lnstance, a first-13 in-first-out (FIFO) buffer may be used to receive data from a 14 terminal. The system processor may then periodically poll the FIFO buf~er, and process any available data. This scheme, 16 however, requires memory space on the interface between the 17 terminal and the system processor. Also, thls polling 18 implementation is somewhat less ef~icient than DMA trans~ers.
19 A second scheme used in the prior art is for the terminal to interrupt the system processor to handle every character. This 21 scheme may be disadvantageous in that a large portion of system 22 processor time can be consumed if each character is individually 23 processed~ Interrupting per character can be especially 24 consumptive o~ processor time when a sys~em processor ls servicing several terminals simultaneously.
26 A third scheme used in the prior art is ~or a terminal to 27 transfer blocks of characters, which are delimited by special 28 characters (for instance, a carriage return). This scheme, 1~, however, may not be used in conjunction with certain operating systems, such as UMIX (Trade Mark), which allow application programs to process individual characters from a terminal as they are receivedO
~ r, ~ t~e IDVeDt;~n In accordance with the preferred embodiment of the present invention a method and apparatus for performing variable length data read transactions is presented. An input/output (I/O) device which performs variable length data read transactions, such as on~ which includes a terminal, has associated with it a command linked list, located in system memory, in which a system processor or memory controller has placed command elements. For read transactions, each element typically specifies the place in system memory where data will be transferred, and the number of bytes of data to be transferred.
The I/O device autonomously fetches elements on the linked list and executes them. As bytes are being transferred from the I/O device to system memory a residual byte count is kept by the I/O device. When the I/O device has completed the data transfer, it may interrupt or otherwise provide the system processor with status information as to the data transfer.
Additionally, the system processor may tPrminate a data transfer by sending a special flush command to the I/O device. Upon receipt of the flush command, the I/O
device stops the data transaction, and returns to the system processor the residual byte count. The residual byte count is used by the system processor to determine how many bytes of information were transferred to svstem memory. When the I/O device has finished respondiny to the flush command, it again starts up data transfers to system memory.
The above scheme for performing variable length data read transactions frees a system processor to specify the length of expected data transfer from an I/O
device and also gives the system processor flexi~ility to terminate the transfer if the amount of data is less than e~pected, or if the system processor wants to begin processing of data already collected.
Various aspects of this invention are as follows:
A method for receiving input from an input/output device comprising:
providing a plurality of consecutive memory locations for receiving data from the input/output device, providing to the input/output device an address of at least one of the plurality of memory locations;
providing to the input/output device a count which specifies the number of memory locations in the plurality of memory locations;
providing a command to the input/output ~evice to terminate transfer of data to the plurality of memory locations; and, receiving information as to how many of the plurality of consecutive mPmory locations received data from the input/output device.
A method utilizing a system processor to oversee a transfer of data from a first device to a system memory, the method comprising:
sending a command instruction from the system to the first device, the command instruction specifying a location in the system memory where data is to be transferred, and a unit count which indicates the amount of data to be transferred;
transferring data from the first device to the system memory;
sending a sec~nd command inctruction from the system to the first device, the command instruction instructing the first device to stop the transfer of data from the first device to the system memory; and ~2~
sending status information from the first device to the system processor, the status in~ormation indicating the amount of data transferred from the first device to the system memory.
A method utilizing a system processor to oversee a transfer of data from a first device to a system memory, the method comprising:
sending a command instruction from the system to the first device, the command instruction specifying a location in the system memory where data is to be transferred, and a unit count which indicates the amount of data to be transferred;
buffering data within the first device;
sending a second command instruction from the system to the first device, the command instruction instructing the first device to transfer the buffered data from the first device to the system memory; and sending status information from the first device to the system processor, the status information indicating the amount of data transferred from the first device to the system memory.
An apparatus for performing variable length data transactions from first device to a system memory, the apparatus comprising:
buffering means to receive data from the first device; command means for specifying to the buffering means a location in the system memory where data is to be transferred, and a unit count which indicates the amount of data to be transferred; and, flush means for specifying to the buPfering means to transfer data it has received from the first device;
and, status means for indicating the amount of data transferred from the first device to the buffering means in a period of time the period of time extending from a 3a ~25~2 point in time at which the command means specified to the bu~fering means the location and the unit count to a point in time when the flush means specified to the buffering means to transfer data.
Brief Description of the Drawinqs Figure 1 shows a system processor, system memory, and various I/0 devices coupled to a bus, in accordance with a preferred embodiment of the present invention.
Figure 2 shows a plurality of elements on a linked list in accordance with the preferred embodiment of the present invention.
Figures 3A, 3B, and 3C show a portion of system memory and an I/O device in accordance with the preferred embodiment of the present invention.
Figure 4 shows a portion of an I/0 device in accordance with a second preferred embodiment of the present invention.
Description of the Preferred ~mbodiment In Figure 1, a system processor 11, a system memory 14, an I/O device 12; an I/O device 13, and an I/0 device 15 are shown coupled to a bus 16. I/O device 15 includes a computer terminal 18 and a direct memory access terminal adaptor 17.
3b ~ 1 ~25~
1 ¦ In order for system processor 11 to obtaln data from
2 ¦ terminal 18, it constructs a linked list o~ command elements in
3 ¦ system memory 14. For example, a linXed list 20 consist~ng of 41 command elements 21, 22, 23, 24 and ~S is shown in Flgure Z.
S¦ Each command element 21-25 includes a pointer representing an 6 address ln system memory 14 where data is to be transferred.
7 Each command element 21-25 also includes a counter represent~ng 8 the number of bytes tor words or some other unit of data having a 9 specified amount of data) to be transferred. For example, in command element 21 is shown a register 21a for storing a pointer, 11 and a register 21b for storing a counter. Once linked list 20 12 has been constructed, system processor 11 trans~ers to terminal 13 adaptor 17 the address in memory of the ~lrst ele~ent in linked I4 l~st 20, in this case element 21. Additionally, system processor 11 transfers to terminal adaptor 17 a command which causes 16 terminal adaptor 17 to ~etch and execute ln order command 17 elements 21-25. Starting with element 21, terminal adaptor 17 18 transfers the contents of each com~and element into registers 19 within terminal adaptor 17.
Figure 3A, Figure 3B, and Figure 3C show memory locations 21 301-311 within system memory 14 and show changes in the content 22 of register~ wlthin terminal adaptor 17 which occur during a DMA
23 transfer o~ data from terminal adaptor 17 to system memory 14.
24 For example, terminal adaptor 17 fetches element 21 and stores the pointer currently in register 2la into a register 17a and 26 the counter currently in register 2lb into a register 17b . The 228 result is shown in Figure 3A where the contents o~ register 17a 1~ 4 1¦ point to a location 302 in system memory 14 and where the 2 I contents o~ register 17b lndicate ter~inal adaptor 17 15 to 3 transfer 8 bytes of data.
S¦ Each command element 21-25 includes a pointer representing an 6 address ln system memory 14 where data is to be transferred.
7 Each command element 21-25 also includes a counter represent~ng 8 the number of bytes tor words or some other unit of data having a 9 specified amount of data) to be transferred. For example, in command element 21 is shown a register 21a for storing a pointer, 11 and a register 21b for storing a counter. Once linked list 20 12 has been constructed, system processor 11 trans~ers to terminal 13 adaptor 17 the address in memory of the ~lrst ele~ent in linked I4 l~st 20, in this case element 21. Additionally, system processor 11 transfers to terminal adaptor 17 a command which causes 16 terminal adaptor 17 to ~etch and execute ln order command 17 elements 21-25. Starting with element 21, terminal adaptor 17 18 transfers the contents of each com~and element into registers 19 within terminal adaptor 17.
Figure 3A, Figure 3B, and Figure 3C show memory locations 21 301-311 within system memory 14 and show changes in the content 22 of register~ wlthin terminal adaptor 17 which occur during a DMA
23 transfer o~ data from terminal adaptor 17 to system memory 14.
24 For example, terminal adaptor 17 fetches element 21 and stores the pointer currently in register 2la into a register 17a and 26 the counter currently in register 2lb into a register 17b . The 228 result is shown in Figure 3A where the contents o~ register 17a 1~ 4 1¦ point to a location 302 in system memory 14 and where the 2 I contents o~ register 17b lndicate ter~inal adaptor 17 15 to 3 transfer 8 bytes of data.
4 As each byte is transferred from termlnal adaptor 17 to system memory 14 the pointer ln register 17a is incremented to 6 polnt to the next location in system memory 14, and the counter 7 in register 17b is decremented to indicate the number o~ bytes 8 left to transfer.
9 In Figure 3fi, three bytes of data have been transferred.
The pointer in register 17a now point~ to m~mory location 305, 11 and the counter in register 17b lndicates there are ~ive 12¦ remaining bytes to be sent. Be~ore terminal adaptor 17 ha~
13¦ transferred the entire elght bytes, terminal adaptor 17 may 14¦ receive from 6ystem processor 11 a data tlu~h command. Upon receipt of the data Plush command, termlnal ad~ptor 17 wlll stop 16 its DMA trans~er to ~ystem ~emory 14 and will send ~o 6ystem 17 processor 11 the counter in reglster 17b, whlch lndicates to 18 system processor 11 the amount of data transferred. At the time 19 shown in Figure 3B, the counter in register 17b would indicate there are fi~e by~es remaining to be sent. System processor 11 21 can then process the bytes of data already trans~erred to system 22 memory 14. Terminal adaptor 17 will fetch the next co~and 23 element, in this case, command element 22, and continue 24 transferring data.
on the other hand, terminal adaptor 17 may transfer the 26 entire eight bytes without receiving a data ~lush command, as 27 shown in Figure 3c. Ter~inal adaptor 17 will then notify system ` I ~5~
1¦ processor 11 that the eight bytes have been transferred. This 21 notification can be done by i~terrupting the processor to deliver 31 the in~ormation, or by some other means.
4¦ In Flgure 4, an alternate embodiment ls shown. Here memory locations 401-411 are shown to be wlthln termlnal adaptor 17. In 6 the implementa~ion shown in ~igure 4, data ~rom ter~lnal 18 is 7 buffered in memory locations 401-411 within term~nal adaptor 17 8 until the counter in register 17b is zero, until all memory 9 locations (represented in Figure 4 by memory locations 401-411) within terminal adaptor are ~illed, or until terminal adaptor 17 11 receives a da~a flush co~mand ~rom system processor 11. In 12 either case, terminal adaptor 17 then writes to system memory 14 13 the data in memory locations 401-411 which te~mlnal adaptor 17 14 has received ~rom termlnal 18. Terminal ~daptor 17 will then fetch the next command alem~nt from lin~ed list 20. Termlnal 16 adaptor 17 will then continue to rec~ive data ~rom termlnal 18 0~ co ~e~ory locations 401-411.
9 In Figure 3fi, three bytes of data have been transferred.
The pointer in register 17a now point~ to m~mory location 305, 11 and the counter in register 17b lndicates there are ~ive 12¦ remaining bytes to be sent. Be~ore terminal adaptor 17 ha~
13¦ transferred the entire elght bytes, terminal adaptor 17 may 14¦ receive from 6ystem processor 11 a data tlu~h command. Upon receipt of the data Plush command, termlnal ad~ptor 17 wlll stop 16 its DMA trans~er to ~ystem ~emory 14 and will send ~o 6ystem 17 processor 11 the counter in reglster 17b, whlch lndicates to 18 system processor 11 the amount of data transferred. At the time 19 shown in Figure 3B, the counter in register 17b would indicate there are fi~e by~es remaining to be sent. System processor 11 21 can then process the bytes of data already trans~erred to system 22 memory 14. Terminal adaptor 17 will fetch the next co~and 23 element, in this case, command element 22, and continue 24 transferring data.
on the other hand, terminal adaptor 17 may transfer the 26 entire eight bytes without receiving a data ~lush command, as 27 shown in Figure 3c. Ter~inal adaptor 17 will then notify system ` I ~5~
1¦ processor 11 that the eight bytes have been transferred. This 21 notification can be done by i~terrupting the processor to deliver 31 the in~ormation, or by some other means.
4¦ In Flgure 4, an alternate embodiment ls shown. Here memory locations 401-411 are shown to be wlthln termlnal adaptor 17. In 6 the implementa~ion shown in ~igure 4, data ~rom ter~lnal 18 is 7 buffered in memory locations 401-411 within term~nal adaptor 17 8 until the counter in register 17b is zero, until all memory 9 locations (represented in Figure 4 by memory locations 401-411) within terminal adaptor are ~illed, or until terminal adaptor 17 11 receives a da~a flush co~mand ~rom system processor 11. In 12 either case, terminal adaptor 17 then writes to system memory 14 13 the data in memory locations 401-411 which te~mlnal adaptor 17 14 has received ~rom termlnal 18. Terminal ~daptor 17 will then fetch the next command alem~nt from lin~ed list 20. Termlnal 16 adaptor 17 will then continue to rec~ive data ~rom termlnal 18 0~ co ~e~ory locations 401-411.
Claims (5)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
I claim:
1. A method for receiving input from a input/output device comprising:
providing a plurality of consecutive memory locations for receiving data from the input/output device;
providing to the input/output device an address of at least one of the plurality of memory locations;
providing to the input/output device a count which specifies the number of memory locations in the plurality of memory locations;
providing a command to the input/output device to terminate transfer of data to the plurality of memory locations; and, receiving information as to how many of the plurality of consecutive memory locations received data from the input/output device.
providing a plurality of consecutive memory locations for receiving data from the input/output device;
providing to the input/output device an address of at least one of the plurality of memory locations;
providing to the input/output device a count which specifies the number of memory locations in the plurality of memory locations;
providing a command to the input/output device to terminate transfer of data to the plurality of memory locations; and, receiving information as to how many of the plurality of consecutive memory locations received data from the input/output device.
2. A method as in claim 1 wherein the providing to the input/output device of an address, and the providing to the input/output device of a count is done by means of a linked list of data entries consisting of memory locations.
3. A method utilizing a system processor to oversee a transfer of data from a first device to a system memory, the method comprising:
sending a command instruction from the system to the first device, the command instruction specifying a location in the system memory where data is to be transferred, and a unit count which indicates the amount of data to be transferred;
transferring data from the first device to the system memory;
sending a second command instruction from the system to the first device, the command instruction instructing the first device to stop the transfer of data from the first device to the system memory; and, sending status information from the first device to the system processor, the status information indicating the amount of data transferred from the first device to the system memory.
sending a command instruction from the system to the first device, the command instruction specifying a location in the system memory where data is to be transferred, and a unit count which indicates the amount of data to be transferred;
transferring data from the first device to the system memory;
sending a second command instruction from the system to the first device, the command instruction instructing the first device to stop the transfer of data from the first device to the system memory; and, sending status information from the first device to the system processor, the status information indicating the amount of data transferred from the first device to the system memory.
4. A method utilizing a system processor to oversee a transfer of data from a first device to a system memory, the method comprising:
sending a command instruction from the system to the first device, the command instruction specifying a location in the system memory where data is to be transferred, and a unit count which indicates the amount of data to be transferred;
buffering data within the first device;
sending a second command instruction from the system to the first device, the command instruction instructing the first device to transfer the buffered data from the first device to the system memory; and, sending status information from the first device to the system processor, the status information indicating the amount of data transferred from the first device to the system memory.
sending a command instruction from the system to the first device, the command instruction specifying a location in the system memory where data is to be transferred, and a unit count which indicates the amount of data to be transferred;
buffering data within the first device;
sending a second command instruction from the system to the first device, the command instruction instructing the first device to transfer the buffered data from the first device to the system memory; and, sending status information from the first device to the system processor, the status information indicating the amount of data transferred from the first device to the system memory.
5. An apparatus for performing variable length data transactions from first device to a system memory, the apparatus comprising:
buffering means to receive data from the first device;
command means for specifying to the buffering means a location in the system memory where data is to be transferred, and a unit count which indicates the amount of data to be transferred; and, flush means for specifying to the buffering means to transfer data it has received from the first device: and, status means for indicating the amount of data transferred from the first device to the buffering means in a period of time, the period of time extending from a point in time at which the command means specified to the buffering means the location and the unit count to a point in time when the flush means specified to the buffering means to transfer data.
buffering means to receive data from the first device;
command means for specifying to the buffering means a location in the system memory where data is to be transferred, and a unit count which indicates the amount of data to be transferred; and, flush means for specifying to the buffering means to transfer data it has received from the first device: and, status means for indicating the amount of data transferred from the first device to the buffering means in a period of time, the period of time extending from a point in time at which the command means specified to the buffering means the location and the unit count to a point in time when the flush means specified to the buffering means to transfer data.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/750,377 US4703418A (en) | 1985-06-28 | 1985-06-28 | Method and apparatus for performing variable length data read transactions |
| US750,377 | 1985-06-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1259422A true CA1259422A (en) | 1989-09-12 |
Family
ID=25017624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000511442A Expired CA1259422A (en) | 1985-06-28 | 1986-06-12 | Method and apparatus for performing variable length data read transactions |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4703418A (en) |
| EP (1) | EP0208430B1 (en) |
| JP (1) | JPH0752418B2 (en) |
| CA (1) | CA1259422A (en) |
| DE (1) | DE3673270D1 (en) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4851991A (en) * | 1987-02-24 | 1989-07-25 | Digital Equipment Corporation | Central processor unit for digital data processing system including write buffer management mechanism |
| AU622626B2 (en) * | 1987-06-03 | 1992-04-16 | Sony Corporation | Method of processing data |
| US4998198A (en) * | 1988-04-07 | 1991-03-05 | Tandem Computers Incorporated | Dynamic burst control for data transfers |
| US5251303A (en) * | 1989-01-13 | 1993-10-05 | International Business Machines Corporation | System for DMA block data transfer based on linked control blocks |
| US5255371A (en) * | 1990-04-02 | 1993-10-19 | Unisys Corporation | Apparatus for interfacing a real-time communication link to an asynchronous digital computer system by utilizing grouped data transfer commands |
| US6751696B2 (en) | 1990-04-18 | 2004-06-15 | Rambus Inc. | Memory device having a programmable register |
| IL96808A (en) | 1990-04-18 | 1996-03-31 | Rambus Inc | Integrated circuit i/o using a high performance bus interface |
| US6324120B2 (en) | 1990-04-18 | 2001-11-27 | Rambus Inc. | Memory device having a variable data output length |
| JPH0520263A (en) * | 1991-07-15 | 1993-01-29 | Nec Corp | Data transfer controller |
| US5379381A (en) * | 1991-08-12 | 1995-01-03 | Stratus Computer, Inc. | System using separate transfer circuits for performing different transfer operations respectively and scanning I/O devices status upon absence of both operations |
| US5444853A (en) * | 1992-03-31 | 1995-08-22 | Seiko Epson Corporation | System and method for transferring data between a plurality of virtual FIFO's and a peripheral via a hardware FIFO and selectively updating control information associated with the virtual FIFO's |
| US5517670A (en) * | 1992-12-30 | 1996-05-14 | International Business Machines Corporation | Adaptive data transfer channel employing extended data block capability |
| US6122717A (en) * | 1996-06-17 | 2000-09-19 | Integrated Device Technology, Inc. | Methods and apparatus for a memory that supports a variable number of bytes per logical cell and a variable number of cells |
| US6802022B1 (en) | 2000-04-14 | 2004-10-05 | Stratus Technologies Bermuda Ltd. | Maintenance of consistent, redundant mass storage images |
| US6886171B2 (en) | 2001-02-20 | 2005-04-26 | Stratus Technologies Bermuda Ltd. | Caching for I/O virtual address translation and validation using device drivers |
| US6766413B2 (en) | 2001-03-01 | 2004-07-20 | Stratus Technologies Bermuda Ltd. | Systems and methods for caching with file-level granularity |
| US6971043B2 (en) | 2001-04-11 | 2005-11-29 | Stratus Technologies Bermuda Ltd | Apparatus and method for accessing a mass storage device in a fault-tolerant server |
| EP1591906A1 (en) * | 2004-04-27 | 2005-11-02 | Texas Instruments Incorporated | Efficient data transfer from an ASIC to a host using DMA |
| US20060259657A1 (en) * | 2005-05-10 | 2006-11-16 | Telairity Semiconductor, Inc. | Direct memory access (DMA) method and apparatus and DMA for video processing |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4038642A (en) * | 1976-04-30 | 1977-07-26 | International Business Machines Corporation | Input/output interface logic for concurrent operations |
| JPS54530A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Reference control unit of memory |
| JPS5455132A (en) * | 1977-10-12 | 1979-05-02 | Toshiba Corp | Input-output control system |
| JPS586173B2 (en) * | 1978-01-20 | 1983-02-03 | 株式会社日立製作所 | Channel control method |
| JPS57113162A (en) * | 1980-12-29 | 1982-07-14 | Fujitsu Ltd | High-speed external storage device |
| US4644463A (en) * | 1982-12-07 | 1987-02-17 | Burroughs Corporation | System for regulating data transfer operations |
-
1985
- 1985-06-28 US US06/750,377 patent/US4703418A/en not_active Expired - Lifetime
-
1986
- 1986-06-09 JP JP61133591A patent/JPH0752418B2/en not_active Expired - Lifetime
- 1986-06-12 DE DE8686304504T patent/DE3673270D1/en not_active Expired - Lifetime
- 1986-06-12 EP EP86304504A patent/EP0208430B1/en not_active Expired
- 1986-06-12 CA CA000511442A patent/CA1259422A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0752418B2 (en) | 1995-06-05 |
| EP0208430B1 (en) | 1990-08-08 |
| DE3673270D1 (en) | 1990-09-13 |
| JPS623362A (en) | 1987-01-09 |
| EP0208430A1 (en) | 1987-01-14 |
| US4703418A (en) | 1987-10-27 |
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