CA1262189A - Method and apparatus for implementing optimum prml codes - Google Patents
Method and apparatus for implementing optimum prml codesInfo
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- CA1262189A CA1262189A CA000532490A CA532490A CA1262189A CA 1262189 A CA1262189 A CA 1262189A CA 000532490 A CA000532490 A CA 000532490A CA 532490 A CA532490 A CA 532490A CA 1262189 A CA1262189 A CA 1262189A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/04—Conversion to or from representation by pulses the pulses having two levels
- H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
- H03M5/145—Conversion to or from block codes or representations thereof
Abstract
ABSTRACT OF THE INVENTION
METHOD AND APPARATUS FOR IMPLEMENTING OPTIMUM PRML CODES
Rate 8/9, constrained codes having run length limitation parameters (0, 4/4) and (0, 3/63 are provided for any partial response (PR) signaling system employing maximum likelihood (ML) detection.
METHOD AND APPARATUS FOR IMPLEMENTING OPTIMUM PRML CODES
Rate 8/9, constrained codes having run length limitation parameters (0, 4/4) and (0, 3/63 are provided for any partial response (PR) signaling system employing maximum likelihood (ML) detection.
Description
MET~OD AND APPAR~TUS FOR I~PLEMENTING OPTIMNM PRML CODES
Background of the Invention Partial Response Maximum Likelihood (PRML) techniques have been long associated with digital communication channels. See fox example, Y. Kabal and S. Pasupathy, "Partial-Response Signaling", IEEE Trans. Commun.
Technol , Vol. COM-23, pp. 921-934, September 1975; R. W.
Lucky, J. Salz and E. J. Weldon, Jr., PRINCIPLES OF DATA
COMM~NICATIONS, New York: McGraw-Hill, 1968; G. D. Forney/
Jr., "The Viterbi Algorithm", Proc. IEEE, VolO 61, pp.
268-278, March 1973; and J. M. Wozencraft and I. M.
Jacobs, PRINCIPLES OF COMMUNICATION ENGINEERING, New York:
Wiley, 1965. Applying the principles of PRML signaling and detectlon to recording channels of mass storage ~devices is also well known. See ~or example, G. D.
Forney, "Maximum Likelihood Sequence Estimation of Digital Sequences in the Presence of Intersymbol Interference", - IEEE Trans. Inform. Theoryj Vol. IT-18, pp. 363-378, May ~ 1982; ~. ~obayashi, "Application of Probabilistic Decoding to Digital Magnetic Recording", IBM. J. RES. DEVELOP., Vol. 15, pp. 64-74, January 1971; and K. Nishimura and K.
Ishii, "A Design Method for Optimal E~ualization in Magnetic Recording Channels with Partial Response Channel Coding", IEEE Trans. Magn~, Vol. MAG-l9, pp. 1719-1721, September 1983.
S~9~85-048 3~
Data detection in conventlonal prior art peak-detection ~agnetic recording channels is achieved by first di~ferentiating the analog signal and then processing the differentiated signal with a zero-crossing 5detector to determine the presence or absence of a zero-crossing event within the detection window. Data detection in a digital communication channel is generally based on periodically sampling the amplitude of the transmitted signal.
10In the absence of noise or other imperfections, the zero crossings of the derivative signal in peak detection occur only at times corresponding to the clocktimes at which a transition wa~ ~ritten. Enhancements such as precompensation, run-length-limited (RLL) codes and more 15sophisticated detectors have extended the perfor~ance of peak detection systems.
In sampled or clocked detection, the amplitude of the signal is periodically sampled and the data which those samples represent is interpreted therefrom. Maximum 20likelihood (ML) detection minimizes the probability of error when the samples are interpreted.
Sampled amplitude detection anticipates the presence of interfering non-zero sample amplitudes corresponding to each input at more than one sampling time~ Such signals 25are referred to as partial response (P~) signals, and channels which transmit PR ~ignals are often referred to as PR ch~nnels.
ML detection is typically used in PR channels (hereafter, PRML channels) al-thoug~, barring cost and complexity considerations, it can be used in peak detection and other applications as well. Typically, for a given ch~nnel bandwidth, a PR signal permits transmission of data ~t a higher rate than full response signals which have zero amplitude at all but one of the sampling times. In addition to filtering the readback signal to condition it for most accurate detection and interpretation, other techniques, such as encoding the data, are usecl to enhance performance of ML detectors.
Encoding data lor use with recording channels is also known The Id,k) constraints, which specify the minimum and maximum run lengths of ~eroes, respectively, in RLL
codes used in peak-detection systems, reduce intersvmbol interferences while maintaining s~ clocking character-istics o~ the data signal. See, for example, IBM
TECHNICAL DISCLOSURE BULLETIN, Vol. 28, No. 5, October 1985, pp. 1938--1940, entitled "Improved Encoder and Decoder for a Byte-Oriented (0,3) 8/9 Code`', and IBM
TECHNICAL DISCLOSURE Bl]LLETIN, Vol. 18, No. 1, June 1975, pp. 248-251, entitled `'Encoder and Decoder for a Byte-Oriented (0,3) 8/9 Code".
~L~6~
In a PR*SL channel, a channel code can also be used to pro~ide clocking and automatic gain control (AGC) information. Since the maximum run length of nominally zero samples must be limited, the k constraint is still appropriate when specifying the channel code re~uirements for PRML channels. However, RLL codes with d grea~er than zero are not necessary in PRML channels because compensation for ISI is inherent in the ML detector.
Thus, there is no need to reduce inter~erence by coding with a d constraint.
On the other hand, the k constraint is not the only constraint required for the PRML channel. Since ML
detection reauires that more than one option be kept open with respect to recent past data estimators, an additional lS constraint is desired to limit both detector delay and hardware complexity. If a data sequence of the input signal is demultiplexed into an even indexed sample subsequence and an odd indexed sample subsequence, and ML
detection is applied to each subsequence independently, a constraint on ~he number of successi~e nominally zero , samples in each subsequence adequately limits the detector delay and hardware. Thus, in terms of NRZI data representation, the required limitation is on the maximum number of sequential zeroes in ~oth the even-indexed and the odd-indexed subsequences. The maximum number of sequential NRZI zeroes in either subsequence is referred to as the kl constx~int, and is analogous to the k constrain~ for the ~verall sequence of data.
.... .
Codes havlng run len~th constraints restrict the allowed code sequences to less than 2n sequences possible, where n specifies the number of data symbols in a sequence. The rate of such a code is less than 1 data bit to 1 code bit, which can be expressed as a ratio of small integers. Thus, if an 8-bit data byte is mapped into a 9-bit codeword, the code rate is 8/9.
Summary of the Invention The present invention relates to modulation codes sultable for PR channels employing ML detectlon. These modulation codes improve performance of the timing and gain control circuits of the channel by providing ~requent non-zero samples. In addition, they limit the complexity of the ML detector by forcing path merging in the path memory during processing of data estimators.
The modulation codes according to the present invention are characterized by three parameters d, k, and kl written (d, klkl). The parameters d and k represent the minimum and maximum of run lengths of zeroes in the channel output code bit sequence, where a run length of zeroes may be regarded as a period of silence in the detection process. The parameter kl represents the maximum run length of zeroes in the particular al7-even or all-odd subsequences. In the codes of the present invention, d equals 0 since a minimum run length of zeroes is inapposite in the context of PR~lL channel. A small value of k is desirable for accurate timing and gain SA9~85-048 5 control, and a small value of k1 reduces the size of the path mem~ry required in the ML detector.
In particular, the presen-t inventlon is related to PRML code constraints for use in magnetlc recording of digital data in disk memory devices. The code constraints and the apparatus for encodinq and decoding data in accordance therewith is applicable, however, to any PR
signaling system employing ML detection.
According to the present invention, the smallest value of the parameters k and k1 for which a rate 8/9, tO,k/kl) block code exists are (0,3l6) and (0,4/4). The present invention provides optimized sequential logic circuits including look-up tables for encoding and decoding rate 8/9 block codes having these parameters.
Description of the Drawing Fig. 1 is a schematic diagram of a PRML system ~odulation code encoder for a code having rate 8/9 and run length constraints (0,4/4), constructed according to the principles of the present invention.
Fig. 2 is a schematic diagram of a P~ML system modulation code decoder for a code having rate 8/9 and run length constraints (0,4/4), constructed according to the principles of ~he present invention.
Fig. 3 is a legend of schematic symbol conventions used in Figs. 1, 2, 5 and 6.
., S~9-85 048 6 g ~321~3i'3 Fig. 4 is a table of 279 decimal numbers equivalent to 9-bit binary sequences derived in accordance with the principles of the present invention for the rate 8/9, (0,4/4) code.
Fig. 5 i5 a schematic diagram of a PRML system modulation code decoder for a code having rate 8/9 and run length constraints (0,3/6), constructed according to the principles of the present invention.
Fig. 6 is a schematic diagram of a PRML system modulation code decoder for an alternative code having rate 8/9 and run length constraints (0,3/6), constructed according to the principles of the present invention.
Fig. 7 is a table of 272 decimal numbers equivalent to 9-bit binary seauences derived in accordance with the principles of the present invention for the rate 8/9, (0,3/6) code.
Description of the Pre~erred Embodiment In accordance with the present invention, a rate 8/9 RLL block code having (0,4/4) constraints provides 279 9-bit codewords from 8-bit data bytes. Thus, at least 256 codewords oE 9 bits each can be uniquely de~ined where all catenations of such codewords comply with the d, k/k1 constraint. The code provides for specific assi~nment of 8-bit data hytes to 9-bit codewords which preserves read ~ 39 backward symmetrv and creates partitions of bytes and codewords with simi].ar structure~ The partitions of bytes are uniquely identifiable and overall mapping of the codewords is produced by gating partltion bits according to simple boolean functions.
If Y denotes a 9-bit codeword in the (O,k/kl) code, then Y [Y1, Y2, Y3, Y4~ Ys~ Y6~ Y7~ Y8~ Yg] (1) The constraint k = 4 in the overall coded sequence can be produced by eliminating 9-bit sequences with run lengths of 3 zeroes at either end thereof, or run lengths of 5 zeroes within each 9-bit sequence. Such a constraint is given by the following boolean relation:
(Yl+Y2+Y3) (Y2+Y3+Y4+Y5+Y6) (Y3+Y4+Y5+Y6+Y7) ( 4~Y5+Y6+Y7ty8) (Y7+Y8+yg) = 1 (2) Similarly, the constraint kl = 4 is described by the following two equations for the sequence of all odd-bit positions and the sequence of all even-bit positions, respectively, in Equations (3) and (4~ given below.
(Yl+Y3+Y5) (Ys+Y7+Yg) = 1 (3) (~2+Y4+Y6) (Y~+Y6+y8) 1 ~ j2 ~ ~3 Two hundred seventy-nine valid 9~bit binary sequences satisfy Equations (2), (3), and (4), the decimal equivalents for whi.ch are given in Fig. 4. Thus, 23 excess codewords are available or special purposes or for use as alternates to eliminate undesirable codeword patterns.
Referring now to Fig. 1, an 8-bit binary data byte, denoted X, and its assigned 9-bit codeword, Y, are given by:
X = lXl, ~2' X3~ X4, ~5, X6, X7, 8]
Y [Yl, Y2, Y3, Y4 " Ys~ Y6~ Y7~ Y8~ ~9] ~6) The first partition of codeword assignments, denoted Mt comprises the set of data bytes in which the first and last four bits of the 8-bit binary data bytes can be : 15 mapped without change into the first and last four bits, respectively, of the 9-bit codeword, YO The middle bit, i.e. the fifth bit position, of the 9 bit codeword in this partition is always 1~ Thus, partition M comprises 163 codewords which can be identified by the relation:
( 1+X2+X3) (X4+xs3 (X6~X7+X8~ ~ X2X7 (7) A second partition, Ml, comprises 8-bit binary data ~ytes in which the first four bytes of Y ~re the same as those in X. Thus, Ml, which includes M, comprises twelve ~ 2 ~ 3 addition~l codeword assignments identified by a speci~ic structure of the first four bits in X given by the equation:
Ml = M ~ ~xl+x3) ~4 (8) The remaining 81 codeword assignments are divided into partitions Nl, Rl and Sl, which identi~y 42, 7 and 32 codeword assignments, respec~ively. These assignments are given by the following structures of the firs~ four bits-in X:
Nl = M (XllX3~ X4 , Rl = M tXl~X3) X2, (10) Sl = M (Xl+X3) X2 (11) The code inherently provides read-backward symmetry, which means that the last four bits of X are mapped into the last four bits of Y symmetrically with respect to the first ~our bits of Y, read backwards. Thus, the last four bits of the last-mentioned remainin~ 81 codeword assignments are given by partitions M2, N2, R2 and S2 n which are backwardly symmetricAl counterparts o~ the partition sets M1, Nl, R1 and Sl, ~espectively, In particularr M2, N2, R2 and S2 are identified by eXclusive structures of the las~ four bi~s of X given by logic equations symmetrical to Equations ~8), ~9), ~101 and (11) as given in Chart I.
.
To avoid an all ones coded sequence, the middle bit, Y5, i~s chan~ed to zero which, in turn, creates another valid codeword. The logic equations for encoder 100 of Fig. 1 are given in Chart I.
The decoder function identifies the same partitions as those in the encoder, using the exclusive structures of bit patterns in the 9-bit sequence Y to obtain logic equations for the components of X. Decoder equations for the decoder o~ Fig. 2 are provided in Chart II.
Referring now to Fig. 1, encoded variables, X1-X8 are received by gates 101-106, 108-112, 114-118, 120-122, 124-127 and 130-142 of encoder 100. In response to such variables, gates 107-110 produce codeword partitions Ml, N1, R1 and S1, respectively. Similarly, gates 113-116 produce codeword partitions M2, N2, R2 and S2. Finally, encoded variables Y1-Yg are produced by gates 117, 119, 121, 128, 129, 134, 138, 139 and 141, respectively.
Coded variables, Y1-Yg, are received by gates 201-204, 207-218 and 225 234 of decoder 200 as shown in Fig. 2. Backward reading, codeword partitions, Ml, N1, R
and S1, for recreating uncoded variables, i.e. the data, are produced by gates 205, 207, 209 and 212, respectively, in response to coded variables Y1~Yg. Similarly, partitions M2, N2, R2 and S2 are produced by gates 206, 208, 210 and 214, respectively. Finally, the data, X1-X8, SA9-85-048 ll ~ 3 is provided by gates 215, 219, 216, 221, 222, 217, 220 and 218, respectively.
Another version of rate 8/9 (0, k/k1) codes in accordance with the present invention have k = 3 and k1 =
6. The partition of codeword assignments for a (0,3/6) block code is given in Chart III which shows logic equations for partitions Ml, M2, M3, M, E, Nl, R1, Sl, N2, R2, and S2. Also shown in Chart III are the encoder logic functions for encoder 500 of Fig. 5.
The decoder function identifies the partitions M, E, Nl, R1, S1, N2, R2, and S2 using the structure of the 9-bit codeword YO Th,e logic equations for these partitions, as well as the decoder logic functions for decoder 600 of Fig. 6 are given in Chart IV.
Referring now to Fig. 5, encoded variables Xl - X8 are received by gates 501-554 of encoder 500. In response to such variables, gates 501-503, 555, 520, 505, 5~6, 513 produce codeword partitions M1, M2, M3, M, E, N1, R1, and S1, respectively. Similarly, gates 515, 557, 519 produce codeword partitions `N2, R2, and S2. Finally, encoded variables Yl - Yg are produced by gates 558~565, respectively.
Finally, coded variables Yl - Yg are received by gates 601-641 of decoder 600 as shown in Fig. 6. ~ecoding partitions E, N1, R1 and S1 are procluced by gates 601, 604, 607 and 608, respectively, in response to coded variable Yl - Y9. Slmilarly, partitions Ml, N2, R2 and S2 are produced by gates 602, 609, 611 and 612, respectively. Decoded data Xl - X8 is provided by gates 642-649, respectively.
The constraints k=3 and kl=6 of the (0,3/6) code are obtained from the following boolean relations:
(Yl+Y2+Y3) (Y2+Y3+Y4+Y5) (Y3~Y4+Y5+Y6) (Y4+Y5+Y6+Y7) (Y5+Y6+Y7+y~)(Y8+y9) = 1 (12) (Yl+Y3+Y5+Y7)(Y3+Y5+Y7+Y9) 1 (13) (Y2+Y4+Y6+Y8) = 1 (14) The decimal equivalents of the 272 valid 9-bit binary sequences which satisfy the equations (12), (13) and (14) are shown in Fig. 7. While the numbers in Fig. 4 are symmetric (i.e., ~or each 9-bit codeword represented, the number formed by reversing to order of those bits is also represented), the numbers in Fig. 7 are not so symmetric.
Both codes described in this specification are optimum block codes in that k cannot be decreased without increasing kl, decreasing the rate or increasing the block length. Similarly, kl cannot be decreased without increasing k, decreasing the rate or increasing the block length.
SA9~85 048 13 . ..
~L~t~ 3 CIIART I
O ,4/4 ENCODER
1 + ~2 + X3)-(~4 + X5)-(X6 + X7 + X8) + X20X7 ~11 = M + (Xl + X3)~X4 M2 = M + (X8 + X6)~X5 Nl = M- (Xl + X3) ~X4 N2 = M (X8 + X6) X5 Rl - M(Xl + X3)-X2 R2 - M-(X8 + X6)oX7 Sl = (Xl + X2 + X3) Sl = (X8 + X7 ~ X6) Yl = Xl + Rl + Sl-X4 Y" = Ml-:;'' + Rl + Sl Y3 = X3 + Rl + Sl-X4 Y4 = Ml-X4 + ~ X2 + Rl-X4 + Sl- (X5 + S2) Y5 - ?1- (`;1-.';"-X3-:;4-.Y;-.';6-';7 ~X8) Y6 = ~ X5 + N2-X7 + R2~X5 + S20 ~X4 'r Sl) Y7 = X6 + R2 + S2-X5 Y8 = M2-X7 + R2 ~ S2 Y9 = X8 + R2 + S2 X5 SA9-85-0'~8 /4~
CII~URT II
0,4/4 DECODER
~1 = Y5 + Yl-Y2~Y3~Y4-Y6-Y70Y80Y9 Al = Y6 + Y2 ~ Y4 A2 = Y4 + Y8 + Y6 ~ 1 ~ A2 M2 = M + Al Nl = MoA2-Y2 N2 = M-AloY8 Rl = M-A2'Y2-Yl-Y3 R2 = M~Al-Y8Y9-Y7 Sl = ~I-A Y ~Yl-Y3) S2 = ~1-Al-Y8-(Y9~Y7) Xl = (~11 + ~ Yl X2 = ~ Y2 + N1Y4 + Rl X3 = (~11 + ~l)'Y3 __ X4 = ~1l^Y4 + Rl-Y4 + Sl-Y3 X5 = Ml-Y6 + R2-Y6 + S2-Y7 X6 = (~12 + ~2)-Y7 X7 = ~12-Y8 + N Y6 + R2 X8 = (~12 ~ N2)-Y9 -._ SA~-85-048 ~5 C~I~RT I I I
O,3/6 ENCODER
Ml = Xl + X2 + X3 ~12 = X7 + X8 M3 = X2 + X4 + X5 + X7 ~ 13E = Xl-X2X3-X4-X5-X6-X7~X8 Nl = N2-(Xl + X3)-X4 N2 = ~ (X8 ~ X6)oX5 Rl = ~17-(X2 + X5-X6)(Xl + X3)-X4 R2 = ~ (X8 + X6)oXS
-Sl = ~ 2 + X5-~6)-(Xl + ~3)~4 S2 = ~(Xl + X3)-X8 Yl = (E-~l + Nl)-Xl + Rl~X4-+ R20(X4 + X7) + Sl-X3-(Xl + X6) Y2 = (E-~l + Nl)-X2 + Rl-X3 + R2-(X4 + X7) + Sl~Xl + S2 Y3 = (~1 + Nl)-X3 + N2 + Rl-Xl + R2-(X4 + X7) + Sl Y4 - (E-~l + Nl~-X4 + N2-X4 + Rl + S2 Y5 = E-M
Y6 = (E-~l + N2)-X5 + Rl + R2 + S2-X6 Y7 = (M + N2)oX6 + N1(X5 + X6) + Rl-X6 + R2-X8 + Sl + S2 Y8 = (~1 + N2)~X7 + Nl-(X5 + X6) ~ Rl~X5 + R2~X6 ~ + Sl~(Xl + X6) ~ S2-Xl Y9 = (E9~1 + N2~-X8 + Nl-(X5 + X6) + Rl-X2 + X5-(R~ + Sl~ + S2-X3 /~ ` .
3~3 CHART IV
O, 3/6 DECODER
E = Yl-Y2~Y4Y5-Y6-Y9 M = Y5 + E
Nl = ~I-(Yl + Y3)oY4-Y6 N2 = Yl-Y2^Y6 Rl = M-(Yl + Y2-Y3)-Y40Y6 R2 = M-(Yl + Y2)-Y4-Y6 Sl = ~I-Y4~Y6 S2 = (M + Yl + Y3) Xl = E + (~1 + Nl)-Yl ~ Rl-Y3 + Sl~Y2 + S2-Y8 X2 = E + (rl ~ Nl)-Y2 + Rl-Y9 ~3 = (~1 + Nl)-Y3 + Rl-Y2 + Sl-(Yl + Y2) + S2-Y9 X4 = E + (~1 + Nl + N2)-Y4 + Rl-Yl + R2-YI-Y2 X5 = E + (M + N2)^Y6 + Nl-Y8-Y9 + Rl-Y8 + Y9-(R2 + Sl) X6 = (~1 + N2)-Y7 + Nl-Y7-Y8 + Rl-Y7 + R2-Y8 ~ Sl-(YloY2 + Y8) + S2-Y6 X7 = (~1 + N2)-Y8 + R2~Y2-Y3 X8 = E + (M + N2)-Y9 + R2-Y7 + S2 .
., .
Background of the Invention Partial Response Maximum Likelihood (PRML) techniques have been long associated with digital communication channels. See fox example, Y. Kabal and S. Pasupathy, "Partial-Response Signaling", IEEE Trans. Commun.
Technol , Vol. COM-23, pp. 921-934, September 1975; R. W.
Lucky, J. Salz and E. J. Weldon, Jr., PRINCIPLES OF DATA
COMM~NICATIONS, New York: McGraw-Hill, 1968; G. D. Forney/
Jr., "The Viterbi Algorithm", Proc. IEEE, VolO 61, pp.
268-278, March 1973; and J. M. Wozencraft and I. M.
Jacobs, PRINCIPLES OF COMMUNICATION ENGINEERING, New York:
Wiley, 1965. Applying the principles of PRML signaling and detectlon to recording channels of mass storage ~devices is also well known. See ~or example, G. D.
Forney, "Maximum Likelihood Sequence Estimation of Digital Sequences in the Presence of Intersymbol Interference", - IEEE Trans. Inform. Theoryj Vol. IT-18, pp. 363-378, May ~ 1982; ~. ~obayashi, "Application of Probabilistic Decoding to Digital Magnetic Recording", IBM. J. RES. DEVELOP., Vol. 15, pp. 64-74, January 1971; and K. Nishimura and K.
Ishii, "A Design Method for Optimal E~ualization in Magnetic Recording Channels with Partial Response Channel Coding", IEEE Trans. Magn~, Vol. MAG-l9, pp. 1719-1721, September 1983.
S~9~85-048 3~
Data detection in conventlonal prior art peak-detection ~agnetic recording channels is achieved by first di~ferentiating the analog signal and then processing the differentiated signal with a zero-crossing 5detector to determine the presence or absence of a zero-crossing event within the detection window. Data detection in a digital communication channel is generally based on periodically sampling the amplitude of the transmitted signal.
10In the absence of noise or other imperfections, the zero crossings of the derivative signal in peak detection occur only at times corresponding to the clocktimes at which a transition wa~ ~ritten. Enhancements such as precompensation, run-length-limited (RLL) codes and more 15sophisticated detectors have extended the perfor~ance of peak detection systems.
In sampled or clocked detection, the amplitude of the signal is periodically sampled and the data which those samples represent is interpreted therefrom. Maximum 20likelihood (ML) detection minimizes the probability of error when the samples are interpreted.
Sampled amplitude detection anticipates the presence of interfering non-zero sample amplitudes corresponding to each input at more than one sampling time~ Such signals 25are referred to as partial response (P~) signals, and channels which transmit PR ~ignals are often referred to as PR ch~nnels.
ML detection is typically used in PR channels (hereafter, PRML channels) al-thoug~, barring cost and complexity considerations, it can be used in peak detection and other applications as well. Typically, for a given ch~nnel bandwidth, a PR signal permits transmission of data ~t a higher rate than full response signals which have zero amplitude at all but one of the sampling times. In addition to filtering the readback signal to condition it for most accurate detection and interpretation, other techniques, such as encoding the data, are usecl to enhance performance of ML detectors.
Encoding data lor use with recording channels is also known The Id,k) constraints, which specify the minimum and maximum run lengths of ~eroes, respectively, in RLL
codes used in peak-detection systems, reduce intersvmbol interferences while maintaining s~ clocking character-istics o~ the data signal. See, for example, IBM
TECHNICAL DISCLOSURE BULLETIN, Vol. 28, No. 5, October 1985, pp. 1938--1940, entitled "Improved Encoder and Decoder for a Byte-Oriented (0,3) 8/9 Code`', and IBM
TECHNICAL DISCLOSURE Bl]LLETIN, Vol. 18, No. 1, June 1975, pp. 248-251, entitled `'Encoder and Decoder for a Byte-Oriented (0,3) 8/9 Code".
~L~6~
In a PR*SL channel, a channel code can also be used to pro~ide clocking and automatic gain control (AGC) information. Since the maximum run length of nominally zero samples must be limited, the k constraint is still appropriate when specifying the channel code re~uirements for PRML channels. However, RLL codes with d grea~er than zero are not necessary in PRML channels because compensation for ISI is inherent in the ML detector.
Thus, there is no need to reduce inter~erence by coding with a d constraint.
On the other hand, the k constraint is not the only constraint required for the PRML channel. Since ML
detection reauires that more than one option be kept open with respect to recent past data estimators, an additional lS constraint is desired to limit both detector delay and hardware complexity. If a data sequence of the input signal is demultiplexed into an even indexed sample subsequence and an odd indexed sample subsequence, and ML
detection is applied to each subsequence independently, a constraint on ~he number of successi~e nominally zero , samples in each subsequence adequately limits the detector delay and hardware. Thus, in terms of NRZI data representation, the required limitation is on the maximum number of sequential zeroes in ~oth the even-indexed and the odd-indexed subsequences. The maximum number of sequential NRZI zeroes in either subsequence is referred to as the kl constx~int, and is analogous to the k constrain~ for the ~verall sequence of data.
.... .
Codes havlng run len~th constraints restrict the allowed code sequences to less than 2n sequences possible, where n specifies the number of data symbols in a sequence. The rate of such a code is less than 1 data bit to 1 code bit, which can be expressed as a ratio of small integers. Thus, if an 8-bit data byte is mapped into a 9-bit codeword, the code rate is 8/9.
Summary of the Invention The present invention relates to modulation codes sultable for PR channels employing ML detectlon. These modulation codes improve performance of the timing and gain control circuits of the channel by providing ~requent non-zero samples. In addition, they limit the complexity of the ML detector by forcing path merging in the path memory during processing of data estimators.
The modulation codes according to the present invention are characterized by three parameters d, k, and kl written (d, klkl). The parameters d and k represent the minimum and maximum of run lengths of zeroes in the channel output code bit sequence, where a run length of zeroes may be regarded as a period of silence in the detection process. The parameter kl represents the maximum run length of zeroes in the particular al7-even or all-odd subsequences. In the codes of the present invention, d equals 0 since a minimum run length of zeroes is inapposite in the context of PR~lL channel. A small value of k is desirable for accurate timing and gain SA9~85-048 5 control, and a small value of k1 reduces the size of the path mem~ry required in the ML detector.
In particular, the presen-t inventlon is related to PRML code constraints for use in magnetlc recording of digital data in disk memory devices. The code constraints and the apparatus for encodinq and decoding data in accordance therewith is applicable, however, to any PR
signaling system employing ML detection.
According to the present invention, the smallest value of the parameters k and k1 for which a rate 8/9, tO,k/kl) block code exists are (0,3l6) and (0,4/4). The present invention provides optimized sequential logic circuits including look-up tables for encoding and decoding rate 8/9 block codes having these parameters.
Description of the Drawing Fig. 1 is a schematic diagram of a PRML system ~odulation code encoder for a code having rate 8/9 and run length constraints (0,4/4), constructed according to the principles of the present invention.
Fig. 2 is a schematic diagram of a P~ML system modulation code decoder for a code having rate 8/9 and run length constraints (0,4/4), constructed according to the principles of ~he present invention.
Fig. 3 is a legend of schematic symbol conventions used in Figs. 1, 2, 5 and 6.
., S~9-85 048 6 g ~321~3i'3 Fig. 4 is a table of 279 decimal numbers equivalent to 9-bit binary sequences derived in accordance with the principles of the present invention for the rate 8/9, (0,4/4) code.
Fig. 5 i5 a schematic diagram of a PRML system modulation code decoder for a code having rate 8/9 and run length constraints (0,3/6), constructed according to the principles of the present invention.
Fig. 6 is a schematic diagram of a PRML system modulation code decoder for an alternative code having rate 8/9 and run length constraints (0,3/6), constructed according to the principles of the present invention.
Fig. 7 is a table of 272 decimal numbers equivalent to 9-bit binary seauences derived in accordance with the principles of the present invention for the rate 8/9, (0,3/6) code.
Description of the Pre~erred Embodiment In accordance with the present invention, a rate 8/9 RLL block code having (0,4/4) constraints provides 279 9-bit codewords from 8-bit data bytes. Thus, at least 256 codewords oE 9 bits each can be uniquely de~ined where all catenations of such codewords comply with the d, k/k1 constraint. The code provides for specific assi~nment of 8-bit data hytes to 9-bit codewords which preserves read ~ 39 backward symmetrv and creates partitions of bytes and codewords with simi].ar structure~ The partitions of bytes are uniquely identifiable and overall mapping of the codewords is produced by gating partltion bits according to simple boolean functions.
If Y denotes a 9-bit codeword in the (O,k/kl) code, then Y [Y1, Y2, Y3, Y4~ Ys~ Y6~ Y7~ Y8~ Yg] (1) The constraint k = 4 in the overall coded sequence can be produced by eliminating 9-bit sequences with run lengths of 3 zeroes at either end thereof, or run lengths of 5 zeroes within each 9-bit sequence. Such a constraint is given by the following boolean relation:
(Yl+Y2+Y3) (Y2+Y3+Y4+Y5+Y6) (Y3+Y4+Y5+Y6+Y7) ( 4~Y5+Y6+Y7ty8) (Y7+Y8+yg) = 1 (2) Similarly, the constraint kl = 4 is described by the following two equations for the sequence of all odd-bit positions and the sequence of all even-bit positions, respectively, in Equations (3) and (4~ given below.
(Yl+Y3+Y5) (Ys+Y7+Yg) = 1 (3) (~2+Y4+Y6) (Y~+Y6+y8) 1 ~ j2 ~ ~3 Two hundred seventy-nine valid 9~bit binary sequences satisfy Equations (2), (3), and (4), the decimal equivalents for whi.ch are given in Fig. 4. Thus, 23 excess codewords are available or special purposes or for use as alternates to eliminate undesirable codeword patterns.
Referring now to Fig. 1, an 8-bit binary data byte, denoted X, and its assigned 9-bit codeword, Y, are given by:
X = lXl, ~2' X3~ X4, ~5, X6, X7, 8]
Y [Yl, Y2, Y3, Y4 " Ys~ Y6~ Y7~ Y8~ ~9] ~6) The first partition of codeword assignments, denoted Mt comprises the set of data bytes in which the first and last four bits of the 8-bit binary data bytes can be : 15 mapped without change into the first and last four bits, respectively, of the 9-bit codeword, YO The middle bit, i.e. the fifth bit position, of the 9 bit codeword in this partition is always 1~ Thus, partition M comprises 163 codewords which can be identified by the relation:
( 1+X2+X3) (X4+xs3 (X6~X7+X8~ ~ X2X7 (7) A second partition, Ml, comprises 8-bit binary data ~ytes in which the first four bytes of Y ~re the same as those in X. Thus, Ml, which includes M, comprises twelve ~ 2 ~ 3 addition~l codeword assignments identified by a speci~ic structure of the first four bits in X given by the equation:
Ml = M ~ ~xl+x3) ~4 (8) The remaining 81 codeword assignments are divided into partitions Nl, Rl and Sl, which identi~y 42, 7 and 32 codeword assignments, respec~ively. These assignments are given by the following structures of the firs~ four bits-in X:
Nl = M (XllX3~ X4 , Rl = M tXl~X3) X2, (10) Sl = M (Xl+X3) X2 (11) The code inherently provides read-backward symmetry, which means that the last four bits of X are mapped into the last four bits of Y symmetrically with respect to the first ~our bits of Y, read backwards. Thus, the last four bits of the last-mentioned remainin~ 81 codeword assignments are given by partitions M2, N2, R2 and S2 n which are backwardly symmetricAl counterparts o~ the partition sets M1, Nl, R1 and Sl, ~espectively, In particularr M2, N2, R2 and S2 are identified by eXclusive structures of the las~ four bi~s of X given by logic equations symmetrical to Equations ~8), ~9), ~101 and (11) as given in Chart I.
.
To avoid an all ones coded sequence, the middle bit, Y5, i~s chan~ed to zero which, in turn, creates another valid codeword. The logic equations for encoder 100 of Fig. 1 are given in Chart I.
The decoder function identifies the same partitions as those in the encoder, using the exclusive structures of bit patterns in the 9-bit sequence Y to obtain logic equations for the components of X. Decoder equations for the decoder o~ Fig. 2 are provided in Chart II.
Referring now to Fig. 1, encoded variables, X1-X8 are received by gates 101-106, 108-112, 114-118, 120-122, 124-127 and 130-142 of encoder 100. In response to such variables, gates 107-110 produce codeword partitions Ml, N1, R1 and S1, respectively. Similarly, gates 113-116 produce codeword partitions M2, N2, R2 and S2. Finally, encoded variables Y1-Yg are produced by gates 117, 119, 121, 128, 129, 134, 138, 139 and 141, respectively.
Coded variables, Y1-Yg, are received by gates 201-204, 207-218 and 225 234 of decoder 200 as shown in Fig. 2. Backward reading, codeword partitions, Ml, N1, R
and S1, for recreating uncoded variables, i.e. the data, are produced by gates 205, 207, 209 and 212, respectively, in response to coded variables Y1~Yg. Similarly, partitions M2, N2, R2 and S2 are produced by gates 206, 208, 210 and 214, respectively. Finally, the data, X1-X8, SA9-85-048 ll ~ 3 is provided by gates 215, 219, 216, 221, 222, 217, 220 and 218, respectively.
Another version of rate 8/9 (0, k/k1) codes in accordance with the present invention have k = 3 and k1 =
6. The partition of codeword assignments for a (0,3/6) block code is given in Chart III which shows logic equations for partitions Ml, M2, M3, M, E, Nl, R1, Sl, N2, R2, and S2. Also shown in Chart III are the encoder logic functions for encoder 500 of Fig. 5.
The decoder function identifies the partitions M, E, Nl, R1, S1, N2, R2, and S2 using the structure of the 9-bit codeword YO Th,e logic equations for these partitions, as well as the decoder logic functions for decoder 600 of Fig. 6 are given in Chart IV.
Referring now to Fig. 5, encoded variables Xl - X8 are received by gates 501-554 of encoder 500. In response to such variables, gates 501-503, 555, 520, 505, 5~6, 513 produce codeword partitions M1, M2, M3, M, E, N1, R1, and S1, respectively. Similarly, gates 515, 557, 519 produce codeword partitions `N2, R2, and S2. Finally, encoded variables Yl - Yg are produced by gates 558~565, respectively.
Finally, coded variables Yl - Yg are received by gates 601-641 of decoder 600 as shown in Fig. 6. ~ecoding partitions E, N1, R1 and S1 are procluced by gates 601, 604, 607 and 608, respectively, in response to coded variable Yl - Y9. Slmilarly, partitions Ml, N2, R2 and S2 are produced by gates 602, 609, 611 and 612, respectively. Decoded data Xl - X8 is provided by gates 642-649, respectively.
The constraints k=3 and kl=6 of the (0,3/6) code are obtained from the following boolean relations:
(Yl+Y2+Y3) (Y2+Y3+Y4+Y5) (Y3~Y4+Y5+Y6) (Y4+Y5+Y6+Y7) (Y5+Y6+Y7+y~)(Y8+y9) = 1 (12) (Yl+Y3+Y5+Y7)(Y3+Y5+Y7+Y9) 1 (13) (Y2+Y4+Y6+Y8) = 1 (14) The decimal equivalents of the 272 valid 9-bit binary sequences which satisfy the equations (12), (13) and (14) are shown in Fig. 7. While the numbers in Fig. 4 are symmetric (i.e., ~or each 9-bit codeword represented, the number formed by reversing to order of those bits is also represented), the numbers in Fig. 7 are not so symmetric.
Both codes described in this specification are optimum block codes in that k cannot be decreased without increasing kl, decreasing the rate or increasing the block length. Similarly, kl cannot be decreased without increasing k, decreasing the rate or increasing the block length.
SA9~85 048 13 . ..
~L~t~ 3 CIIART I
O ,4/4 ENCODER
1 + ~2 + X3)-(~4 + X5)-(X6 + X7 + X8) + X20X7 ~11 = M + (Xl + X3)~X4 M2 = M + (X8 + X6)~X5 Nl = M- (Xl + X3) ~X4 N2 = M (X8 + X6) X5 Rl - M(Xl + X3)-X2 R2 - M-(X8 + X6)oX7 Sl = (Xl + X2 + X3) Sl = (X8 + X7 ~ X6) Yl = Xl + Rl + Sl-X4 Y" = Ml-:;'' + Rl + Sl Y3 = X3 + Rl + Sl-X4 Y4 = Ml-X4 + ~ X2 + Rl-X4 + Sl- (X5 + S2) Y5 - ?1- (`;1-.';"-X3-:;4-.Y;-.';6-';7 ~X8) Y6 = ~ X5 + N2-X7 + R2~X5 + S20 ~X4 'r Sl) Y7 = X6 + R2 + S2-X5 Y8 = M2-X7 + R2 ~ S2 Y9 = X8 + R2 + S2 X5 SA9-85-0'~8 /4~
CII~URT II
0,4/4 DECODER
~1 = Y5 + Yl-Y2~Y3~Y4-Y6-Y70Y80Y9 Al = Y6 + Y2 ~ Y4 A2 = Y4 + Y8 + Y6 ~ 1 ~ A2 M2 = M + Al Nl = MoA2-Y2 N2 = M-AloY8 Rl = M-A2'Y2-Yl-Y3 R2 = M~Al-Y8Y9-Y7 Sl = ~I-A Y ~Yl-Y3) S2 = ~1-Al-Y8-(Y9~Y7) Xl = (~11 + ~ Yl X2 = ~ Y2 + N1Y4 + Rl X3 = (~11 + ~l)'Y3 __ X4 = ~1l^Y4 + Rl-Y4 + Sl-Y3 X5 = Ml-Y6 + R2-Y6 + S2-Y7 X6 = (~12 + ~2)-Y7 X7 = ~12-Y8 + N Y6 + R2 X8 = (~12 ~ N2)-Y9 -._ SA~-85-048 ~5 C~I~RT I I I
O,3/6 ENCODER
Ml = Xl + X2 + X3 ~12 = X7 + X8 M3 = X2 + X4 + X5 + X7 ~ 13E = Xl-X2X3-X4-X5-X6-X7~X8 Nl = N2-(Xl + X3)-X4 N2 = ~ (X8 ~ X6)oX5 Rl = ~17-(X2 + X5-X6)(Xl + X3)-X4 R2 = ~ (X8 + X6)oXS
-Sl = ~ 2 + X5-~6)-(Xl + ~3)~4 S2 = ~(Xl + X3)-X8 Yl = (E-~l + Nl)-Xl + Rl~X4-+ R20(X4 + X7) + Sl-X3-(Xl + X6) Y2 = (E-~l + Nl)-X2 + Rl-X3 + R2-(X4 + X7) + Sl~Xl + S2 Y3 = (~1 + Nl)-X3 + N2 + Rl-Xl + R2-(X4 + X7) + Sl Y4 - (E-~l + Nl~-X4 + N2-X4 + Rl + S2 Y5 = E-M
Y6 = (E-~l + N2)-X5 + Rl + R2 + S2-X6 Y7 = (M + N2)oX6 + N1(X5 + X6) + Rl-X6 + R2-X8 + Sl + S2 Y8 = (~1 + N2)~X7 + Nl-(X5 + X6) ~ Rl~X5 + R2~X6 ~ + Sl~(Xl + X6) ~ S2-Xl Y9 = (E9~1 + N2~-X8 + Nl-(X5 + X6) + Rl-X2 + X5-(R~ + Sl~ + S2-X3 /~ ` .
3~3 CHART IV
O, 3/6 DECODER
E = Yl-Y2~Y4Y5-Y6-Y9 M = Y5 + E
Nl = ~I-(Yl + Y3)oY4-Y6 N2 = Yl-Y2^Y6 Rl = M-(Yl + Y2-Y3)-Y40Y6 R2 = M-(Yl + Y2)-Y4-Y6 Sl = ~I-Y4~Y6 S2 = (M + Yl + Y3) Xl = E + (~1 + Nl)-Yl ~ Rl-Y3 + Sl~Y2 + S2-Y8 X2 = E + (rl ~ Nl)-Y2 + Rl-Y9 ~3 = (~1 + Nl)-Y3 + Rl-Y2 + Sl-(Yl + Y2) + S2-Y9 X4 = E + (~1 + Nl + N2)-Y4 + Rl-Yl + R2-YI-Y2 X5 = E + (M + N2)^Y6 + Nl-Y8-Y9 + Rl-Y8 + Y9-(R2 + Sl) X6 = (~1 + N2)-Y7 + Nl-Y7-Y8 + Rl-Y7 + R2-Y8 ~ Sl-(YloY2 + Y8) + S2-Y6 X7 = (~1 + N2)-Y8 + R2~Y2-Y3 X8 = E + (M + N2)-Y9 + R2-Y7 + S2 .
., .
Claims (18)
1. Apparatus for encoding a preselectable number of bits of binary data into codewords having a preselectable number of bits, said apparatus comprising:
receiver means for receiving the binary data;
and encoder means, coupled to the receiver means, for producing sequences of fixed length codewords;
said sequences having no more than a first preselected number of consecutive zeroes therein; and said sequences comprising two subsequences, one consisting only of odd bit positions and another consisting only of even bit positions, each of said subsequences having no more than a second preselected number of consecutive zeroes therein.
receiver means for receiving the binary data;
and encoder means, coupled to the receiver means, for producing sequences of fixed length codewords;
said sequences having no more than a first preselected number of consecutive zeroes therein; and said sequences comprising two subsequences, one consisting only of odd bit positions and another consisting only of even bit positions, each of said subsequences having no more than a second preselected number of consecutive zeroes therein.
2. Apparatus as in claim 1 wherein the first and second preselected number of consecutive zeroes are equal.
3. Apparatus as in claim 2 wherein the first and second preselected number of consecutive zeroes are 4.
4. Apparatus as in claim 1 wherein the first and second preselected number of consecutive zeroes are unequal.
5. Apparatus as in claim 4 wherein the first preselected number of consecutive zeroes is three and the second preselected number of consecutive zeroes is six.
6. Apparatus as in claim 1 wherein the ratio of the number of bits in the encoded binary data to the number of bits in the codewords is 8/9.
7. Apparatus as in claim 1 wherein:
the codewords comprise a plurality of partitions; and the encoder means includes a plurality of gating means for producing the partitions of codewords and output gating means for combining the partitions of codewords into the sequences of codewords,
the codewords comprise a plurality of partitions; and the encoder means includes a plurality of gating means for producing the partitions of codewords and output gating means for combining the partitions of codewords into the sequences of codewords,
8. Apparatus as in claim 1 further including decoding means for decoding a preselectable number of codewords into a preselectable number of bits of binary data, said decoding means comprising:
receiver means for receiving the codewords; and sequential means, coupled to the receiver means, for producing sequences of binary data in response to said codewords.
receiver means for receiving the codewords; and sequential means, coupled to the receiver means, for producing sequences of binary data in response to said codewords.
9. Apparatus as in claim 8 wherein the sequential means includes a plurality of gating means for producing the partitions of binary data and output gating means for combining the partitions of binary data into the sequences of binary data.
10. A method for encoding a preselectable number of bits of binary data into codewords having a preselectable number of bits, said method comprising the steps of:
receiving the binary data; and producing sequences of fixed length codewords;
said sequences having no more than a first preselected number of consecutive zeroes therein; and said sequences comprising two subsequences, one consisting only of odd bit positions and another consisting only of even bit positions, each of said subsequences having no more than a second preselected number of consecutive zeroes therein.
receiving the binary data; and producing sequences of fixed length codewords;
said sequences having no more than a first preselected number of consecutive zeroes therein; and said sequences comprising two subsequences, one consisting only of odd bit positions and another consisting only of even bit positions, each of said subsequences having no more than a second preselected number of consecutive zeroes therein.
11. The method as in claim 10 wherein the first and second preselected number of consecutive zeroes are equal.
12. The method as in claim 11 wherein the first and second preselected number of consecutive zeroes are 4.
13. The method as in claim 10 wherein the first and second preselected number of consecutive zeroes are unequal.
14. The method as in claim 13 wherein the first preselected number of consecutive zeroes is three and the second preselected number of consecutive zeroes is six.
15. The method as in claim 10 wherein the ratio of the number of bits in the encoded binary data to the number of bits in the codewords is 8/9.
16. The method as in claim 10 for decoding a preselectable number of codewords into a preselectable number of bits of binary data further comprising the steps of:
receiving the codewords; and producing sequences of binary data from said codewords:
receiving the codewords; and producing sequences of binary data from said codewords:
17. Apparatus as in claim 1 wherein the first or second preselected number of consecutive zeroes cannot be decreased without increasing the second or first, respectively, preselected number of consecutive zeroes.
18. Apparatus as in claim 6 wherein the first or second preselected number of consecutive zeroes cannot be decreased with decreasing said ratio.
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|---|---|---|---|
| US855,641 | 1986-04-24 | ||
| US06/855,641 US4707681A (en) | 1986-04-24 | 1986-04-24 | Method and apparatus for implementing optimum PRML codes |
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| CA1262189A true CA1262189A (en) | 1989-10-03 |
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| CA000532490A Expired CA1262189A (en) | 1986-04-24 | 1987-03-19 | Method and apparatus for implementing optimum prml codes |
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| US (1) | US4707681A (en) |
| EP (1) | EP0243708A1 (en) |
| JP (1) | JPS6318821A (en) |
| AU (1) | AU593096B2 (en) |
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| US6819512B2 (en) * | 2003-02-18 | 2004-11-16 | Protoscience, Inc. | Triple-attribute method of encoding and decoding magnetic data |
| US7030789B1 (en) | 2004-12-01 | 2006-04-18 | Hitachi Global Storage Technologies Netherlands B.V. | Techniques for applying modulation constraints to data using periodically changing symbol mappings |
| US7064687B1 (en) | 2005-01-31 | 2006-06-20 | Hitachi Global Storage Technologies Netherlands B.V. | Techniques for modulating data using short block encoders |
| US7071851B1 (en) | 2005-01-31 | 2006-07-04 | Hitachi Global Storage Technologies Netherlands B.V. | Techniques for implementing non-uniform constraints in modulation encoded data |
| US7142134B2 (en) * | 2005-02-01 | 2006-11-28 | Hitachi Global Storage Technologies Netherlands B.V. | Techniques for generating modulation codes using running substitutions |
| US7126502B2 (en) * | 2005-02-01 | 2006-10-24 | Hitachi Global Storage Technologies Netherlands B.V. | Techniques for using interleaved encoders to obtain modulation constraints |
| US7715137B2 (en) * | 2006-10-19 | 2010-05-11 | Hitachi Global Storage Technologies Netherlands B.V. | Servo patterns for patterned media |
| US7486208B2 (en) * | 2007-05-16 | 2009-02-03 | International Business Machines Corporation | High-rate RLL encoding |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3815028A (en) * | 1972-08-09 | 1974-06-04 | Itt | Maximum-likelihood detection system |
| US3969700A (en) * | 1974-04-10 | 1976-07-13 | International Business Machines Corporation | Regional context maximum likelihood error correction for OCR, keyboard, and the like |
| US4382300A (en) * | 1981-03-18 | 1983-05-03 | Bell Telephone Laboratories Incorporated | Method and apparatus for decoding cyclic codes via syndrome chains |
| JPS57155857A (en) * | 1981-03-23 | 1982-09-27 | Kokusai Denshin Denwa Co Ltd <Kdd> | Maximum likelihood method and apparatus for error |
| US4500994A (en) * | 1982-10-04 | 1985-02-19 | Motorola, Inc. | Multi-rate branch metric processor for maximum-likelihood convolutional decoder |
| US4567464A (en) * | 1983-01-28 | 1986-01-28 | International Business Machines Corporation | Fixed rate constrained channel code generating and recovery method and means having spectral nulls for pilot signal insertion |
| GB8313331D0 (en) * | 1983-05-14 | 1983-06-22 | Int Computers Ltd | Decoding run-length encoded data |
| US4573155A (en) * | 1983-12-14 | 1986-02-25 | Sperry Corporation | Maximum likelihood sequence decoder for linear cyclic codes |
| JPS60173930A (en) * | 1984-02-20 | 1985-09-07 | Fujitsu Ltd | Pipeline processing viterbi decoder |
-
1986
- 1986-04-24 US US06/855,641 patent/US4707681A/en not_active Expired - Lifetime
-
1987
- 1987-03-19 CA CA000532490A patent/CA1262189A/en not_active Expired
- 1987-03-24 JP JP62068172A patent/JPS6318821A/en active Granted
- 1987-04-01 EP EP87104807A patent/EP0243708A1/en not_active Withdrawn
- 1987-04-14 BR BR8701783A patent/BR8701783A/en unknown
- 1987-04-23 AU AU71888/87A patent/AU593096B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| AU593096B2 (en) | 1990-02-01 |
| US4707681A (en) | 1987-11-17 |
| JPH036699B2 (en) | 1991-01-30 |
| EP0243708A1 (en) | 1987-11-04 |
| AU7188887A (en) | 1987-10-29 |
| JPS6318821A (en) | 1988-01-26 |
| BR8701783A (en) | 1988-02-02 |
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