CA1280496C

CA1280496C - Virtual pbx call processing method

Info

Publication number: CA1280496C
Application number: CA000545300A
Authority: CA
Inventors: William Walter Parker; Paul Douglas Hunter; Benjamin Cecil Widrevitz
Original assignee: American Telephone and Telegraph Co Inc
Current assignee: AT&T Corp
Priority date: 1986-09-05
Filing date: 1987-08-25
Publication date: 1991-02-19
Anticipated expiration: 2008-02-19
Also published as: JPS6365735A; DE3783543T2; JP2956969B2; SG60693G; US4764919A; DE3783543D1; EP0260043A3; EP0260043B1; EP0260043A2

Abstract

VIRTUAL PBX CALL PROCESSING METHOD

Abstract A virtual PBX capability is provided to a group of user packet stations served by a packet switching system. The system establishes a virtual circuit between each distinct pair of stations in the group. The stations exchange signaling packets via the virtual circuits and respond to such packets by coordinating the initiation and disconnection of voice, data, or image calls. All call processing, including the provision of features such as call forwarding andautomatic callback, is accomplished by the stations without the aid of the switching system. A fraud prevention mechanism is included in the switching system to prevent unauthorized stations from communicating as part of the virtual PBX group.

Description

12~ 96 VIRTUAL PBX CALL PROCESSING MET~IOD

Technical Field This invention relates to switching system customer equipment and, more particularly, to customer equipment that provides advanced telephony S features to a group of highly interactive customers.
Background of the Inv_ntion There are presently two general classes of switching system configurations available to serve the communication needs of business customers:1) private branch exchange (PBXs) located on the customers' premises, and 10 2) central office based systems, e.g., CENTREX systems, where lines are extended from the central office to individual customer stations but advanced features are provided by means of call processing software executed in the central office system. PBXs are considered advantageous by customers who desire a great deal of control and flexibility in their communications. Central office systems are 15 preferred by customers who wish to avoid the responsibility and cost associated with operating and maintaining an on-premises switch.
One development inflllencing the flltllre evolution of system configurations of either type is the increasing sophistication of customer terminal equipment made possible by the incorporation of microprocessors in such 20 equipment. In one known PBX arrangemellt, the customer terminals perform much of the advanced feahlre call processing themselves but still involve the PBX
system control at various pOilltS d~lring the establishment and termination of all calls. The involvement of the switch contlol in key phases of every call subseantially limits the extent to which business customers can tailor call 25 processing features to meet their specific needs. This is particularly true for customers using central office systems under the control of local telephone companies.
In view of the foregoing, a recognized problem in the art is the limited customer control and flexibility that is possible when the switching system 30 control entities must be involved in processing every call.
Summary of the Invention The foregoing problem is solved and a technical advance is achieved in accordance with the principles of ~he invention in an exemplary method for processing calls among a group of highly interactive and intelligent user stations 35 served by a packet switching arrangement, where virtual circuits are illustratively pelmanently established among the group of stations by way of example through a 8~ 96 central office, and the established virtual circuits are used both for the cornmunication of intra-group call control packets to coordinate initiation, disconnection and other processing of calls by the user stations without involving the packet system control, and for the con~nunication of packetized information of 5 various types, e.g, voice~ data or image information, during the intra-group calls.
Customers have full control over intra-group call features whether the packet switching system is located on their premises or at a telephone company central office because such features are fully implemented in the intelligent user stations.
Customer groups of this type are referred to herein as "virtual PBX" groups lO because a high degree of customer control and flexibility in the implementation of advanced telephony features has in the past been primarily associated with PBX
systems. Thus, a group of intelligent stations that process calls in the manner of the invention operate, in effect, as tho~lgh they were served by an on-premises switch even though they may, in fact, be served by a central office system.
lS ~lthough the packet switching arrangement in the exemplary embodiment described herein is a single packet switching system, the invention is also applicable to arrangements comprising an interconnected network of packet systems.
A method in accordance with the invention is used to establish a call 20 from a first one of a group of user stations. Each pair of user stations of the group is interconnected by a different one of a number of virtual circuits of a packet switching ~rrangement serving a plurality of user stations including the group. The ffrst user station responds to call address information for the call and determines whether the user station defined by the call address information is part 25 of the group. Upon determining that the defined user station is part of the group, the first user station determines the virtual circuit interconnecting the first user station and the dclined llser sl.ltioll. 'I'ilc ~irst user stalion then ~r,msmits a setup packet via the determined virhlal circllit to tlle dcfined user station to initiate the establishment of the call.
In the illustrative method described herein, when the defined user station is idle, it begins ringing in response to the setup packet and transn~its an alerting packet via the determined virtual circuit to the first user station. The first user station generates an audible alerting signal in response to the alerting packet.
The delSned user station subsequently stops ringing in response to a user action35 and transmits a connect packet via the determined virtual circuit to the first user station. Subsequent to the receipt of the connect packet by the first user station, the first user station and the defined user station exchange user information gL21~ 6 packees via the determined virtual circuit. The user information packets may include voice, image, and data packets.
The user stations of the group can effect a wide variety of custom calling features such as automatic callback and call forwarding without involving 5 the packet switching arrangement control. For example, when the defined user sta~ion is busy, it responds to the setup packet by transmitting a busy packet via the determined virtual circuit to the first user station. The busy packet defines the busy state of the defined user station. The first user station responds to the busy packet and to a user action, by transmitting a callback request packet via the 10 determined virtual circuit to the defined user station. The defined user station responds to the callback request packet and to an idling of the defined user station, by transrnitting an idle packet vhl the determille(l virtulll circuit to the first user station. The first user station responds to the idle packet by transrnitting a setup packet via the determined virtual circuit to the defined user station to again initiate 15 the establishment of the call.
~ s a second example, the defined user station may respond to the setup packet by transmitting a call forward packet including forward-to information via the determined virtual circuit. The first user sta~ion then ~etermines whether the user station specified by the forward-to inforrnation is part 20 of the group. Upon determining that the specified user station is part of thegroup, the first user station ascertains the virtual circuit interconnecting the first llser station and the specified user station. The first user station then transmits a setup packet via the ascertainecl virtual circuit to the specified user station to initiate thc establishtncllt of thc call.
Any user station of thc group lrallslllits packets by first detcrmining WhClhCr a ~iVell puckct is ~o be tr;lnslllillc~l lO allotllcr llser station of thc group.
When the packet is to be trallsmitted ~o anolller user station of the group, the first user station determines the virtual circuit that interconnects the two user stations and also determines whether the given packet is an intra-group signaling packet.30 When the packet is an intra-group signaling packet, the firs~ user station transmits the given packet via the determined virtual circuit to the other user station with an identification of the given packet as an inhu-group signaling packet. However, when the packet is not an intra-grollp si61lnling packet, the first user stationtransmits the given packe~ via the detelmilled virtulll circuit lo the o~her user 35 station with an identification of the given packet as a user information packet comprising voice, data or image information.

~z~

The header of each packet transmitted between two user stations of the group includes an identification of the transmitting user station as the packet source and also includes a definition of the virhlal circuit interconnecting the two stations. The packet switching arrangement stores data defining the pair of user5 stations interconnected by each of the virtual circuits. For each packet received by the packet switching arrangement including a header defining one of the virtual circuits, the packet switching arrangement reads the stored data to determine the pair of user stations interconnected by the defined virtual circuit. The packet switching arrangement then determines whether the user station defined as the 10 packet source by the header is one of the determined pair of user stations. Only when the user station defined as the packet source by the header is one of the determined pair of llser stations, is each packet transmitted to the other user station.
Brief Description of the Drawin~
A more complete understanding of the present invention may be obtained by a consideration of the following description when read in conjunction with the drawing in which:
FIG. 1 is a filnctional diagram of a packet switching system interconnecting the members of a virtllal PBX group for processing calls in 20 accordance with the method of the invention;
FIGS. 2 and 3, when arranged in accordance with FIG. 12, present a '~
more detailed diagram of the switching system of FIG. 1;
FIGS. 4 and 5 are diagrams of a circuit switching unit and an associated control unit included in the system of FIGS. 2 and 3;
FIGS. 6 throllgh ~ are diagrams of a transmit control node, a selector control node, and a ring repeater which are connected in a control ring as shownin PIG. 3;
FIG. 9 is a diagram of all incoming packet buffer used in an incomin~
packet buffer arrangement as shown in FIG. 10;
FIG. 10 is a diagram of the incoming packet buffer arrangement included in the system of FIGS. 2 and 3;
FIG. 11 is a diagram of an outgoing packet buffer arrangement included in the systern of FIGS. 2 and 3;
FIG. 13 is a diagram of a packet line unit included in the system of 35 FIGS. 2 and 3;

~8~)496 FIG. 14 is a signaling sequence diagram for the setup of a packet-switched call in the system of FIGS. 2 and 3;
FIG. 15 is a table defining the permanent assignment of virtual circuits between different pairs of user stations in a virtual PBX group 5 implemented using the system of FIGS. 2 and 3;
FIG. 16 shows portions of the packet format used by members of the virtual PBX group of FIG. 15;
F~GS. 17 through 19 are signaling sequence diagrams for the setup of various call examples illustrating featllres such as .lutornatic callback and call 10 forwarding among the members of the virtual PB~ group of FIG. 15;
FIG. 20 is a diagram of a switching module used in an alternate embodiment o~ the system shown in FIGS. 2 and 3; and FIG. 21 is a more detailed diagram of a banyan interconnection network included in the switchin~ module of FIC. 20.
15 General Description FlG. 1 is a functional diagram of a packet switching system 10 used to interconnect a virtual PBX group of user packet stations including stations 1005, 1006, 1055 and 1056. Packet network terminations, 1007 and 1057 are used to interface multiple user packet stations to a single packet digital subscriber 20 line to switching sys~em 10. Eacll of the user packet stations 1005, 1006, 1055, and 1056 is, in the present example, associated with a different one of four protocol handlers 1700-0, 1700-95, 9700-95, and 9700-0. Each distinct pair of the group of four user paclcet stations is intercollnected by a different one of sixvirtual circuits 9001 through 9006, shown by dashed lines in FIG. 1. The virtual25 circuits are used both for the communication of intra-group call control packets to coordinate initiation, disconnection and other processing of calls by the user packet stations without involving the control entities of system 10, and ~or thecommunication of packetized information of various types, e.g., voice, data, or image information, during the intra-group calls. Each of the protocol handlers 30 stores routing information such that packets, received from the associated virtual PBX group member with a header defining one of the other group members as the packet destination or equivalently defining one of the virtual circuits 9001 through 9006, is appropriately transmitted throllgh switching system 10 in the defined virtual circuit. Such routing inforrnation is stored in the protocol handlers at35 system initialization or in response to a customer order.

~L2~ 6 Detailed Description FIGS. 2 and 3, when arranged in uccordance with FIG. 12, present a block diagram of the exemplary switching system 10. Switching system 10 also includes a plurality of circuit/packet switching modules, e.g., 1000 and 1050.
5 Switching system 10 provides circuit switching service to a plurality of analog stations, e.g., 1001, 1002, 1051 and 1052, via conventional analog lines, e.g., 1003, 1004, 1053 and 1054. Switching system 10 also provides packet switching service to a plurality of use~ packet stations, e.g., 1005, 1006, 1055, and 1056, via 144 kilobits per second packet digital subscriber lines (PDSLs), e.g., 1008, 1009, 10 1058, and 1059. PDSLs 1008, 1009, 1058 and 1059 are interfaced to access ports P6 and P7 of switching module l0()0 and access ports P56 and P57 of switching module 1050. Switching system 10 also provides packet switching connectivity to other packet switching systems, e.g., private branch exchanges or central officesystems, via a 1.544 megabits per second high speed link 1010 connected at 15 access port P10.
Each user packet station, e.g., 1005, includes a low bit rate voice codec (coder/decoder) with silence suppression and packetizing functions. Any ofa number of low bit rate voice coding techniqlles can be used, for example, 32 kilobits per second Adaptive Differential Pulse Code Modulation (ADPCM) or 9.6 20 kilobits per seconcl ~ulti-Pulse Linear Preclictive Coding (MPLPC). In addition to the coding, the data rate is further reduced by silence suppression. Voice packets are sent only while voice cnergy is present. No voice packets are sent while a speakcr quic~ly li~tens ~o thc olllcr l~al~y, or wllile the speaker i~ between words or syllables. l')lC coclcd voicc is rormcd into l~uckcts. r;or ADPCM codinL~, 25 VOiGC packc~s are upploxilllatcly 7() bylcs inclllding the hcudcr. ~ach packet represents upproximately 16 millisecon(ls of speech, E~ach voice packet includes a time stamp which is used by the receiving end to compensate for the variable network delay.
In addition to voice coding, each user packet station uses low bit rate 30 video coding for still-frame or low-resolution real time image transfer. The user packet station also conveys low-speed or high-speed data. All information, including signaling, is carried in packets. The user pucket stution statistlcally multiplexes the information from its various sources.
As shown in FIG. 2, some user packet stations, e.g., 1006 and 1056, 35 are connected directly via PDSLs to switching system 10. However, a number ofuser packet stations, e.g., five stations, can share a single PDSL. A packet network termination (PNT) provides multiple station interface ports for point-to-3L28~
point connection to user packet stations to provide such shared access to PDSLs.For example, PNT 1007 and PNT 1057 provide station interface ports from a number of user packet stations, e.g., station 1005 and station 1055, to PDSL 1008 and PDSL 1058, respectively. A PNT, e.g., 1007, includes a plurality of buffers (not shown) to store packets received from each associated user packet station.
PNT 1007 statistically multiplexes the packets onto PDSL 1008. In the reverse direction PNT 1007 receives the 144 kilobits per second packet stream from PDSL 1008 and broadcasts all received packets to the associated user packet stations. Each station detern1incs whether it is the intended destination of a 10 received packet based on the packet header.
In the present exemplary embodiment, information is conveyed on a PDSL using one pair of wires for each direction of transmission. PDSL 1008, for example, transmits a serial bit stream at the rate of 1~2 kilobits per second including the above-mentioned 144 kilobits per second packet stream and which 15 further includes 48 kilobits per second used for a number of functions including framing, DC balancing, control and maintenance. The physical level characteristics of a PDSL are the same ns those specified by tlle International Telegraph and Telephone Consultative Committee (CCITT) as the T-interface.
The use of T-interface access is only exemplary. ï'he invention is equally 20 applicable to systems using other access metllods including lines having a variety of bit rates.
In switching moclule l()ûO, the allalog lines, e.g., lines 1003 and 1004, are terminatecl by annlog line units, e.~., 1101 and 1102, which perforrn the conventional functions, e.g., supervision, ringin~, etc., as required to interface with 25 analog stations, including the digitization of the incoming analog signals and the transmission of the digital information to a circuit switching unit 1011 via a pair of 32-channel time-multiplexed data buses. As shown in FIG. 2, analog line unit 1101 is connected to circuit switchin~ unit 1011 via the 32-channel data buses 1103 and 1104.
Circuit-switching unit 1011 is shown in greater detail in FIG. 4.
Incoming information is received on the 32-channel bidirectional data buses suchas 1103 and 1104 from analog line unit 1101. A pair of data interfaces 401 and 402 multiplex the received information onto a pair of 256-channel time-multiplexed lines 403 and 405. A multiplexer/demultiplexer 407 further multiplexes the two 256-channel lines 403 and 405 onto a single 512-channel time-multiplexed line 408 for transmission to a time-slot interchanger 410. Time-slot interchanger 410 perforrns the circuit switching function of interchanging the 4~6 order of time slots in accordance with instructions read from a control random access memory (KAM) 411. The reordered time slots are transmitted on a 512-channel time-multiplexed line 412 to a multiplexer/demultiplexer 414, which demultiplexes the 512 channels onto two 256-channel time-multiplexed lines 415 5 and 417. Lines 415 and 417 are received by a pair of link interfaces 441 and 442, which perform synchroni~ing and si~nal conditioning functions and then transmit the 256 channels received on each of the lines 415 and 417, to time-multiplexed switch 2010 via 256-channel incoming links 15 and 16.
In the reverse direction, time-multiplexed switch 2010 transmits 10 information on two 256-channel outgoing links 13 and 14 to link interfaces 441 and 442. The 256 channels from each of thc lines 13 and 14 are !hen transmitted by link interfaces 441 and 442 on two 256-channel time-multiplexed lines 418 and416 to multiplexer/demultiplexer 414 which multiplexes the information onto a single 512-channel time-multiplexed line 413 to time-slot interchanger 410.
15 Time-slot interchanger 410 reorders tlle received time slots in accordance with instructions read from control RAM 411, and transmits the reordered time slots on a 512-channel time-multiplexed line 409 to multiplexer/demultiplexer 407.
Multiplexer/demultiplexer 407 demultiplexes the 512 channels onto two 256-channel time-multiplexed lines 404 and 406 to the data interfaces 401 and 402, 20 which further demultiplex tlle information onto the 32-channel data buses such as 1103 and 110~1.
Circuit/packet time-multiplexed switch (TMS) 2010 (FIG. 3) operates to provide inter-module connections ~or both circuit-switched and packet-switched calls as well as for conveying inter-module control packets between the control 25 units of the switching modules, e.g., between control unit 1017 of switching module 1000 and a correspondhlg control unit in switching module 1050. The following description pcrtains to the operation of TMS 2010 in provic5ing inter-module connections for circuit-switched calls. TMS 2010 includes a time-shared space division switch which operates in frames of 256 time slots or channels of 30 approximately 488 nanoseconds each to complete paths from its input ports IP1through IP255 to its output ports OP1 through OP255. Each switching module is connected to two input ports and two output ports. For example, switching module 1000 is connected via 256-channel incoming links 15 and 16 to input ports IP1 and IP2 and via 256-channel outgoing links 13 and 14 from output ports35 OP1 and OP2. TMS 2010 comprises two substantially identical switch units, oddswitch unit 2100 and even switch unit 2200. Within odd switch unit 2100, conductors from every input port, e.g., conductor 1 from input port IP1 and 8~
conductor 253 from input port IP253, are combined into a multi-conductor E-bus 2102, and are coupled via bus portion 2103 to 128 input terminals of each of128 selectors associated with the 128 output ports OP1 through OP255 of odd switching unit 2100. Only selector 2131-1 associated with output port OP1 and 5 selector 2131-2 associated with output port OP253 are shown in FI&. 3. Selector 2131-1, for example, operates in response to instructions stored in a control RAM 2132-1 to connect different ones of its input terminals to a multiplexer 2133-1 during each of the 256 time slots of each frame. The output terminal of multiplexer 2133-1 is connected to output port OP1. As part of the 10 process of establishing a conventional circuit-switched call from analog station 1001 to analo~ station 1051, for example, a time slot is selected that is available both to connect input port IP1 to output port OP253 and to connect input port IP253 to output port OP1. Assume that time slot TS43 is selected. As part of the establishment of the call, a TMS controller 2101 writes instructions via a 15 control bus (not shown) into the control RAMs 2132-1 and 2132-2. The instructions written into control RAM 2132-1 define that during time slot TS43, conductor 253 is to be selected by selector ~131-l for connection to output portOP1. The instructions written into control RAM 2132-2 define that during time slot TS43, conductor 1 is to be selected by selector 2131-2 for connecdon to 20 output port OP253.
Onc time ~k~t on ench Ihlk bclwccll n .~wilChill~ m(xllllc nn(l l MS 2()10 is reserved for contlol conlm~ icntions between the switchin~ module control units and nll adlllinistrnlivc mo(llllc 2()3() which rcprescnts thc central control of switchinL~ systcm 10. I;or example, tinne slot TSl is the reserved 25 control time slot on link 15 to input port IPl and on link 13 from output port OP1. During time slot TS1, input port IP1 is always connected to output port OP255 and input port IP255 is always connected to output port OP1. Time slot TS2 is the reserved control time slot on link 16 to input port IP2 and on linlc 14 from output port OP2. During time slot TS2, input port IP2 is always 30 connected to output port OP255 and input port IP255 is always connected to output port OP2. Similarly, the links to and frorn each of the other input/output port pairs have unique reserved control time slots. Control messages are generated by processor 566 (FIG. 5) within control unit 1017 and stored in a memory 567. A control message for administrative module 2030 is transmitted 35 frorn memory 567 via a direct memory access (DMA) unit 558 and path 440 to link interface 441 where the message is inserted in six-bit segmen~s into repetitions of time slot TSI on incoming link 15 to input port IP1. During each g occurrence of time slot TS1, input port IP1 is connected to output port OP255 and the six-bit segments of the control message are conveyed via output port OP255 to a message switch 2031 which accumulates the bits of the control message and then forwards the complete messa~e on to administrative module 2030. Similarly 5 control messages from àdministrative module 2030to control unit 1017 are transmitted via message switch 2031, input port IP255, output port OP1 and outgoing link 13 to link h1terface 441 where the six-bit segments are extracted from time slot TS1 and conveyed via path 440 and DMA unit 558 to memory 567 within control unit 1017.
Within switching module 1000, the PDSLs, e.g., 1008 and 1009, are terminated by a packet line unit 1108, shown in greater detail in FIG. 13. Packet line unit 1108 includes a number of groups of32 packet line circuits. PDSL 1008 is terminated by packet line circuit 5001 which together with 31 other packet line circuits, e.g., 5002, comprise a packet line group controlled by a line group controller 5021. Similarly, line group controller 5022 controls a group of 32 packet line circuits, e.g., 5003 and 5004. l'l1e packet line circuits within a line group share a pair of time-multiplexcd lines 5006 and 5007 llsed for transmitting information between the packet line circuits and their associated line group controller. For example, information is conveyecl between line group controller 5021 and the associated grollp of line circuits including circuits 5001 and 5002, on the time-multiplexed lines 5006 and 5007. Similarly, information isconveyed between linc ~roup contloller 5()22 ancl the associated ~roup of line circuits including circuits 50()3 and 5004, Oll the time-multiplexed lines 5016 and 5017. Each of the time-multiplexed lines 5006, 5007, 5016 and 5017 comprise 32 time slots that recur in 125-microsecond frames. The first two time slots of each frame are reservecl for control communication between the ]ine circuits and the associated line group controller. The remaining 30 time slots of each frame are available for the transmission of packets between the packet linecircuits and the line group controller.
As mentioned above, the electrical characteristics of the PDSLs, e.g., 1008 and 100g, are the same as that for the T-interface. Each packet line circuit, e.g., 5001, in addition to providing the necessary electrical interface to PDSL 1008, also includes two packet buffers (not shown). A first packet buffer accumulates incoming bits from PDSL 1008 into packets for transmission on time-multiplexed line 5006 to line group controller 5021. A second packet bufferaccumulates bits received from line group controller 5021 on time-multiplexed line 5007 into packets for subsequent transmission on PDSL 1008.

The line circuits within a group share an additional time-multiplexed line to their line group controller for use in bidding to transmit a packet. The line circuits of the groups controlled by line group controllers 5021 and 5022 bid using time-multiplexed lines 5008 and 5018, respectively. Each of the time-multiplexedS lines 500~3 and 5018 also has 32 time slots, one time slot associated with each line circuit of the group, When packet line circuit 5001, for example, has received acomplete packet from PDSL 1008, it tr~nsmits a bid during its associated time slot, e.g., time slot TS1, on time-multiplexed line 5008. Packet line circuit 5001 monitors the bids of the other line circuits in the group as asserted during the10 other time slots on time-multiplexed line 5008. If packet line circuit 5001 determines that it has transmitted the highest bid of the group, it proceeds to transmit a line identifier in a first time slot followed by the stored packet. The stored packet is ~ransmitted using 14 of 16 bits during each of the 30 availabletime slots on time-multiplexed line 5006. The other two bits of each time slot are 15 a parity bit computed over the time slot and a bit used to differentiate between the initial line identifier time slot and the subsequent packet conveying time slots.
The packet transmission conth1ues over several frames as necessary to complete the transmission of the packet. If packet line circuit 5001 has received anothercomplete packet before the transmission of the first packet has been completed, it 20 will retain access to time-multiplexed line 5006 and continue with the transmission of the second packet.
If packet line circuit 500l determilles that its initial bid is lower than one or more of the other packet line circuits in the group, it increases its bid and asserts the increased bid during its associated time slot on time multiplexed 25 line 5008 during the next frame. Packet line circuit 5001 continues to increase its bid until it has the highest bid and obtahls access to transmit its packet. Note that line group controller 5021 does not grant access~ Each packet line circuit determines independently whether it has the highest bid and controls the transmission of packets in response to such determination. Although line group 30 controller 5021 does not perform arbitration, it does audit the statistical multiplexing of information from its associated group of line circuits, e.g., 5001, 5002, to detect faults such as more than one line circuit gaining access at the same time or one line circuit holding access for an excessively long time period.
Packets could optionally include a service class identifier field defining a packet 35 priority. A line circuit receiving a high priority packet would start bidding with an advanced bid.

1~8~g~
In the reverse direction, line group controller 5021 transmits reeeived packets using 30 of the 32 time slots on time-multiplexed line 5007. Only packetline circuits defined by the packet headers actually store received packets in their packet buffers for transmission on the PDSLs. Packetized information is S conveyed between the line group controllers, e.g., 5021 and 5022, and packet switching unit 1400 via a common data unit 5030, and a number of bidirectional, time-multiplexed data buses, e.g., 1109 and 1110.
In the present exemplary embodiment, packet switching unit 1400 (FIG. 2) includes 96 protocol handlers 1700-0 through 1700-95, and packet 10 interconnect 1800 which interconnects protocol handlers 1700-0 through 1700-95 and a processor interface 1300. Access from packet line unit 1108 to the protocol handlers 1700-0 through 1700-95 is obtained via six data fanout units 1600-0 through 1600-5, each associated with a group of 16 protocol handlers. Bach user packet station, e.g., 1005, is associated with one of the protocol handlers 1700-0 15 through 1700-95, and, more particularly, with one of 32 High-level Data Link Control (HDLC) circuits (not shown) inclllded in that assoeiated protocol handler.
In the present embodiment, commullication links are established between the HDLC circuits of the protocol handlers and peer HDLC circuits (not shown) in theuser packet stations at system initialization. These links are used to convey 20 packets within HDLC frames in accordance with the well-known HDLC protocol.
The packets conveyed between user packet stations and associated protocol handlers are, in ~eneral, of v.lriablc lenl3th. Each user packet station, e.~., 1()()5, trunsl~ .Y an(J rCCC;VCS ~ackets via one or more logic;ll links. In ;ICCOId;lnCC W;~ 1C l)rC.~;Cnt CX;U~ C~ IO~;Cnl Ih~k IJI..() ;S USCd ~0 convey signaling 25 p~lckets to set up packc~-switchttl CallS tO and l`rom user packet st;ltion l005 and logical link LL1 is used to convey data packets during packet-switched calls to and from user packet station 1005. The logical link LL1 can be further subdivided into a plurality of logical channels for use when user packet station 1005 is engaged in a number of simultaneolls packet-switched data calls.30 The logieal link and logical channel numbers of each packet are defined by part of a header of that packet. Logical links LL2 and LL3 are used to convey voice packets and image packets, respectively. Data, voice and image packets are referred to generically herein as user in~ormation packets. Each packet receivedby a protocol handler from a user packet station is stored in a random access 35 memory (not shown) in that protocol handler. If the received packet is a signaling packet, i.e., it was received in logical link LL0, it is transmitted via packet interconnect 1800 to processor intelface 13()() for subsetluent transmission to - l2 -~'~8~96 control unit 1017. If the received packet is a user information packet, i.e., it was received in one of the logical channels of one of the logical links LL1, LL2 and LL3 and a packet-switched call has previously been established to one of theuser packet stations associated with switching module 1000, the user information5 packet is transmitted via packet inter~onl1ect 180() to the protocol handler associated with the destination user packet station for subsequent transmission thereto. (If the packet-swi~ched call is established between two user packet stations that are associated with the same protocol handler, the user information packets need not be transmitted via packet interconnect 1800. Instead the protocol 10 handler simply transmits ~he user information packets in the appropriate channel to the destination user packet station.~ In the present embodiment, six of the 96 protocol handlers are designated as inter-module protocol handlers. Protocol handlers 1700-15 and 1700-80 may, for example, be two of the six inter-module protocol handlers in packet switching unit 1400. Inter-module packet traffic is 15 conveyed between the inter-module protocol handlers and circuit/packet time-multiplexed switch 2010, via the data fanout units 1600-0 through 1600-5, a number of bidirectional time-multiplexed datA buses, e.g., 1 l05 and 1106, and circuit switching llnit 1011. Ench of thc bidirec~io~ l data buses, e.g., 1105, comprises 32 time slots. Inter-module protocol handler 1700-lS, for example, 2() transmits inter-module packets via datcl fanollt Ullit 1600-0, data bus 1105, and predetermined connections througll circuit switching unit l011 to an incoming packet channel comprishlg 32 predetermined packet time slots on the 256 time slot incoming time-multiplexed lhlk lS. Similarly, packets are transmitted from an outgoing packet ch;lnnel comprisin~ 32 predetermined packet time slots on 25 the 256 time slot outgoing time-multiplexed link 13, via predetermined connections through circuit switching unit 1011, data bus 1105 and data fanout unit 1600-0 to inter-module protocol h.llldler 1700-15. Since 12 bits of each packet time slot are used to convey packets, the incoming and outgoing packet channels are 3.072 megabits per second channels. One incoming and outgoing 30 packet channel is used for inter-module packet traffic between each of the six inter-module protocol handlers and circuitlpacket time-multiplexed switch 2010.
In the present embodiment, each of the incoming links 15 and 16 include three 3.072 megabits per second incomillg packet channels and each of the outgoing links 13 and 14 include three 3.072 megabits per second outgoing packet35 channels. If a user information packet is received in a logical channel which has previously been established for use in a packet-switched call to a user packet station served by one of the other switching modules, e.g., user packet 9~

station 1056 served by switching module 1050, the user information packet is transmitted via packet interconnect 1800 to inter-module protocol handler 1700-15 for subsequent transmission via circuit switching unit 1011 and time-multiplexedswitch 2010, and then via an inter-module protocol handler and packet 5 interconnect in switching module 1050 to the protocol handler that is associated with the destination user packet station 1056.
When a given protocol handler, e.g., 1700-0, has received a complete packet from a user packet station and has determined the destination of that packet, i.e., either one of the other protocol handlers or processor interface 1300, 10 it transmits a logic zero Request To Send (RTS) signal on one conductor of a six-conductor bus 1701-0 to packet interconnect 1800. Similarly, when processor interface 1300 has a packet ready for transmission to one of the protocol handlers, it transmits a logic zero RTS signal on one conductor of six-conductor bus 1301.Packet interconnect 1800 enables each of the protocol handlers and processor 15 interface 1300 to transmit in a predetern~ined sequence. Since processor interface 1300 transmits signaling packets to all of the user packet stations served by switching module 1000 and, in addition, tr~msmits all inter-module control packets from contro! unit 1017, the sequence effectecl by packet interconnect 1800 enables processor interface 1300 sixteen times for each enabling of an individual 20 ~rotocol handler. When the packet interconnect l800 sequence reaches protocol handler 1700-0, packet interconnect 1800 responds to the ~TS signal on bus 1701-0 by transmitting a lo~ic zero Clelr 'I'o Send (CIS) signal on a second conductor of bus 1701-0 to protocol handler 1700-0~ Protocol handler 1700-0 responds to the CTS signal by transmit~ g its stored packet at a high rate, e.g., 10 25 megabits per second, via packet interconnect 1800 to its destination. All of the protocol handlers and processor interface 1300 can receive the packet, but in the present embodiment, typically only one destination as defined by the packet header actually stores the packet for subsequent transmission. Only after the complete packet has been transn itted by protocol handler 1700-0, does the packet 30 interconnect 1800 sequence resume. The receipt of the packet by the destination protocol handler or by processor interface 1300 is acknowledged by the transmission of an acknowledgment packet back to protocol handler 1700-0.
A code converter 1107, interposed via 32-channel bidirectional data buses 1121 and 1122 between circuit switching unit 1011 and packet switching 35 unit 1400, is used to allow communication between an analog station, e.g., 1001, and a user packet station, e.g., 1005. The code converter 1107 receives voice packets from user packet stations via packet switching unit 1400, performs a ~2~ 9~

conversion to digital PCM voice samples, and transmits the samples in the time slots of consecutive frames via circuit switching unit 1011 to analog station 1001.
In the reverse direction, code converter receives digital PCM voice samples fromcircuit switching unit 1011 representing analog speech signals from analog 5 station 1001, and formulates voice packets for transmission via packet switching unit 1400 to user packet station 1005.
A digital facility interface 1111 is used to interface the high speed link 1010 from another packet switching system to switching system 10.
The 1.544 megabits per second packet channel received on high speed link 1010 10 is conveyed on a 32-time slot bidirectional data bus 1112 to data fanout unit 1600-0 in packet switching unit 1400.
One incoming and outgoing packet channel on the links 15 and 13, respecti~ely, are reserved ~or conveying inter-module control packets. Within control unit 1017, processor 566 (FIG.S) generates inter-module control packets 15 and stores such packets in memory 567. The packets are subsequently transferred via path 559 to processor inter~ace 1300. Processor interface 1300 subsequently transmits the packets via packet interconnect 18()0, one of the inter-module protocol handlers, e.~., protocol handler 1700-80, data bus 1106 and circuit switching unit 1011, to one of the 3.072 megabits per second incoming packet 20 channels on incon1ing link 15. In the reverse direction, inter-module controlpackets received on one of the 3.072 megabits per second outgoing packet channels on outgoing link 13, are conveyed via circuit switching unit 1011, datablls lI06, inter-module protocol handler 1700-80, packet interconnect 1800, and processor interface 1300 to control unit 1017. The functions of inserting and 25 extracting the packet time slots formillg the packet channels are carried out in link interfaces 441 and 4~2 of circuit switchin~ Ullit l011 (FIG. 4) in accordance with packet time slot definitions stored in control RAMs (not shown).
Within TMS 201(), ~hc hlformlltion in the three incoming packet ch;lllncls each comr)ri~iin~ 32 I-nckct lilllC slols rcccivcd 011 incollling link 15 nt 3() input port lI'l is stored in all incomillg pncket bufFer arrangement 2120-1, The definition of the time slots Oll illCOlllill~ lillk 15 ~hat lll-C packct time slots are stored in control RAM 2132-l at systcm initializatioll by TMS controller 2101, Such definitions are then conveyed ~rom control RAM 2132-1 to incoming packet buffer arrangement 2120-1 such that the proper time slots from link 15 are 35 extracted. Each input port has a similar associated incoming packet buffer arrangement. For example, input port IP253 has associated incoming packet buffer arrangement 2120-2. The output conductors from every incoming packet 8~49~

buffer arrangement, e.g., conductor lP from incoming packet buffer arrangement 2120-1 and conductor 253P from incoming packet buffer arrangement 2120-2, are combined into m~llti-conductor E-bus 2102, and are coupled via bus portion 2104 to 12X inp~lt terminals of each of 128 selectors S associatcd with the 128 Olltpllt por~s OPI thro~lgh OP255 of odd switch unit 2100.
Only selector 2128-1 associated with output port OPl and selector 2128-2 associated with output port OP253 are shown in ~IG. 3. The transmission of packets from incoming packet buffer arrangements, e.g., 2120-1 and 2120-2, and the selection of input conductors by the selectors, e.g., 2128-1 and 2128-2, are10 controlled by a control ring 2110 including a plurality of transmit control nodes, e.g., 2123-1 and 2123-2, a plurality of selector control nodes, e.g., 2124-1 and 2124-2, and a ring repeater 2140. Control ring 2110 includes an eight-conductor bus 2111 comprising a seven-bit status bus and a single throttle ~it.
The status bus is used to define the status of the selectors, e.g., 2128-1 and 2128-15 2, as to whether they are presently being used to convey a packet or not. Thestatus bus defines the status of each of the 128 selectors by a sequence of 128 status words repetitively transmitted aroul1d rhlg 2110. A status word comprising seven logic zeroes (0000000) defines that the selector is presently idle, i.e., it is not conveying a packet. A nonzero status word defines that the selector is 20 presently conveying a packet and the partic~llar seven-bit status word defines which of the 128 incoming packet buffer alran~ements is presently transmitting apacket to that selector. The ring cycle of 128 status words repeats 32 dmes during each 125-microsecond frame Assllme that a packet has been received by incoming packet buffer arrangen1ent 2120-1 alld that the packet address defines 25 that the packet is destin~d for switching module 1()50. Incoming packet buffer arranL~cment ~12()-1 lr~ln~mits ~ nal, re~rrc~l lo ller~ln as a packet present signal, on a conductor 2119-1 to transmit control node 2123-1. Incoming packet buffer arrangement 2120-1 also transmits a request pulse on a conductor 2121-1 to transmit control node 2123-1 coincident with the arrival of the status word 30 defining the status of selector 2128-2. If that status word is 0000000 defining that selector 2128-2 is presently idle, transmit control ncde 2123-1 substitutes a nonzero status word 0000001 defining input port IP1, or equivalently switching module 1000. When selector control node 2124-2 subsequently receives the nonzero status word 0000001 at the time associated with selector 2128-2, 35 node 2124-2 transmits the status word 0000001 via a path 2126-2 for storage in a latch 2129-2. The storage in latch 2129-2is effected by the transmission of a strobe pulse from selector control node 2124-2 via a conductor 2125-2 to 1'~8~9~
latch 2129-2. The contents of latch 2129-2 define which of the 128 input terminals is selected by selector 2128-2 for connection to an outgoing packet buffer arrangement 2130-2. The status word 0000001 in latch 2129-2 defines that selector 2128-2 is to connect conductor lP to outgoing packet buffer 5 arrangement 2130-2. Transmit control node 2123-1 subsequently transmits a go signal via a conductor 2122-1 tO incoming packet buffer arrangement 2120-1. The go signal is transmitted by transmit control node 2123-1 at least one ring cycleafter the request signal was received from incoming packet buffer arrangement 2120-l in order to assllre that selector 2128-2 has been appropriately 10 set. In response to the go signal, incoming packet buffer arrangement 2120-1 transmits the received packet via conductor lP of E-bus 2102 and selector 2128-2to outgoing pacl~et buffer arrangement 2130-2. Control RAM 2132-2 controls the operation of a multiplexer 2133-2 to combine circuit-switched information from selector 2131-2 and packet-switched information from outgoing packet buffer lS arrangement 2130-2 onto the single 256-channel time-multiplexed link 21 from output port OP253. During each of the ~6 predetermined packet time slots of the three packet channels, outgoing packet buffer arrangement 2130-2 transmits a 12-bit segment of a stored packet via multiplexer 2133-2 to output port OP253 for transmission to switching module 1050. During the remaining time slots, the 20 circuit-switched information from selector 2131-2 is transmitted via multiplexer 2133-2 to output port OP253 for transmission to switching module 1050.
Once the complete packet is trallsmitted by incoming packet buffer arrangement 2120-1, it removes the packet present signal from conductor 2119-1.
25 In response to such removal, transmit control node 2123-l substitutes the idle status word 0000000 for the status word ()0()()001 defining the status of selector 2128-2.
Even if the selector 2128-2 is idle at a particular time such that the status word 0000000 is present at the appropriate point of each ring cycle, the 30 outgoing packet buffer arrangement 2130-2 may not be ready to receive a packet.
If not, outgoing packet buffer arrangement 2130-2 transmits a logic zero throttle bit via a conductor 2127-2 to selector control node 2124-2. The logic zero throttle bit is inserted on control ring 2110 by selector control node 2142-2, a~ the same point in the ring cycle that the status word associated with selector 2128-2 is 35 transmitted. The logic zero throttle bit prevents any of the transmit control nodes from effecting the transmission of a packet to selector 2128-2.

~ ~8~g~

Each incoming packet bu~fer arrangement includes one incoming packet buffer for each incoming packet channel on the associated incoming link.
For example, incoming packet buffer arrangement 2120-1 (FIG. 10) includes three incoming packet buffers 3001, 3002 and 3003, one for each of the 3.072 megabits 5 per second incoming packet channels received at input port ~P1 on incoming link 15.
Incoming packet buffer 2120-1 (FIG. 9) includes a memory 901 for storing bits received in the packet time slots on incoming link lS to input portIP1. Such packets are conveyed to memory 901 via conductor 1. The writing and 10 reading of memory 901 are controlled by a write address generator 903 and a read address generator 904, which selectively access memory 901 via a selector 902.
Signals on conductor 2135-1 from control RAM 2132-1 define the input port IP1 packet time slots to write address generator 903 and to a flag detector 920, which detects the opening and closing Hags of each received packet. When flag detectorlS 920 informs write address generator 903 that an opening flag has been received, wnte address generator 903 effects the writing of the bits of the packet into memory 901. When flag detector 920 informs write address generator 901 that the closing l'lag has been received, write address generator controls the termination of writing into memory 901 and also increments by onè a packet counter 935, 20 used to count the number of packets stored in memory 901. After the complete packet has been stored, read address generator 90~ effects the transmission of the initial bits of the packet to a flng detector 93(), which upon detecting the packet openin~ Hag, controls the subsequcllt lransn1ission of the module subfield of the packet header (with ;Iny inserted zero bits deleted) to a header latch 905. Read25 address generator 904 transmits a logic one signal on conductor 933 to cause the storage of the module subfield in l~ltch 905 and to set a S-R flip-flop 910. An AND gate 936, which receives at its two input terminals the output signal from llip-flop 91() antl n si~nal from packel col~ cr 935 indicating thnt at least one packet is available in memory 901, then transmits the packet present signal on 30 conductor 3021 to a multiplexer 3025 included in incoming packet buffer arrangement 2120-1 (FI(3. 10). A counter 906 receives a 32.768-megahertz clock signal C1 and an 8.0-kilohert~ synchronizing signal S~NC from a system clock 2150. Counter 906 is a seven-bit counter which is incremented from 0000000 to 1111111 once during each cycle of control ring 2110. Counter 906 counts an 35 internally delayed version of the synchronizing signal SYNC. The amount of internal delay depends on the position of incoming packet buffer arrangement 2120-1 with respect to control ring 211(). A con1parator 907 compares the count present in çounter 906 with the module subfield stored in header latch 905. Whenthe count present in counter 906 is equal to the module subfield stored in header latch 905, comparator 907 transmits a logic one request pulse on a conductor to a multiplexer 3015 included in incoming packet buffer arrangement 2120-1. When S the module subfield defines switching module 1050, for example, as the packet destination, the re~uest pulse transmitted by comparator 907 coincides with the presence on control ring 2110 at transmit control node 2123-1 of the status worddefining the status of selector 2128-2.
When transmit control node 2123-1 returns a go signal on conductor 2122-1, the go signal is conveyed via a demultiplexer 3035 (FIG.10) and a conductor 3031 to read address generator 904, which initiates the transmission of the packet (including the packet header~ on conductor ' P. When flag detector 930 detects the packet closing ~ag, detector 930 transmits a stop signal on conductor 932 to reset flip-flop 910 such that thc packet present signal on conductor 3021 is removed. An AND gate 934, which receives the stop signal on conductor 932 and the go signlll on conductor 3031 at its two illpllt terminals, transmits a logic one signal to packet counter 935 to dccremellt counter 935 by one to properly account for the transmitted packet. An additional counter (not shown) is used to assure that write address ~enerator 903 does not overtake read address generator 904.
Incoming pacl~et buffers 3002 and 3003 (FIG. 10) are coupled to multiplexer 3015, multiplexer 30~5, demultiplexer 3035 and multiplexer 3045 via conductors 3012, 3022, 3032, 3042 alld condllctors 3()13, 3()23, 3033 and 3043 rcspectively. A request arbitration circuit 3()5() also receives the packet present signals transmitted on conductors 3()21 lhrough 3023 and the go signal transmitted 25 on conductor 2122-l and determines which one of the incoming packet buffers 3001 through 3003 is allowed to next transmit a stored packet. Request arbitration circuit 3050 controls multiplexer 3015, multiplexer 3025, demultiplexer 3035, and multiplexer 3045 such that the appropriate signals are conveyed between the selected packct buffer and transmit control node 2123-1 and she bits30 of the packe~ stored in the selected packet buffer are transmitted to conductor lP
of multi-conductor bus 2102. Request arbitration circuit 3050 does not change multiplexer and demultiplcxer selectiolls unlil llle go signal on conductor 2122-1 is removed.
Transmit con~rol node 2123-1 (FIG. 6) includes a word recognition 35 circuit 601 that receives the seven-conductor status bus 610-S of control ring 2110 and transmits a logic one signal to one input terminal of a four-input ~ND gate 604 whenever status bus 610-S de~ines the idle status word 0000000. The other ~za~

three input terminals of AND gate 6U4 receive the request pulse and packet present signal on conductors 2121-1 and 2119-1 from incoming packet buffer arrangement 2120-1, and a throttle bit conductor 610-T of control ring 2110.
Assume again that the reqllest ~lllse defines sclcctor 2128-2 associated with 5 switching module 1050. AND gate 604 generates a logic one pulse coincident with the request pulse received on conductor 2121-1 only when: 1) the packet present signal is present on condllctor 2119-1, 2) word recognition circuit 601 is generating a logic one indicating the presence of the idle status word UOûO000 on status bus 610-~, and 3) the throttle bit associated with the idle status word 10 0000000 is a logic one indicating that outgoing packet buffer arrangement 2130-2 is presently able to receive a packet. Statlls bus 610-S is also received by a selector 603 which, in the absence of a logic one signal from AND gate 604, transmits ~he status word on status bus 610-S via AND gates 606-1 through 606-7 for storage in flip-flops 607-1 through 607-7. However, when AND gate 604 15 transmits a logic one signal, selector 603 instead transmits the status word stored in register 602 to AND gates 606-l through 606-7 for storage in flip-flops 607-1through 607-7. For transmit control node 2123-1, register 602 stores the status word 0000001 defining the associated input port IP1 and switching module 1000.
Each status word and associated throttle bit stored by flip-flops 607-1 through 20 607-7 and 608 are subsequently transmitted via status bus 611-S and throttle conductor 611-T to control ring 2110 in response to the clock signal C1. The logic one pulse generated by AND gate 604 is also~ transmitted to a flip-flop 621, which in turn sets a S-R type Hip-Moy 622. A selector 623, which is controlled by the request pulse on conductor 2121-l, receives the Q output signal from flip-flop 25 622 and the Q output signal from a flip-flop 624. When the request pulse occurs again on conductor 2121-l after the completion of a full ring cycle, the logic one sigl1;l1 generated at the Q output of flip-flop 622 is transmitted by selector 623 to be stored by flip-flop 624. Since the Q output of flip-flop 624 is returned to selector 623, it remains at a logic one level until 19ip-flop 624 is subsequently 30 reset as described herein. The logic one level is transmitted as the go signal via conductor 2122-1 to incoming packet buffer arrangement 2120-1. The D and ~-R
flip-flops of transmit control node 2123-1 operate synchronously.
When incoming pacl~et buffer arrangement 2120-1 completes the transmission of the packet, it removes the packet present signal on conductor 35 2119-1. Such removal is detected by a three-input NAND gate 605, which receives conductor 2119-1 at al1 inverting input terminal, and which receives the request pulses generatecl on collclllc~or 2121-l ancl ~hc loL~ic OllC !iiglllll gCllCr;l~Cd by flip-flop 622 at its two non-inverting inpllt terrninals. When the packet present signal is removed on conductor 2119-1, NAND gate 605 transmits a logic zero pulse coincident with the next request pulse received on conductor 2121-1. The logic zero pulse transmitted by NAND gate 605 acts to reset flip-flops 622 and 5 624 such that they are ready to control the transmission of another packet. The logic zero pulse is also coupled to input terminals of the AND gates 606-1 through 606-7 such that the idle status word 0000000 is substituted for the status word 0000001 on status bus 611-S again defining selector 2128-2 as idle.
Selector control node 2124-2 (FIG. 7) receives via eight-conductor 10 bus 2111 each status word and associated throttle bit from control ring 2110 on a ssatus bus 710-S and a throttle bit concl~lctor 710-T. The status words are stored in flip-flops 707-1 through 707-7 and subsequently transmitted in response to the clock signal C1. A seven-bit counter 701 receives the clock signal C1 and the synchronizing signal SYNC from system clock 2150 and is se~uentially 15 incremented from 0û00000 to 1111111 once during each ring cycle. A
comparator 703 compares the count generated by counter 701 with a seven-bit word stored in a register 702 defining the output port or switching module associated with that selector control node. In selector control node 2124-2, theword stored in register 702 is 1111110 defining the output port OP253 and the 20 associated switching module 1050. Accordingly, comparator 703 generates a logic one strobe pulse which coinc;des with the presence on control ling 2110 at selector control node 2124-2 of the status word defining the status of selector 2128-2. The logic one strobe pulse is delayed by one cycle of clock signal ~1 bya flip-flop 721 and i9 then transmittecl on cotlductor 2125-2 to latch 2129-2 to25 effect the storage in latch 2129-2 of the statlls word on the OUtp-lt status bus 711-S from flip-flops 707-l through 7()7-7 The throttle bit from outgoing packet buffer arrangement 2130-2 is transmitted via conductor 2127-2 to a selector 704 which also receives the throttle bit conductor 710-T from control ring 2110. Thethrottle bits from conductor 710-T are all transmitted by selector 704 to a flip-flop 30 705 with the excepti~n of the throttle bit coinciding with the strobe pulse from comparator 703. When the strobe pulse is present, the throttle bit on conductor 2127-2 from outgoing packet buffer arrangement 2130-2 is instead transmitted to flip-flop 705 for subsequent transmission via conductor 711-T to control ring 2110. In this manner, a logic zero throttle bit from outgoing packet buffer 35 arrangement 2130-2, which indicates that outgoing packet buffer arrangement 2130-2 is unable to receive a packet, is inserted on control ring 2110 in association with the status word defining the status of selector 2128-2.

~2~g~

The packet header of each packet transmitted on an incoming packet channel on one of the incoming links, e.~., 15, to TMS 2010 includes in additionto the seven-bit address defining the destination outgoing link, a subaddress defining which of the multiple packet channels on the destination outgoing link is 5 to receive the packet. Outgoing packet buffer arrangement 2130-2 (FIG. 11) includes a subaddress recognition circuit 4005, which determines the appropriateone of three outgoing packet buffers 4001 through 4003 to receive each packet onconductor 2145-2 from selector 2128-2 based on the packet subaddress. The outgoing packet buffers 40(!1 through 4003 are each associated with one of three10 3.072 megahertz outgoing packet channels on outgoing link 21 to switching module 1050. The packets transmitted by outgoing packet buffers 4001 through 4003 are conveyed via conductors 2141-2 through 2143-2 to multiplexer 2133-2 where such packets are combined with the circuit-switched information from selector 2131-2 for transmission on outgoing link 21. The definitions of the 32 15 predetermined packet time slots of each of the three packet channels are conveyed from control RAM 2132-2 to the three outgoing packet buffers 4001 through 4003 via a path 2146-2 and to multiplexer 2133-2 to control the transmission and insertion of 12-bit packet segments into the proper time slots on link 21. When one of the outgoing packet buffers 4001 throllgh 4003 is unavailable to receive a 20 packet, it transmits a logic zero signal on the associated one of three conductors 4011 through 4013 to an AND gate 4006. In response, AND gate 4006 transmits a logic zero throttle bit on conductor 2127-2 to selector control node 2124-2.
System clock 2150 (FIG. 2) derives its timing frorn an external source, e.g., another switching system, and clistributes its 32.768 megahertz system 25 clock signal Cl and its n.o kilohertz synchrollizillg sign~l SYNC via E-bus 2102 to the various components witl~in TMS 2010. The clock signals are delayed as they traverse e-bus 21()2. A ring rcpcatcr 214t) which joins tllc bcginnin~ of control ring 21 In with the end of control ring 211() operates to resynchronize the status words and throttle bits received on the conductors of control ring 2100 as 30 they begin their next cycle. Ring repeater (FIG. 8) includes ei~ht synchronizing clrcuits 801-l through 801-8, one for each conductor of bus 2111, and two clock circuits 802 and 803. Synchronizing circuit 801-1 includes four flip-flops 811 through 814 which sequentially receive and store four bits from a first conductor of bus 2111 in response to the delayed clock signal C1. The four bits stored in 35 flip-flops 811 throll~h B14 are simult.llleously stored in a latch X15 in response to a clock signal derived by clock circuit 8()3 fiom the delayed clock and synchronizing signals, C1 and SYNC. The contents of latch 815 are subsequently 1~8~3~96 transmitted in parallel to four ilip-flops 816 th~ough ~19 in response ta a clock signal derived by clock circuit 8()2 from the non-delayed clock and synchronizing signals C1 and SYNC. Multiplexers 827, 828 and 829 select either the parallel inputs from latch 815 for storage in flip-flops ~17, 818 and 819 respectively, or 5 the output signals from the preceding flip-flops 816, 817 and 818. The four bits stored in ~lip-flops 816 through 819 are sequentially transmitted on the first conductor of bus 2111 in response to the non-delayed clock signal C1. Seven additional synchronizing circuits, e.g., synchronizing circuit 801-8, perform the same function for the other seven conductors of bus 2111. Thus any dming skew 10 which may result from the traversal of the signals around control ring 2110 is removed before the next ring cycle is initiated.
The call processing required to establish both circuit-switched calls and paclcet-switched calls within system 10 is performed cooperatively by the control units of the swi~ching modules, e.g., control llnit 1017 in switching 15 module 1000, and by administrative module 2030. In the present embodiment, administrative module 2030 stores global data such as the available circuit-switched paths throllgh time-mllltiplexed switch 2010. Recall that establishing a ` circuit-switched path between modules 1()()0 ~llCI 1()50 involves selecting anavailable circuit-switched time slot on the links between modules 1000 and 1050 20 and time-multiplexed switcl1 2010. AdMinistrative module 2030 stores the global data definin~ the availability of circllit-switchetl time slots to time-multiplexed switch 2010 and perforrns the selection of the time slot to be llsed for a giveninter-module circuit-switched call. Admillistlative module 203() also stores thedata defining the association of protocol handlers, e.g., 1700-0, to user packet25 stations. Such data is used during the establisl1ment of a packet-switched call to generate the requirecl rollting table entlies in the protocol hal1dlers associated with both the originadng and terrninating user pncket stations. Although administrative module ~030 is used to store such global clata in the present embodiment, a switching rnodule could also be used to store that data. In the latter case, all30 interprocessor communication needed for processing calls could be effected using the packet switching capability of time-multiplexed switch 10 without involving message switch 2031 and administrative module 2030.
FIG. 14 is a signaling diagram illustrating the exchange of call control messages using logical link LL0 for setting up a virh~al circuit for a packet-35 switched call from user packet station 1005 to user packet station 1056. Assumethat a user at user packet station 1005 goes off-hook by lifting a handset. Stadon 1005 initially transmits a SETUP message to swi~ching system 10. The SETUP

8~34~6 message includes a call reference value (CRV) selected by station 1005. The selected CRV is included in all subsequent signaling messages between station 1005 and switching system 10 concerning the particular call. Switching system 10returns a SETUP ACK message to station 1005. The user at station 1005 then 5 enters via a keypad ~he directory number assigned to station 1056 and station 1005 transmits a sequence of INFO messa~es each including one or more digits of the directory number. Switching system 10 uses the received directory number as a key to translation data to determine the iden~ity of station 1056. Switching system 10 selects a CRV for use in identifying the call in the signaling messages 10 to be conveyed between switching system 10 and station 1056. Swi~ching system10 then transmits a SETUP message informing station 1056 of the incoming call.
Switching system 10 also returns a CALL PROC message to station 1005 indicating that a call is being set up in response to the received directory number.
In response to the SETUP message, station 1056 enters an alerting state and 15 begins ringing. Station 1056 then returns an ALERTING message to switching system 10, which message is also conveyed back to originating station 1005.
Subsequently when the handset of station 1056 is lifted to answer the call, station 1056 transmits a CONNECT message to switching system 10, which in turn transmits the CONNECT message on to station 1005. The two parties can now 20 communicate.
Within ~witchill~ Syxtclll It), ~hc pllckct-switcllcd call is established by creating a virtual circuit. This is accomplished by storing routing information in the protocol handlers associated with the originating and terminating stations (and in the inter-module protocol handlers if the call is an inter-module call) such that 25 packets received from the originating station by the associated protocol handler in the particular originating logical channel assigned to the call are always transmitted to the protocol h,lncllcr as!ioci.ltc(l with thc termill,lting station, and packets received from the terrninating station by the associated protocol handler in the terminating logical channel assigned to the call are always transmitted to the 30 protocol handler associated with the originating station.
Once the virtual circuit has been established, voice packets are e~cchanged between stations 1005 and 1056 as the two parties engage in conversation. When the user at station 1005, for example, returns the handset, station 1005 transmits a DISCONNECT message to switching system 10 ~5 Switching systern 10 then tears down the virtllal circuit by removing the various routing entries made in the protocol handlers and then transmits RELEASE
message to both stations 1005 and 1056. In response, stations 1005 and 1056 8~

both return RELCOMP messages to switching system 10.
Virtual PBX (~roups Assume that the users at stations 1005, 1006, 1055 and 1056 are highly interactive and wish to have control over the processing of their 5 cornmunications independent of switching system 10. Stations 1005,1006,1055 and 1056 may form what is referred to herein as a virtual PBX group. Switching system 10 establishes permanent virtual circuits between each pair of stations in the group, either at system initialization or in a response to a customer order. For the group of four stations 1()05, 1006, 1055 and 1056, six pennanent virtual 10 circuits, designated as virtual circuits 9001 tllrough 9006 are established (FIG. 15).
FIG. 16 shows portions of the packet forrnat used by members of the virtual PBX
group~ The packet header includes an identification of the virtual circuit number and source address and, in addition, a packet type field defining the packet as a virtual PBX packet and whether the packet is for signaling, voice, data or image15 communication. For virtual PBX signalin~ packets, the initial bits of the information field define one of a number of call control packets that are used in controlling the establishment and termination of intra-group calls. The protocolhandlers check the source address of all virtual PBX packets as a means of preventing the fraudulent communication of packets fron1 stations that are not 20 included in the group. The protocol handlers associated with the stations in the group each count nll packets conveyecl on the established permanent virtual circuits for use in billing.
Once tlle ~roup is est;lblisllcd, i.e., switchhlg system 10 has set up permanent virtual circuits 9()0t tllrou~ll 9()()(i, a voicc call from station 1005 to 25 station 1056 can be completed withollt involving the control entities of switching system 10. A signaling diagram for such a call is shown in FIG. 17. Assume that the user at station 1005 goes off-hook by lifting the handset and then enters a directory number or speed call designation defining station 1056. Station 1005 determines that station 1056 is part of its virtual P~X group and that virtual 30 circuit 9003 has been established between station 1005 and 1056. Station 1005then transmits a SETUP packet via circuit 9003 to station 1056. The SETUP
packet may include a call reference value (CRV) for use by both stations 1005 and 1056 in identifying packets that are part of the call. If station 1056 is idle, it responds to the SETUP packet by ringing alld by returning an ALERTlNG packct 35 via circuit 9()()3 to slation l()()5 Station l()()5 may gcllel.lte all(iible ringing in rcsponsc t~ Ihc ALI~R'l'lNa packcl. Wl~cn a llser at station 1056 lifts the handset to answer the call, station 1056 returns an CONNECT packet via circuit 9003 to 3Q~L9~;

station 1005. In response to the CONNECT packet, station 1005 terrninates audible ringing. The two parties can now communicate and voice packets are exchanged between stations 1005 and 1056 using circuit 9003. The voice packets are distinguished from the previous signaling packets by a logic zero identifier bit 5 at the beginning of the packet information field. When the user at station 1005 returns the handset, station 1005 transmits a DISCONNECT packet via circuit 9003 to s~ation 1056. Stations 1056 and 1005 subsequently exchange REL COMP
packets via circuit 9003.
A signaling diagram for a sccond illustrative call is shown in FIG. 18.
Station 1005 transmits a SETUP packet via circuit 9003 to station 1056 as in FIG.
17. However, in this case station 1056 is busy. Accordingly, station 1056 returns a BUSY packet via circuit 9003 to station 1005 defining the busy state of station 1056. The user at station 1005 depresses a feature button or enters a code defining a callback request and then returns the handset. Station 1005 transrnits a CALLBACK REQUEST packet via circuit 9003 to station 1056. At some later point when station 1056 again becomes idle, station 1056 transmits a NOW IDLE
paclcet via circuit 9003 to station l00S. In response to the NOW IDLE packet, station 1005 retransmits the SETUP packet via circuit 9003 to station 1056 and the remainder of the call proceeds as described above with respect to FIG. 17.
A signaling diagram for n third illustrative cnll is shown in FlG. 19.
Station 1005 transmits an a SETUP packet via circuit 9003 to station 1056 as in FIGS. 17 and 18. However, in this case the user at station 1056 has previously activated a call forwarding feature tor intra-L~rollp cRlls by depressing a feature button or entering a code defining call forwarding to station 1055. Therefore, station 1056 returns a C~LL FWD packet via circuit 9003 to station 1005 indicating thnt the call is to be forwarded to station 1055. In response, station 1005 determines that station 1055 is part of its virtual PBX group and that virtual circuit 9002 has been established between station 1005 and station 1055.
Accordingly, station 1005 transmits a SETUP packet via circuit 9002 to station 1055. If station 1055 is idle, the remainder of the call proceeds in the manner described above with respect to FIG. 17.
Although each of the examples illustrated the use of virtual circuits for virtual PBX group voice communication, the principles apply to the communication of data, image or other types of information as well.

~a~4~

Alternative Embodiment An alternative embodiment of switching system 10 is obtained by substituting switching modules of the type illustrated by switching module 1000'(FIG. 20) for the switching modules shown in FIG. 2. Switching module 1000' 5 differs from switching module 1000 in that packet switching unit 1400'is substituted for paclset switching unit 1400 and a packet network controller 1350 is added between processor interface ]300 and packet switching unit 1400'. Packet switching unit 1400' has the capability of concurrently switching multiple packet streams. Packet switch unit 1400' includes a self-routing, banyan interconnection 10 netwo~k 1404 shown in more detail in FIG. 21. Network 1404 comprises three stages of switching elements. The first stage comprises switching elements 500-0through 500-15, the second stage comprises switching elements 501-0 through 501-15, and the third stage comprises switching elements 502-0 through 502-15.
Transmission through the network is from left to right. Each switching element is 15 a packet switch. Each switching element has four inputs and is capable of buffering one packet on each input. The packets received on any input are transmittable on any of the four output terminals of the switching element. After receipt of a packet on an input terminal, the address contained in that packet is used to determine which output terminal should be used to retransmit the packet.20 Only the two most significant bits of tlle address are used to designate the output terrninal for a particul~lr switching element. F~or example, switching element 500-12 retransmits the pAcket on line 505 if the most significant bits are equal to zero, on line 506 if the most significant bits are equal to one, on line 507 if the most significant bits are equal to two, and on line 508 if the most significant bits are 25 equal to three.
Each switching nocle properly rearrallges the address bits so that the receiving switching element in the next stage has the correct bits in the most significant bit positions in order to determine which output terminal should be used to retransmit the packet at th.lt stage.
Packets are conveycd bctween intcrconnection network 1404 (FIG. 20) and packet line unit 110~ and digital facility interface 1111 via a plurality ofpelipheral interfaces ports, e.g., ports 1401, 1402 and 1403. The peripheral interface ports receive information from the periphery at one rate, e.g., 3.072 megabits per second, and transmit this information to network 1404 at a higher rate, e.g., 8.192 megabits per second, for example via paths 1409 and 1410. Fachperipheral interface port is capable of buffcling m~lltiple packets of information from the attached data bus, e.g., 1109, 1110, 1112. The buffering of packets at - ~7 -~8~9~ii the input from the data buses is necessary because the packets may have to be delayed before they can be transmitted through the network. Buffering is also needed by the peripheral interface ports for information being received from network 1404. Each peripheral interface port is capable of buffering multiple 5 packets of information from network 1404 before commencing transmission on theattached data bus. As part of the process of setting up packet-switched calls (other than the virtual PBX intra-group calls previously described)l call setup signaling packets received from user packet stations in logical link LL0 are conveyed via the peripheral interface ports and interconnection network 1404 to 10 packet network controller 1350. Such call setllp packets are subs~quently conveyed via processor interface 1300 to control unit 1017. To set up a packet-switched call, control unit 1017 effects the transmission of control packets by packet network controller 1350 to a particular peripheral interface port, e.g., 1402, which result in the storage of necessary routing infolmation in port 1402 such that 15 the logical addresses of packets subsequently received during the call are converted to physical addresses to allow the packets to properly traverse network 1404. Six network interface ports, e.g., ports 1405 and 1406, are coupled to network 1404 via paths 1415 and 1416, for example, and perforrn a function similar to that of the peripheral interface ports, for packets conveyed between 20 network 1404 and TMS 2010 via data buses such as 1105 and 1106, and via circuit switching unit 1()11. Recall ttl.lt there are six, 3.192 megabits per second incoming packet channels on the incoming links 15 and 16 to TMS 2010 and six, 3.192 megabits per second OUtgOillg packet challnels on the outgoing links 13 and 14 from TMS 2010. Each of the network interface ports, e.g., 1405 and 1406, 25 transmits packets on one incoming packet channel and receives packets from one outgoing packet channel.

Claims

1. A method of establishing a call from a first one of a group of user stations, where each pair of user stations of said group is interconnected by a different one of a plurality of virtual circuits of a packet switching arrangement, serving a plurality of user stations including said group, said method comprising said first user station, in response to call address information for said call, determining whether the user station defined by said call address information is part of said group, upon determining that said defined user station is part of said group, said first user station determining the one of said virtual circuits interconnecting said first user station and said defined user station, and said first user station transmitting a setup packet via said determined virtual circuit to said defined user station to initiate the establishment of said call.

2. A method in accordance with claim 1 further comprising upon determining that said defined user station is not part of said group, said first user station transmitting a setup packet to said packet switching arrangement requesting the establishment by said packet switching arrangement of a virtual circuit between said first user station and said defined user station.

3. A method in accordance with claim 1 further comprising when said defined user station is busy, said defined user station, in response to said setup packet, transmitting a busy packet via said determined virtual circuit to said first user station, said busy packet defining the busy state of said defined user station, said first user station, in response to said busy packet and to a user action, transmitting a callback request packet via said determined virtual circuit to said defined user station, said defined user station, in response to said callback request packet and to an idling of said defined user station, transmitting an idle packet via said determined virtual circuit to said first user station, said idle packet defining the idle state of said defined user station, and said first user station, in response to said idle packet, transmitting a setup packet via said determined virtual circuit to said defined user station to again initiate the establishment of the said call.

4. A method in accordance with claim 1 further comprising said defined user station transmitting a call forward packet to said first user station via said determined virtual circuit in response to said setup packet, said call forward packet including forward-to information, said first user station determining whether the user station specified by said forward-to information is part of said group, upon determining that said specified user station is part of said group, said first user station ascertaining the one of said virtual circuits interconnecting said first user station and said specified user station, and said first user station transmitting a setup packet via said ascertained virtual circuit to said specified user station to initiate the establishment of said call.

5. A method in accordance with claim 1 further comprising when said defined user station is idle, said defined user station, in response to said setup packet, transmitting an alerting packet via said determined virtual circuit to said first user station, and said first user station generating an audible alerting signal in response to said alerting packet.

6. A method in accordance with claim 1 further comprising said defined user station generating an alerting signal in response to said setup packet when said defined user station is idle.

7. A method in accordance with claim 6 further comprising said defined user station discontinuing the generation of said alerting signal in response to a user action and, said defined user station transmitting a connect packet via said determined virtual circuit to said first user station.

8. A method in accordance with claim 7 further comprising subsequent to a receipt of said connect packet by said first user station, said first user station and said defined user station exchanging user information packets via said determined virtual circuit.

9. A method in accordance with claim 8 where said user information packets include voice packets.

10. A method in accordance with claim 8 where said user information packets include image packets.

11. A method in accordance with claim 8 where said user information packets include data packets.

12. A method of transmitting packets from any one of a group of user stations, where each pair of user stations of said group is interconnected by a different one of a plurality of virtual circuits of a packet switching arrangement serving a plurality of user stations including said group, said method comprising said one user station determining whether a given packet is to be transmitted to another one of said user stations of said group, upon determining that said given packet is to be transmitted to another one of said user stations of said group, said one user station determining the one of said virtual circuits interconnecting said one user station and said another user station and determining whether said given packet is an intra-group signaling packet, and upon determining that said given packet is an intra-group signaling packet, said one user station transmitting said given packet via said determined virtual circuit to said another user station with an identification of said given packet as an intra-group signaling packet.

13. A method in accordance with claim 12 further comprising upon determining that said given packet is not an intra-group signaling packet, said one user station transmitting said given packet via said determined virtual circuit to said another user station with an identification of said given packet as a user information packet.

14. A method of processing packets by a packet switching arrangement serving a plurality of user stations including a group of user stations, of said group is interconnected by a different one of a plurality of virtual circuits, and where the header of each packet transmitted by one user station of said group to another user station of said group includes an identification of said one user station as the packet source and also includes a definition of the one of said virtual circuits interconnecting said one user station and said another user station, said packet switching arrangement including means for storing data defining for each of said virtual circuits, the pair of user stations interconnected by that virtual circuit, said method comprising for each packet received including a header defining one of said virtual circuits, reading said stored data to determine the pair of user stations interconnected by said defined virtual circuit, determining whether the user station defined as the packet source by said header is one of said determined pair of user stations, and only upon determining that the user station defined as the packet source by said header is one of said determined pair of user stations, transmitting said each packet to the other one of said determined pair of user stations.

15. A method of serving calls over virtual circuits of a packet switching arrangement for a group of user stations, each user station in said group being interconnected with a different user station in said group by an individual one of a plurality of virtual circuits of said packet switching arrangement, said method comprising determining in each station in response to address information for a call, one of said plurality of virtual circuits that is defined by said address information, transmitting a setup packet via said one of said virtual circuits to a user station defined by said address information for initiating communication over said one of said virtual circuits.

16. A method in accordance with claim 15 wherein each of said stations is equipped for providing custom calling features and further comprising the step of processing in each station of said group communication entitlement and service for said custom calling features via said one of said virtual circuits.

17. A method of serving calls over virtual circuits of a packet switching arrangement for a group of user stations, said method comprising said packet switching arrangement establishing a plurality of virtual circuits, where each user station in said group is interconnected with a different user station in said group by an individual one of said plurality of virtual circuits, determining in each station in response to address information for a call, one of said plurality of virtual circuits that is defined by said address information, transmitting a setup packet via said one of said virtual circuits to a user station defined by said address information and for initiating communication over said one of said virtual circuits.