CA1281432C - Multipoint link data-transmission control system - Google Patents
Multipoint link data-transmission control systemInfo
- Publication number
- CA1281432C CA1281432C CA000533235A CA533235A CA1281432C CA 1281432 C CA1281432 C CA 1281432C CA 000533235 A CA000533235 A CA 000533235A CA 533235 A CA533235 A CA 533235A CA 1281432 C CA1281432 C CA 1281432C
- Authority
- CA
- Canada
- Prior art keywords
- transmission
- transmission device
- data
- slave
- master
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005540 biological transmission Effects 0.000 claims abstract description 203
- 238000013500 data storage Methods 0.000 claims description 11
- 230000001360 synchronised effect Effects 0.000 claims description 6
- 230000002401 inhibitory effect Effects 0.000 claims description 5
- 239000002674 ointment Substances 0.000 claims description 3
- 230000002457 bidirectional effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 2
- SZKKRCSOSQAJDE-UHFFFAOYSA-N Schradan Chemical compound CN(C)P(=O)(N(C)C)OP(=O)(N(C)C)N(C)C SZKKRCSOSQAJDE-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/403—Bus networks with centralised control, e.g. polling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
Abstract
Abstract of the Disclosure According to a multipoint link data-transmission control system, a master transmission device delivers message data via a bidirectional transmission path to a plurality of slave transmission devices, the data containing a control field for designating control data for setting or resetting a flag. The transmitting of data from the slave transmission device to the master transmission device is allowed when the flag is set, and is inhibited when the flag is reset. Where the transmitting of data from a faulty slave transmission device is to be inhibited, the master transmission device transmits the data to the faulty slave trans-mission device, by designating flag reset data to the control field of the message data. As a result, a transmission-enable signal, which is delivered in syn-chronization with a transmission-timing clock signal, is reset, thereby stopping the transmitting of data from the slave transmission device to the master transmission device.
Description
1~14~2 -- 1 ~
This invention relates to a multipoint link data-transmission control system.
Generally, a multipoint link data-transmission system is known which controls the transmission of data among data-transmission devices connected, through a bidirectional transmission path, in a one-to-n fashion.
As is shown in Fig. 1, for example, a multiproces-sor system has been developed which, through use of a plurality of processors lar lb, ..., ln, hierarchically dlstributes their processing functions, as demanded by an information-processing system, as well as their loads, so as to enhance the overall processing capa-bility.
In the multiprocessor system shown in Fig. 1, high-level processor la is connected to master transmissiondevice ~a, and low-level processors lb, ..., ln are connected to slave transmission devices 2b, ..., 2n, respectively. Master transmission device 2a is con-nected via a bidirectional transmission path to slave transmission devices 2b, ~ D ~ ~ 2n of low-level proces-sors lb, ..., ln.
When data is transmitted from master transmission device 2a to slave transmission devices 2b, ..., 2n, a header containing a destination address is attached to the transmission data On the other hand, when data is transmitted from slave transmission devices 2b, ..., 2n to master transmission device 2a or to other , ~
4~
transmission devices, a header containing a source address is attached to the transmission data.
Of this type of system, in which data is transmit-ted from a master transmission device to a respective slave transmission device, three types are known.
The first system is a type in which the master transmission device simultaneously transmits data to the respective slave transmission devices, and, when necessary, this master device is able to inhibit the transmitting of data from all the slave transmission devices~
The second systam is a type which transmits the same data message to a respective group into which slave transmission devices having the same processing function have been assembled. This system effectively controls the transmitting of data by the slave transmission de-vices per~orming the same processing.
The third system is a type which transmits data to a desired slave transmission device, by designating the corresponding destination address thereof.
When data is to be transmitted from the respective slave transmission device to the master transmission devic0, the master transmission device receives data, at a predetermined time interval, from the respective slave transmission device, on the basis of a time slot allotted thereto. Another transmission sys-tem allows one time slot to be shared among a plurality of slave ~ ~ 8~3~
-transmission devices, through the slave transmission device transmitting data to the master transmission device, with a corresponding identification code attached to the message data.
A practical application of such a multiprocessor is in, for example, an electronic telephone exchange system.
In such a system, if a fault develops in any of slave transmission devices 2b, ..., ~n, and particularly in low-level processors lb, ..., ln, master transmission device 2a 5upper-level processor la) operates to prevent the normally-operating slave transmission devices (slave processors) from b~lng u disabled, by receiving data from the faulty slave transmission device and then discarding this data.
In this way, the conventional system provides a bar efficient data-transmission control, since it is pointless to 1~ perform data communication with the faulty slave transmission device (slave processor~.
Accordingly the present invention provides a multipoint link data-transmission control system which can inhibit erroneous data from being transmitted from a faulty slave transmission device (slave processor), by controlling the salve transmission device by a master transmission dsvice, and by inhibiting the transmltting of data from the master transmission device to all the slave transmission devices, without the loss of any da-ta.
~!;
According to $he present invention, a multipoint link data-transmission control system is provided a multipoint link data-transmission control system having a master transmission device to which a master processor is connected, and a slave 3~ transmission device connected via a synchronous bus to said mater transmission device, to which a plurality of s7ave processor are connected, said lave processor transmitting message data to said master transmission device, said slave transmission device comprising: a receiving section csmprisiny decoding means for 3~
3~ .
decoding message data transmission from sald master transmission device vla said synchronous bus; said recelving section further comprising: flag means for indicating whether said slave transmission device transmits or not to said master transmission device, in accordance with a decoded output from said decoding means, said flag means connected to said synchronous bus; a -transmission section comprising transmission data storage means for storing a message data to be transmitted to said master transmission device; said transmission device; said transmission section ~urther comprising, transmitting means for transmitting the message data stored in said transmission data storage means;
transmission control mean for transmitting message data from said transmission data storage means to said transmitting means in accordance with flag data representing the resetting of said flag means during the transmission of the message data from said transmission data storage means, and said transmission control means stopping operation of said transmitting means after detecting that the message data has been sent from said transmission data stoxage means, said transmission control means being connected to said flag means; and said plurality of slave 2U processors transmit the message data from said transmission data storage means to said master transmission device in accordance with a corresponding time slot assigned to each of said plurality of slave processors.
In the multipoint link data-transmission control system 2~ of the present invention, the master transmission device sets or resets a flag for determining the starting or the suspension of the transmitting of data, relative to the slave transmission device. It is therefore possible to effectlvely control the transmitting of data by the slave transmission device, by means 3~ of the master transmission device.
In one embodiment of the present invention said master transmission device has means for inhibiting said slave transmission device so that faulty message data is not 3~
1'~8143~
transmitted to said master transmission device.
In another embodiment of the present .lnvention said master transmission device has means for deslgnating the same message data to all the slave transmission devices of said plurality of salve processors which are operating normally.
In a further embodiment of the present invention said master transmission device has means for designatin~ a particular message data and for sending a data transmission disbale flag to said transmission control means so that said master transmission device can inhibit a group of slave transmission devices of the Lu same processing function from transmitting their message data to the master transmission device.
In another embodiment of the present invention the same time slot is assigned to said plurality o~ slave processor, said 1~ slave transmission dev1ce having a means for delivering delivers to the master transmission device the message date with said ~lave transmission devicP's own corresponding identification code attached thereto. Suitably the message data transmitted from the master transmission device contains control informatlon.
2~
Features of the present invention wi.ll be apparent from the followiny description taken in connetion with the accompanying drawings in which:
ZL' Fig. 1 is a block diagram schematically illustrating a general multipoint link data-transmission control system;
Fig. ~ is a block diagram showing a slave transmlsslon device in a multipoint link data-transmission control system 3~ according to the embodiment of the present invention;
Fig. 3 shows a format of data as transmitted from a master transmission device to a slave transmisslon device;
3~
This invention relates to a multipoint link data-transmission control system.
Generally, a multipoint link data-transmission system is known which controls the transmission of data among data-transmission devices connected, through a bidirectional transmission path, in a one-to-n fashion.
As is shown in Fig. 1, for example, a multiproces-sor system has been developed which, through use of a plurality of processors lar lb, ..., ln, hierarchically dlstributes their processing functions, as demanded by an information-processing system, as well as their loads, so as to enhance the overall processing capa-bility.
In the multiprocessor system shown in Fig. 1, high-level processor la is connected to master transmissiondevice ~a, and low-level processors lb, ..., ln are connected to slave transmission devices 2b, ..., 2n, respectively. Master transmission device 2a is con-nected via a bidirectional transmission path to slave transmission devices 2b, ~ D ~ ~ 2n of low-level proces-sors lb, ..., ln.
When data is transmitted from master transmission device 2a to slave transmission devices 2b, ..., 2n, a header containing a destination address is attached to the transmission data On the other hand, when data is transmitted from slave transmission devices 2b, ..., 2n to master transmission device 2a or to other , ~
4~
transmission devices, a header containing a source address is attached to the transmission data.
Of this type of system, in which data is transmit-ted from a master transmission device to a respective slave transmission device, three types are known.
The first system is a type in which the master transmission device simultaneously transmits data to the respective slave transmission devices, and, when necessary, this master device is able to inhibit the transmitting of data from all the slave transmission devices~
The second systam is a type which transmits the same data message to a respective group into which slave transmission devices having the same processing function have been assembled. This system effectively controls the transmitting of data by the slave transmission de-vices per~orming the same processing.
The third system is a type which transmits data to a desired slave transmission device, by designating the corresponding destination address thereof.
When data is to be transmitted from the respective slave transmission device to the master transmission devic0, the master transmission device receives data, at a predetermined time interval, from the respective slave transmission device, on the basis of a time slot allotted thereto. Another transmission sys-tem allows one time slot to be shared among a plurality of slave ~ ~ 8~3~
-transmission devices, through the slave transmission device transmitting data to the master transmission device, with a corresponding identification code attached to the message data.
A practical application of such a multiprocessor is in, for example, an electronic telephone exchange system.
In such a system, if a fault develops in any of slave transmission devices 2b, ..., ~n, and particularly in low-level processors lb, ..., ln, master transmission device 2a 5upper-level processor la) operates to prevent the normally-operating slave transmission devices (slave processors) from b~lng u disabled, by receiving data from the faulty slave transmission device and then discarding this data.
In this way, the conventional system provides a bar efficient data-transmission control, since it is pointless to 1~ perform data communication with the faulty slave transmission device (slave processor~.
Accordingly the present invention provides a multipoint link data-transmission control system which can inhibit erroneous data from being transmitted from a faulty slave transmission device (slave processor), by controlling the salve transmission device by a master transmission dsvice, and by inhibiting the transmltting of data from the master transmission device to all the slave transmission devices, without the loss of any da-ta.
~!;
According to $he present invention, a multipoint link data-transmission control system is provided a multipoint link data-transmission control system having a master transmission device to which a master processor is connected, and a slave 3~ transmission device connected via a synchronous bus to said mater transmission device, to which a plurality of s7ave processor are connected, said lave processor transmitting message data to said master transmission device, said slave transmission device comprising: a receiving section csmprisiny decoding means for 3~
3~ .
decoding message data transmission from sald master transmission device vla said synchronous bus; said recelving section further comprising: flag means for indicating whether said slave transmission device transmits or not to said master transmission device, in accordance with a decoded output from said decoding means, said flag means connected to said synchronous bus; a -transmission section comprising transmission data storage means for storing a message data to be transmitted to said master transmission device; said transmission device; said transmission section ~urther comprising, transmitting means for transmitting the message data stored in said transmission data storage means;
transmission control mean for transmitting message data from said transmission data storage means to said transmitting means in accordance with flag data representing the resetting of said flag means during the transmission of the message data from said transmission data storage means, and said transmission control means stopping operation of said transmitting means after detecting that the message data has been sent from said transmission data stoxage means, said transmission control means being connected to said flag means; and said plurality of slave 2U processors transmit the message data from said transmission data storage means to said master transmission device in accordance with a corresponding time slot assigned to each of said plurality of slave processors.
In the multipoint link data-transmission control system 2~ of the present invention, the master transmission device sets or resets a flag for determining the starting or the suspension of the transmitting of data, relative to the slave transmission device. It is therefore possible to effectlvely control the transmitting of data by the slave transmission device, by means 3~ of the master transmission device.
In one embodiment of the present invention said master transmission device has means for inhibiting said slave transmission device so that faulty message data is not 3~
1'~8143~
transmitted to said master transmission device.
In another embodiment of the present .lnvention said master transmission device has means for deslgnating the same message data to all the slave transmission devices of said plurality of salve processors which are operating normally.
In a further embodiment of the present invention said master transmission device has means for designatin~ a particular message data and for sending a data transmission disbale flag to said transmission control means so that said master transmission device can inhibit a group of slave transmission devices of the Lu same processing function from transmitting their message data to the master transmission device.
In another embodiment of the present invention the same time slot is assigned to said plurality o~ slave processor, said 1~ slave transmission dev1ce having a means for delivering delivers to the master transmission device the message date with said ~lave transmission devicP's own corresponding identification code attached thereto. Suitably the message data transmitted from the master transmission device contains control informatlon.
2~
Features of the present invention wi.ll be apparent from the followiny description taken in connetion with the accompanying drawings in which:
ZL' Fig. 1 is a block diagram schematically illustrating a general multipoint link data-transmission control system;
Fig. ~ is a block diagram showing a slave transmlsslon device in a multipoint link data-transmission control system 3~ according to the embodiment of the present invention;
Fig. 3 shows a format of data as transmitted from a master transmission device to a slave transmisslon device;
3~
4;3~
Fig. 4 is a circuit arrangement showirlg, in more .U
l!;
2!
3t~
- 5a ~Z8~3~
detail, a transmission control section of the slave transmission device as shown in Fig. 2; and Figs. 5A through 5H are timing charts relating to the transmitting of data by the slave transmission de-vice, showing, respectively, an initial reset, buffer-write pulse, transmission-request, internal-flag, transmission-timing clock, transmission-enable, transmission-complete, and transmission-output signals.
The embodiment of the present invention will now be explained belowr with respect to Figs. 2 through 5 in which li~e reference numerals are employed to desig-nate like components or elements throughout the specifi-cation.
In this embodiment it should be understood that three types of transmission systems are employed, namely--(1) a system for simultaneously transmitting mess-age data from a master transmission device to all the slave transmission devices;
(2) a system for transmitting message data from a master transmission device to a respective slave device;
and (3) a system for transmitting a message from a master transmission device to a slave transmission device, by designating the destination address thereof.
In the case where a message is to be transmi-tted from a slave transmission device to a master transmission 3'~
device, the master transmission device allocates a time slot to the respective slave transmission device, and receives data therefrom, or else allows one time slot to be shared among a plurality of slave transmission devices.
As is shown in Fig. 2, the slave transmission de-vice is comprised of a receiving section A for receiving data transmitted via transmission path 3, transmission section B for transmitting data via transmission path 3, and interface section C for connecting receiving section A and transmission section B to ~ processor.
Receiving section A delivers data sent from the master transmission device via the transmission path, into a receiving buffer, as is set out below.
The data sent from the master transmission device comprises, as is shown in Fig. 3, a flag (F) field re-presenting the beginning of the data, an address (ADR) field representing a destination address, a control (CONT) field representing flag-setting and -resetting requests with respect to the slave transmission device, and a data field.
Receiving-control section 12 checks the destination address stored in receiving buffer 11, to see if it is directed to an intra-slave transmission device. If so, the data is loaded into receiving register 13 and com-mand decoder 1~. The data thus stored in receiving register 13 is delivered, via CPU interface 15 in ~143~
interface section C, into a processor.
Command decoder 14 decodes the control field of the received data and, when data "00" is decoded, instructs receiving register 13 to supply the data which has been set therein, to processor lb. Command decoder 14 sets flag register 16 when data "10" is decoded, and resets it when data "11" is decoded. Receiving section B com-prises transmission buffer 17 for storing transmission data supplied from the processor via interface section C; transmission register 18 for receiving the transmis-sion data stored in transmission buffer 17, in a pre-determined timing, and for transmitting it onto the transmission path; transmission control section 19 for controlling the transmitting of data, and timing signal generator 20 for supplying a transmission clock signal to transmission register 18, and a transmission buffer-write pulse and transmission-timing clock signal to transmission control section l9.
Transmission control section 19 controls the trans-mitting of data in accordance with various transmissioncontrol signals supplied from the processor via CPU
interface 15, and with the set state of flag register 16.
Fig. 4 shows a circuit arrangement of transmission control section 19 in more detail. First Elip-flop 21 is set upon receipt of a write pulse which is supplied when the transmission data is written onto transmission 1~8~.432 _ 9 _ buffer 17. The l'set" state of Eirst flip-flop 21 indi-cates that the transmission data is stored in transmis-sion buffer 17. The output signal of first flip-flop 21 is used as a transmission-request signal.
Upon receipt of the aforementioned transmission-request signal, gate circuit 22 supplies flag data, which has been held in flag register 16, to second ~lip-flop 23. In synchroni~ation with the transmission-timing clock signal, as shown in Fig~ 5E, ~lip-~lop 23 supplies a transmission-enable signal to transmission register 18, output gate circuit 24 for the transmission path, and transmitted-bit number counter 25. As a re-sult, transmission register 18 sequentially delivers the transmission data as an output signal, via output gate circuit 24, on the basis of the transmission clock signal supplied from timiny signal generator 20. This clock signal is supplied to transmitted-bit number counter 25 where the transmitted clocks are counted.
Bit number counter 25 delivers a "transmission-complete"
output signal when all the data held in transmission register 18 have been delivered. The "transmission-complete" signal, together with the initial reset signal fed from the processor, is supplied via OR gate 26 to the reset terminals of Eirst and second flip-10ps 21 and 23, respectively.
The operation of the embodiment oE the present invention will now be explained below.
1'~8~.43'~
Suppose that, with flag regist0r 16 of Fig. 2 set, a transmission-request signal is being supplied from first flip-flop 21 to AND gate 22 (see Fig. 4). At this time, a high-level signal i5 supplied from AND gate 22 5 to second flip-flop 23, to set the latterO Flip-flop 23 supplies a transmission-enable signal to transmission register 18 and transmitted-bit number counter 25, noting that the data which has been held in transmission regis~
ter 18 is supplied in accordance with the transmission clock, as indicated by a phase (I) in Fig. 5H.
Let it be assumed that, in this state, the afore-mentioned master transmission device supplies, to the slave transmission device, data containing flag-reset data which is written in the control field. As a re-sult, flag register 16 is reset, transmitting the resetdata to AND gate 22 at which time the transmitting of data continues, since AND gate 22 supplies the data from flag register 16 to second flip-flop 23, in synchroniza-tion with a transmission-timing clockO In this connec-tion, phase (II) in Fig. 5H should be referred to.
After the transmission data of transmissionregister 18 have all been transmitted, flip-flops 21 and 23 are reset. As a result, since the flag data supplied from flag register 16 is reset at the time a transmission-request signal (as shown in Fig. 5C) is delivered as an output signal, no transmission-enable signal is delivered from flip-flop 23, and ~8~32 thus no data is trans~mitted from transmission register 18, as is indicated by a phase (III) in Fig. 5H.
As is set out above, with the multipoint link data-transmission control system of the present invention, the flag of slave transmission device 2b is set or reset on the basis of control data supplied from master trans-mission device 2a, thus allowing or inhibi-ting the transmitting oE data from slave transmission device 2b to master transmission device 2a, respectively~
lOWhen the flag is reset during the transmitting of data, the slave transmission device, upon the completion of this data transmission, inhibits further data trans-mission from taking place. The transmitting of data by the slave transmission device is inhibited where:
15(1) it is desired to inhibit the transmitting of data by all the slave processors, while all the slave transmission devices (slave transmission control devices and slave processors) are operating normally; and t2) it is desired to inhibit the transmitting of data by a faulty slave transmission device.
It does not matter even i~ the transmitting of data by the faulty slave transmission device is inhi-: bited during the data-transmission process, since this will not affect the transmitting of data by the other normally-operating slave transmission devices. Suppose that, with all the slave transmission devices in the normal operating state, the transmitting of data from ,, , :: : .i.
43~
the master transmission device to all the slave transmission devices is to be inhibited by ~'broadcasting", as in case ~l). If this data transmission process is inhibited when any of the slave transmission devices is transmi-tting data, then that data will become ineffective. According to the present inventlon, however, such an inconvenience is inhibited by inhibiting the furthar transfer of such data after the current data~transmission process has been completed.
The master transmission device may for example be a dual type.
,,
Fig. 4 is a circuit arrangement showirlg, in more .U
l!;
2!
3t~
- 5a ~Z8~3~
detail, a transmission control section of the slave transmission device as shown in Fig. 2; and Figs. 5A through 5H are timing charts relating to the transmitting of data by the slave transmission de-vice, showing, respectively, an initial reset, buffer-write pulse, transmission-request, internal-flag, transmission-timing clock, transmission-enable, transmission-complete, and transmission-output signals.
The embodiment of the present invention will now be explained belowr with respect to Figs. 2 through 5 in which li~e reference numerals are employed to desig-nate like components or elements throughout the specifi-cation.
In this embodiment it should be understood that three types of transmission systems are employed, namely--(1) a system for simultaneously transmitting mess-age data from a master transmission device to all the slave transmission devices;
(2) a system for transmitting message data from a master transmission device to a respective slave device;
and (3) a system for transmitting a message from a master transmission device to a slave transmission device, by designating the destination address thereof.
In the case where a message is to be transmi-tted from a slave transmission device to a master transmission 3'~
device, the master transmission device allocates a time slot to the respective slave transmission device, and receives data therefrom, or else allows one time slot to be shared among a plurality of slave transmission devices.
As is shown in Fig. 2, the slave transmission de-vice is comprised of a receiving section A for receiving data transmitted via transmission path 3, transmission section B for transmitting data via transmission path 3, and interface section C for connecting receiving section A and transmission section B to ~ processor.
Receiving section A delivers data sent from the master transmission device via the transmission path, into a receiving buffer, as is set out below.
The data sent from the master transmission device comprises, as is shown in Fig. 3, a flag (F) field re-presenting the beginning of the data, an address (ADR) field representing a destination address, a control (CONT) field representing flag-setting and -resetting requests with respect to the slave transmission device, and a data field.
Receiving-control section 12 checks the destination address stored in receiving buffer 11, to see if it is directed to an intra-slave transmission device. If so, the data is loaded into receiving register 13 and com-mand decoder 1~. The data thus stored in receiving register 13 is delivered, via CPU interface 15 in ~143~
interface section C, into a processor.
Command decoder 14 decodes the control field of the received data and, when data "00" is decoded, instructs receiving register 13 to supply the data which has been set therein, to processor lb. Command decoder 14 sets flag register 16 when data "10" is decoded, and resets it when data "11" is decoded. Receiving section B com-prises transmission buffer 17 for storing transmission data supplied from the processor via interface section C; transmission register 18 for receiving the transmis-sion data stored in transmission buffer 17, in a pre-determined timing, and for transmitting it onto the transmission path; transmission control section 19 for controlling the transmitting of data, and timing signal generator 20 for supplying a transmission clock signal to transmission register 18, and a transmission buffer-write pulse and transmission-timing clock signal to transmission control section l9.
Transmission control section 19 controls the trans-mitting of data in accordance with various transmissioncontrol signals supplied from the processor via CPU
interface 15, and with the set state of flag register 16.
Fig. 4 shows a circuit arrangement of transmission control section 19 in more detail. First Elip-flop 21 is set upon receipt of a write pulse which is supplied when the transmission data is written onto transmission 1~8~.432 _ 9 _ buffer 17. The l'set" state of Eirst flip-flop 21 indi-cates that the transmission data is stored in transmis-sion buffer 17. The output signal of first flip-flop 21 is used as a transmission-request signal.
Upon receipt of the aforementioned transmission-request signal, gate circuit 22 supplies flag data, which has been held in flag register 16, to second ~lip-flop 23. In synchroni~ation with the transmission-timing clock signal, as shown in Fig~ 5E, ~lip-~lop 23 supplies a transmission-enable signal to transmission register 18, output gate circuit 24 for the transmission path, and transmitted-bit number counter 25. As a re-sult, transmission register 18 sequentially delivers the transmission data as an output signal, via output gate circuit 24, on the basis of the transmission clock signal supplied from timiny signal generator 20. This clock signal is supplied to transmitted-bit number counter 25 where the transmitted clocks are counted.
Bit number counter 25 delivers a "transmission-complete"
output signal when all the data held in transmission register 18 have been delivered. The "transmission-complete" signal, together with the initial reset signal fed from the processor, is supplied via OR gate 26 to the reset terminals of Eirst and second flip-10ps 21 and 23, respectively.
The operation of the embodiment oE the present invention will now be explained below.
1'~8~.43'~
Suppose that, with flag regist0r 16 of Fig. 2 set, a transmission-request signal is being supplied from first flip-flop 21 to AND gate 22 (see Fig. 4). At this time, a high-level signal i5 supplied from AND gate 22 5 to second flip-flop 23, to set the latterO Flip-flop 23 supplies a transmission-enable signal to transmission register 18 and transmitted-bit number counter 25, noting that the data which has been held in transmission regis~
ter 18 is supplied in accordance with the transmission clock, as indicated by a phase (I) in Fig. 5H.
Let it be assumed that, in this state, the afore-mentioned master transmission device supplies, to the slave transmission device, data containing flag-reset data which is written in the control field. As a re-sult, flag register 16 is reset, transmitting the resetdata to AND gate 22 at which time the transmitting of data continues, since AND gate 22 supplies the data from flag register 16 to second flip-flop 23, in synchroniza-tion with a transmission-timing clockO In this connec-tion, phase (II) in Fig. 5H should be referred to.
After the transmission data of transmissionregister 18 have all been transmitted, flip-flops 21 and 23 are reset. As a result, since the flag data supplied from flag register 16 is reset at the time a transmission-request signal (as shown in Fig. 5C) is delivered as an output signal, no transmission-enable signal is delivered from flip-flop 23, and ~8~32 thus no data is trans~mitted from transmission register 18, as is indicated by a phase (III) in Fig. 5H.
As is set out above, with the multipoint link data-transmission control system of the present invention, the flag of slave transmission device 2b is set or reset on the basis of control data supplied from master trans-mission device 2a, thus allowing or inhibi-ting the transmitting oE data from slave transmission device 2b to master transmission device 2a, respectively~
lOWhen the flag is reset during the transmitting of data, the slave transmission device, upon the completion of this data transmission, inhibits further data trans-mission from taking place. The transmitting of data by the slave transmission device is inhibited where:
15(1) it is desired to inhibit the transmitting of data by all the slave processors, while all the slave transmission devices (slave transmission control devices and slave processors) are operating normally; and t2) it is desired to inhibit the transmitting of data by a faulty slave transmission device.
It does not matter even i~ the transmitting of data by the faulty slave transmission device is inhi-: bited during the data-transmission process, since this will not affect the transmitting of data by the other normally-operating slave transmission devices. Suppose that, with all the slave transmission devices in the normal operating state, the transmitting of data from ,, , :: : .i.
43~
the master transmission device to all the slave transmission devices is to be inhibited by ~'broadcasting", as in case ~l). If this data transmission process is inhibited when any of the slave transmission devices is transmi-tting data, then that data will become ineffective. According to the present inventlon, however, such an inconvenience is inhibited by inhibiting the furthar transfer of such data after the current data~transmission process has been completed.
The master transmission device may for example be a dual type.
,,
Claims (6)
1. A multipoint link data-transmission control system having a master transmission device to which a master processor is connected, and a slave transmission device connected via a synchronous bus to said master transmission device! to which a plurality of slave processors are connected, said slave processor transmitting message data to said master transmission device, said slave transmission device comprising a receiving section comprising decoding means for decoding message data transmission from said master transmission device via said synchronous bus;
said receiving section further comprising: flag means for indicating whether said slave transmission device transmits or not to said master transmission device, in accordance with a decoded output from said decoding means, said flag means connected to said synchronous bus; a transmission section comprising transmission data storage means for storing a message data to be transmitted to said master transmission device; said transmission section further comprising, transmitting means for transmitting the message data stored in said, transmission data storage means; transmission control mean for transmitting message data from said transmission data storage means to said transmitting means in accordance with flag data representing the resetting of said flag means during the transmission of the message data from said transmission data storage means, and said transmission control means stopping operation of said transmitting means after detecting that the message data has been sent from said transmission data storage means, said transmission control means being connected to said flag means; and said plurality of slave processors transmit the message data from said transmission data storage means to said master transmission device in accordance with a corresponding time slot assigned to each of said plurality of slave processors.
said receiving section further comprising: flag means for indicating whether said slave transmission device transmits or not to said master transmission device, in accordance with a decoded output from said decoding means, said flag means connected to said synchronous bus; a transmission section comprising transmission data storage means for storing a message data to be transmitted to said master transmission device; said transmission section further comprising, transmitting means for transmitting the message data stored in said, transmission data storage means; transmission control mean for transmitting message data from said transmission data storage means to said transmitting means in accordance with flag data representing the resetting of said flag means during the transmission of the message data from said transmission data storage means, and said transmission control means stopping operation of said transmitting means after detecting that the message data has been sent from said transmission data storage means, said transmission control means being connected to said flag means; and said plurality of slave processors transmit the message data from said transmission data storage means to said master transmission device in accordance with a corresponding time slot assigned to each of said plurality of slave processors.
2. The system according to claim 1, wherein said master transmission device has means for inhibiting said slave transmission device so that faulty message data is not transmitted to said master transmission device.
3. The system according to claim 1, wherein said master transmission device has means for designating the same message data to all the slave transmission devices of said plurality of salve processors which are operating normally.
4. The system according to claim 1, wherein said master transmission device has means for designating a particular message data and for sending a data transmission disable flag to said transmission control means so that said master transmission device can inhibit a group of slave transmission devices of the same processing function from transmitting their message data to the master transmission device.
5. The system according to claim 1, wherein with the same time slot assigned to said plurality of slave processor, said slave transmission device having a means for delivering delivers to the master transmission device the message data with said slave transmission device's own corresponding identification code attached thereto.
6. The system according to claim 1, wherein the message data transmitted from the master transmission device contains control information.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP72130/86 | 1986-03-29 | ||
| JP61072130A JPS62227243A (en) | 1986-03-29 | 1986-03-29 | Transmission control system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1281432C true CA1281432C (en) | 1991-03-12 |
Family
ID=13480410
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000533235A Expired - Lifetime CA1281432C (en) | 1986-03-29 | 1987-03-27 | Multipoint link data-transmission control system |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4888728A (en) |
| JP (1) | JPS62227243A (en) |
| CA (1) | CA1281432C (en) |
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-
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-
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- 1987-03-30 US US07/031,576 patent/US4888728A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US4888728A (en) | 1989-12-19 |
| JPS62227243A (en) | 1987-10-06 |
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