CA1288828C - Clock pulse generator for microcomputer - Google Patents
Clock pulse generator for microcomputerInfo
- Publication number
- CA1288828C CA1288828C CA000566629A CA566629A CA1288828C CA 1288828 C CA1288828 C CA 1288828C CA 000566629 A CA000566629 A CA 000566629A CA 566629 A CA566629 A CA 566629A CA 1288828 C CA1288828 C CA 1288828C
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- CA
- Canada
- Prior art keywords
- clock pulse
- pulse signals
- clock
- pulses
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 4
- 238000004134 energy conservation Methods 0.000 claims 1
- 230000008859 change Effects 0.000 description 7
- 230000001143 conditioned effect Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009131 signaling function Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
- H03K5/15066—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using bistable devices
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F41—WEAPONS
- F41J—TARGETS; TARGET RANGES; BULLET CATCHERS
- F41J13/00—Bullet catchers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
Abstract
ABSTRACT OF THE DISCLOSURE
The output of a single source of pulses is sequentially frequency divided and gate circuits arranged so that one of the plurality of divisions can be selectively supplied to an output terminal of the device.
The output of a single source of pulses is sequentially frequency divided and gate circuits arranged so that one of the plurality of divisions can be selectively supplied to an output terminal of the device.
Description
~8~
CLOCK PULSE GENERATOR FOR MICROCOMPUTER
BACKGF<OUND OF THE INVENTION
Field of -the Invention The present invention relates generally to a clock pulse generator for a microcomputer and more specifically to an improved arrangement for use with one chip type microcomputers.
Description of the Prior Art Normally silicon chip microprocessors including a central processing unit CPU, a read only memory ROM, a random access memory RAM and an output input interface I/O are formed on a single chip (one chip microcomputer) and are arranged to operated on a 5V power supply. However, of recent times a demand for a one chip microprocessor which an be operated on batteries has developed. This requires that the supply on which the device is operated be selectively reduced from 5V to 3V. This reduction induces a change in the generation of clock pulses which are ~sed in connection with the operation of the CPU.
When this change occurs however, improper operation is apt to occur.
Accordingly, it is required to be able to produce low speed clock pulses when this reduction in power occurs in a manner which renders it possible to maintain proper operation. It is additionally required to be able to provide low speed clock signals when the power supply is reduced for the ' purposes of conserving electrical power and/or in the event of a power blackout.
Moreover, it is desirable to be able to expand control over the reading and writing cycles when accessing an external low speed expansion memory.
In order to achieve the above it has been proposed to use two clock pulse generators - one for -: ' high speed pulse signals and one for low speed pulse signals. However, this arrangement i5 such that when one is in use the other is rendered redundant.
Further, when swi-tching from one to another, it often occurs that an asynchronism or misalignment occurs in the positional relationship between the pulses.
SUMMARY OF THE INVENTIOM
It i5 an object of the present invention to provide a clock pulse generator which features simple construction and cost and which enables the switching between high and lows speed pulses without undesirable interruption of CPU activity.
In brief, the above object is achieved by an arrangement wherein in order to permit a one-chip type microprocessor to be operated on two different power sources such as a household supply and batteries and in order to facilitate slow speed external memory access, the output of a single source of pulses is sequentially frequency divided and gate circuits arranged so that one oE the plurality of divisions can be selectively supplied to an output terminal of the device.
More specifically, a first aspect of the present invention comes the ~orm of a one chip microprocessor c.lock pulse generator which features:
a source of clock pulses: means for successively dividing the clock pulses by the same ratio and producing a plurality of clock pulse signals the pulse widths of which are different;~a plurality of gate circuits, the gate circuits being arranged to selectivel~ supply one of the clock pulse signals to an output terminal arrangement.
A second aspect of the invention comes in that the dividing means comprises: a plurality of frequency dividers, the frequency dividers being connected in manner wherein the first frequency :
. . . ~ `, .
- ; ' ` :, ;' ' .~,, divider is arranged to divide the pulses supplied from the source in a predetermined manner, the next frequency divider being arranged -to receive the output of the first frequency divider and perform essentially the same division.
A fur-ther aspect of the invention comes in that the above mentioned plurality of clock pulse signals are divided in a manner that one of the leading and trailing edges of the pulses occur coincidently and thus enable switching from one to ano-ther without phase difference occuring.
Another aspect of the invention comes in the form of a method of generating clock pulses in a microprocessor which features the steps of: using a single source to produced a basic clock pulse signal;
successively dividing the basic clock pulse signal to form a series of pulse signals~ each having successively longer pulse widths; selectively using one of the series of pulse signals in connection with the control of the processor.~
A yet further aspect of the invention comes in that the above mentioned method further features: arranging one of the leadirlg and trailing edges of the series of pulse signal to occur synchronously.
BRIEF DESCRIPTION OF THE DRAWINGS
The features and ~advantages inherent with the prasent inven~ion will become more clearly ' appreciated as the~ following description of the preferred embodiment is made with reference to the appended drawin~s in which:
Fig.l is a circuit diagram ~showing the construction of an embodiment of a clock pulse generator accordi.ng to the present invention; and Fig. 2 is~a timing chart which demonstrates the operational characteristics of the arrangement ;::
:
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shown in Fig. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Fig. 1 shows a circuit arrangement which characterizes the present invention. This arrangement includes input terminals which are arranged to receive clock pulses from a liquid crystal type clock pulse generator tnot shown);
frequency dividers 2 - 5; gate circuits 6a, 6b, 7a, 7b, 8a, 8b and 9a, 9b; clock pulse output terminals 10a, 10b; gate control signal generator circuits 12 -15; designated signal input terminals lla, llb, 16a and 16b; and a discrimination signal input terminal 17 which is arranged to receive a signal from a memory address decoder, all connected as shown.
With this arrangement the first frequency divider 2 is arranged to perform a first division (1/2) and divide the inpu-t pulses la shown in Fig.
2A, in a manner to produce a pulse train 2a such as shown in Fig. 2B. The second pulse divider 3 is arranged to perform a second division ~ and produce a pulse train having a frequency 1/4 of the original one. Viz., produce a signal 3a of the nature shown in Fig. 2C.
The third and fourth frequency dividers are arranged to perform subsequent frequency divisions and produce signals 4a and Sa (see Figs.
2D, 2E) which respectively have frequencies which are 1/8 and 1/16 of the input signal la. As will be ' noted each of the clock pulses are arranged to be formed with a 90 phase difference.
The outputs of the frequency dividers 2 -5 are respectively supplied through the gate circuits 6a 9b to the clock signal output terminals 10a, 10b.
A two bit digital signal from the computer control circuit i9 suQplie~ to the designated input - .
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,, .
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terminals lla, llb. This signal functions to selectively control the gate circui-ts 6a - 9b. Viz., when both of the signals appearing on the terminals lla and llb, assume a low level "0" gate 6a, 6b is 5switched to assume an ON condition whereby the clock pulses 2a which have been (1/2) divided appear on the clock pulse output terminals 10a, 10b. When the levels on the -terminals lla and llb assume low and high levels ( 0, 1) respectively, ~ate circuit 7a, 7b 10is selectively conditioned to assume an ON state.
Under these conditions clock pulse train 3a is supplied to the clock pulse output terminals 10a, 10b.
In -the event that the signals appearing on 15terminals lla and llb assume levels 1 and 0, gate circuit 8a, 8b is opened and the clock pulses 4a are selectively appl~ied to terminals 10a, 10b. Finally, if the signals appearing on the terminals lla, llb both assume high levels (viz., 1, 1) then the last of 20the gate circuits is conditioned to open and apply the (1/16) divided pulse train 4a to terminals 10a, 10b.
When a ~two bit signal from an external memory is applied to the terminals 16a and 16b, a ~ 25similar control wherein the gate control circuits 12 `~ ~ to 15 selectively open the gates 6a - 9b is possible.
In the case that the ex-ternal memory is selected and a discrimination signal is applied to ' terminal 17 therefrom, the gate control circuits 12 30to 15 are selectively conditionable to open the gate circuits 6a to 9b.
When the above disclosed circuit ~; arrangement is put~into operation in a manner wherein th0 high speed clock pulses 2a are changed to those 35shown in Fig. 2E (viz., 5a), low level signals are applied to both the terminals lla and llb. This ~ . , .
~88~B
induces gate control circuit 12 to apply a high level signal (1) and condition gate 6a, 6b to assume an ON
state. Under these conditions high speed pulses are applied to the output terminals 10a, 10b in the manner illustrated in Fig. 2F and are supplied to the CPU of the microprocessor.
In the event that the control circuit of the microprocessor applies high level signals (1, 1) to both of the terminals lla and llb, the gate control circuit 15 is conditioned to apply a high level signal to the gate 9a, 9b and thus open the same. This results in the pulses appearing on the clock pulse output terminals 10a, 10b to assume the form shown in the latter half of Fig. 2F.
As both of these signals have been derived from the same basic signal la when the change occurs, as the trailing edges of the two signals are alinged at the moment of switching, no shift in signal timing can occur and disturb the operation of the microprocessor.
In the case that the reverse change is indu~ed and low speed clock pulses are changed to ; high speed ones, the le~els of the signals applied to terminals lla and llb are switched from 1, 1 to 0, 0.
At this time the gate 9a, 9b is rendered non-conductive while the gate 6a, 6b is op~ned. The results o~ this is shown in Fig. 2G. As will noted as the ~CPU is responsive to the clock ~pulses the above mentioned switching will be timed in accordance with ; 30 the currently supplied pulse train and thus, in this instance, will wait ~or a trailing edge of the low speed pulses before inducing the signal:level change which will induce the supply of~high speed pulses.
As before, as the trailing edges of pulses 2a and 5a are inherently aligned, upon the change the phasing ~ ~ of the two signals are perfectly matched ensuring ::: :
.
, error free CPU opera-tion.
In the case that a low speed external memory access cycle i.s to induced, a high level signal is applied from a memory address decoder (not shown) is applied -to -terminal 17. Prior to this time the program being run in the CPU controlled in accordance with the high speed pulses 2a. However, upon the application of the high level signal to terminal 17 gate circuit ~a, 6b is closed and gate circuit 9a, 9b rendered conductive. Under these circumstances the clock pulses supplied change in the manner illustrated in Fig. 2H and low speed clock pulses are then fed to the CPU.
The high level signal applied to terminal 17 is maintained for 1 memory cycle and is then automatically swi-tched to low level. This switching of course permits the resumption of the supply of high speed clock pulses to the CPU to permit appropriate processing.
In accordance with the above disclosed : arrangement,it is possible to selec-tively supply four different clock pulses simply by changing a two bit signal. Accordinyly, when the device is required to be operated on a low voltage source such as torch batteries or the like, it is possible to from the 2a pulses to the 5a ones. It is also possible to switch : to the low speed pulses in the event of a blackout without adverse effect on the operation of the processor. Fu~ther, the present invention permits ~: 30 low speed external memory access bus cycle control : with the same simple hardware.: Moreover, in the event that a system includes a high speed memory in : addition the above méntioned low speed type, the instant invention facilitates appropriate clock signal control without the need of additional circuitry and increases the system throughput.
It will be understood that the present invention is not limited to a the illustrated arrangement and that various changes and modifications can be made without departing from the scope of the instant invention is which limited only the appended claims.
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I
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;:: ' ~ ~ ' ., .: ~ ' - . ' .
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CLOCK PULSE GENERATOR FOR MICROCOMPUTER
BACKGF<OUND OF THE INVENTION
Field of -the Invention The present invention relates generally to a clock pulse generator for a microcomputer and more specifically to an improved arrangement for use with one chip type microcomputers.
Description of the Prior Art Normally silicon chip microprocessors including a central processing unit CPU, a read only memory ROM, a random access memory RAM and an output input interface I/O are formed on a single chip (one chip microcomputer) and are arranged to operated on a 5V power supply. However, of recent times a demand for a one chip microprocessor which an be operated on batteries has developed. This requires that the supply on which the device is operated be selectively reduced from 5V to 3V. This reduction induces a change in the generation of clock pulses which are ~sed in connection with the operation of the CPU.
When this change occurs however, improper operation is apt to occur.
Accordingly, it is required to be able to produce low speed clock pulses when this reduction in power occurs in a manner which renders it possible to maintain proper operation. It is additionally required to be able to provide low speed clock signals when the power supply is reduced for the ' purposes of conserving electrical power and/or in the event of a power blackout.
Moreover, it is desirable to be able to expand control over the reading and writing cycles when accessing an external low speed expansion memory.
In order to achieve the above it has been proposed to use two clock pulse generators - one for -: ' high speed pulse signals and one for low speed pulse signals. However, this arrangement i5 such that when one is in use the other is rendered redundant.
Further, when swi-tching from one to another, it often occurs that an asynchronism or misalignment occurs in the positional relationship between the pulses.
SUMMARY OF THE INVENTIOM
It i5 an object of the present invention to provide a clock pulse generator which features simple construction and cost and which enables the switching between high and lows speed pulses without undesirable interruption of CPU activity.
In brief, the above object is achieved by an arrangement wherein in order to permit a one-chip type microprocessor to be operated on two different power sources such as a household supply and batteries and in order to facilitate slow speed external memory access, the output of a single source of pulses is sequentially frequency divided and gate circuits arranged so that one oE the plurality of divisions can be selectively supplied to an output terminal of the device.
More specifically, a first aspect of the present invention comes the ~orm of a one chip microprocessor c.lock pulse generator which features:
a source of clock pulses: means for successively dividing the clock pulses by the same ratio and producing a plurality of clock pulse signals the pulse widths of which are different;~a plurality of gate circuits, the gate circuits being arranged to selectivel~ supply one of the clock pulse signals to an output terminal arrangement.
A second aspect of the invention comes in that the dividing means comprises: a plurality of frequency dividers, the frequency dividers being connected in manner wherein the first frequency :
. . . ~ `, .
- ; ' ` :, ;' ' .~,, divider is arranged to divide the pulses supplied from the source in a predetermined manner, the next frequency divider being arranged -to receive the output of the first frequency divider and perform essentially the same division.
A fur-ther aspect of the invention comes in that the above mentioned plurality of clock pulse signals are divided in a manner that one of the leading and trailing edges of the pulses occur coincidently and thus enable switching from one to ano-ther without phase difference occuring.
Another aspect of the invention comes in the form of a method of generating clock pulses in a microprocessor which features the steps of: using a single source to produced a basic clock pulse signal;
successively dividing the basic clock pulse signal to form a series of pulse signals~ each having successively longer pulse widths; selectively using one of the series of pulse signals in connection with the control of the processor.~
A yet further aspect of the invention comes in that the above mentioned method further features: arranging one of the leadirlg and trailing edges of the series of pulse signal to occur synchronously.
BRIEF DESCRIPTION OF THE DRAWINGS
The features and ~advantages inherent with the prasent inven~ion will become more clearly ' appreciated as the~ following description of the preferred embodiment is made with reference to the appended drawin~s in which:
Fig.l is a circuit diagram ~showing the construction of an embodiment of a clock pulse generator accordi.ng to the present invention; and Fig. 2 is~a timing chart which demonstrates the operational characteristics of the arrangement ;::
:
.
shown in Fig. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Fig. 1 shows a circuit arrangement which characterizes the present invention. This arrangement includes input terminals which are arranged to receive clock pulses from a liquid crystal type clock pulse generator tnot shown);
frequency dividers 2 - 5; gate circuits 6a, 6b, 7a, 7b, 8a, 8b and 9a, 9b; clock pulse output terminals 10a, 10b; gate control signal generator circuits 12 -15; designated signal input terminals lla, llb, 16a and 16b; and a discrimination signal input terminal 17 which is arranged to receive a signal from a memory address decoder, all connected as shown.
With this arrangement the first frequency divider 2 is arranged to perform a first division (1/2) and divide the inpu-t pulses la shown in Fig.
2A, in a manner to produce a pulse train 2a such as shown in Fig. 2B. The second pulse divider 3 is arranged to perform a second division ~ and produce a pulse train having a frequency 1/4 of the original one. Viz., produce a signal 3a of the nature shown in Fig. 2C.
The third and fourth frequency dividers are arranged to perform subsequent frequency divisions and produce signals 4a and Sa (see Figs.
2D, 2E) which respectively have frequencies which are 1/8 and 1/16 of the input signal la. As will be ' noted each of the clock pulses are arranged to be formed with a 90 phase difference.
The outputs of the frequency dividers 2 -5 are respectively supplied through the gate circuits 6a 9b to the clock signal output terminals 10a, 10b.
A two bit digital signal from the computer control circuit i9 suQplie~ to the designated input - .
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,, .
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terminals lla, llb. This signal functions to selectively control the gate circui-ts 6a - 9b. Viz., when both of the signals appearing on the terminals lla and llb, assume a low level "0" gate 6a, 6b is 5switched to assume an ON condition whereby the clock pulses 2a which have been (1/2) divided appear on the clock pulse output terminals 10a, 10b. When the levels on the -terminals lla and llb assume low and high levels ( 0, 1) respectively, ~ate circuit 7a, 7b 10is selectively conditioned to assume an ON state.
Under these conditions clock pulse train 3a is supplied to the clock pulse output terminals 10a, 10b.
In -the event that the signals appearing on 15terminals lla and llb assume levels 1 and 0, gate circuit 8a, 8b is opened and the clock pulses 4a are selectively appl~ied to terminals 10a, 10b. Finally, if the signals appearing on the terminals lla, llb both assume high levels (viz., 1, 1) then the last of 20the gate circuits is conditioned to open and apply the (1/16) divided pulse train 4a to terminals 10a, 10b.
When a ~two bit signal from an external memory is applied to the terminals 16a and 16b, a ~ 25similar control wherein the gate control circuits 12 `~ ~ to 15 selectively open the gates 6a - 9b is possible.
In the case that the ex-ternal memory is selected and a discrimination signal is applied to ' terminal 17 therefrom, the gate control circuits 12 30to 15 are selectively conditionable to open the gate circuits 6a to 9b.
When the above disclosed circuit ~; arrangement is put~into operation in a manner wherein th0 high speed clock pulses 2a are changed to those 35shown in Fig. 2E (viz., 5a), low level signals are applied to both the terminals lla and llb. This ~ . , .
~88~B
induces gate control circuit 12 to apply a high level signal (1) and condition gate 6a, 6b to assume an ON
state. Under these conditions high speed pulses are applied to the output terminals 10a, 10b in the manner illustrated in Fig. 2F and are supplied to the CPU of the microprocessor.
In the event that the control circuit of the microprocessor applies high level signals (1, 1) to both of the terminals lla and llb, the gate control circuit 15 is conditioned to apply a high level signal to the gate 9a, 9b and thus open the same. This results in the pulses appearing on the clock pulse output terminals 10a, 10b to assume the form shown in the latter half of Fig. 2F.
As both of these signals have been derived from the same basic signal la when the change occurs, as the trailing edges of the two signals are alinged at the moment of switching, no shift in signal timing can occur and disturb the operation of the microprocessor.
In the case that the reverse change is indu~ed and low speed clock pulses are changed to ; high speed ones, the le~els of the signals applied to terminals lla and llb are switched from 1, 1 to 0, 0.
At this time the gate 9a, 9b is rendered non-conductive while the gate 6a, 6b is op~ned. The results o~ this is shown in Fig. 2G. As will noted as the ~CPU is responsive to the clock ~pulses the above mentioned switching will be timed in accordance with ; 30 the currently supplied pulse train and thus, in this instance, will wait ~or a trailing edge of the low speed pulses before inducing the signal:level change which will induce the supply of~high speed pulses.
As before, as the trailing edges of pulses 2a and 5a are inherently aligned, upon the change the phasing ~ ~ of the two signals are perfectly matched ensuring ::: :
.
, error free CPU opera-tion.
In the case that a low speed external memory access cycle i.s to induced, a high level signal is applied from a memory address decoder (not shown) is applied -to -terminal 17. Prior to this time the program being run in the CPU controlled in accordance with the high speed pulses 2a. However, upon the application of the high level signal to terminal 17 gate circuit ~a, 6b is closed and gate circuit 9a, 9b rendered conductive. Under these circumstances the clock pulses supplied change in the manner illustrated in Fig. 2H and low speed clock pulses are then fed to the CPU.
The high level signal applied to terminal 17 is maintained for 1 memory cycle and is then automatically swi-tched to low level. This switching of course permits the resumption of the supply of high speed clock pulses to the CPU to permit appropriate processing.
In accordance with the above disclosed : arrangement,it is possible to selec-tively supply four different clock pulses simply by changing a two bit signal. Accordinyly, when the device is required to be operated on a low voltage source such as torch batteries or the like, it is possible to from the 2a pulses to the 5a ones. It is also possible to switch : to the low speed pulses in the event of a blackout without adverse effect on the operation of the processor. Fu~ther, the present invention permits ~: 30 low speed external memory access bus cycle control : with the same simple hardware.: Moreover, in the event that a system includes a high speed memory in : addition the above méntioned low speed type, the instant invention facilitates appropriate clock signal control without the need of additional circuitry and increases the system throughput.
It will be understood that the present invention is not limited to a the illustrated arrangement and that various changes and modifications can be made without departing from the scope of the instant invention is which limited only the appended claims.
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Claims (7)
1. A clock pulse generator for a one-chip microprocessor, comprising:
a single source of clock pulses;
means on said chip with said microprocessor for successively dividing said clock pulses a plurality of times and for producing a corresponding plurality of clock pulse signals each having a different respective pulse width, wherein one period of the slowest of said clock pulse signals is equal to a respective predetermined integer number of the periods of each of the faster clock pulse signals, each said period defining a respective cycle, and, for each pair of said clock pulse signals, a predetermined one of the leading and trailing edges of the clock pulse of the clock pulse signal having the longer period of said pair coincides with a predetermined one of the leading and trailing edges of a clock pulse of the clock pulse signal having the shorter period;
a plurality of gate circuits and means for controlling said gate circuits, on said chip, each said gate circuit being arranged to selectively supply a respective one of the clock pulse signals at a time, wherein a selected sequence of said periods of a plurality of said clock pulse signals can be provided; and an output terminal arrangement on said chip for outputting said selected sequence of periods of said clock pulse signals to said microprocessor.
a single source of clock pulses;
means on said chip with said microprocessor for successively dividing said clock pulses a plurality of times and for producing a corresponding plurality of clock pulse signals each having a different respective pulse width, wherein one period of the slowest of said clock pulse signals is equal to a respective predetermined integer number of the periods of each of the faster clock pulse signals, each said period defining a respective cycle, and, for each pair of said clock pulse signals, a predetermined one of the leading and trailing edges of the clock pulse of the clock pulse signal having the longer period of said pair coincides with a predetermined one of the leading and trailing edges of a clock pulse of the clock pulse signal having the shorter period;
a plurality of gate circuits and means for controlling said gate circuits, on said chip, each said gate circuit being arranged to selectively supply a respective one of the clock pulse signals at a time, wherein a selected sequence of said periods of a plurality of said clock pulse signals can be provided; and an output terminal arrangement on said chip for outputting said selected sequence of periods of said clock pulse signals to said microprocessor.
2. A clock pulse generator as claimed in claim 1 wherein said dividing means comprises:
a plurality of frequency dividers, said frequency dividers being connected in a manner wherein a first one of said frequency dividers is arranged to divide said clock pulses supplied from said clock source in a predetermined manner, and a next one of said frequency dividers after said first one being arranged to receive an output of said first frequency divider and to perform essentially the same division on said output of said first frequency divider as said first frequency divider performs on said clock pulses from said source.
a plurality of frequency dividers, said frequency dividers being connected in a manner wherein a first one of said frequency dividers is arranged to divide said clock pulses supplied from said clock source in a predetermined manner, and a next one of said frequency dividers after said first one being arranged to receive an output of said first frequency divider and to perform essentially the same division on said output of said first frequency divider as said first frequency divider performs on said clock pulses from said source.
3. A clock pulse generator as claimed in claim 1 wherein said plurality of clock pulse signals are divided in a manner that enables switching from one to another by said plurality of gate circuits without phase difference occurring between corresponding parts of said clock pulse signals, and each said selected sequence consists of a succession of full periods of the respective clock pulse signals.
4. A clock pulse generator as claimed in claim 1, further including:
first and second pairs of input terminals via each pair of which a respective two-bit control signal can be applied in a manner which permits selective control of said gate circuits; and a further input terminal and control means on said chip for determining which of said first and second pairs of input terminals are enabled for said selective control.
first and second pairs of input terminals via each pair of which a respective two-bit control signal can be applied in a manner which permits selective control of said gate circuits; and a further input terminal and control means on said chip for determining which of said first and second pairs of input terminals are enabled for said selective control.
5. A method of producing clock pulses for controlling a microprocessor on a single chip, comprising the steps of:
using a single source to produce a basic clock pulse signal which is provided to respective terminals on said chip;
successively dividing said basic clock pulse signal by means on said chip to form a series of pulse signals, each said pulse signal being constituted of pulses of a respective width, and said pulses having successively longer pulse width along said series;
selectively using different ones of said pulse signals in connection with the control of said microprocessor;
wherein each said pulse signal has a respective period and said selective use of said pulse signals of said different periods includes (1) use of a serial combination of plural periods of one of said pulse signals with a short period and at least one period of one of said pulse signals with a longer period, when said processor is operated in a normal mode and an access to a lower speed component is to be performed, and (2) use of one of said pulse signals with a longer period for operating said microprocessor at a lower speed in an energy conservation mode.
using a single source to produce a basic clock pulse signal which is provided to respective terminals on said chip;
successively dividing said basic clock pulse signal by means on said chip to form a series of pulse signals, each said pulse signal being constituted of pulses of a respective width, and said pulses having successively longer pulse width along said series;
selectively using different ones of said pulse signals in connection with the control of said microprocessor;
wherein each said pulse signal has a respective period and said selective use of said pulse signals of said different periods includes (1) use of a serial combination of plural periods of one of said pulse signals with a short period and at least one period of one of said pulse signals with a longer period, when said processor is operated in a normal mode and an access to a lower speed component is to be performed, and (2) use of one of said pulse signals with a longer period for operating said microprocessor at a lower speed in an energy conservation mode.
6. A method as claims in claim 5 further comprising the step of:
arranging, by said means on said chip for said dividing, for one of the leading and trailing edges of said pulses of each pair of said pulse signals to occur synchronously during the longer period of said periods of said pair of pulse signals.
arranging, by said means on said chip for said dividing, for one of the leading and trailing edges of said pulses of each pair of said pulse signals to occur synchronously during the longer period of said periods of said pair of pulse signals.
7. The clock pulse generator of claim 1, wherein said clock pulses are divided only by 2, 4, 8 and 16 to produce said respective clock pulse signals.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62-117508 | 1987-05-14 | ||
| JP62117508A JP2643146B2 (en) | 1987-05-14 | 1987-05-14 | Clock generation circuit of microcomputer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1288828C true CA1288828C (en) | 1991-09-10 |
Family
ID=14713494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000566629A Expired - Lifetime CA1288828C (en) | 1987-05-14 | 1988-05-12 | Clock pulse generator for microcomputer |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5167031A (en) |
| EP (1) | EP0291335B1 (en) |
| JP (1) | JP2643146B2 (en) |
| KR (1) | KR960003061B1 (en) |
| CA (1) | CA1288828C (en) |
| DE (1) | DE3850808T2 (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5636367A (en) * | 1991-02-27 | 1997-06-03 | Vlsi Technology, Inc. | N+0.5 wait state programmable DRAM controller |
| JP2745869B2 (en) * | 1991-07-11 | 1998-04-28 | 日本電気株式会社 | Variable clock divider |
| JPH05108195A (en) * | 1991-10-11 | 1993-04-30 | Toshiba Corp | Portable computer |
| US5254888A (en) * | 1992-03-27 | 1993-10-19 | Picopower Technology Inc. | Switchable clock circuit for microprocessors to thereby save power |
| US5734877A (en) * | 1992-09-09 | 1998-03-31 | Silicon Graphics, Inc. | Processor chip having on-chip circuitry for generating a programmable external clock signal and for controlling data patterns |
| US5752011A (en) | 1994-06-20 | 1998-05-12 | Thomas; C. Douglas | Method and system for controlling a processor's clock frequency in accordance with the processor's temperature |
| US5513152A (en) * | 1994-06-22 | 1996-04-30 | At&T Global Information Solutions Company | Circuit and method for determining the operating performance of an integrated circuit |
| US5586308A (en) * | 1994-10-19 | 1996-12-17 | Advanced Micro Devices, Inc. | Clock control unit responsive to a power management state for clocking multiple clocked circuits connected thereto |
| US5794021A (en) * | 1994-11-02 | 1998-08-11 | Advanced Micro Devices, Inc. | Variable frequency clock generation circuit using aperiodic patterns |
| US6272465B1 (en) | 1994-11-02 | 2001-08-07 | Legerity, Inc. | Monolithic PC audio circuit |
| US5524035A (en) * | 1995-08-10 | 1996-06-04 | International Business Machines Corporation | Symmetric clock system for a data processing system including dynamically switchable frequency divider |
| US5754867A (en) * | 1996-03-20 | 1998-05-19 | Vlsi Technology, Inc. | Method for optimizing performance versus power consumption using external/internal clock frequency ratios |
| JP3493096B2 (en) * | 1996-06-07 | 2004-02-03 | 株式会社東芝 | Semiconductor integrated circuit, IC card, and IC card system |
| US8086977B2 (en) * | 2006-08-18 | 2011-12-27 | International Business Machines Corporation | Design Structure for switching digital circuit clock net driver without losing clock pulses |
| US7752480B2 (en) * | 2006-08-18 | 2010-07-06 | International Business Machines Corporation | System and method for switching digital circuit clock net driver without losing clock pulses |
| JP5199392B2 (en) * | 2008-12-08 | 2013-05-15 | パナソニック株式会社 | System clock monitoring device and motor control system |
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| US3941989A (en) * | 1974-12-13 | 1976-03-02 | Mos Technology, Inc. | Reducing power consumption in calculators |
| US4059842A (en) * | 1975-10-31 | 1977-11-22 | Westinghouse Electric Corporation | Method and apparatus for synchronizing a digital divider chain with a low frequency pulse train |
| US4229699A (en) * | 1978-05-22 | 1980-10-21 | Data General Corporation | Multiple clock selection system |
| US4463440A (en) * | 1980-04-15 | 1984-07-31 | Sharp Kabushiki Kaisha | System clock generator in integrated circuit |
| JPS5775335A (en) * | 1980-10-27 | 1982-05-11 | Hitachi Ltd | Data processor |
| US4365203A (en) * | 1981-02-05 | 1982-12-21 | General Electric Company | Multi-frequency clock generator with error-free frequency switching |
| US4423383A (en) * | 1982-03-05 | 1983-12-27 | Ampex Corporation | Programmable multiple frequency ratio synchronous clock signal generator circuit and method |
| JPS6010318A (en) * | 1983-06-29 | 1985-01-19 | Sanyo Electric Co Ltd | Microcomputer |
| JPS6019222A (en) * | 1983-07-13 | 1985-01-31 | Nec Corp | Clock generating circuit |
| US4584698A (en) * | 1983-11-02 | 1986-04-22 | Motorola, Inc. | Sharable prescaled timer and method for a data processor |
| US4893271A (en) * | 1983-11-07 | 1990-01-09 | Motorola, Inc. | Synthesized clock microcomputer with power saving |
| US4819164A (en) * | 1983-12-12 | 1989-04-04 | Texas Instruments Incorporated | Variable frequency microprocessor clock generator |
| JPS60198618A (en) * | 1984-03-21 | 1985-10-08 | Oki Electric Ind Co Ltd | Dynamic logical circuit |
| JPS60263523A (en) * | 1984-06-08 | 1985-12-27 | Mitsubishi Electric Corp | Microprocessor |
| US4748417A (en) * | 1985-02-05 | 1988-05-31 | Siemens Aktiengesellschaft | Method and circuit arrangement for switching a clock-controlled device having a plurality of operating statuses |
| US4821229A (en) * | 1985-12-12 | 1989-04-11 | Zenith Electronics Corporation | Dual operating speed switchover arrangement for CPU |
| JPS62166419A (en) * | 1986-01-17 | 1987-07-22 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Multifrequency clock generator |
| US5086387A (en) * | 1986-01-17 | 1992-02-04 | International Business Machines Corporation | Multi-frequency clock generation with low state coincidence upon latching |
| GB8615399D0 (en) * | 1986-06-24 | 1986-07-30 | Int Computers Ltd | Switching circuit |
| JPS63131616A (en) * | 1986-11-20 | 1988-06-03 | Mitsubishi Electric Corp | Programmable clock frequency divider |
-
1987
- 1987-05-14 JP JP62117508A patent/JP2643146B2/en not_active Expired - Lifetime
-
1988
- 1988-04-29 KR KR1019880004894A patent/KR960003061B1/en not_active IP Right Cessation
- 1988-05-10 US US07/192,363 patent/US5167031A/en not_active Expired - Lifetime
- 1988-05-12 CA CA000566629A patent/CA1288828C/en not_active Expired - Lifetime
- 1988-05-13 EP EP88304367A patent/EP0291335B1/en not_active Expired - Lifetime
- 1988-05-13 DE DE3850808T patent/DE3850808T2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| KR960003061B1 (en) | 1996-03-04 |
| DE3850808D1 (en) | 1994-09-01 |
| DE3850808T2 (en) | 1995-01-19 |
| JPS63282511A (en) | 1988-11-18 |
| EP0291335B1 (en) | 1994-07-27 |
| US5167031A (en) | 1992-11-24 |
| KR880014446A (en) | 1988-12-23 |
| EP0291335A2 (en) | 1988-11-17 |
| EP0291335A3 (en) | 1989-10-18 |
| JP2643146B2 (en) | 1997-08-20 |
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Legal Events
| Date | Code | Title | Description |
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| MKEX | Expiry |