CA1297205C - Method and apparatus for making a flexible interconnect - Google Patents
Method and apparatus for making a flexible interconnectInfo
- Publication number
- CA1297205C CA1297205C CA000606222A CA606222A CA1297205C CA 1297205 C CA1297205 C CA 1297205C CA 000606222 A CA000606222 A CA 000606222A CA 606222 A CA606222 A CA 606222A CA 1297205 C CA1297205 C CA 1297205C
- Authority
- CA
- Canada
- Prior art keywords
- insulating material
- studs
- holes
- flexible
- electrically conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/50—Fixed connections
- H01R12/59—Fixed connections for flexible printed circuits, flat or ribbon cables or like structures
- H01R12/62—Fixed connections for flexible printed circuits, flat or ribbon cables or like structures connecting to rigid printed circuits or like structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/70—Coupling devices
- H01R12/71—Coupling devices for rigid printing circuits or like structures
- H01R12/712—Coupling devices for rigid printing circuits or like structures co-operating with the surface of the printed circuit or with a coupling device exclusively provided on the surface of the printed circuit
- H01R12/714—Coupling devices for rigid printing circuits or like structures co-operating with the surface of the printed circuit or with a coupling device exclusively provided on the surface of the printed circuit with contacts abutting directly the printed circuit; Button contacts therefore provided on the printed circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10378—Interposers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0338—Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0548—Masks
- H05K2203/0554—Metal used as mask for etching vias, e.g. by laser ablation
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/063—Lamination of preperforated insulating layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0726—Electroforming, i.e. electroplating on a metallic carrier thereby forming a self-supporting structure
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49204—Contact or terminal manufacturing
- Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
- Y10T29/49222—Contact or terminal manufacturing by assembling plural parts forming array of contacts or terminals
Abstract
METHOD AND APPARATUS FOR MAKING A FLEXIBLE INTERCONNECT
Abstract of the Disclosure A method and apparatus for making a flexible interconnect for connection between stacks of electronic components. The method includes forming a plurality of holes through a flexible insulating material, depositing electrically conductive metal studs into the holes extending out of at least one side and preferably both sides of the flexible material, and electrically interconnecting some of the electrically conductive metal studs by interconnects supported by the flexible material. The interconnects may be supported from the outside of the flexible material or embedded therein.
Dummy studs may be provided in the flexible material extending to the outside and aligned with studs extending on the other side of the insulating material which are connected to the electrical interconnects.
Abstract of the Disclosure A method and apparatus for making a flexible interconnect for connection between stacks of electronic components. The method includes forming a plurality of holes through a flexible insulating material, depositing electrically conductive metal studs into the holes extending out of at least one side and preferably both sides of the flexible material, and electrically interconnecting some of the electrically conductive metal studs by interconnects supported by the flexible material. The interconnects may be supported from the outside of the flexible material or embedded therein.
Dummy studs may be provided in the flexible material extending to the outside and aligned with studs extending on the other side of the insulating material which are connected to the electrical interconnects.
Description
~2~7~15 13 --l-23 3ackaround of the Invention 24 The present invention is directed to a flexible 25 electrical interccnne^t for connecti.on between adjacent 26 stacks of electro..ic components which may be arranged in 27 various configura,ions. Conductive metal studs embedded in the 28 insulating material extend out of both sides of the 29 insulating material for coacting with adjacent stacked electronic components such as electronic chips or carriers z~
1 for interconnecti~ he stacks. Routing between the 2 inlets and outlets of the electronic components is 3 provlded by elect--_ally interconnecting some of the studs 4 by interconnects s~pported either on the outside or embe~ded in the flexible material. Some of the studs may 6 be dummies which a-e not connected to any of the 7 electrical interccnnects, but which are aligned with studs 8 that are connected to the interconnects, for providing 3 physical support ~or the active studs for making good 1o electrical contacts with the electronic components.
12 Summarv 13 The presen~ invention is directed to a method and 14 apparatus for mak ng a flexible interconnect for connection between stacks of electronic components which includes forming a 16 plurality of holes through a flexible insulating material, 17 depositing electrically conductive metal studs into said holes 18 extending out of at least one side of the insulating material, 19 and electrically connecting at least some of the studs by interconnects supported by the flexible material.
21 Another ooject of the present invention is 22 wherein some of t~e electrically conductive metal studs may extend 23 out of both sides of the insulating material and in some embodiments 24 dummy studs may be provided on the flexible insulating 25 material on a side opposite and aligned with some of the 26 studs which are connected to the electrical interconnects.
27 Yet a fu-_her object of the present invention is 28 the method of maklng a flexible interconnect by forming a 29 plurality of holes through a flexible insulating material having a layer of conductive material on at least one 72~ 3_ 1 side, addina a ~esist mask layer on the conductive material 2 and depositing electrically conductive metal studs into 3 at least some c- said holes extending out of the top and bottom 4 of the holes an extending out of the insulating material and 5 conductive material. The method includes removing the 6 resist mask layer and applying an etch mask layer on the 7 conductive mate_ia~ over the conductive material to cover 8 desired electrl_al interconnections while leaving 9 undesired elect-i^al interconnections uncovered.
lo Thereafter, the undesired electrical interconnectlons are 11 etched and the etched mask is removed.
2 Still a urther object of the present invention 13 iS the method of making a flexible interconnect by 14 forming a plura'i-y of holes through a first flexible 15 insulating mate~i_1 having a layer of conductive material 16 on a first side a-.d depositing electrically conductive metal 17 studs into the ho:es. The method includes applying an etch 8 mask layer on the conductive material to cover desired 19 electrical inte-c-nnections while leaving undesired electrical interconnecticns uncovered and etching the undesirable 21 electrical interccnnections and removing the etched mask.
22 The method includes forming a plurality of holes through 23 a second flexible insulating material and bonding one side 24 of the second insulating material to the conductive 25 material. Therea ~er, the method includes applying a 26 resist mask on the second side of the second insulating 27 material and depositing electrically conductive metal studs into 28 ~he holes of the second insulating material.
29 Anot~.e- cbject of the present invention is 30 -lherein at least some of the holes in the first 97Z~5 1 insulating material are aligned with the holes in 2 the second insllating material. The method further 3 includes providing dummy studs on the outside of one of 4 the insulating materials aligned with studs on the other s side of the insulating materials.
6 A further object of the invention is wherein the 7 dummy studs are provided by applying a resist mask to the 8 insulating material leaving the desired locations of the 3 dummy stud bare and depositing a dummy stud into the 0 bare locations.
Other and further objects, features and 12 advantages will be apparent from the following description 13 of presently ~referred embodiments of the invention, given 14 for the purpose o- disclosure and taken in conjunction with the accompaniing drawings.
17 Brief_~escription of the Drawinqs 18 Fig. l is a schematic perspective view of one 19 form of the flexible interconnect and one coacting electronic component, 21 Fig. 2 is an enlarged elevational view, partly in 22 section, illustrating the use of the flexible interconnect 23 between two spaced electronic components, 24 Fig. 3 is a schematic perspective view of one form of the flexible interconnect of the present invention 26 illustrating providing electrical interconnects between 27 certain of the studs in the interconnect, 28 - Fig. 4 is an enlarged elevational view of the 29 flexible interconnect of the present invention illustrating interconnection between adjacent stacks of ~297~(~S -5-1 electronic components, 2 Fig. 5 is an elevational view illustrating the 3 use of the flexible interconnect of the present inven~ion ~ in another configuration of stacked electronic components, Fig. 6 is an enlarged fragmentary elevational 6 view, in cross section, of one form of the present 7 invention between adjacent stacks of electronic components, 8 Figs. 6A, 6B, 6C and 6D are fragmentary 3 elevational views illustrating the method of manufacturing o the flexible interconnect of Fig. 6, Fig. 7 is an enlarged elevational view, in cross 12 section, of another embodiment of the present invention in 13 position between two stacked electronic components, and Figs. 7A, 7B, 7C, 7D and 7E illustrate the method of manufacturing the embodiment of Fig. 7.
17 Descri~tion of the Preferred Embodiment 8 Referring now to the drawings, particularly to 19 Figs. 1 and 2, one form of the flexible interconnect of the present invention is generally indicated by the 21 reference numeral 10, to serve as an interconnection 22 between at least two stacked electronic components 12 and 23 14, such as electronic chips or chip carriers. The 2q electronic components 12 and 14 include a plurality of inlet or outlet pads 16 and 18, respectively, whlch are to 26 be interconnected with each other or other components.
27 The flexible interconnect 10 includes a plurality of 28 electrically conductive metal studs 20 which serve the purpose 29 of interconnecting the pads 16 and 18 to desired connections as well as providing an interconnect which will physically 2 ~ S ' -6-1 coact with the comporAents 12 and 14 to provide good electrical 2 contact.
3 The elec~~i-ally conductive metal that is used for the 4 studs is not limi~ed to elemental metal, and can include alloyed mixtures as well. Preferrably the studs are made of copper.
6 Referring now to Figs. 3 and 4, another 7 embodiment of the present invention is generally indicated 8 by the reference ~._meral lOa includes a plurality of electrically 9 conductive contac~ metal studs 20a having a plurality of electrical o interconnects 22 ~or interconnecting some of the conductive studs 20a. ~he p'acement of the interconnects 22 may be 12 as desired depend-'ng upon the requirements of the 13 electronic components 12a, 14a and 15a. Fig. 5 14 illustrates another configuration for stacking components 1S 12a and 14a with a different use of the flexible connector 16 lOa.
17 Referring to Fig. 6, the flexible interconnect 10 18 is shown in an enlarged cross-sectional view being 19 connected between electronic components 12 and 14 and 20 their respective 'nlet and outlet pads 16 and 18, 21 respectively, by electrically conductive metal studs 20 and 22 suitable interconr.ects such as X directed interconnects 24 23 and 26 and Y directed interconnects 28, 30, 32 and 34.
24 Preferably, the er.ds of the studs 20 are coated 25 with a low meltinc point liquid metal or fusible alloy 36 26 such as Woods metal, Darcy alloy, gallium tin or gallium 27 indium tin for ma~ing a good electrical contact between 28 the electrically conductive metal studs 20 and the pads 29 16 and 18.
Referring now to Figs. 6A-6D, the method of ~72~;7-1 making the flexib_e i?.terconnect pln of Fig. 6 is best 2 seen. A flexible _nsulating material 11, such as 3 polyimide or kapt^n is provided with one or .nore layers of 4 an electrical con_uc_or, such as copper, as a top layer 40 and a bottom laye- 42. By way of example only, the thickness 6 of the insulation 11 may be 1 to 5 mils and the thickness of 7 the copper layers 40 and 42 may be 1 ~o 2 mils. A resist 8 mask is provided over the layers 40 and 42 such as layers of reslst 3 mask 44 and 46. Any conventional resist mask may be used 0 such as novalak or a dry film resist.
plural ty of holes 48, for example 10-25 mils 2 in diameter, are -^ormed through the structure of Fig. 6A by such 3 means as punching, d-llling, laser drilling, spark erosion, etc.
As best seen in F g. 6B the holes 48 are filled by depositing an ele_trically conductive materlal therein, by such 16 methods as electroplating, electroless deposition, chemical vapor 17 deposition, laser assisted deposition, evaporation, or sputtering 18 to provide e]ectrica'ly conductive metal studs 20 which extend 19 outwardly of the electrically conductive layers 40 and 42 and the insulating ma_erial 11. The resist mask layers 44 and 21 46 are then strip?ed, by conventional means, leaving the 22 studs 20 and laye-s 40 and 42 exposed. Thereafter, an etch resist ~3 pattern, such as Shipley 1375 when copper layers are used, 24 is placed on the ayers 40 and 42 over the layers 40 and 42 and the studs 20 to c~ve- desired electrical connections such as the 26 electrical interconnections desired to form the X interconnections 27 24 and 26 and the Y -nterconnections 28, 30, 32 and 34. The 28 r-emainder of the :ayers 40 and 42 are left uncovered for removal.
29 Thus, referring to Fig. 6C an etch resist 52 is placed to cover the desired electrica interconnections and the bare portions of the 1297;~05 -8-1 layers 40 and 42 are etched away by any suitable etching 2 solution, such as sulfuric acid and hydrogen peroxide for copper 3 layers, thereby leaving the structure of Fig. 6D. It is to be 4 noted that this me~hod provides studs 20 embedded in a flexible insulating material 11 for coacting with the 6 pads 16 and 1~ of the electrical components 12 and 14 for 7 making good contact with the ability to be sandwiched 8 inbetween -the planar components 12 and 14 and pro~ide any 9 suitable manner of electrical connections required.
0 Obviously, any desired pattern of X and Y electrical 11 interconnects may be provided. And while the electrical 12 interconnects can be formed by masking the conductor layers 40 and 42 in the desired pattern and etched, the electrical interconnections may be patterned and formed along with the studs 20 by providing a resist mask directly on the flexible 16 insulating material 11 and depositing the interconnects 17 thereon such as by electroplating.
i8 In the embodiment of Fig. 6, the electrical 19 interconnections 24, 26, 28, 30, 32, and 34 are shown on the exterior of the flexible insulating material 11 and 21 are there~ore exposed and possibly subjected to 22 deterioration. Referring now to Fig. 7, another 23 embodiment of the present invention is shown in which the 24 electrical interconnects are formed embedded within the flexible insulating material and thus protected from such 26 corrosion.
27 In Fig. 7, the flexible interconnect 10b is shown 28 positioned between electrical components 12b and 14b and 29 generally includes a first flexible insulating material layer 60 and a second flexible insulating material 62, at 1 least one electrically conductive metal stud 20b extending 2 through the first and second insulating materials 60 and 62 3 ~or making contact between one set of contact pads 16b and 4 18b. In addition, the connection lOb may include one or s more studs 64 and 66 which only make connection between one 6 of the contact pads, such as one of pads 18b and 16b, 7 respectively, and the electrical interconnects, but ~hich 8 are backed up by dummy studs 68 and 70, respectively, for 9 making good contact between the active studs 64 and 66 and o their coating contacts.- Suitable X and Y interconnections are provided embedded between the insulating material 12 layers 60 and 62, such as Y directed interconnections 28b, 13 30b and 34b and X directed interconnection 24b.
14 Referring now to Figs. 7A-7E, the process of manufacturing the flexible interconnect lOb is best seen.
16 A first flexible insulating material 62 having a layer of 17 electrically conduc'~ive material 70, such as copper, 18 on a first side 72 is provided in which a plurality of holes 19 74 are formed. A suitable resist mask 76 is provided on the second side 78 of the flexible material 62, as best seen in Fig. 7B, 21 for depositing electrically conductive metal stud 66, the 22 dummy stud 68, and one-half of electrically conductive metal 23 stud 2Ob.
24 Referring now to Fig. 7C, an etch resist mask 80 is provided over the layer 70, to cover the desired 26 electrical interconnections while leaving the remainder of 27 the layer 70 bare for forming the desired X and Y
28 direction interconnections. The bare rnaterial is then 29 etched away by any desired process, such as ion milling or wet etchlng, and the etched mask is removed leaving the X
~2~9~2~S - 1 o -1 and Y directed electrical interconnections 28b, 30b, 24b 2 and 34b, as best seen in the lower half of Fig. 7D.
3 Thereafter, a plurality of holes 82 are formed in a 4 second flexible insulating material 60. The first insulating material 62 and second insulating material 60 6 are bonded together by bonding the side 84 of the second 7 insulating material 60 to the electrically conductive layer of 8 interconnects the-eby embedding the X and Y directed g interconnects the-ebetween.
1o As best seen in Fig. 7E, a resist mask 86 is 11 applied on the other side 89 of the second insulating 2 material 60 to fo-m a pattern for depositing the electrically 3 dummy metal stud ~0, electrically conductive metal stud 64 and 14 the remainder of electrically conductive metal stud 20b.
The resist mas~ is then removed forming the structure shown 16 in Fig. 7. The s~ructure of Fig. 7E may be 17 utilized, as best seen in Fig. 7, to provide a flexible 18 electrical interc~nnect lOb between electrical components 19 12b and 14b after coating the contacting surfaces of the electrically conductive metal stud with a suitable liquid ~1 metal 90.
22 If desired, other means of support besides the dummy 23 studs may be used assure a good electrical connection between 24 the conductive studs 64 and 66, and their respective contact pads 18b and 16b.
26 The present invention, therefore, is well adapted 27 to carry out the objects and attain the ends and 28 advantages mentioned as well as others inherent therein.
29 ~hile presently p-eferred embodiments of the invention have been given for the purpose of disclosure, numerous ~29~05 1 changes in the details of construction and arrangement of 2 parts will be readily apparent to those skilled in the art 3 and which are encompassed within the spirit of the 4 invention and the scope of the appended claims.
6 What is claimed is:
1 for interconnecti~ he stacks. Routing between the 2 inlets and outlets of the electronic components is 3 provlded by elect--_ally interconnecting some of the studs 4 by interconnects s~pported either on the outside or embe~ded in the flexible material. Some of the studs may 6 be dummies which a-e not connected to any of the 7 electrical interccnnects, but which are aligned with studs 8 that are connected to the interconnects, for providing 3 physical support ~or the active studs for making good 1o electrical contacts with the electronic components.
12 Summarv 13 The presen~ invention is directed to a method and 14 apparatus for mak ng a flexible interconnect for connection between stacks of electronic components which includes forming a 16 plurality of holes through a flexible insulating material, 17 depositing electrically conductive metal studs into said holes 18 extending out of at least one side of the insulating material, 19 and electrically connecting at least some of the studs by interconnects supported by the flexible material.
21 Another ooject of the present invention is 22 wherein some of t~e electrically conductive metal studs may extend 23 out of both sides of the insulating material and in some embodiments 24 dummy studs may be provided on the flexible insulating 25 material on a side opposite and aligned with some of the 26 studs which are connected to the electrical interconnects.
27 Yet a fu-_her object of the present invention is 28 the method of maklng a flexible interconnect by forming a 29 plurality of holes through a flexible insulating material having a layer of conductive material on at least one 72~ 3_ 1 side, addina a ~esist mask layer on the conductive material 2 and depositing electrically conductive metal studs into 3 at least some c- said holes extending out of the top and bottom 4 of the holes an extending out of the insulating material and 5 conductive material. The method includes removing the 6 resist mask layer and applying an etch mask layer on the 7 conductive mate_ia~ over the conductive material to cover 8 desired electrl_al interconnections while leaving 9 undesired elect-i^al interconnections uncovered.
lo Thereafter, the undesired electrical interconnectlons are 11 etched and the etched mask is removed.
2 Still a urther object of the present invention 13 iS the method of making a flexible interconnect by 14 forming a plura'i-y of holes through a first flexible 15 insulating mate~i_1 having a layer of conductive material 16 on a first side a-.d depositing electrically conductive metal 17 studs into the ho:es. The method includes applying an etch 8 mask layer on the conductive material to cover desired 19 electrical inte-c-nnections while leaving undesired electrical interconnecticns uncovered and etching the undesirable 21 electrical interccnnections and removing the etched mask.
22 The method includes forming a plurality of holes through 23 a second flexible insulating material and bonding one side 24 of the second insulating material to the conductive 25 material. Therea ~er, the method includes applying a 26 resist mask on the second side of the second insulating 27 material and depositing electrically conductive metal studs into 28 ~he holes of the second insulating material.
29 Anot~.e- cbject of the present invention is 30 -lherein at least some of the holes in the first 97Z~5 1 insulating material are aligned with the holes in 2 the second insllating material. The method further 3 includes providing dummy studs on the outside of one of 4 the insulating materials aligned with studs on the other s side of the insulating materials.
6 A further object of the invention is wherein the 7 dummy studs are provided by applying a resist mask to the 8 insulating material leaving the desired locations of the 3 dummy stud bare and depositing a dummy stud into the 0 bare locations.
Other and further objects, features and 12 advantages will be apparent from the following description 13 of presently ~referred embodiments of the invention, given 14 for the purpose o- disclosure and taken in conjunction with the accompaniing drawings.
17 Brief_~escription of the Drawinqs 18 Fig. l is a schematic perspective view of one 19 form of the flexible interconnect and one coacting electronic component, 21 Fig. 2 is an enlarged elevational view, partly in 22 section, illustrating the use of the flexible interconnect 23 between two spaced electronic components, 24 Fig. 3 is a schematic perspective view of one form of the flexible interconnect of the present invention 26 illustrating providing electrical interconnects between 27 certain of the studs in the interconnect, 28 - Fig. 4 is an enlarged elevational view of the 29 flexible interconnect of the present invention illustrating interconnection between adjacent stacks of ~297~(~S -5-1 electronic components, 2 Fig. 5 is an elevational view illustrating the 3 use of the flexible interconnect of the present inven~ion ~ in another configuration of stacked electronic components, Fig. 6 is an enlarged fragmentary elevational 6 view, in cross section, of one form of the present 7 invention between adjacent stacks of electronic components, 8 Figs. 6A, 6B, 6C and 6D are fragmentary 3 elevational views illustrating the method of manufacturing o the flexible interconnect of Fig. 6, Fig. 7 is an enlarged elevational view, in cross 12 section, of another embodiment of the present invention in 13 position between two stacked electronic components, and Figs. 7A, 7B, 7C, 7D and 7E illustrate the method of manufacturing the embodiment of Fig. 7.
17 Descri~tion of the Preferred Embodiment 8 Referring now to the drawings, particularly to 19 Figs. 1 and 2, one form of the flexible interconnect of the present invention is generally indicated by the 21 reference numeral 10, to serve as an interconnection 22 between at least two stacked electronic components 12 and 23 14, such as electronic chips or chip carriers. The 2q electronic components 12 and 14 include a plurality of inlet or outlet pads 16 and 18, respectively, whlch are to 26 be interconnected with each other or other components.
27 The flexible interconnect 10 includes a plurality of 28 electrically conductive metal studs 20 which serve the purpose 29 of interconnecting the pads 16 and 18 to desired connections as well as providing an interconnect which will physically 2 ~ S ' -6-1 coact with the comporAents 12 and 14 to provide good electrical 2 contact.
3 The elec~~i-ally conductive metal that is used for the 4 studs is not limi~ed to elemental metal, and can include alloyed mixtures as well. Preferrably the studs are made of copper.
6 Referring now to Figs. 3 and 4, another 7 embodiment of the present invention is generally indicated 8 by the reference ~._meral lOa includes a plurality of electrically 9 conductive contac~ metal studs 20a having a plurality of electrical o interconnects 22 ~or interconnecting some of the conductive studs 20a. ~he p'acement of the interconnects 22 may be 12 as desired depend-'ng upon the requirements of the 13 electronic components 12a, 14a and 15a. Fig. 5 14 illustrates another configuration for stacking components 1S 12a and 14a with a different use of the flexible connector 16 lOa.
17 Referring to Fig. 6, the flexible interconnect 10 18 is shown in an enlarged cross-sectional view being 19 connected between electronic components 12 and 14 and 20 their respective 'nlet and outlet pads 16 and 18, 21 respectively, by electrically conductive metal studs 20 and 22 suitable interconr.ects such as X directed interconnects 24 23 and 26 and Y directed interconnects 28, 30, 32 and 34.
24 Preferably, the er.ds of the studs 20 are coated 25 with a low meltinc point liquid metal or fusible alloy 36 26 such as Woods metal, Darcy alloy, gallium tin or gallium 27 indium tin for ma~ing a good electrical contact between 28 the electrically conductive metal studs 20 and the pads 29 16 and 18.
Referring now to Figs. 6A-6D, the method of ~72~;7-1 making the flexib_e i?.terconnect pln of Fig. 6 is best 2 seen. A flexible _nsulating material 11, such as 3 polyimide or kapt^n is provided with one or .nore layers of 4 an electrical con_uc_or, such as copper, as a top layer 40 and a bottom laye- 42. By way of example only, the thickness 6 of the insulation 11 may be 1 to 5 mils and the thickness of 7 the copper layers 40 and 42 may be 1 ~o 2 mils. A resist 8 mask is provided over the layers 40 and 42 such as layers of reslst 3 mask 44 and 46. Any conventional resist mask may be used 0 such as novalak or a dry film resist.
plural ty of holes 48, for example 10-25 mils 2 in diameter, are -^ormed through the structure of Fig. 6A by such 3 means as punching, d-llling, laser drilling, spark erosion, etc.
As best seen in F g. 6B the holes 48 are filled by depositing an ele_trically conductive materlal therein, by such 16 methods as electroplating, electroless deposition, chemical vapor 17 deposition, laser assisted deposition, evaporation, or sputtering 18 to provide e]ectrica'ly conductive metal studs 20 which extend 19 outwardly of the electrically conductive layers 40 and 42 and the insulating ma_erial 11. The resist mask layers 44 and 21 46 are then strip?ed, by conventional means, leaving the 22 studs 20 and laye-s 40 and 42 exposed. Thereafter, an etch resist ~3 pattern, such as Shipley 1375 when copper layers are used, 24 is placed on the ayers 40 and 42 over the layers 40 and 42 and the studs 20 to c~ve- desired electrical connections such as the 26 electrical interconnections desired to form the X interconnections 27 24 and 26 and the Y -nterconnections 28, 30, 32 and 34. The 28 r-emainder of the :ayers 40 and 42 are left uncovered for removal.
29 Thus, referring to Fig. 6C an etch resist 52 is placed to cover the desired electrica interconnections and the bare portions of the 1297;~05 -8-1 layers 40 and 42 are etched away by any suitable etching 2 solution, such as sulfuric acid and hydrogen peroxide for copper 3 layers, thereby leaving the structure of Fig. 6D. It is to be 4 noted that this me~hod provides studs 20 embedded in a flexible insulating material 11 for coacting with the 6 pads 16 and 1~ of the electrical components 12 and 14 for 7 making good contact with the ability to be sandwiched 8 inbetween -the planar components 12 and 14 and pro~ide any 9 suitable manner of electrical connections required.
0 Obviously, any desired pattern of X and Y electrical 11 interconnects may be provided. And while the electrical 12 interconnects can be formed by masking the conductor layers 40 and 42 in the desired pattern and etched, the electrical interconnections may be patterned and formed along with the studs 20 by providing a resist mask directly on the flexible 16 insulating material 11 and depositing the interconnects 17 thereon such as by electroplating.
i8 In the embodiment of Fig. 6, the electrical 19 interconnections 24, 26, 28, 30, 32, and 34 are shown on the exterior of the flexible insulating material 11 and 21 are there~ore exposed and possibly subjected to 22 deterioration. Referring now to Fig. 7, another 23 embodiment of the present invention is shown in which the 24 electrical interconnects are formed embedded within the flexible insulating material and thus protected from such 26 corrosion.
27 In Fig. 7, the flexible interconnect 10b is shown 28 positioned between electrical components 12b and 14b and 29 generally includes a first flexible insulating material layer 60 and a second flexible insulating material 62, at 1 least one electrically conductive metal stud 20b extending 2 through the first and second insulating materials 60 and 62 3 ~or making contact between one set of contact pads 16b and 4 18b. In addition, the connection lOb may include one or s more studs 64 and 66 which only make connection between one 6 of the contact pads, such as one of pads 18b and 16b, 7 respectively, and the electrical interconnects, but ~hich 8 are backed up by dummy studs 68 and 70, respectively, for 9 making good contact between the active studs 64 and 66 and o their coating contacts.- Suitable X and Y interconnections are provided embedded between the insulating material 12 layers 60 and 62, such as Y directed interconnections 28b, 13 30b and 34b and X directed interconnection 24b.
14 Referring now to Figs. 7A-7E, the process of manufacturing the flexible interconnect lOb is best seen.
16 A first flexible insulating material 62 having a layer of 17 electrically conduc'~ive material 70, such as copper, 18 on a first side 72 is provided in which a plurality of holes 19 74 are formed. A suitable resist mask 76 is provided on the second side 78 of the flexible material 62, as best seen in Fig. 7B, 21 for depositing electrically conductive metal stud 66, the 22 dummy stud 68, and one-half of electrically conductive metal 23 stud 2Ob.
24 Referring now to Fig. 7C, an etch resist mask 80 is provided over the layer 70, to cover the desired 26 electrical interconnections while leaving the remainder of 27 the layer 70 bare for forming the desired X and Y
28 direction interconnections. The bare rnaterial is then 29 etched away by any desired process, such as ion milling or wet etchlng, and the etched mask is removed leaving the X
~2~9~2~S - 1 o -1 and Y directed electrical interconnections 28b, 30b, 24b 2 and 34b, as best seen in the lower half of Fig. 7D.
3 Thereafter, a plurality of holes 82 are formed in a 4 second flexible insulating material 60. The first insulating material 62 and second insulating material 60 6 are bonded together by bonding the side 84 of the second 7 insulating material 60 to the electrically conductive layer of 8 interconnects the-eby embedding the X and Y directed g interconnects the-ebetween.
1o As best seen in Fig. 7E, a resist mask 86 is 11 applied on the other side 89 of the second insulating 2 material 60 to fo-m a pattern for depositing the electrically 3 dummy metal stud ~0, electrically conductive metal stud 64 and 14 the remainder of electrically conductive metal stud 20b.
The resist mas~ is then removed forming the structure shown 16 in Fig. 7. The s~ructure of Fig. 7E may be 17 utilized, as best seen in Fig. 7, to provide a flexible 18 electrical interc~nnect lOb between electrical components 19 12b and 14b after coating the contacting surfaces of the electrically conductive metal stud with a suitable liquid ~1 metal 90.
22 If desired, other means of support besides the dummy 23 studs may be used assure a good electrical connection between 24 the conductive studs 64 and 66, and their respective contact pads 18b and 16b.
26 The present invention, therefore, is well adapted 27 to carry out the objects and attain the ends and 28 advantages mentioned as well as others inherent therein.
29 ~hile presently p-eferred embodiments of the invention have been given for the purpose of disclosure, numerous ~29~05 1 changes in the details of construction and arrangement of 2 parts will be readily apparent to those skilled in the art 3 and which are encompassed within the spirit of the 4 invention and the scope of the appended claims.
6 What is claimed is:
Claims (18)
1. A method of making a flexible interconnect for connection between stacks of electronic components comprising, forming a plurality of holes through a flexible insulating material, depositing electrically conductive metal studs into said holes extending out of the top and bottom of the insulating material, and electrically interconnecting at least some of the deposited studs by interconnects supported by the flexible material.
2. The method of claim 1 wherein at least some of the interconnects are non-parallel.
3. A method of making a flexible interconnect for connection between stacks of electronic components comprising, forming a plurality of holes through a flexible insulating material having a layer of electrically conductive material on at least one side, adding a resist mask layer on the conductive material, depositing electrically conductive metal studs into at least some of said holes extending out of the top and bottom of the holes beyond the insulating material and conductive material, removing the resist mask layer, applying an etch mask layer on the conductive material over the conductive material to cover desired electrical interconnections while leaving undesired electrical interconnections uncovered, etching the undesired electrical interconnections, and removing the etch mask.
4. The method of claim 3 wherein at least some of the interconnects are non-parallel.
5. A method of making a flexible interconnect for connection between stacks of electronic components comprising, forming a plurality of holes through a first flexible insulating material having a layer of electrically conductive material on a first side, depositing electrically conductive metal studs into said holes, applying an etch mask layer on the conductive material to cover desired electrical interconnections while leaving undesired electrical interconnections uncovered, etching the undesired electrical interconnections, removing the etch mask, forming a plurality of holes through a second flexible insulating material, bonding one side of the second insulating material to the electrically conductive material, applying a resist mask on the second side of the second insulating material, and depositing electrically conductive metal studs into the holes of the second insulating material.
6. The method of claim 5 wherein at least some of the holes in the first insulating material are aligned with the holes in the second insulating material.
7. The method of claim S including providing dummy studs on the outside of one of the insulating materials aligned with studs on the other of the insulating materials.
8. The method of claim 7 wherein the dummy studs are provided by applying a resist mask to the insulating material leaving the desired locations of the dummy studs bare, and depositing dummy studs into the bare locations.
9. A method of making a flexible interconnect for connection between stacks of electronic components comprising, forming a plurality of holes through a first flexible insulating material having a layer of electrically conductive material on a first side, depositing electrically conductive metal studs into said holes, applying an etch mask layer on the conductive material to cover desired electrical interconnections, wherein at least some of the interconnections are non-parallel, while leaving undesired electrical interconnections uncovered, etching the undesired electrical interconnections, removing the etch mask, forming a plurality of holes through a second flexible insulating material, bonding one side of the second insulating material to the electrically conductive material, applying a resist mask on the second side of the second insulating material, and depositing electrically conductive metal studs into the holes of the second insulating material.
10. The method of claim 9 wherein at least some of the holes in the first insulating material are aligned with the holes in the second insulating material.
11. The method of claim 9 including providing dummy studs on the outside of one of the insulating materials aligned with studs on the other of the insulating materials.
12. The method of claim 11 wherein the dummy studs are provided by applying a resist mask to the insulating material leaving the desired location of the dummy stud bare, and depositing a dummy stud into the bare location.
13. A method of making a flexible interconnect for connection between stacks of electronic components comprising, forming a plurality of holes through a flexible insulating material having first and second sides, depositing electrically conductive metal studs into said holes extending out of at least one side of the insulating material, electrically interconnecting at least some of the studs by interconnects supported by the flexible material, and providing dummy studs on the second side of the flexible insulating material aligned with some of the electrically conductive metal studs.
14. The method of claim 13 wherein at least some of the interconnects are non-parallel.
15. A flexible interconnect for connection between stacks of electronic components comprising, a flexible insulating material having a plurality of holes electrically conductive metal studs deposited in said holes extending out of the top and bottom of the insulating material, and electrical interconnects between at least some of the studs by interconnects supported by the flexible material.
16 The interconnect of claim 15 wherein at least some of the interconnects are non-parallel.
17. A flexible interconnect for connection between stacks of electronic components comprising, flexible insulating material having first and second sides having a plurality of holes, electrically conductive metal studs deposited in said holes extending out of at least one side of the insulating material, electrical interconnects between at least some of the electrically conductive studs by interconnects supported by the flexible material, and dummy studs on the second side of the flexible insulating material aligned with some of the electrically conductive studs.
18. The interconnect of claim 17 wherein at least some of the interconnects are non-parallel.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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US07/222,487 US4862588A (en) | 1988-07-21 | 1988-07-21 | Method of making a flexible interconnect |
US07/222,487 | 1988-07-21 | ||
US07/369,596 | 1989-06-16 | ||
US07/369,596 US4991290A (en) | 1988-07-21 | 1989-06-16 | Flexible electrical interconnect and method of making |
Publications (1)
Publication Number | Publication Date |
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CA1297205C true CA1297205C (en) | 1992-03-10 |
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ID=26916845
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA000606222A Expired - Fee Related CA1297205C (en) | 1988-07-21 | 1989-07-20 | Method and apparatus for making a flexible interconnect |
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US (1) | US4991290A (en) |
EP (1) | EP0351851A3 (en) |
JP (1) | JPH0279380A (en) |
CA (1) | CA1297205C (en) |
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-
1989
- 1989-06-16 US US07/369,596 patent/US4991290A/en not_active Expired - Lifetime
- 1989-07-20 EP EP19890113348 patent/EP0351851A3/en not_active Withdrawn
- 1989-07-20 CA CA000606222A patent/CA1297205C/en not_active Expired - Fee Related
- 1989-07-21 JP JP1190423A patent/JPH0279380A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
JPH0279380A (en) | 1990-03-19 |
US4991290A (en) | 1991-02-12 |
EP0351851A3 (en) | 1991-11-06 |
EP0351851A2 (en) | 1990-01-24 |
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