CA1298673C - Pseudo-status signal generator - Google Patents
Pseudo-status signal generatorInfo
- Publication number
- CA1298673C CA1298673C CA000537403A CA537403A CA1298673C CA 1298673 C CA1298673 C CA 1298673C CA 000537403 A CA000537403 A CA 000537403A CA 537403 A CA537403 A CA 537403A CA 1298673 C CA1298673 C CA 1298673C
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- CA
- Canada
- Prior art keywords
- circuit
- safety
- message
- tape
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
Abstract
ABSTRACT OF THE DISCLOSURE
In a pseudo-status signal generator interposed between a main device in which a ready state is always maintained and an input/output requesting device adapted to produce a predetermined input/output request to the main device characterized to alternatively repetitively produce a status signal representing a ready state and a status signal representing a busy state to the input/output requesting device whenever a status request is output from the input/output requesting device, thereby alternatively repetitively producing the status signal representing the ready state and the status signal representing the busy state to the input/output requesting device whenever the status request is output from the input/output requesting device, i.e., repeating the busy or ready for the status request of this time when the ready or busy is repeated to the previous status
In a pseudo-status signal generator interposed between a main device in which a ready state is always maintained and an input/output requesting device adapted to produce a predetermined input/output request to the main device characterized to alternatively repetitively produce a status signal representing a ready state and a status signal representing a busy state to the input/output requesting device whenever a status request is output from the input/output requesting device, thereby alternatively repetitively producing the status signal representing the ready state and the status signal representing the busy state to the input/output requesting device whenever the status request is output from the input/output requesting device, i.e., repeating the busy or ready for the status request of this time when the ready or busy is repeated to the previous status
Description
6~3 This invention relates to a pseudo-status signal gener-ator such as, for example, a pseudo-status signal generator for an electronic circuit like CRT device in which data input and output are always enabled.
The present invention will be illustrated by way of the accompanying drawings, in which:-Fig. 1 is a block diagram showing a general arrangement of a prior art example;
Fig. 2 is a flowchart of an algorithm used generallyfor data input/output request;
Fig. 3 is a block diagram showing a general arrangement of an embodiment of a pseudo-status signal generator according to this invention;
Fig. 4 is a detailed diagram of a main device where the main device is a CRT device;
Fig. 5 is a timechart of the synchronous signal; and Fig. 6 is a detailed block diagram of the main device lA in Fig. 1.
Fig. 1 is a block diagram showing the general arrange-ment of a prior-art example. In Fig. 1, numeral 1 denotes a main device such as a CRT device, and numeral 2 denotes an input/
output requesting device like an input/output controller. The main device 1 and the input/output requesting device 2 are con-nected to each other through a data bus 3. The data bus 3 includes an input request signal line 3A for transmitting a data input request to the main device 1 by the input/outpu-t requesting device 2, an output request signal line 3B for transmitting a data output request, a status request signal line 3C for request-. ~
36~3 ing status information such as "busy~' or "ready", and a data sig-nal line 3D for transmitting predetermined data. The main device 1 further contains a status signal generator (not shown) for indicating the actual status to an external device.
The operation of the prior-art example will be des-cribed. The input/output requesting device 2 applies a prede-termined request through the input request signal line 3A, the output request signal line 3B and the status request signal line 3C in the data ~us 3 to the main device 1, and inputs or outputs the data from or to the main device 1 in response to the - la 7~3 application o, the request to the main device 1. The input/output requesting device 2 must complete the input or output operation of the predetermined data within a period that the main device 1 is ready, i.e., within a period that the input or output operation is enabledO Thus, the inpu-t/output requesting device 2 generates a predetermined status request to thereby read corresponding status information from the main device 1 side and inputs or outputs the predetermined data after confirming that the main device 1 has entered the ready period.
However, according to this method, there is a possibility that the main device 1 might enter a busy period, i.e., within a period where the data input or output operation is disabled while inputting or outputting data. From this, the input requesting device 2 needs to input or output the data synchronously with the start of the ready period of the main device 1 according to an algorithm represented in Fig. 2. Fig. 2 shows a flowchart of an algorithm used generally to request the input or output of data.
The abovementioned CRT device is considered here to be a representative example of the main device 1. In this CRT
device, the ready period is a blanking period corresponding to a period where data to be displayed can be input and output, and the busy period is a displaying period corresponding, for example, to a period where the input data is displayed on the CRT
device. The length of the busy period is generally set larger than that of the ready period, and when the data is input or output by fully utilizing the ready period, the data to be displayed within the busy period is reliably supplied to the CRT
device. However, if the data input or output is, for example, started from the vicinity of the end of the ready period, the period will have shifted to the busy period before the input or output operation has finished, and a certain noise is thus displayed on the screen of the CRT device.
The flowchart in Fig. 2 shows an example of an algorithm devised to eliminate the abovementioned drawback. If an I/O request is output in step S31, a status signal of the main device l is input in step S32, and it is determined whether the main device 1 has entered a ready period or not in step S33. If NO is determined in step S33, the operation is shifted to following step S34. If YES is determined in step S33j the operation is returned to step S32. The status signal of the main device 1 is input in step S34, and whether the main device l has entered a busy period or not is determined in step S35. If YES
is determined in step S35, the operation is returned to step S34, but iE NO is determined in step S35, the operation is shifted to step S36. After the predetermined data is input or output, the operation is ended in step S37.
The data input to or output from the main device l is s-tarted from the vicinity of the starting point of the ready period according to the algorithm represented in Fig. 2. In other words, the data input/output is started substantially synchronously with the starting point of the ready period of the main device 1.
The main device in the abovementioned prior-art example is constructed so that ready periods and busy periods are taken 6~3 at a certain repetitive ratio, and there is a drawback that, when the data input/output is not completed within the ready period, a noise is generated in the busy period. Even if a main device is prepared in which data input/output is always enabled, its func-tion cannot be utilized unless the algorithm in Fig. 2 is modi-fied. Therefore, another drawback arises in which data input/
output speed cannot be improved.
The present invention eliminates such drawbacks, and provides a pseudo-status signal generator which improves data input/output speed without adding particular modifications to the input/output requesting device.
According to the present invention therefore there is provided a pseudo-status signal generator interposed between a main device in which a ready state is always maintained and an input/output requesting device adapted to produce a predetermined input/output request to said main device characterized in that said pseudo-status signal generator alternatively repetitively produces a status signal representing a ready state and a status signal representing a busy state to said input/output requesting device whenever a status request is output from said input/output requesting device.
Re~erring once more to the accompanying drawings. Fig.
3 is a block diagram of a general arrangement of an embodiment of a pseudo-status signal generator according to '73 this invention. In Fig. 3, symbol lA denotes a main device in which input/output is always enabled, numeral 2 denotes an input/output requesting device, and numeral 4 denotes a pseudo-status signal generator for pseuod-generating status inEormation of the main device lA. The main device lA, the input/output requesting device 2 and the pseudo-status signal generator 4 are connected to each other through a data bus 3. An input request signal line 3A and an output request signal line 3~
of the data bus 3 connect the main device 1~ and the input/output requesting device 2 to each other, and a status request signal line 3C connects the pseudo-status signal generator 4 and the input/output requesting device 2 to each other. ~ data signal line 3D is connected among the main device lA, the pseudo-status signal generator 4 and the input/output requesting device 4 each other. In this embodiment, the pseudo-status signal generator 4 alternatively generates status information of ready and status information of busy when status information is requested from the input/output requesting device 2. In other words, if the status information of ready is output at a certain time, the status information of busy is output to the request of the subsequent status information.
Here, the operation of the embodiment described above will be described. When the input/output requesting device 2 operates to input or output data to or from the main device lA, the input/output requesting device 2 requests the status information to t~e pseudo-status signal generator 4 through the status request signal line 3C, and receives -the status information as the response through the data signal line 3D. If the status of busy is output in case of the immediately previous status request, the status information of ready is output in the subsequent status request. Therefore, the operation does not enter into the loop in the flowchart of Fig. 2, and the data input or output operation is accelerated by that amount.
In the embodiment described above, the pseudo-status signal generator 4~ is provided as an independent piece of hard-ware. However, this invention is not limited to this particularembodiment. For example, the pseudo-status signal generator may be associated in the main device lA or the input/output request-ing device 2 if functional independence is maintained, thereby performing similar advantages as those of the above-mentioned embodiment.
Fig. 4 is a detailed diagram of a main device where the main device is a CRT device. In Fig. 4, a synchronous signal generator (5) generates a synchronous signal of a CRT (7), and a memory (6) stores data to be displayed by the CRT (7). When a write signal is valid~ the data is written into the memory (6), and when the write signal is other than valid, the data stored in the memory (6) is read out. The CRT (7) displays the data read out of the memory (6). When an output request signal ( 3B ) is valid, a buffer (8) transfers the data on a data signal line ( 3D) to the memory (6). When an input request signal (3A) is valid, a buffer (9) transfers the data in the memory (6) to the data sig-nal line (3D). When a status request signal ~ 3C) is valid, a buffer (10) transfers the synchronous signal as a status signal to the data signal line ~ 3D) .
When both the input request signal ~3A) and the output request signal (3B) are invalid, the data to be displayed is read out of the memory ~6) and displayed by the CRT ~7). Then, when 3S the input request signal ~3A) becomes valid, the data requested to be input is read out of the memory ~6) instead of the memory .
, to be displayed, and therefore, the display of the CRT (7) becomes disturbedO However, since -the CRT (7) is provided with a period of non-display (non-displaying period), the CRT (7) is not disturbed even if the input request signal (3A) becomes valid during this period. This non-displaying period can be discerned from the synchronous signal read out as the status signal. ~ur-ing this non-displaying period, input/output operation becomes operable.
Fig. 5 is a timechart of the synchronous signal. A
memory (2A) is formed, for example, as a 2~port type RAM, and the read/write operation of the data to the memory is operable inde-pendently from the data to be displayed. Therefore, the display of the CRT is not disturbed even if the read/write operation is carried out during the display to be displayed.
As described above, the pseudo-status signal generated according to this invention is interposed between the main device in which the ready state is always set and the input/output requesting device for producing the predetermined input/output request to the main device and alternatively repeats the status signal representing the ready state and the status signal repre-senting the busy state to the input/output requesting device whenever the status request signal is output from the input/ out-put requesting device. Therefore, the data input/output opera-tion can be accelerated without the need for any particular modi-fication in the input/output requesting device.
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The present invention will be illustrated by way of the accompanying drawings, in which:-Fig. 1 is a block diagram showing a general arrangement of a prior art example;
Fig. 2 is a flowchart of an algorithm used generallyfor data input/output request;
Fig. 3 is a block diagram showing a general arrangement of an embodiment of a pseudo-status signal generator according to this invention;
Fig. 4 is a detailed diagram of a main device where the main device is a CRT device;
Fig. 5 is a timechart of the synchronous signal; and Fig. 6 is a detailed block diagram of the main device lA in Fig. 1.
Fig. 1 is a block diagram showing the general arrange-ment of a prior-art example. In Fig. 1, numeral 1 denotes a main device such as a CRT device, and numeral 2 denotes an input/
output requesting device like an input/output controller. The main device 1 and the input/output requesting device 2 are con-nected to each other through a data bus 3. The data bus 3 includes an input request signal line 3A for transmitting a data input request to the main device 1 by the input/outpu-t requesting device 2, an output request signal line 3B for transmitting a data output request, a status request signal line 3C for request-. ~
36~3 ing status information such as "busy~' or "ready", and a data sig-nal line 3D for transmitting predetermined data. The main device 1 further contains a status signal generator (not shown) for indicating the actual status to an external device.
The operation of the prior-art example will be des-cribed. The input/output requesting device 2 applies a prede-termined request through the input request signal line 3A, the output request signal line 3B and the status request signal line 3C in the data ~us 3 to the main device 1, and inputs or outputs the data from or to the main device 1 in response to the - la 7~3 application o, the request to the main device 1. The input/output requesting device 2 must complete the input or output operation of the predetermined data within a period that the main device 1 is ready, i.e., within a period that the input or output operation is enabledO Thus, the inpu-t/output requesting device 2 generates a predetermined status request to thereby read corresponding status information from the main device 1 side and inputs or outputs the predetermined data after confirming that the main device 1 has entered the ready period.
However, according to this method, there is a possibility that the main device 1 might enter a busy period, i.e., within a period where the data input or output operation is disabled while inputting or outputting data. From this, the input requesting device 2 needs to input or output the data synchronously with the start of the ready period of the main device 1 according to an algorithm represented in Fig. 2. Fig. 2 shows a flowchart of an algorithm used generally to request the input or output of data.
The abovementioned CRT device is considered here to be a representative example of the main device 1. In this CRT
device, the ready period is a blanking period corresponding to a period where data to be displayed can be input and output, and the busy period is a displaying period corresponding, for example, to a period where the input data is displayed on the CRT
device. The length of the busy period is generally set larger than that of the ready period, and when the data is input or output by fully utilizing the ready period, the data to be displayed within the busy period is reliably supplied to the CRT
device. However, if the data input or output is, for example, started from the vicinity of the end of the ready period, the period will have shifted to the busy period before the input or output operation has finished, and a certain noise is thus displayed on the screen of the CRT device.
The flowchart in Fig. 2 shows an example of an algorithm devised to eliminate the abovementioned drawback. If an I/O request is output in step S31, a status signal of the main device l is input in step S32, and it is determined whether the main device 1 has entered a ready period or not in step S33. If NO is determined in step S33, the operation is shifted to following step S34. If YES is determined in step S33j the operation is returned to step S32. The status signal of the main device 1 is input in step S34, and whether the main device l has entered a busy period or not is determined in step S35. If YES
is determined in step S35, the operation is returned to step S34, but iE NO is determined in step S35, the operation is shifted to step S36. After the predetermined data is input or output, the operation is ended in step S37.
The data input to or output from the main device l is s-tarted from the vicinity of the starting point of the ready period according to the algorithm represented in Fig. 2. In other words, the data input/output is started substantially synchronously with the starting point of the ready period of the main device 1.
The main device in the abovementioned prior-art example is constructed so that ready periods and busy periods are taken 6~3 at a certain repetitive ratio, and there is a drawback that, when the data input/output is not completed within the ready period, a noise is generated in the busy period. Even if a main device is prepared in which data input/output is always enabled, its func-tion cannot be utilized unless the algorithm in Fig. 2 is modi-fied. Therefore, another drawback arises in which data input/
output speed cannot be improved.
The present invention eliminates such drawbacks, and provides a pseudo-status signal generator which improves data input/output speed without adding particular modifications to the input/output requesting device.
According to the present invention therefore there is provided a pseudo-status signal generator interposed between a main device in which a ready state is always maintained and an input/output requesting device adapted to produce a predetermined input/output request to said main device characterized in that said pseudo-status signal generator alternatively repetitively produces a status signal representing a ready state and a status signal representing a busy state to said input/output requesting device whenever a status request is output from said input/output requesting device.
Re~erring once more to the accompanying drawings. Fig.
3 is a block diagram of a general arrangement of an embodiment of a pseudo-status signal generator according to '73 this invention. In Fig. 3, symbol lA denotes a main device in which input/output is always enabled, numeral 2 denotes an input/output requesting device, and numeral 4 denotes a pseudo-status signal generator for pseuod-generating status inEormation of the main device lA. The main device lA, the input/output requesting device 2 and the pseudo-status signal generator 4 are connected to each other through a data bus 3. An input request signal line 3A and an output request signal line 3~
of the data bus 3 connect the main device 1~ and the input/output requesting device 2 to each other, and a status request signal line 3C connects the pseudo-status signal generator 4 and the input/output requesting device 2 to each other. ~ data signal line 3D is connected among the main device lA, the pseudo-status signal generator 4 and the input/output requesting device 4 each other. In this embodiment, the pseudo-status signal generator 4 alternatively generates status information of ready and status information of busy when status information is requested from the input/output requesting device 2. In other words, if the status information of ready is output at a certain time, the status information of busy is output to the request of the subsequent status information.
Here, the operation of the embodiment described above will be described. When the input/output requesting device 2 operates to input or output data to or from the main device lA, the input/output requesting device 2 requests the status information to t~e pseudo-status signal generator 4 through the status request signal line 3C, and receives -the status information as the response through the data signal line 3D. If the status of busy is output in case of the immediately previous status request, the status information of ready is output in the subsequent status request. Therefore, the operation does not enter into the loop in the flowchart of Fig. 2, and the data input or output operation is accelerated by that amount.
In the embodiment described above, the pseudo-status signal generator 4~ is provided as an independent piece of hard-ware. However, this invention is not limited to this particularembodiment. For example, the pseudo-status signal generator may be associated in the main device lA or the input/output request-ing device 2 if functional independence is maintained, thereby performing similar advantages as those of the above-mentioned embodiment.
Fig. 4 is a detailed diagram of a main device where the main device is a CRT device. In Fig. 4, a synchronous signal generator (5) generates a synchronous signal of a CRT (7), and a memory (6) stores data to be displayed by the CRT (7). When a write signal is valid~ the data is written into the memory (6), and when the write signal is other than valid, the data stored in the memory (6) is read out. The CRT (7) displays the data read out of the memory (6). When an output request signal ( 3B ) is valid, a buffer (8) transfers the data on a data signal line ( 3D) to the memory (6). When an input request signal (3A) is valid, a buffer (9) transfers the data in the memory (6) to the data sig-nal line (3D). When a status request signal ~ 3C) is valid, a buffer (10) transfers the synchronous signal as a status signal to the data signal line ~ 3D) .
When both the input request signal ~3A) and the output request signal (3B) are invalid, the data to be displayed is read out of the memory ~6) and displayed by the CRT ~7). Then, when 3S the input request signal ~3A) becomes valid, the data requested to be input is read out of the memory ~6) instead of the memory .
, to be displayed, and therefore, the display of the CRT (7) becomes disturbedO However, since -the CRT (7) is provided with a period of non-display (non-displaying period), the CRT (7) is not disturbed even if the input request signal (3A) becomes valid during this period. This non-displaying period can be discerned from the synchronous signal read out as the status signal. ~ur-ing this non-displaying period, input/output operation becomes operable.
Fig. 5 is a timechart of the synchronous signal. A
memory (2A) is formed, for example, as a 2~port type RAM, and the read/write operation of the data to the memory is operable inde-pendently from the data to be displayed. Therefore, the display of the CRT is not disturbed even if the read/write operation is carried out during the display to be displayed.
As described above, the pseudo-status signal generated according to this invention is interposed between the main device in which the ready state is always set and the input/output requesting device for producing the predetermined input/output request to the main device and alternatively repeats the status signal representing the ready state and the status signal repre-senting the busy state to the input/output requesting device whenever the status request signal is output from the input/ out-put requesting device. Therefore, the data input/output opera-tion can be accelerated without the need for any particular modi-fication in the input/output requesting device.
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Claims (10)
1. A recorded voice warning system for providing safety alerts and personal messages to a device in a vehicle comprising: (a) a modified reversible cassette tape recorder having a dual record and playback head assembly and an endless-loop magnetic tape that incorporates a set of prerecorded safety alert messages, (b) a set of fault detecting sensors where each of said sensors provides an electrical signal when a change corresponding to a specific safety alert occurs and where each of said sensors is optimally located in a section of said vehicle that best provides the chanve, (c) a set of electronic circuits where said circuits have the means to accept and process the signals from said respective sensors and to then turn on and off said recorder playback mode at a precise time to allow the playback of a selected ssfety alert message corresponding to the specific fault detected by the respective said sensor, (d) means to annunciate each of said safety alert messages to the driver in said vehicle, and (e) a timed message circuit that allows a timed personalized message to be recorded on said recorder where said circuit comprises: A) a digital clock that is programmed to provide an output signal at the expiration of any preselected time within a one-year period, BO a flip-flop that is set by the output signal from said clock, C) a two-input AND gate that is enabled when a signal from said flip-flip is received together with a signal from a speed timer that produces the second enabling signal when the drive exceeds a speed of 20 mph, D) a two-input OR gate that is enabled by the output signal from said AND gate, and E) an output timer that when triggered by the signal from the enabled OR gate produces an output signal F) for a period of time that is needed by said endless loop tape to complete one revolution where said F) signal simultaneously turns on said tape motor and closes the respective switch on said multiplexer to allow the personal message to be annunicated over a speaker located in said tape recorder.
2. The system as specified in claim 1 wherein a plurality of personal messages may be recorded on one track of said recorder and heard over said speaker at any selectable time within a one year period.
3. The system as specified in claim 1 wherein the output signal of said flip-flop is also used to turn-on a message indicator that when on, indicates that the message time has expired and that a message is available.
4. The system as specified in claim 1 wherein a reset switch is connected between the output of said AND gate and the reset input of said flip-flop where when said AND gate is enabled, its output signal resets said flip-flop and turns off said message indicator.
5. The system as specified in claim 1 wherein a message activation switch is connected to said OR gate such that when said OR gate is enabled said output timer is triggered to produce the output signal F).
6. The system as specified in claim 1 wherein all circuit devices, visual indicators and manually operated controls and switches are enclosed within a dash mounted enclosure.
7. A recorded voice warning system for providing safety alerts and personal messages to a driver in a vehicle comprising: (a) a modified reversible cassette tape having a dual record and playback head assembly and an endless-loop magnetic tape that incorporates a set of prerecorded safety alert messages, (b) a set of fault detecting sensors where each of said sensors provides an electrical signal when a change corresponding to a specific safety alert occurs and where each of said sensors is optimally located in a section of said vehicle that best provides the changes, (c) a set of electronic circuits which comprises: A) a safety message circuit having the means to accept, condition and process the electrical signals from the respective sensors and where the output of said safety message circuit is a set of safety message signals that initiate the sequencing of the safety messages and establish the duration of time the recorder motor in said tape recorder operates, BO a time sequencer circuit having the means to accept the safety message signals from said safety message circuit and to set-up the safety message timing signal that control the processing of the safety messages and insure that the safety message occur in sequential order, C) a multiplexer having the means to accept the safety message from said recorder and to provide a single message output, where the message timing sequence is controlled by said timer sequencer circuit, D) a tape sychronization circuit having the means to be activated by the signals from said safety message circuit and to synchronize the endless loop magnetic located on said recorder so that the endless loop tape starts at the same tape location to assure that each sequential safety message commences at the beginning of the message, E) a speed indicator circuit having the means to sense and provide an output signal when a preselected speed has been exceeded where the input to said circuit is provided by said over speed limit sensor and where the output signal of said circuit activates said tape synchronization circuit and is applied to said multiplexer for further processing, F) a siren detector circuit having the means to accept a signal from said siren alert sensor and the means to process the signal to produce a signal that corresponds to a preselected db level where the resultant output signal activates said tape synchronization circuit and is applied to said multiplexer for further processing, G) a tape drive circuit having the means to be activated by the applicable sensor signal processing circuit and the means to provide the logic, drive and protection circuits to assure that said tape motor starts and stops the magnetic tape at the proper time, H) a timed message circuit that allows a timed personalized message to be recorded on said tape recorder where said circuit comprises: (a) a digital clock that is programmed to provide an output signal at the expiration of any preselected time within a one-year period, (b) a flip-flop that is set by the output signal from said clock, (c) a two-input AND gate that is enabled when a signal from said flip-flop is received together with a signal from a speed timer that produces the second enabling signal when the driver exceeds a speed of 20 mph, (d) a two-input OR gate that is enabled by the output signal from said AND gate, and (e) an output timer that when triggered by the signal from the enabled OR gate produces an output signal F) for a period of time that is needed by said endless loop tape to complete one revolution where said F) signal simultaneously turns on said tape motor and closes the respective switch on said multiplexer to allow the personal message to be annunicated over a speaker on said tape recorder, and (d) means to annunicate each of said safety alert messages to the driver in said vehicle.
8. A recorded voice warning system for providing safety alerts and personal messages to a driver in a vehicle comprising: (a) a modified reversible cassette tape recorder having a dual record and playback head assembly and an endless-loop magnetic tape that incorporates a set of prerecorded safety alert messages, (b) a set of fault detecting sensors where each of said sensors provides an electrical signal when a change corresponding to a specific safety alert occurs and where each of said sensors is optimally located in a section of said vehicle that best provides the changes, (c) a set of electronic circuits which comprises: A) a safety message circuit having the means to accept, condition and process the electrical signals from the respective sensors and where the output of said safety message circuit is a set of safety message signals that initiate the sequencing of the safety messages and establish the duration of time the recorder motor in said tape recorder operates, wherein said safety message circuit further comprises: so a time sequencer circuit having the means to accept the safety message signals from said safety message circuit and to set-up the safety message timing signal that control the processing of the safety messages and insure that the safety message occur in sequential order, C) a multiplexer having the means to accept the safety message from said recorder and to provide a single message output, where the message timing sequence is controlled by said timer sequencer circuit, D) a tape sychronization circuit having the means to be activated by the signals from said safety message circuit and to synchronize the endless loop magnetic located on said recorder so that the endless loop tape starts at the same tape location to assure that each sequential safety message commences at the beginning of the message, E) a speed indicator circuit having the means to sense and provide an output signal when a preselected speed has been exceeded where the input to said circuit is provided by said over speed limit sensor and where the output signal of said circuit activates said tape synchronization circuit and is applied to said multiplexer for further processing, wherein the speed indicator circuit uses a speed detection scheme that is based on an average speed thus, annoying and unnecessary over speed alerts are prevented during momentary vehicle excursions that are above the preset speed, where the speed averaging is determined by a timer and a shaft register that comprise a section of said speed indicator circuit, where said shift register is designed to accumulate a plurality of speed pulses, supplied by said over-speed limit sensor, over a time period that is determined by said timer, when the pulses are received in a time period that is less than the preset time in said timer an over-speed alert is produced that is heard over a speaker located in said tape recorder and where said speed circuit has the means to turn off the over speed alert by either disabling the speed sensor or by suspending the alert to a higher preset speed, F) a siren detector circuit having the means to accept a signal from said siren alert sensor and the means to process the signal to produce a signal that corresponds to a preselected db level where the resultant output signal activates said tape synchronization circuit and is applied to said multiplexer for further processing, and G) a tape drive circuit having the means to be activated by the applicable sensor signal processing circuit and the means to provide the logic, drive and protection circuits to assure that said tape motor starts and stops the magnetic tape at the proper time, and (d) means to annunicate each of said safety alert messages to the driver in said vehicle.
9. A recorded voice warning system for providing safety alerts and personal messages to a driver in a vehicle comprising: (a) a modified reversible cassette tape recorder having a dual record and playback head assembly and an endless-loop magnetic tape that incorporates a set of prerecorded safety alert messages, (b) a set of fault detecting sensors where each of said sensors provides an electrical signal when a change corresponding to a specific safety alert occurs and where each of said sensors is optimally located in a section of said vehicle that best provides the changes, (c) a set of electronic circuits which comprises:A) a safety message circuit having the means to accept, condition and process the electrical signals from the respective sensors and where the output of said safety message circuit is a set of safety message signals that initiate the sequencing of the safety messages and establish the duration of time the recorder motor in said tape recorder operates, wherein said safety message circuit further comprises: (1) a timer circuit that is normally in a reset condition and which has the capability to reset itself after each of said safety message faults are corrected and at the end of a six second time period which corresponds to the length of said tape, (2) a latch circuit that upon receiving a signal from one of said sensors is energized preventing other sensor signals from being processed until said timer has completed its six second time period, thus two safety messages cannot be heard simultaneously or the safety message in process cannot be truncated and where said latched circuit provides a control signal that: (a) sets said timer circuit and controls the timing operations of said system, (b) energizes said tape motor at a precise time, and (c) in combination with the timing signal from said timer sequencer circuit controls the operation of the switches in said multiplexer to allow the selected safety alert message to be played, BO a time sequencer circuit having the means to accept the safety message signals from said safety message circuit and to set-up the safety message timing signal that control the processing of the safety messages and insure that the safety message occur in sequential order, C) a multiplexer having the means to accept the safety message from said recorder and to provide a single message output, where the message timing sequence is controlled by said timer sequencer circuit, D) a tape sychronization circuit having the means to be activated by the signals from said safety message circuit and to synchronize the endless loop magnetic located on said recorder so that the endless loop tape starts at the same tape location to assure that each sequential safety message commences at the beginning of the message, E) a speed indicator circuit having the means to sense and provide an output signal when a preselected speed has been exceeded where the input to said circuit is provided by said over speed limit sensor and where the output signal of said circuit activates said tape synchronization circuit and is applied to said multiplexer for further processing, F) a siren detector circuit having the means to accept a signal from said siren alert sensor and the means to process the signal to produce a signal that corresponds to a preselected db level where the resultant output signal activates said tape synchronization circuit and is applied to said multiplexer for further processing, and G) a tape drive circuit having the means to be activated by the applicable sensor signal processing circuit and the means to provide the logic, drive and protection circuits to assure that said tape motor starts and stops the magnetic tape at the proper time, and (d) means to annunicate each of said safety alert messages to the driver in said vehicle.
10. The system as specified in claim 9 wherein said safety message circuit further comprises a latch circuit and a timer circuit that function together to allow a plurality of said safety messages to be sequentially selected.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP113641/1986 | 1986-05-20 | ||
| JP61113641A JPS62271012A (en) | 1986-05-20 | 1986-05-20 | Pseudo status signal generator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1298673C true CA1298673C (en) | 1992-04-07 |
Family
ID=14617385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000537403A Expired - Fee Related CA1298673C (en) | 1986-05-20 | 1987-05-19 | Pseudo-status signal generator |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4839794A (en) |
| EP (1) | EP0246887B1 (en) |
| JP (1) | JPS62271012A (en) |
| KR (1) | KR900009181B1 (en) |
| CA (1) | CA1298673C (en) |
| DE (1) | DE3786598T2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930008042B1 (en) * | 1991-04-03 | 1993-08-25 | 삼성전자 주식회사 | Microcontroller unit |
| JP2536984B2 (en) * | 1991-09-26 | 1996-09-25 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Peripheral device control method, floppy disk device control method, peripheral device, floppy disk device, and data processing system |
| US5414831A (en) * | 1993-12-30 | 1995-05-09 | Lsi Logic Corporation | Apparatus and method for accessing a plurality of computer devices having a common address |
| US6912607B2 (en) * | 2002-02-06 | 2005-06-28 | Hewlett-Packard Development Company, L.P. | Method and apparatus for ascertaining the status of multiple devices simultaneously over a data bus |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4167041A (en) * | 1977-04-05 | 1979-09-04 | International Business Machines Corporation | Status reporting |
| US4271479A (en) * | 1977-10-20 | 1981-06-02 | International Business Machines Corporation | Display terminal with modularly attachable features |
| US4315310A (en) * | 1979-09-28 | 1982-02-09 | Intel Corporation | Input/output data processing system |
| JPS57123455A (en) * | 1981-01-23 | 1982-07-31 | Nec Corp | Instruction executing device |
| US4413319A (en) * | 1981-03-09 | 1983-11-01 | Allen-Bradley Company | Programmable controller for executing block transfer with remote I/O interface racks |
| US4443863A (en) * | 1981-06-16 | 1984-04-17 | International Business Machines Corporation | Timer driven display updating |
| EP0069829B1 (en) * | 1981-07-10 | 1985-08-14 | Siemens-Albis Aktiengesellschaft | Bus system |
| JPS58195265A (en) * | 1982-05-10 | 1983-11-14 | Sony Corp | Microcomputer |
| JPS59114639A (en) * | 1982-12-22 | 1984-07-02 | Olympus Optical Co Ltd | Ready signal generating circuit of high speed operating element |
| US4698770A (en) * | 1984-01-13 | 1987-10-06 | Bell & Howell Company | Computer controlled video device and slide projector interface arrangement |
-
1986
- 1986-05-20 JP JP61113641A patent/JPS62271012A/en active Pending
-
1987
- 1987-05-12 KR KR1019870004629A patent/KR900009181B1/en not_active IP Right Cessation
- 1987-05-19 CA CA000537403A patent/CA1298673C/en not_active Expired - Fee Related
- 1987-05-20 EP EP87304502A patent/EP0246887B1/en not_active Expired - Lifetime
- 1987-05-20 DE DE87304502T patent/DE3786598T2/en not_active Expired - Fee Related
- 1987-11-18 US US07/122,131 patent/US4839794A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP0246887A3 (en) | 1990-02-07 |
| EP0246887A2 (en) | 1987-11-25 |
| JPS62271012A (en) | 1987-11-25 |
| KR870011567A (en) | 1987-12-24 |
| EP0246887B1 (en) | 1993-07-21 |
| DE3786598D1 (en) | 1993-08-26 |
| US4839794A (en) | 1989-06-13 |
| DE3786598T2 (en) | 1994-02-24 |
| KR900009181B1 (en) | 1990-12-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |