CA1299707C - Process and packet flow control system - Google Patents
Process and packet flow control systemInfo
- Publication number
- CA1299707C CA1299707C CA000567644A CA567644A CA1299707C CA 1299707 C CA1299707 C CA 1299707C CA 000567644 A CA000567644 A CA 000567644A CA 567644 A CA567644 A CA 567644A CA 1299707 C CA1299707 C CA 1299707C
- Authority
- CA
- Canada
- Prior art keywords
- transmit
- authorization
- flow
- transmission
- virtual circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5614—User Network Interface
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5629—Admission control
- H04L2012/563—Signalling, e.g. protocols, reference model
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5629—Admission control
- H04L2012/5631—Resource management and allocation
- H04L2012/5636—Monitoring or policing, e.g. compliance with allocated rate, corrective actions
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5629—Admission control
- H04L2012/5631—Resource management and allocation
- H04L2012/5636—Monitoring or policing, e.g. compliance with allocated rate, corrective actions
- H04L2012/5637—Leaky Buckets
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5647—Cell loss
Abstract
ABSTRACT
The packet flow of each virtual circuit is measured and compared to an allocated average value.
At each transmission authorization request, when found to be less than the average value, a positive difference brings about an authorization to transmit and is translated into a right to transmit which is proportional to the time span since the previous request, the right to transmit being accumulated.
When it is found to be greater than the average value, a negative difference brings about, if the number of accumulated transmission rights is positive, on one hand, the authorization to transmit and, on the other hand, a decrementing of the accumulated number, and if the accumulated number is nil, a refusal of authorization to transmit. The process and systems are applicable in particular to packets carried by asynchronous time multiplexers.
The packet flow of each virtual circuit is measured and compared to an allocated average value.
At each transmission authorization request, when found to be less than the average value, a positive difference brings about an authorization to transmit and is translated into a right to transmit which is proportional to the time span since the previous request, the right to transmit being accumulated.
When it is found to be greater than the average value, a negative difference brings about, if the number of accumulated transmission rights is positive, on one hand, the authorization to transmit and, on the other hand, a decrementing of the accumulated number, and if the accumulated number is nil, a refusal of authorization to transmit. The process and systems are applicable in particular to packets carried by asynchronous time multiplexers.
Description
01 The present invention relates to a system 02 ~or controlling the flow of packets carried by 03 asynchronous time division mult;plexers.
04 The routing of whatever Elows and the 05 sharing of the same transmission resources constitutes 06 the main concern of the asynchronous time method of 07 transmission. In fact, asynchronous time division 08 multiplexing allows the transmission on the same Og facility, that is the asynchronous time multiplexing, of packets belonging to different virtual circuits.
11 Each packet is made up oE a label identifying the 12 virtual circuit to which it belongs and an information 13 block. The maximum number of virtual circuits on a 14 multiplexer is determined by the number of bits in the label.
16 However, the allocation of resources when 17 setting up the virtual circuits generally relies on 18 rate of activity statistics of the different 19 transmission sources, such that there exists a non-zero risk of informa-tion loss through overflow of 21 the queueing files due to instantaneous overloads. We 22 must obviously minimize these losses, but the solution 23 is not easy because the flow generated by the 24 different sources may be constant, variable or sporatic.
26 In principle, the flow of information 27 generated on a virtual circuit, which shall be 28 designated more simply below by "communication flow"
29 or "virtual circuit flow", must not exceed the flow which was assigned to the virtual circuit or to the 31 communication link when it was established. In 32 practice, the network has no means to limit the flow 33 from a source. A source may thus accidentally or 34 through foul play, generate a flow of information greatly superior to that which it was allocated. The 36 saturation of the network may result at a location 37 distant from the source of transmission and can ~k 7~7 01 degrade the quality of the other signals transmitted 02 b~ the network.
03 One object of the present invention is to 04 provide a method allowing the guarantee, in real time, 05 of the management of flow of -the virtual circuits.
06 Following this method, the flow is monitored of each 07 of the vir-tual circuits established on the set of time 08 multiplexers of an input switch, in order to prevent 09 bottlenecking and saturation of the network resources triggered by consecutive overloads due either to 11 abnormal operation or due to not respecting the flow 12 threshold for which the communication was established.
13 Another object of the invention is to 14 provide means allowing the guarantee of source flow control for all the virtual circuits of a multiplexer.
16 Another object of the invention is to 17 provide means to limit to average flow of a vlrtual 18 circuit to a value allocated during the establishment 19 of the virtual circuit.
In accordance with one embodiment of the 21 method of the invention, the flow of packets in each 22 virtual circuit is measured and compared to an 23 allocated value and, with each request for 24 -transmission, when it is found to be smaller than the allocated value, a positive difference, on one hand, 26 brings about an authorization to transmit and, on the 27 other hand, is translated to right to transmit 28 proportional to the time elapsed since the previous 29 request, the transmission rights being accumulated, or, when it is greater than the said allocated value, 31 the negative difEerence brings about, if the number of 32 accumulated transmission rights is positive, on one 33 hand, the authorization to transmit, and, on the other 34 hand, the decrementing of the cumulative number, and, if the cumulative number is nil, the refusal to 36 authorize transmission.
37 In accordance with another embodiment, the 01 method is comprised of initially attributing to a 02 virtual circuit, on one hand, a first number which i8 03 later incremented at a fixed rate, and, on the other 04 hand, a second number, each transmission authorization 05 request coming from the virtual circuit bringing about 06 the calculation of the difference between the first 07 and the second number and, when the sign o~ the 08 difference is positive, the generation of an 09 authorization to transmit as well as the substitution of the value of the difference for the first number, 11 and, iE the sign of the difference is negative, the 12 generation of a signal -Eorbidding transmission as well 13 as conserving the first number, the first number 14 representing the accumulation of rights to transmit and the second number being a function of the flow 16 associate~ with the virtual circuit.
17 In accordance with the invention, the 18 generation of the signal forbidding transmission is 19 used by switching apparatus of the virtual circuit which transmit towards the source of the virtual 21 circuit a message requesting it to reduce its flow, 22 when this is possible, and, in any case, a message 23 alarming it to the loss of packets.
24 In accordance with another embodiment of the invention, a first transmission authorization 26 request detector, a clock, a counter, a storage 27 register, a subtractor, a second detector for the sign 28 of the contents of the subtractor, a control unit are 29 provided, the outputs of the counter and the storage register being connected to the operand inputs of the 31 subtractor whose output is connected to the input of 32 the counter, the counter input receiving the periodic 33 clock signal and the storage register being, at the 34 start of establishing the virtual circuit, loaded by -the control unit, each output signal of the first 36 detector triggering the operation of the second 37 detector whose output signal at a low level brings 7~
about the transmission of an authorization to transmit 2 and the loading oP the result from the subtractor into 3 the counter and, at a high level, brings about the 4 forbiddin~ o~ transmission.
In accordance with another embodiment of the 6 invention, a system capable of managing all the virtual 7 circuits processed by a switch for packets carried by 8 asynchronous time multiplexers is provided, the system 9 comprising a first memory whose words store the first numbers, and a second memory whose words store the 11 second numbers, the addresses of the f irst and second 12 memories being determined by the packet labels entering 13 in the switch, the system comprising also a label 14 receiving circuit used as the first detector, a subtractor, a second detector and a control unit.
16 In accordance with another embodiment, the 17 control unit has a microprocessor controlling the word 18 cycles of the system, each CyClQ having three phases:
19 an allocation phase during which one word of the first memory is incremented, the address of the word of the 21 first memory being incremented Erom one cycle to the 22 next, an authorization phase during which the receiving 23 circuit allows the successive addressing of the first 24 and second memories whose words which are read are subtracted in the subtractor, the second detector 26 generating the authorization or forbidding signal, as 27 well as the loading or not of the contents of the 28 subtractor into the f irst memory, and an access phase to 29 the control unit to write a new word in the second memory.
31 In accordance with another embodiment, in a 32 process for controlling the flow of packets, the packets 33 of a virtual circuit being identified by their label and 34 the identity of the multiplex which carries them, the ~9707 flow of packets from each virtual circuit is measured 2 and compared to an allocated average value and at each 3 request for transmission authorization, when it is found 4 to be less than the value, a positive difference, on one S hand, bringing about authorization to transmit and, on 6 the othar hand, is translated inko rights to transmit 7 proportional to the time lapsed since the previous 8 re~uest, the transmission rights being accumulated, or 9 when it is greater than the value, the negative difference brings about, if the number of accumulated 11 rights to transmit is positive, on one hand, the 12 authorization to transmit and, on the other hand, the 13 decrementing of the cumulative number, and if the 14 cumulative number is null, the refusal to authorize transmission.
16 In accordance with another embodiment, a 17 system for controlling the flow of packets is comprised 18 of a first detector of transmission authorization 19 requests, a clock, a counter, a storage register, a subtractor, a second detector for the sign of the 21 contents of the subtractor, a control unit, the outputs 22 of counter and storage register being connected to the 23 operand inputs of subtractor whose output is connected 24 to the input of counter, the input of counter receiving the periodic clock signal and the storage register 26 being, at the initial establishment of the virtual 27 circuit, loaded by the control unit, each output signal 28 of the first detector triggering the operation of the 29 second detector whose output signal at a low level brings about the transmission of an authorization to 31 transmit and the loading of the result of subtractor 32 into the counter and, at a high level forbids 33 transmission.
- ~a -7~37 In accordance with another embod.iment, a process Eor controlling the flow of data packets carried 3 on a plurality of virtual circuits from a plurality of 4 multiple demands, the process is comprised of the steps S of (a) identiîying each of the data packets in response 6 to each request for an authorization to transmit, each 7 data packet being identified by a label included in the 8 packet and by an identi:Eication of a multiplex channel 9 carrying the data packet; ~b) measuring the :Elow of data packets flowing on each o~ the virtual circuits and 11 comparing the measured flow with an avarage rate to 12 determine whether the measured flow is positive, 13 negative, or null with respect to the average rate; if 14 the flow compared in step (b) indicates that the measured flow of data packets is positive with respect 16 to the average flow rate, giving an authorization to 17 transmit and translating into rights to transmit which 18 are proportional to the time which has elapsed since the 19 last previous request for a transmission authorization, the rights to transmit being accumulated; (d) if the 21 flow compared in step (b) indicates that the measured 22 flow of data packets is negative with respect to the 23 average flow rate, and if the accumulated rights to 24 transmit are positive, giving an authorization to transmit and decrementing the accumulated rights; and 26 (e) if the flow compared in step (b) indicates that the 27 measured flow of data packets is negative with respect 28 to the average flow rate and if the accumulated rights 29 are nil, denying an authorization to transmit.
In accordance with another embodiment, a 31 system for controlling the flow of data packets carried 32 on a virtual circuit is comprised of a first detector of 33 transmission authorization requests, a clock for 34 delivering periodic clock signals, a counter having an 36 - 4b -~2~
1 input and output, a storage register having an ou.tput, a 2 subtractor having operand inputs and an output, a second 3 cletector for detecting the arithmatic sign of the output 4 of the subtractor, a control unit, the outputs o~ the S counter and the storage register being connected to the 6 operand inputs of the subtractor, the output of the 7 subtractor being connected to the input of the counter, 8 the input of the counter receiving the periodic clock g signal, apparatus responsive to the control unit for loading the storage register at the initial 11 establishment of the virtual circuit, appara-tus 12 responsive to each output signal of the first detector 13 for triggering an operation of the second detector, and 14 apparatus responsive to an output signal at a low level from the second detector for bringing about a 16 transmission of an authorization to transmit the data 17 packet and for loading the result of the subtractor into 18 the counter and responsive to the high level for 19 forbidding any transmission of packets via the virtual 20 circuit.
21 The above-mentioned embodiments of the 22 invention as well as others, will become clearer upon 23 reading the following descripti.on of e,mbodiment, the 24 description being done with reference to the attached drawings, among which:
26 Figure 1 is a timing diagram illustrating - 4c -.J,, 01 in a general manner the process in accordance with the 02 inven-tion, 03 Figure 2 is a block diagram of a first 04 embodiment of a system in accordance with the 05 invention, 06 Figure 3 is a schematic block diayram 07 illustrating another embodiment of the system in 08 acordance with the invention, 09 Figure 4 is a block diagram of a logic circui-t for the system of Figure 3, and 11 Figure 5 shows the timing diagrams 12 illustrating the operation of the circuits of Figures 13 3 and 4.
14 In Figure 1 is shown the instantaneous time variation of the flow di generated by a source on 16 a virtual circuit of a multiplexer, as well as an 17 average flow value. From 0 to tl, the instantaneous 18 flow is less than the value dm, which in practice 19 represents the average flow allowed. The positive difference (dm-di) brings about the accumulation of 21 the right to transmit. At the instant tl, which 22 corresponds to the instant where the curve di cuts the 23 line dm, the area of the domain I corresponds to the 24 accumulated number of rights to transmit.
From tl to t2 which will be defined below, 26 the difference (dm-di) is negative. The number of 27 rights to transmit is decremented. When the area of 28 domain II is equal to that of domain I, which defines 29 the position of t2, all rights to transmit have been restored.
31 From t2 to t3, where the curve di 32 intersects again the straight line dm in its downward 33 path, the difference (dm-di) is always negative and 34 the number of rights to transmit is nil. No authorization to transmit is given and the 36 data corresponding to the requests for authorization 37 to transmit are eliminated from the network.
7 [)7 01 AEter t3, the diference ~d~-di) becomes 02 positive again, the authorizations to transmi-t are 03 given and rights to transmit are once again 0~ accumulated.
05 In Figure 2 is shown a packet swi-tch XPAC
06 with its input junctions EPAC, its output junc-tions or 07 lines SPAC and its time base BT. The switch XPAC is 08 controlled and ordered by a control uni-t UX which 09 establishes the virtual circuits between the input junctions and the output junc-tions. For the sake of 11 an example, the junctions or lines EPAC and SPAC can 12 transmit the time multiplex such as that which i5 13 described in document EP-A-O 108 028 and the switch 14 XPAC can be of the type described in document EP-A-AO 113 639, the control unit UX thus including 1~ the control unit UCC which is a part of this 17 autoswitch.
18 In shunt with one of the input junctions 19 EPAC, namely EPACi, a framing circuit CCAD is shown which is capable of framing the packets carried by the 21 junction EPACi and extracting the labels. One input 22 f3 of the framing circuit is connected to a 23 corresponding output of the time base BT and is 24 intended to synchroni~e the extraction of labels. The output of circuit CCAD is connected to the first input 26 of a comparator COMPl whose second input is connected 27 to the output of a storage register REGl whose loading 28 input is connected to a corresponding output of -the 29 control unit UX. The output of comparator COMPl is connected to the input of a sequencer SEQ with two 31 outputs R and W. The sequencer SEQ also has a clock 32 input connected to an output of a time base BTC. The 33 output R is connected, on one hand, to the read input 34 R of a storage register REG2 and, on the other hand, to the read input R of a binary counter CPT. The 36 output W of the sequencer SEQ is connected to the 37 write input W of counter CPT.
~2~
01 The storage register REG2 has a data input 02 which is connected to a corresponding data output of 03 the control unit UX and a write input Wl which is also 04 connected to a corresponding output of the unit UX.
05 The output oE the storage register REG2 is connected 06 to the operand input B of a subtractor SOU.
07 The binary coun~er CPT, which is not a 08 cyclic counter, has a data loading input which is 09 connected to the output of subtractor SOU, an incrementing input which is connected to an output Hl 11 of time base BTC, a "1" setting input for each of the 12 cells connected to a corresponding output of the 13 control unit UX and its output is connected to the 14 operand input A of subtractor SOU.
The subtractor SOU, which carries out the 16 subtraction (A-B) has an output with the sign AAE
17 which is enabled when the diEference is negative and 18 which is connected to a corresponding input of the 19 control unit UX.
The operation of the circuit of Figure 2 21 is as follows. Upon establishing a virtual circuit on 22 the input junction EPACi, the control unit UX assigns 23 it, on one hand, a label at the beginning of each 24 packet, and, on the other hand, an average flow value. In the embodiment described, the label will be 26 "ETIj" and the average flow value "MOYj". The unit UX
27 thus writes the word ETIj in the storage register REGl 28 and the word MOYj in the storage register REG2, then 29 sets the counter CPT to the maximum count through the "1" setting input. In the example described, we will 31 assume that the counter CPT has four cells and the 32 register REG2 has five cells. Finally, we shall 33 assume the value 00011 for the word MOYj.
34 For each packet carried by the multiplexer oE junction EPACi, the circuit CCAD generates the 36 label to comparator COMPl. When the label generated 01 is the word ETIj, the comparator generates a cycle 02 triggering signal to se~uencer SEQ. Through its 03 output R, it causes the reading oE the contents of 04 counter CPT and of register REG2. The subtractor SOIJ
05 thus receives at its A input the word 1111 and at its 06 B input the word 00011. (A-B) is, on one hand, 07 positive and, on the other hand, equal to 1100. The 08 output W of sequencer SEQ causes the wri-ting of the 09 word 1100 into counter CPT. While waiting for the next label ETIj, the contents of counter CPT are 11 incremented at the rate of signal Hl supplied by the 12 time base BTC. Thus, it appears that the contents of 13 the counter increases constantly, with however a 14 maximum, for the whole duration of the commmunication on the virtual circuit concerned.
16 Two cases can occur:
17 (1) The averaga rate of appearance of the 18 labels ETIj is equal or less than that which was 19 foreseen, the contents of counter CPT should thus remain greater than the value of the word MOYj, and 21 all the packets of the communicaion concerned will be 22 admitted.
23 (2) The average rate of appearance of the 24 label ETIj becomes greater than the predetermined value, the contents of counter CPT will be reduced, in 26 spite of being incremented at the rate Hl and, at a 27 given time, the difference (A-B) will be negative, the 28 AAE output will be enabled and the control unit UX
29 will order the matrix XPAC not to transmit any more packets having the label ETIj. As we shall see below, 31 in that case the value recopied into the counter CPT
32 is that o:E the operand A and not the result of the 33 subtraction.
34 As soon as (A-B) becomes positive again, the transmission can resume.
36 I-t may be seen that the value of the two 37 word MOYj is inversely proportional to the average 38 - 8 ~
~2~
01 flow allocated and proportional to the frequency oE
02 the time base BTC.
03 We have seen above, that the number of 04 cells, in register REG2, was greater by one unit than 05 the number of cells in coun-ter CPT. This is not 06 necessary, but provides an ease of control easily 07 usable by the control uni-t UX. In fact, when the unit 08 UX wants -to completely disallow a communication, it is 09 suE-Eicient to load the word 11111 into register REG2.
B will thus be greater than A. This possibility can 11 be used when the control unit UX has declared a packet 12 source to be in error.
13 On the other hand, for some communications 14 which it deems of high priority, the control unit UX
can load 00000 into register REG2. All the packets of 16 such a communication will be transmitted.
17 It should be noted that with a switch 18 XPAC, such as that which is described in document 19 EP-A-0 113 639, each label from arriving packets is examined, to route the packet, into a programmable 21 memory intended for this purpose. The unit UX is 22 assumed capable of modifying the contents of this 23 memory, such that upon receiving a disallowed label, 24 there corresponds no routing.
The circuit of Figure 2 has permitted the 26 description of the basic operation of the packet flow 27 control system in accordance with the invention, but 28 which is applicable to a single communication. In 29 prac-tice, a really efficient control system must allow flow control on the whole set of input multiplex EPAC
31 from a packet switch and, in each multiplex EPACi, all 32 the established virtual circuits. For the sake of an 33 embodiment of the invention, a basic module is 34 provided capable of monitoring 16 entering multiplex from a switching matrix such as that which is shown in 36 Figure 8 of document EP-A-0 113 639. Hence, there 37 will be as many basic modules as switching matrices in 38 _ 9 _ ~2~
01 the first stage of a packet switch.
02 Figure 3 illustrates a 'basic modu:Le MOB
03 associated with a switching matrix XPAC with 16 04 entering multiplexer junctions or lines EPAC and 16 05 outgoing multiplexer junctions or lines SPAC, such as 06 mentioned above, the basic module MOB being controlled 07 by a control unit with a processor UX. In the matrix 08 XPAC, we have shown the input circuits CE of the 09 entering multiplexer junctions or lines EPAC, the rotation matrix MRE, the packet buffer memory MP, the 11 output rotation matrix MRS, the output circuits p/s, 12 the central control unit UCC, the routing circuit ACE
13 including the label conversion memory MC, the time 14 base CTS and the local byte clock H.
Between the matrix XPAC and the module 16 MOB, we have shown the links Dl, e, H and AAE. The 17 outgoing link Dl from XPAC generates the successive 18 labels ETI of the packets which enter into the matrix 19 XPAC. It may be recalled, that in accordance with document EP-A-O 113 639, the link Dl is connected to 21 the first output of the input rotation matrix MRE
22 which generates the lables ETl to memory MC. The link 23 e, coming from the time base CTS, serves to identify 24 the number of the entering multiplex which carries -the packet whose label is ETI, the information e carried 26 by this link playing the same role in the matrix 27 XPAC. The link H transmits the internal byte clock H
28 used in the matrix XPAC. The link AAE starts from the 29 basic module MOB towards the unit UCC which deduces the order to transmit to the memory MC to no longer 31 process a particular label ETI coming from a 32 par-ticular entering multiplexer. T'he link AAE is also 33 connected to the control unit UX.
34 Between the basic module MO and the control unit UX, are provided two write control wires 36 le' and dc', addressing wires AP, data wires DP and an 37 access con-trol wire DAP'.
01 Finally, between the control units VX and 02 UCC is provided a data exchange link LL thro~lgh which 03 the control unit UCC transmits -to the unit UX data 04 concerning the value oE the average ~low allocated to 05 a newly es-tablished communication. These data will be 06 explained below.
07 The basic module MOB, shown in Figure 3 08 comprises a set of sequencing logic LOG, which is 09 shown in detail in Figure 4, a random access memory MVD containing, -for each communication, a value to be 11 subtracted at each request for authorization to 12 transmit, a random access memory MDT containing, Eor 13 each communication, the accumulated number o~ rights 14 to transmit, with classically between the set LOG and the memories, data buses BUSDON, addressing buses 16 BUSAD and control buses.
17 The logic set LOG, Figure 4, comprises a 18 clock signal generator GEN, a control signal generator 19 GSC, a buffer MDAE storing an authorization to transmit request, a buffer MDAP storing a 21 microprocessor access request from the control unit 22 UX, an access mul-tiplexer MUXA to the address bus 23 BUSAD, an access multiplexer MUXD to the data bus 24 BUSDO~, a logic circuit ALL to allocate rights -to transmit and a logic circuit AVT to authorize 26 transmission.
27 The clock signal generator GEN comprises a 28 binary cyclic counter Cl and a logic decoder Dl. The 29 counter Cl has a clock input which receives the signal hO whose frequency is equal to the bit rate on the 31 entering multiplex of the matrix XPAC, and a zero 32 reset input RAZ which receives from this matrix the 33 signal H at the byte frequency. The counter Cl has 34 three outputs supplying the signals hl, h2 and h3 whose frequencies are respectively one half, one 36 quarter and one eighth that oE signal hO. The decoder 37 Dl receives the signals hl to h3 of counter Cl and 7(3'7 01 processes them logically to supply the sir~nals t'O to 02 t'7 which are defined by the followiny logic 03 equations:
04 t'O - hl.h2.h3 05 t'l = hl/.h2.h3 06 t'2 = hl.h2/.h3 07 _________ 08 t'7 = hl/.h2/.h3/
09 The seven outputs t'O to t'7 of decoder Dl are connected to the first inputs of eight AND gates 11 PO to P7 whose second inputs receive the signal hO
12 which samples the signals t'O to t'7 to generate 13 signals tO to t7. In practice a signal t'i is at a 14 high level for one period of hO and at the low level during the seven following periods and these signals 16 are shifted one with respect to the other. The 17 signals tO to t7 have, at the high level a duration 18 which is half that of t'O to t'7.
19 The chronograms hO, tO to t7, and t'O to t'7 of Figure 5 illustrate the signals of the same 21 name respectively.
22 The transmission rights allocation logic 23 circuit ALL comprises a counter C2, an adder Al and a 24 multiplexer Ml. The counter C2 is a modulo-N counter, where N is the number of words in the random access 26 memories MVD and MDT, and it is incremented at the 27 rate of signal t3. At the end of N periods of signal 28 t3, the counter Cl will have accomplished a complete 29 cycle supplying successively all the addresses of the memories MDT and MVD. The output of counter C2 is 31 connected to the first input of multiplexer MUXA.
32 The adder Al has its operand input A
33 connected to the data bus BUSDOM. The high level 34 corresponding to a "1" is applied to its B operand input. The adder Al has its data output connected to 36 the first input of a multiplexer Ml and its overflow 37 input connected to the control input of multiplexer 37~3~7 01 Ml, whose second input is connec-ted to the data bus 02 BUSDON. The output of mul-tiplexer Ml is connected to 03 the firs~ input of multiplexer MUXD.
04 The logic circuit AVT comprises a buffer 05 register Bl, a subtractor Sl and a multiplexer M2.
06 The input of the buffer register Bl is connected to 07 the bus BUSDON and its output is connected to the B
08 operand input of subtractor Sl whose A opexand input 09 is connected to bus BUSDO~. The subtractor Sl has an output which generates the difference (A-B) and which 11 is connected to the first input of multiplexer M2. It 12 also has a sign output which is connected, on one 13 hand, to the control input of multiplexer M2 and, on 14 the other hand, to the output AAE. The second input of multiplexer M2 is connected to bus BUSDON and its 16 output is connected to the second input of multiplexer 17 MUXD.
18 The buffer circuit MDAE comprises two 19 buffer registers B2 and B3. The inpu-t of register B2 is connected to links Dl and e which transmit the 21 data ETIj and e, and its output is connected to the 22 second input of multiplexer MUXA. The register B3 has 23 its input which receives -the value "1" and its output 24 which is connected to the DAE input of the control signal generator GSC. The two registers B2 and B3 26 have write enable inputs which are connected throuyh 27 an inverter INV, to the output of a comparator COMP2 28 one input of which is connected to link Dl and the 29 other to the output of a register Z0 in which is stored the word corresponding to the label of an empty 31 packet, such as that, for example, described in 32 document EP-A-0 108 028~
33 Each label ETIj from a packet transmitted 34 by link Dl is compared in comparator COMP2 with the empty packet label. If the result of the comparison 36 is negative, the inverter INV generates the signal 37 DAE' which indicates that there is a request to ~2~7()7 01 authorize transmission. IE the result is positive, 02 the signal DAE' is not transmitted. The signal t3 03 stores a request for authorization to transmit. The 04 buffer circuit MDAP comprises three buffer registers 05 B4 to B6. The register B4 has its input connected to 06 a bundle of wires AP coming from the control unit UX
07 and its output is connected to the third input of a 08 multiplexer MUXA. The register B5 has its input 09 connected to a bundle of wires DP coming from the control unit UX and its output is connected to the 11 third input of multiplexer MUXD. The register B6 12 receives at its input the value "1" and its output is 13 connected to the input DAP of the control signal 14 generator GSC. The three registers B4 to B6 have write enable inputs which are connected, in parallel 16 to the output DAP' of the control unit UX. The signal 17 t0 stores the access request from the unit UX.
18 The multiplexer MUXA has its output 19 connected to the address bus BUSAD while the multiplexer MUXD has its output connected to bus 21 BUSDON.
22 The inputs of control signal generator GSC
23 are the inputs DAE and DAP, already mentioned, the 24 signal inputs t'0 to t'7 and t0 to t7 connected to the generator GEN, and the inputs le' and dc' which are 26 connected to the corresponding outputs of the control 27 unit UX. The generator GSC generates, at its corres-28 ponding outputs, the signals le, dc and sel, towards 29 the control bus BUSC and signals Fhl and Ph2 towards the control inputs of multiplexers MUXA and MUXD.
31 The generator GSC is a logic circuit which 32 resolves the following logic equations:
33 sel = tO+t2+DAE.(t3+t4+t6)+DAP.t7 34 dc = DAE.t'3-~DAP.t'7.dc' le = (-t'0+t'1-~t'2-~t'3+t'4+t'5~t'6)~1.t'7 36 Phl = 0.(t'0+t'1+t'2+t'3~t'4-~t'5+t'6)+1.t'7 37 Ph2 = 0.(t'0~t'1~t'2-~t'3)+1.(t'3+t'4+t'5+t'6) 70~7 01 The timing diagram for the signals le, dc, 02 sel, Phl and Ph2 are shown in Figure 5. The signal 03 sel is at the high level to trigger all read or write 04 operation in one or the other of memories MVD and 05 MDT. The signal le/ triggers a write operation into 06 the memory MDT. The signal dc routes the reading or 07 writing towards the memory MVD while the signal dc/
08 routes the reading towards memory MDT.
09 The combination of signals Phl/ and Ph2/
point the multiplexers MUXA and MUXD towards the 11 outputs of counter C2 and multiplexer Ml, 12 respectively, to allow the allocation phase. The 13 combination Phl/ and Ph2/ point the multiplexers MUXA
14 and MUXD to the output of buffer B2 and the output of multiplexer M2, respectively, to allow the 16 authorization phase. The combination Phl and Ph2/
17 point the multiplexers MUXA and MUIXD to the outputs 18 of buffers B4 and B5 respectively, to allow read or 19 write access from the microprocessor of the unit UX.
In Figure 5, we have shown the three operational 21 phases: allocation, authori~ation and access to UX.
22 The allocation phase starts at time t0 23 with sel.le.dc/ with the transmission, through MUXA, 24 of the address contained in counter C2 to bus BUSAD in order to read the word CPT corresponding to this 26 address in memory MDT. This word CPT is transmitted, 27 by the bus BUSDON, to the operand input A of adder Al 28 which is enabled during the time tl. At the time t2, 29 the output of adder Al displays the word (CPT+l).
Whether its overflow output is enabled or not, the 31 multiplexer Ml causes the word CPT or (CPT~l) to go to 32 multiplexer MUXD in order to immediate:Ly rewrite this 33 word at the same address in memory MDT. In practice, 34 the set of circuits Al and Ml has -the only purpose of preventing an untimely return to zero of the word CPT
36 when it has reached its upper limit.
~.2~
01 The authorization phase starts at time t3 02 with sel.le.dc by the transmission, through MUXA, of 03 the address contained in buffer B2 towards the bus 04 BUS~D in order to read the word MDYj corresponding to 0~ this address in memory MVD. This word MOYj is 06 transmitted, by the bus BUSDON, to the input of buEEer 07 Bl. At time t4, with sel.le.dc/, at the same address, 08 but in memory MDT, the corresponding word CPT is read 09 and applied, by the bus BUSDON, to the operand input A
of subtractor Sl, which receives at its B operand 11 input, the word JOYj contained in buffer Bl. the 12 subtraction is carried out at time t5. If the result 13 of the operation is positive, the link A~E is at the 14 low level and this result is transmitted by the multiplexers M2 and MUXD to be written in memory MDT
16 and become the new word CPT, always at the same 17 address. If the result is negative, the link AAE is 18 at the high level, such that the multipelxer M2 19 transmits to multiplexer MUXD the previous word CPT
which is rewritten in memory MDT.
21 Of course, this authorization phase is 22 only carried out if the signal DAE' is transmitted by 23 the inverter INV, that is the label received is not 24 that of an empty packet. In other respects, we must note that at time t3, the counter C2 has been 26 incremented in anticipa-tion of the next allocation 27 phase.
28 The access phase to UX starts at time t7 29 and allows the unit UX:
- with sel.le.dc, to read in the memory MVD, 31 - with sel.le/.dc, to write in the memory MVD, 32 - with sel.le.dc/, to read in the memory MDT, and 33 - with sel.le/.dc/, to write in the memory MDT.
34 During reading or writing, -the multiplexer MUXA transmits the address contained in buffer B4 to 36 bus BUSAD. During writing, the data to be written 37 goes from buffer B5 to bus BUSDON through multiplexer 01 MUXD. During reading, the data read is transmitted to 02 the unit UX directly by the bus sUSDON.
03 I-t may be seen that a comple-te cycle lasts 04 eight periods of hO, that is eight bi-t durations of 05 the pacXets transmitted on the entering multiplex 06 junctions EPAC. Thus, each label appearing on the 07 link Dl can be processed in real time.
08 It may also be seen that upon establishing 09 a virtual circuit, the control unit UX can decide to write an initial number CPT into the memory MDT at the 11 address of the virtual circuit. If this initial 12 number is nil, it is because the control unit assigns 13 a delay at the transmission of the source.
14 In the example described in relation to Figure 2, we had assumed, otherwise, that a maximum 16 value was given to CPT.
17 It may be seen that each time a 18 communication is established, only the value of the 19 word MOYj need necessarily be fixed by the control unit, which makes the system of the invention very 21 easy to carry out.
04 The routing of whatever Elows and the 05 sharing of the same transmission resources constitutes 06 the main concern of the asynchronous time method of 07 transmission. In fact, asynchronous time division 08 multiplexing allows the transmission on the same Og facility, that is the asynchronous time multiplexing, of packets belonging to different virtual circuits.
11 Each packet is made up oE a label identifying the 12 virtual circuit to which it belongs and an information 13 block. The maximum number of virtual circuits on a 14 multiplexer is determined by the number of bits in the label.
16 However, the allocation of resources when 17 setting up the virtual circuits generally relies on 18 rate of activity statistics of the different 19 transmission sources, such that there exists a non-zero risk of informa-tion loss through overflow of 21 the queueing files due to instantaneous overloads. We 22 must obviously minimize these losses, but the solution 23 is not easy because the flow generated by the 24 different sources may be constant, variable or sporatic.
26 In principle, the flow of information 27 generated on a virtual circuit, which shall be 28 designated more simply below by "communication flow"
29 or "virtual circuit flow", must not exceed the flow which was assigned to the virtual circuit or to the 31 communication link when it was established. In 32 practice, the network has no means to limit the flow 33 from a source. A source may thus accidentally or 34 through foul play, generate a flow of information greatly superior to that which it was allocated. The 36 saturation of the network may result at a location 37 distant from the source of transmission and can ~k 7~7 01 degrade the quality of the other signals transmitted 02 b~ the network.
03 One object of the present invention is to 04 provide a method allowing the guarantee, in real time, 05 of the management of flow of -the virtual circuits.
06 Following this method, the flow is monitored of each 07 of the vir-tual circuits established on the set of time 08 multiplexers of an input switch, in order to prevent 09 bottlenecking and saturation of the network resources triggered by consecutive overloads due either to 11 abnormal operation or due to not respecting the flow 12 threshold for which the communication was established.
13 Another object of the invention is to 14 provide means allowing the guarantee of source flow control for all the virtual circuits of a multiplexer.
16 Another object of the invention is to 17 provide means to limit to average flow of a vlrtual 18 circuit to a value allocated during the establishment 19 of the virtual circuit.
In accordance with one embodiment of the 21 method of the invention, the flow of packets in each 22 virtual circuit is measured and compared to an 23 allocated value and, with each request for 24 -transmission, when it is found to be smaller than the allocated value, a positive difference, on one hand, 26 brings about an authorization to transmit and, on the 27 other hand, is translated to right to transmit 28 proportional to the time elapsed since the previous 29 request, the transmission rights being accumulated, or, when it is greater than the said allocated value, 31 the negative difEerence brings about, if the number of 32 accumulated transmission rights is positive, on one 33 hand, the authorization to transmit, and, on the other 34 hand, the decrementing of the cumulative number, and, if the cumulative number is nil, the refusal to 36 authorize transmission.
37 In accordance with another embodiment, the 01 method is comprised of initially attributing to a 02 virtual circuit, on one hand, a first number which i8 03 later incremented at a fixed rate, and, on the other 04 hand, a second number, each transmission authorization 05 request coming from the virtual circuit bringing about 06 the calculation of the difference between the first 07 and the second number and, when the sign o~ the 08 difference is positive, the generation of an 09 authorization to transmit as well as the substitution of the value of the difference for the first number, 11 and, iE the sign of the difference is negative, the 12 generation of a signal -Eorbidding transmission as well 13 as conserving the first number, the first number 14 representing the accumulation of rights to transmit and the second number being a function of the flow 16 associate~ with the virtual circuit.
17 In accordance with the invention, the 18 generation of the signal forbidding transmission is 19 used by switching apparatus of the virtual circuit which transmit towards the source of the virtual 21 circuit a message requesting it to reduce its flow, 22 when this is possible, and, in any case, a message 23 alarming it to the loss of packets.
24 In accordance with another embodiment of the invention, a first transmission authorization 26 request detector, a clock, a counter, a storage 27 register, a subtractor, a second detector for the sign 28 of the contents of the subtractor, a control unit are 29 provided, the outputs of the counter and the storage register being connected to the operand inputs of the 31 subtractor whose output is connected to the input of 32 the counter, the counter input receiving the periodic 33 clock signal and the storage register being, at the 34 start of establishing the virtual circuit, loaded by -the control unit, each output signal of the first 36 detector triggering the operation of the second 37 detector whose output signal at a low level brings 7~
about the transmission of an authorization to transmit 2 and the loading oP the result from the subtractor into 3 the counter and, at a high level, brings about the 4 forbiddin~ o~ transmission.
In accordance with another embodiment of the 6 invention, a system capable of managing all the virtual 7 circuits processed by a switch for packets carried by 8 asynchronous time multiplexers is provided, the system 9 comprising a first memory whose words store the first numbers, and a second memory whose words store the 11 second numbers, the addresses of the f irst and second 12 memories being determined by the packet labels entering 13 in the switch, the system comprising also a label 14 receiving circuit used as the first detector, a subtractor, a second detector and a control unit.
16 In accordance with another embodiment, the 17 control unit has a microprocessor controlling the word 18 cycles of the system, each CyClQ having three phases:
19 an allocation phase during which one word of the first memory is incremented, the address of the word of the 21 first memory being incremented Erom one cycle to the 22 next, an authorization phase during which the receiving 23 circuit allows the successive addressing of the first 24 and second memories whose words which are read are subtracted in the subtractor, the second detector 26 generating the authorization or forbidding signal, as 27 well as the loading or not of the contents of the 28 subtractor into the f irst memory, and an access phase to 29 the control unit to write a new word in the second memory.
31 In accordance with another embodiment, in a 32 process for controlling the flow of packets, the packets 33 of a virtual circuit being identified by their label and 34 the identity of the multiplex which carries them, the ~9707 flow of packets from each virtual circuit is measured 2 and compared to an allocated average value and at each 3 request for transmission authorization, when it is found 4 to be less than the value, a positive difference, on one S hand, bringing about authorization to transmit and, on 6 the othar hand, is translated inko rights to transmit 7 proportional to the time lapsed since the previous 8 re~uest, the transmission rights being accumulated, or 9 when it is greater than the value, the negative difference brings about, if the number of accumulated 11 rights to transmit is positive, on one hand, the 12 authorization to transmit and, on the other hand, the 13 decrementing of the cumulative number, and if the 14 cumulative number is null, the refusal to authorize transmission.
16 In accordance with another embodiment, a 17 system for controlling the flow of packets is comprised 18 of a first detector of transmission authorization 19 requests, a clock, a counter, a storage register, a subtractor, a second detector for the sign of the 21 contents of the subtractor, a control unit, the outputs 22 of counter and storage register being connected to the 23 operand inputs of subtractor whose output is connected 24 to the input of counter, the input of counter receiving the periodic clock signal and the storage register 26 being, at the initial establishment of the virtual 27 circuit, loaded by the control unit, each output signal 28 of the first detector triggering the operation of the 29 second detector whose output signal at a low level brings about the transmission of an authorization to 31 transmit and the loading of the result of subtractor 32 into the counter and, at a high level forbids 33 transmission.
- ~a -7~37 In accordance with another embod.iment, a process Eor controlling the flow of data packets carried 3 on a plurality of virtual circuits from a plurality of 4 multiple demands, the process is comprised of the steps S of (a) identiîying each of the data packets in response 6 to each request for an authorization to transmit, each 7 data packet being identified by a label included in the 8 packet and by an identi:Eication of a multiplex channel 9 carrying the data packet; ~b) measuring the :Elow of data packets flowing on each o~ the virtual circuits and 11 comparing the measured flow with an avarage rate to 12 determine whether the measured flow is positive, 13 negative, or null with respect to the average rate; if 14 the flow compared in step (b) indicates that the measured flow of data packets is positive with respect 16 to the average flow rate, giving an authorization to 17 transmit and translating into rights to transmit which 18 are proportional to the time which has elapsed since the 19 last previous request for a transmission authorization, the rights to transmit being accumulated; (d) if the 21 flow compared in step (b) indicates that the measured 22 flow of data packets is negative with respect to the 23 average flow rate, and if the accumulated rights to 24 transmit are positive, giving an authorization to transmit and decrementing the accumulated rights; and 26 (e) if the flow compared in step (b) indicates that the 27 measured flow of data packets is negative with respect 28 to the average flow rate and if the accumulated rights 29 are nil, denying an authorization to transmit.
In accordance with another embodiment, a 31 system for controlling the flow of data packets carried 32 on a virtual circuit is comprised of a first detector of 33 transmission authorization requests, a clock for 34 delivering periodic clock signals, a counter having an 36 - 4b -~2~
1 input and output, a storage register having an ou.tput, a 2 subtractor having operand inputs and an output, a second 3 cletector for detecting the arithmatic sign of the output 4 of the subtractor, a control unit, the outputs o~ the S counter and the storage register being connected to the 6 operand inputs of the subtractor, the output of the 7 subtractor being connected to the input of the counter, 8 the input of the counter receiving the periodic clock g signal, apparatus responsive to the control unit for loading the storage register at the initial 11 establishment of the virtual circuit, appara-tus 12 responsive to each output signal of the first detector 13 for triggering an operation of the second detector, and 14 apparatus responsive to an output signal at a low level from the second detector for bringing about a 16 transmission of an authorization to transmit the data 17 packet and for loading the result of the subtractor into 18 the counter and responsive to the high level for 19 forbidding any transmission of packets via the virtual 20 circuit.
21 The above-mentioned embodiments of the 22 invention as well as others, will become clearer upon 23 reading the following descripti.on of e,mbodiment, the 24 description being done with reference to the attached drawings, among which:
26 Figure 1 is a timing diagram illustrating - 4c -.J,, 01 in a general manner the process in accordance with the 02 inven-tion, 03 Figure 2 is a block diagram of a first 04 embodiment of a system in accordance with the 05 invention, 06 Figure 3 is a schematic block diayram 07 illustrating another embodiment of the system in 08 acordance with the invention, 09 Figure 4 is a block diagram of a logic circui-t for the system of Figure 3, and 11 Figure 5 shows the timing diagrams 12 illustrating the operation of the circuits of Figures 13 3 and 4.
14 In Figure 1 is shown the instantaneous time variation of the flow di generated by a source on 16 a virtual circuit of a multiplexer, as well as an 17 average flow value. From 0 to tl, the instantaneous 18 flow is less than the value dm, which in practice 19 represents the average flow allowed. The positive difference (dm-di) brings about the accumulation of 21 the right to transmit. At the instant tl, which 22 corresponds to the instant where the curve di cuts the 23 line dm, the area of the domain I corresponds to the 24 accumulated number of rights to transmit.
From tl to t2 which will be defined below, 26 the difference (dm-di) is negative. The number of 27 rights to transmit is decremented. When the area of 28 domain II is equal to that of domain I, which defines 29 the position of t2, all rights to transmit have been restored.
31 From t2 to t3, where the curve di 32 intersects again the straight line dm in its downward 33 path, the difference (dm-di) is always negative and 34 the number of rights to transmit is nil. No authorization to transmit is given and the 36 data corresponding to the requests for authorization 37 to transmit are eliminated from the network.
7 [)7 01 AEter t3, the diference ~d~-di) becomes 02 positive again, the authorizations to transmi-t are 03 given and rights to transmit are once again 0~ accumulated.
05 In Figure 2 is shown a packet swi-tch XPAC
06 with its input junctions EPAC, its output junc-tions or 07 lines SPAC and its time base BT. The switch XPAC is 08 controlled and ordered by a control uni-t UX which 09 establishes the virtual circuits between the input junctions and the output junc-tions. For the sake of 11 an example, the junctions or lines EPAC and SPAC can 12 transmit the time multiplex such as that which i5 13 described in document EP-A-O 108 028 and the switch 14 XPAC can be of the type described in document EP-A-AO 113 639, the control unit UX thus including 1~ the control unit UCC which is a part of this 17 autoswitch.
18 In shunt with one of the input junctions 19 EPAC, namely EPACi, a framing circuit CCAD is shown which is capable of framing the packets carried by the 21 junction EPACi and extracting the labels. One input 22 f3 of the framing circuit is connected to a 23 corresponding output of the time base BT and is 24 intended to synchroni~e the extraction of labels. The output of circuit CCAD is connected to the first input 26 of a comparator COMPl whose second input is connected 27 to the output of a storage register REGl whose loading 28 input is connected to a corresponding output of -the 29 control unit UX. The output of comparator COMPl is connected to the input of a sequencer SEQ with two 31 outputs R and W. The sequencer SEQ also has a clock 32 input connected to an output of a time base BTC. The 33 output R is connected, on one hand, to the read input 34 R of a storage register REG2 and, on the other hand, to the read input R of a binary counter CPT. The 36 output W of the sequencer SEQ is connected to the 37 write input W of counter CPT.
~2~
01 The storage register REG2 has a data input 02 which is connected to a corresponding data output of 03 the control unit UX and a write input Wl which is also 04 connected to a corresponding output of the unit UX.
05 The output oE the storage register REG2 is connected 06 to the operand input B of a subtractor SOU.
07 The binary coun~er CPT, which is not a 08 cyclic counter, has a data loading input which is 09 connected to the output of subtractor SOU, an incrementing input which is connected to an output Hl 11 of time base BTC, a "1" setting input for each of the 12 cells connected to a corresponding output of the 13 control unit UX and its output is connected to the 14 operand input A of subtractor SOU.
The subtractor SOU, which carries out the 16 subtraction (A-B) has an output with the sign AAE
17 which is enabled when the diEference is negative and 18 which is connected to a corresponding input of the 19 control unit UX.
The operation of the circuit of Figure 2 21 is as follows. Upon establishing a virtual circuit on 22 the input junction EPACi, the control unit UX assigns 23 it, on one hand, a label at the beginning of each 24 packet, and, on the other hand, an average flow value. In the embodiment described, the label will be 26 "ETIj" and the average flow value "MOYj". The unit UX
27 thus writes the word ETIj in the storage register REGl 28 and the word MOYj in the storage register REG2, then 29 sets the counter CPT to the maximum count through the "1" setting input. In the example described, we will 31 assume that the counter CPT has four cells and the 32 register REG2 has five cells. Finally, we shall 33 assume the value 00011 for the word MOYj.
34 For each packet carried by the multiplexer oE junction EPACi, the circuit CCAD generates the 36 label to comparator COMPl. When the label generated 01 is the word ETIj, the comparator generates a cycle 02 triggering signal to se~uencer SEQ. Through its 03 output R, it causes the reading oE the contents of 04 counter CPT and of register REG2. The subtractor SOIJ
05 thus receives at its A input the word 1111 and at its 06 B input the word 00011. (A-B) is, on one hand, 07 positive and, on the other hand, equal to 1100. The 08 output W of sequencer SEQ causes the wri-ting of the 09 word 1100 into counter CPT. While waiting for the next label ETIj, the contents of counter CPT are 11 incremented at the rate of signal Hl supplied by the 12 time base BTC. Thus, it appears that the contents of 13 the counter increases constantly, with however a 14 maximum, for the whole duration of the commmunication on the virtual circuit concerned.
16 Two cases can occur:
17 (1) The averaga rate of appearance of the 18 labels ETIj is equal or less than that which was 19 foreseen, the contents of counter CPT should thus remain greater than the value of the word MOYj, and 21 all the packets of the communicaion concerned will be 22 admitted.
23 (2) The average rate of appearance of the 24 label ETIj becomes greater than the predetermined value, the contents of counter CPT will be reduced, in 26 spite of being incremented at the rate Hl and, at a 27 given time, the difference (A-B) will be negative, the 28 AAE output will be enabled and the control unit UX
29 will order the matrix XPAC not to transmit any more packets having the label ETIj. As we shall see below, 31 in that case the value recopied into the counter CPT
32 is that o:E the operand A and not the result of the 33 subtraction.
34 As soon as (A-B) becomes positive again, the transmission can resume.
36 I-t may be seen that the value of the two 37 word MOYj is inversely proportional to the average 38 - 8 ~
~2~
01 flow allocated and proportional to the frequency oE
02 the time base BTC.
03 We have seen above, that the number of 04 cells, in register REG2, was greater by one unit than 05 the number of cells in coun-ter CPT. This is not 06 necessary, but provides an ease of control easily 07 usable by the control uni-t UX. In fact, when the unit 08 UX wants -to completely disallow a communication, it is 09 suE-Eicient to load the word 11111 into register REG2.
B will thus be greater than A. This possibility can 11 be used when the control unit UX has declared a packet 12 source to be in error.
13 On the other hand, for some communications 14 which it deems of high priority, the control unit UX
can load 00000 into register REG2. All the packets of 16 such a communication will be transmitted.
17 It should be noted that with a switch 18 XPAC, such as that which is described in document 19 EP-A-0 113 639, each label from arriving packets is examined, to route the packet, into a programmable 21 memory intended for this purpose. The unit UX is 22 assumed capable of modifying the contents of this 23 memory, such that upon receiving a disallowed label, 24 there corresponds no routing.
The circuit of Figure 2 has permitted the 26 description of the basic operation of the packet flow 27 control system in accordance with the invention, but 28 which is applicable to a single communication. In 29 prac-tice, a really efficient control system must allow flow control on the whole set of input multiplex EPAC
31 from a packet switch and, in each multiplex EPACi, all 32 the established virtual circuits. For the sake of an 33 embodiment of the invention, a basic module is 34 provided capable of monitoring 16 entering multiplex from a switching matrix such as that which is shown in 36 Figure 8 of document EP-A-0 113 639. Hence, there 37 will be as many basic modules as switching matrices in 38 _ 9 _ ~2~
01 the first stage of a packet switch.
02 Figure 3 illustrates a 'basic modu:Le MOB
03 associated with a switching matrix XPAC with 16 04 entering multiplexer junctions or lines EPAC and 16 05 outgoing multiplexer junctions or lines SPAC, such as 06 mentioned above, the basic module MOB being controlled 07 by a control unit with a processor UX. In the matrix 08 XPAC, we have shown the input circuits CE of the 09 entering multiplexer junctions or lines EPAC, the rotation matrix MRE, the packet buffer memory MP, the 11 output rotation matrix MRS, the output circuits p/s, 12 the central control unit UCC, the routing circuit ACE
13 including the label conversion memory MC, the time 14 base CTS and the local byte clock H.
Between the matrix XPAC and the module 16 MOB, we have shown the links Dl, e, H and AAE. The 17 outgoing link Dl from XPAC generates the successive 18 labels ETI of the packets which enter into the matrix 19 XPAC. It may be recalled, that in accordance with document EP-A-O 113 639, the link Dl is connected to 21 the first output of the input rotation matrix MRE
22 which generates the lables ETl to memory MC. The link 23 e, coming from the time base CTS, serves to identify 24 the number of the entering multiplex which carries -the packet whose label is ETI, the information e carried 26 by this link playing the same role in the matrix 27 XPAC. The link H transmits the internal byte clock H
28 used in the matrix XPAC. The link AAE starts from the 29 basic module MOB towards the unit UCC which deduces the order to transmit to the memory MC to no longer 31 process a particular label ETI coming from a 32 par-ticular entering multiplexer. T'he link AAE is also 33 connected to the control unit UX.
34 Between the basic module MO and the control unit UX, are provided two write control wires 36 le' and dc', addressing wires AP, data wires DP and an 37 access con-trol wire DAP'.
01 Finally, between the control units VX and 02 UCC is provided a data exchange link LL thro~lgh which 03 the control unit UCC transmits -to the unit UX data 04 concerning the value oE the average ~low allocated to 05 a newly es-tablished communication. These data will be 06 explained below.
07 The basic module MOB, shown in Figure 3 08 comprises a set of sequencing logic LOG, which is 09 shown in detail in Figure 4, a random access memory MVD containing, -for each communication, a value to be 11 subtracted at each request for authorization to 12 transmit, a random access memory MDT containing, Eor 13 each communication, the accumulated number o~ rights 14 to transmit, with classically between the set LOG and the memories, data buses BUSDON, addressing buses 16 BUSAD and control buses.
17 The logic set LOG, Figure 4, comprises a 18 clock signal generator GEN, a control signal generator 19 GSC, a buffer MDAE storing an authorization to transmit request, a buffer MDAP storing a 21 microprocessor access request from the control unit 22 UX, an access mul-tiplexer MUXA to the address bus 23 BUSAD, an access multiplexer MUXD to the data bus 24 BUSDO~, a logic circuit ALL to allocate rights -to transmit and a logic circuit AVT to authorize 26 transmission.
27 The clock signal generator GEN comprises a 28 binary cyclic counter Cl and a logic decoder Dl. The 29 counter Cl has a clock input which receives the signal hO whose frequency is equal to the bit rate on the 31 entering multiplex of the matrix XPAC, and a zero 32 reset input RAZ which receives from this matrix the 33 signal H at the byte frequency. The counter Cl has 34 three outputs supplying the signals hl, h2 and h3 whose frequencies are respectively one half, one 36 quarter and one eighth that oE signal hO. The decoder 37 Dl receives the signals hl to h3 of counter Cl and 7(3'7 01 processes them logically to supply the sir~nals t'O to 02 t'7 which are defined by the followiny logic 03 equations:
04 t'O - hl.h2.h3 05 t'l = hl/.h2.h3 06 t'2 = hl.h2/.h3 07 _________ 08 t'7 = hl/.h2/.h3/
09 The seven outputs t'O to t'7 of decoder Dl are connected to the first inputs of eight AND gates 11 PO to P7 whose second inputs receive the signal hO
12 which samples the signals t'O to t'7 to generate 13 signals tO to t7. In practice a signal t'i is at a 14 high level for one period of hO and at the low level during the seven following periods and these signals 16 are shifted one with respect to the other. The 17 signals tO to t7 have, at the high level a duration 18 which is half that of t'O to t'7.
19 The chronograms hO, tO to t7, and t'O to t'7 of Figure 5 illustrate the signals of the same 21 name respectively.
22 The transmission rights allocation logic 23 circuit ALL comprises a counter C2, an adder Al and a 24 multiplexer Ml. The counter C2 is a modulo-N counter, where N is the number of words in the random access 26 memories MVD and MDT, and it is incremented at the 27 rate of signal t3. At the end of N periods of signal 28 t3, the counter Cl will have accomplished a complete 29 cycle supplying successively all the addresses of the memories MDT and MVD. The output of counter C2 is 31 connected to the first input of multiplexer MUXA.
32 The adder Al has its operand input A
33 connected to the data bus BUSDOM. The high level 34 corresponding to a "1" is applied to its B operand input. The adder Al has its data output connected to 36 the first input of a multiplexer Ml and its overflow 37 input connected to the control input of multiplexer 37~3~7 01 Ml, whose second input is connec-ted to the data bus 02 BUSDON. The output of mul-tiplexer Ml is connected to 03 the firs~ input of multiplexer MUXD.
04 The logic circuit AVT comprises a buffer 05 register Bl, a subtractor Sl and a multiplexer M2.
06 The input of the buffer register Bl is connected to 07 the bus BUSDON and its output is connected to the B
08 operand input of subtractor Sl whose A opexand input 09 is connected to bus BUSDO~. The subtractor Sl has an output which generates the difference (A-B) and which 11 is connected to the first input of multiplexer M2. It 12 also has a sign output which is connected, on one 13 hand, to the control input of multiplexer M2 and, on 14 the other hand, to the output AAE. The second input of multiplexer M2 is connected to bus BUSDON and its 16 output is connected to the second input of multiplexer 17 MUXD.
18 The buffer circuit MDAE comprises two 19 buffer registers B2 and B3. The inpu-t of register B2 is connected to links Dl and e which transmit the 21 data ETIj and e, and its output is connected to the 22 second input of multiplexer MUXA. The register B3 has 23 its input which receives -the value "1" and its output 24 which is connected to the DAE input of the control signal generator GSC. The two registers B2 and B3 26 have write enable inputs which are connected throuyh 27 an inverter INV, to the output of a comparator COMP2 28 one input of which is connected to link Dl and the 29 other to the output of a register Z0 in which is stored the word corresponding to the label of an empty 31 packet, such as that, for example, described in 32 document EP-A-0 108 028~
33 Each label ETIj from a packet transmitted 34 by link Dl is compared in comparator COMP2 with the empty packet label. If the result of the comparison 36 is negative, the inverter INV generates the signal 37 DAE' which indicates that there is a request to ~2~7()7 01 authorize transmission. IE the result is positive, 02 the signal DAE' is not transmitted. The signal t3 03 stores a request for authorization to transmit. The 04 buffer circuit MDAP comprises three buffer registers 05 B4 to B6. The register B4 has its input connected to 06 a bundle of wires AP coming from the control unit UX
07 and its output is connected to the third input of a 08 multiplexer MUXA. The register B5 has its input 09 connected to a bundle of wires DP coming from the control unit UX and its output is connected to the 11 third input of multiplexer MUXD. The register B6 12 receives at its input the value "1" and its output is 13 connected to the input DAP of the control signal 14 generator GSC. The three registers B4 to B6 have write enable inputs which are connected, in parallel 16 to the output DAP' of the control unit UX. The signal 17 t0 stores the access request from the unit UX.
18 The multiplexer MUXA has its output 19 connected to the address bus BUSAD while the multiplexer MUXD has its output connected to bus 21 BUSDON.
22 The inputs of control signal generator GSC
23 are the inputs DAE and DAP, already mentioned, the 24 signal inputs t'0 to t'7 and t0 to t7 connected to the generator GEN, and the inputs le' and dc' which are 26 connected to the corresponding outputs of the control 27 unit UX. The generator GSC generates, at its corres-28 ponding outputs, the signals le, dc and sel, towards 29 the control bus BUSC and signals Fhl and Ph2 towards the control inputs of multiplexers MUXA and MUXD.
31 The generator GSC is a logic circuit which 32 resolves the following logic equations:
33 sel = tO+t2+DAE.(t3+t4+t6)+DAP.t7 34 dc = DAE.t'3-~DAP.t'7.dc' le = (-t'0+t'1-~t'2-~t'3+t'4+t'5~t'6)~1.t'7 36 Phl = 0.(t'0+t'1+t'2+t'3~t'4-~t'5+t'6)+1.t'7 37 Ph2 = 0.(t'0~t'1~t'2-~t'3)+1.(t'3+t'4+t'5+t'6) 70~7 01 The timing diagram for the signals le, dc, 02 sel, Phl and Ph2 are shown in Figure 5. The signal 03 sel is at the high level to trigger all read or write 04 operation in one or the other of memories MVD and 05 MDT. The signal le/ triggers a write operation into 06 the memory MDT. The signal dc routes the reading or 07 writing towards the memory MVD while the signal dc/
08 routes the reading towards memory MDT.
09 The combination of signals Phl/ and Ph2/
point the multiplexers MUXA and MUXD towards the 11 outputs of counter C2 and multiplexer Ml, 12 respectively, to allow the allocation phase. The 13 combination Phl/ and Ph2/ point the multiplexers MUXA
14 and MUXD to the output of buffer B2 and the output of multiplexer M2, respectively, to allow the 16 authorization phase. The combination Phl and Ph2/
17 point the multiplexers MUXA and MUIXD to the outputs 18 of buffers B4 and B5 respectively, to allow read or 19 write access from the microprocessor of the unit UX.
In Figure 5, we have shown the three operational 21 phases: allocation, authori~ation and access to UX.
22 The allocation phase starts at time t0 23 with sel.le.dc/ with the transmission, through MUXA, 24 of the address contained in counter C2 to bus BUSAD in order to read the word CPT corresponding to this 26 address in memory MDT. This word CPT is transmitted, 27 by the bus BUSDON, to the operand input A of adder Al 28 which is enabled during the time tl. At the time t2, 29 the output of adder Al displays the word (CPT+l).
Whether its overflow output is enabled or not, the 31 multiplexer Ml causes the word CPT or (CPT~l) to go to 32 multiplexer MUXD in order to immediate:Ly rewrite this 33 word at the same address in memory MDT. In practice, 34 the set of circuits Al and Ml has -the only purpose of preventing an untimely return to zero of the word CPT
36 when it has reached its upper limit.
~.2~
01 The authorization phase starts at time t3 02 with sel.le.dc by the transmission, through MUXA, of 03 the address contained in buffer B2 towards the bus 04 BUS~D in order to read the word MDYj corresponding to 0~ this address in memory MVD. This word MOYj is 06 transmitted, by the bus BUSDON, to the input of buEEer 07 Bl. At time t4, with sel.le.dc/, at the same address, 08 but in memory MDT, the corresponding word CPT is read 09 and applied, by the bus BUSDON, to the operand input A
of subtractor Sl, which receives at its B operand 11 input, the word JOYj contained in buffer Bl. the 12 subtraction is carried out at time t5. If the result 13 of the operation is positive, the link A~E is at the 14 low level and this result is transmitted by the multiplexers M2 and MUXD to be written in memory MDT
16 and become the new word CPT, always at the same 17 address. If the result is negative, the link AAE is 18 at the high level, such that the multipelxer M2 19 transmits to multiplexer MUXD the previous word CPT
which is rewritten in memory MDT.
21 Of course, this authorization phase is 22 only carried out if the signal DAE' is transmitted by 23 the inverter INV, that is the label received is not 24 that of an empty packet. In other respects, we must note that at time t3, the counter C2 has been 26 incremented in anticipa-tion of the next allocation 27 phase.
28 The access phase to UX starts at time t7 29 and allows the unit UX:
- with sel.le.dc, to read in the memory MVD, 31 - with sel.le/.dc, to write in the memory MVD, 32 - with sel.le.dc/, to read in the memory MDT, and 33 - with sel.le/.dc/, to write in the memory MDT.
34 During reading or writing, -the multiplexer MUXA transmits the address contained in buffer B4 to 36 bus BUSAD. During writing, the data to be written 37 goes from buffer B5 to bus BUSDON through multiplexer 01 MUXD. During reading, the data read is transmitted to 02 the unit UX directly by the bus sUSDON.
03 I-t may be seen that a comple-te cycle lasts 04 eight periods of hO, that is eight bi-t durations of 05 the pacXets transmitted on the entering multiplex 06 junctions EPAC. Thus, each label appearing on the 07 link Dl can be processed in real time.
08 It may also be seen that upon establishing 09 a virtual circuit, the control unit UX can decide to write an initial number CPT into the memory MDT at the 11 address of the virtual circuit. If this initial 12 number is nil, it is because the control unit assigns 13 a delay at the transmission of the source.
14 In the example described in relation to Figure 2, we had assumed, otherwise, that a maximum 16 value was given to CPT.
17 It may be seen that each time a 18 communication is established, only the value of the 19 word MOYj need necessarily be fixed by the control unit, which makes the system of the invention very 21 easy to carry out.
Claims (13)
1. A process for controlling the flow of packets, the packets of a virtual circuit being identified by their label and the identity of the multiplex which carries them, the flow of packets from each virtual circuit is measured and compared to an allocated average value and at each request for transmission authorization, when it is found to be less than said value, a positive difference, on one hand, bringing about authorization to transmit and, on the other hand, is translated into rights to transmit proportional to the time lapsed since the previous request, the transmission rights being accumulated, or, when it is greater than the said value, the negative difference brings about, if the number of accumulated rights to transmit is positive, on one hand, the authorization to transmit and, on the other hand, the decrementing of the said cumulative number, and if the cumulative number is null, the refusal to authorize transmission.
2. A process in accordance with claim 1, further including initially allocating a virtual circuit, on one hand, a first number which is then incremented at a fixed rate, independently of the rate of the virtual circuit, and, on the other hand, a second number, each request for authorization to transmit coming from the virtual circuit bringing about the computation of the difference between the first and the second number and, when the sign of this difference is positive, the generation of an authorization to transmit as well as the substitution of the value of the difference for the first number, and, if the sign of the difference is negative, the generation of a signal forbidding transmission as well as conservation of the first number, the first number representing the accumulation of transmission rights and the second number being a function of the average flow allocated to the virtual circuit and the incrementing rate of the first number.
3. A process in accordance with claim 1 or 2, whereby the generation of the signal forbidding transmission is used by switching means of the virtual circuit which transmits to the source of the virtual circuit a message asking it to reduce its flow, when this is possible, and, in any case, a message notifying it of the loss of packets.
4. A process in accordance with claim 2 in which the second number is selected larger than an upper bound of the first number in order to forbid the transmission of any packet belonging to the virtual circuit concerned.
5. A process in accordance with claim 2 in which the second number is selected to be nil to transmit all the packets of the virtual circuit concerned.
6. A system for controlling the flow of packets comprised of a first detector of transmission authorization requests, a clock, a counter, a storage register, a subtractor, a second detector for the sign of the contents of the subtractor, a control unit, the outputs of counter and storage register being connected to the operand inputs of subtractor whose output is connected to the input of counter, the input of counter receiving the periodic clock signal and the storage register being, at the initial establishment of the virtual circuit, loaded by the control unit, each output signal of the first detector triggering the operation of the second detector whose output signal at a low level brings about the transmission of an authorization to transmit and the loading of the result of subtractor into the counter and, at a high level forbids transmission.
7. A system in accordance with claim 6 for managing all the virtual circuits processed by a packet switch carried by asynchronous time multiplexers, further comprising a first memory whose words store the said first numbers and a second memory whose words store the second numbers, the addresses of the first and second memories being determined by the identities of the packets entering into the said switch, the system comprising also a label receiving circuit being used as a first detector, a subtractor, a second detector and a control unit.
8. A system in accordance with 7, in which the control unit contains a microprocessor for controlling the activity cycles of the system, each cycle comprising three phases: an allocation phase during which one word of the first memory is incremented, the address of the said word of the first memory being incremented by one cycle to the next, an authorization phase during which the said receiver circuit allows the successive addressing of the first and second memories whose words read are subtracted in the subtractor, the second detector generating the authorization or not signal as well as the loading or not of the contents of the subtractor into the first memory, and an access phase to the control unit to read or write a new word in one of the two memories.
9. A process for controlling the flow of data packets carried on a plurality of virtual circuits from a plurality of multiple demands, said process comprising the steps of:
(a) identifying each of said data packets in response to each request for an authorization to transmit, each data packet being identified by a label included in said packet and by an identification of a multiplex channel carrying the data packet;
(b) measuring the flow of data packets flowing on each of said virtual circuits and comparing said measured flow with an average rate to determine whether the measured flow is positive, negative, or null with respect to said average rate;
(c) if the flow compared in step (b) indicates that the measured flow of data packets is positive with respect to the average flow rate, giving an authorization to transmit and translating into rights to transmit which are proportional to the time which has elapsed since the last previous request for a transmission authorization, the rights to transmit being accumulated;
(d) if the flow compared in step (b) indicates that the measured flow of data packets is negative with respect to the average flow rate, and if the accumulated rights to transmit are positive, giving an authorization to transmit and decrementing said accumulated rights; and (e) if the flow compared in step (b) indicates that the measured flow of data packets is negative with respect to the average flow rate and if the accumulated right are nil, denying an authorization to transmit.
(a) identifying each of said data packets in response to each request for an authorization to transmit, each data packet being identified by a label included in said packet and by an identification of a multiplex channel carrying the data packet;
(b) measuring the flow of data packets flowing on each of said virtual circuits and comparing said measured flow with an average rate to determine whether the measured flow is positive, negative, or null with respect to said average rate;
(c) if the flow compared in step (b) indicates that the measured flow of data packets is positive with respect to the average flow rate, giving an authorization to transmit and translating into rights to transmit which are proportional to the time which has elapsed since the last previous request for a transmission authorization, the rights to transmit being accumulated;
(d) if the flow compared in step (b) indicates that the measured flow of data packets is negative with respect to the average flow rate, and if the accumulated rights to transmit are positive, giving an authorization to transmit and decrementing said accumulated rights; and (e) if the flow compared in step (b) indicates that the measured flow of data packets is negative with respect to the average flow rate and if the accumulated right are nil, denying an authorization to transmit.
10. The process of claim 9 and the further step of:
(1) initially allocating first and second numbers to each of said virtual circuits, said first number representing the accumulated transmission rights and said second number representing an average rate of data packet flow allocated to the concerned virtual circuit, incrementing said first number at a fixed rate which is independent of the flow of the concerned virtual circuit having said first number allocated thereto, computing a difference between said first and second number assigned to the concerned virtual circuit in response to each request for an authorization to transmit which is received from the virtual circuit, (2) if the sign of the difference computed in step (1) is positive, generating an authorization to transmit and a substitution of the computed difference for the first number allocated to said concerned virtual circuit, and (3) if the sign of the difference computed in (1) is negative, generating a signal forbidding transmission and preserving the existing file number.
(1) initially allocating first and second numbers to each of said virtual circuits, said first number representing the accumulated transmission rights and said second number representing an average rate of data packet flow allocated to the concerned virtual circuit, incrementing said first number at a fixed rate which is independent of the flow of the concerned virtual circuit having said first number allocated thereto, computing a difference between said first and second number assigned to the concerned virtual circuit in response to each request for an authorization to transmit which is received from the virtual circuit, (2) if the sign of the difference computed in step (1) is positive, generating an authorization to transmit and a substitution of the computed difference for the first number allocated to said concerned virtual circuit, and (3) if the sign of the difference computed in (1) is negative, generating a signal forbidding transmission and preserving the existing file number.
11. The process of claim 9 or 10 further including the steps of generating a signal requesting the concerning virtual circuit to reduce the rate at which its data packets flow in response to a non-authorization of transmission signal and of returning a message to said concerned virtual circuit indicating any loss of said data packets during transmission.
12. A system for controlling the flow of data packets carried on a virtual circuit, said system comprising, a first detector of transmission authorization requests, a clock for delivering periodic clock signals, a counter having an input and output, a storage register having an output, a subtractor having operand inputs and an output, a second detector for detecting the arithmetic sign of the output of the subtractor, a control unit, the outputs of the counter and the storage register being connected to the operand inputs of the subtractor, the output of said subtractor being connected to the input of the counter, the input of the counter receiving the periodic clock signal, means responsive to the control unit for loading the storage register at the initial establishment of said virtual circuit, means responsive to each output signal of the first detector for triggering an operation of the second detector, and means responsive to an output signal at a low level from said second detector for bringing about a transmission of an authorization to transmit the data packet and for loading the result of the subtractor into the counter and responsive to a high level for forbidding any transmission of packets via the virtual circuit.
13. The system in accordance with claim 12 and a plurality of virtual circuits, asynchronous time multiplexers including packet switch means, means for managing all of the virtual circuits in response to processing by said packet switch means, said system further comprising a first memory storing first numbers developed from said output signal of said first detector, and a second memory storing second numbers developed from said output signal of said second detector, and addresses of the first and second memories being determined by the identities of the packets entering into the said packet switch means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8707556A FR2616025B1 (en) | 1987-05-26 | 1987-05-26 | METHOD AND SYSTEM FOR PACKET FLOW CONTROL |
| FR8707556 | 1987-05-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1299707C true CA1299707C (en) | 1992-04-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000567644A Expired - Lifetime CA1299707C (en) | 1987-05-26 | 1988-05-25 | Process and packet flow control system |
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| US (1) | US4896316A (en) |
| EP (1) | EP0293314B1 (en) |
| JP (1) | JP2630812B2 (en) |
| CA (1) | CA1299707C (en) |
| DE (1) | DE3866953D1 (en) |
| ES (1) | ES2028351T3 (en) |
| FR (1) | FR2616025B1 (en) |
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| FR2643532B1 (en) * | 1989-02-17 | 1991-05-10 | France Etat | METHOD FOR RESERVING RATES AND TIME SWITCHES OF ASYNCHRONOUS PACKETS |
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| FR2648645B1 (en) * | 1989-06-20 | 1991-08-23 | Cit Alcatel | METHOD AND DEVICE FOR EVALUATING THE THROUGHPUT OF VIRTUAL CIRCUITS EMPLOYING A TIME-MULTIPLEXED TRANSMISSION CHANNEL |
| FR2648648B1 (en) * | 1989-06-20 | 1991-08-23 | Cit Alcatel | METHOD AND DEVICE FOR EVALUATING THE FLOW RATE OF CIRCUITS EMPLOYING AN ASYNCHRONOUS TIMED MULTIPLEXED TRANSMISSION CHANNEL |
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-
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- 1987-05-26 FR FR8707556A patent/FR2616025B1/en not_active Expired
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1988
- 1988-04-18 US US07/182,940 patent/US4896316A/en not_active Expired - Lifetime
- 1988-04-26 DE DE8888460006T patent/DE3866953D1/en not_active Expired - Lifetime
- 1988-04-26 EP EP88460006A patent/EP0293314B1/en not_active Expired - Lifetime
- 1988-04-26 ES ES198888460006T patent/ES2028351T3/en not_active Expired - Lifetime
- 1988-05-25 CA CA000567644A patent/CA1299707C/en not_active Expired - Lifetime
- 1988-05-26 JP JP12722288A patent/JP2630812B2/en not_active Expired - Fee Related
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| EP0293314A1 (en) | 1988-11-30 |
| JP2630812B2 (en) | 1997-07-16 |
| FR2616025B1 (en) | 1989-07-21 |
| ES2028351T3 (en) | 1992-07-01 |
| FR2616025A1 (en) | 1988-12-02 |
| DE3866953D1 (en) | 1992-01-30 |
| EP0293314B1 (en) | 1991-12-18 |
| US4896316A (en) | 1990-01-23 |
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