CA1308811C - Method and apparatus for implementing a prml code - Google Patents
Method and apparatus for implementing a prml codeInfo
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- CA1308811C CA1308811C CA000572185A CA572185A CA1308811C CA 1308811 C CA1308811 C CA 1308811C CA 000572185 A CA000572185 A CA 000572185A CA 572185 A CA572185 A CA 572185A CA 1308811 C CA1308811 C CA 1308811C
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/04—Conversion to or from representation by pulses the pulses having two levels
- H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
- H03M5/145—Conversion to or from block codes or representations thereof
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/497—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems
Abstract
ABSTRACT OF THE INVENTION
METHOD AND APPARATUS FOR IMPLEMENTING A PRML CODE
A rate 8/9, constrained partial response class IV
code having run length limitation parameters (0,3/5) is provided for any partial response (PR) signaling system employing maximum likelihood (ML) detection.
METHOD AND APPARATUS FOR IMPLEMENTING A PRML CODE
A rate 8/9, constrained partial response class IV
code having run length limitation parameters (0,3/5) is provided for any partial response (PR) signaling system employing maximum likelihood (ML) detection.
Description
~ 1 308~ 1 1 METHOD AND APPARATUS FOR IMPLEMENTING A PRML CODE
CROSS REFE~ENCE TO RELATED APPLICATION
The present invention is related to Canadian application S.N. 532,490 entitled "Method and A~paratus for Implementing Optimum PRML Cocles" filed April 14, 1987.
BACKGROUND OF THE INVENTION
Field of the Invention This invention relates to techniques for encoding data. More particularly, it relates to a Partial Response Maximum Likelihood technique for encoding a preselectable number of bits of binary data into codewords having a preselectable number of bits on a class-IV channel using a run length limited (RLL) code.
DESCRIPTION OF THE RELATED ART
Partial Response Maximum Likelihood techniques have long been associated with digital communication channels.
ML detection is typically used in PR class-IV channels (hereinafter, the acronym PRML is used to denote the combination of PR class-IV channels with ML detection).
Further, encoding data for use with recording channels is also known. The ~d,k~ cons-traints, which specify the minimum and maximum run lengths of zeroes, respectively, in RLL codes used in peak-detection systems, reduce intersymbol interferences (hereinafter, ISI) while maintaining self-clocking characteristics of the data signal. See, for example, IBM TECHNICAL
DISCLOSURE BULI,ETIN, Vol. 28, No. 5, October 1985, pp.
1938-1940, entitled "Improved Encoder and Decoder for a Byte-Oriented (0,3) 8/9 Code", IBM TECHNICAL DISCLOSURE
BULLETIN, Vol. 18, No. 1, June 1975, pp. 248-251, entitled "Encoder and Decoder for a Byte-Oriented ~0,3) 8/9 Code", and the above-identified related application S.N.
`~k -~ 1 3nssl 1 532,490 which discloses both a (0,3/6~ and a (0,4/4) PRML
method and apparatus.
In a PRML channel, a channel code can also be used to provide clocking and automatic gain control (AGC) information. Since the maximum run length of nominally zero samples must be limited, the k constraint is still appropriate when specifying the channel code requirements for PRM~ channels. However, RLL codes with d greater than zero are not necessary in PRML charmels because compensation for ISI is inherent in the ML detector.
Thus, there is no need to reduce interference by coding with a d constraint.
On the other hand, the k constraint is not the only constraint re~lired for the PRML channel. The kl constraint is an additional constraint that is used to limit both detector delay and hardware complexity. If a data sequence of the input signal is demultiple~ed into an even indexed sample subsequence and an odd indexed sample subsequence, and ML detection is applied to each subsequence independently, a constraint on the number of successive nominally zero samples in each subsequence adequately limits the detector delay and hardware. Thus, in terms of NRZI data representation, the required limitation is on the maximum number of sequential zexoes in both the even-indexed and the odd-indexed subsequences. The maximum number of sequential NRZI
zeroes in either subsequence is referred to as the kl constraint, and is analogous to the k constraint for the interleaved sequence of data.
Codes having run length constraints restrict the allowed code sequences to less than 2 to the power o~ n sequences possible, where n specifies the number of data symbols in a sequence. The rate of such a code is less than 1 data bit to 1 code bit, which can be expressed as a ratio of small integers. Thus, if an 8-bit data byte is mapped into a 9-bit codeword, the code rate is 8/9.
The (0,3/6) and ~0,4/4) codes disclosed by Eggenberger differ in the following manner. The k parameter is desirable for accurate timing and gain control.
. sAs86-013 `` 1308~1 1 Therefore, the (0,3/6) code disclosed by Eggenberger, which uses a smaller value of k (3) will provide more accurate timing and gain control than the (0,4/4) code.
However, it has a disadvantage relative to the (0,4/4) code in that it requires more hardware in the Viterbi detector path memory. Alternatively, a small k1 parame-ter will reduce the size of the path memory required in the ML detector. Therefore, the (0,4/4) code will re--- quire a smaller path memory t:han the (0,3/6) code.
Likewise, the (0,4/4) code has a disadvantage relative to the (0,3/6) code in that it ~oes not have timing and gain control equal to the (0,3/6) code. Since these codes cannot be simultaneously used, a design choice must be made depending on the relative importance of the advan-tages inherent in each code.
SUMMARY OF THE INVENTION
It is an object of this invention to implement a single class-IV PRML modulation code which has the timing and gain control advantages of the (0,3/6) PRML code, and the reduced Viterbi detector path memory hardware re-quirement advantages of ~he (O,4/4) PRML code.
This and other objects will become apparent when read in light of the accompanying specification and drawings. The above object is carried out by a ~0,3/5) ~5 modulation code suitable for class-IV PR channels employ-ing ML detection. The (0,3/5) code receives input data comprised of a preselectable number of bits of binary data which are encoded into sequences of codewords having a preselectable number of bits. The sequences of codewords are arranged into odd and even interleaved subsequences, each sequence having no more than three consecutive zero bits of binary data and each odd and even subsequence having no more than five consecutive zero bits of binary data. In like fashion, the codewords produced by the encoder can be used as input to a decoder. The decoder receives the codewords and produces sequences of binary data in response to the codewords.
_ , ~
.~.
:
S.~986-013 '1 DESCRIPTION OF TIIE DF~INGS
Fig. 1 is a schematic diagram of a PRML system modulation code encodcr for a code having rate 8/9 and run length constraillts (0,3/5) t constructed according to the principles of the present invention.
Fig. 2 is a schema~ic diagram of a P~L system modulation code decoder for a code having rate 8/9 and run length constraints (0,3/5), constructed according to the principles of the present invention.
DESCRIPTION ~F THE PP~EFERRED EMBODIMENT
In accordance with the present invention, a method and apparatus is disclosed for encoding and decoding a preselectable number of binary bits into codewords having a preselectable number of hits. The methcd and a paratus utilize a (0,3/5) P~IL modulation code to encode 8 bit binary data into codewords com~rised of 9 bit code se-quences. The maximum number or consecutive zeroes 21-lowed within a code sequence is 3, and the ma~imum number of consecutive ~eroes in the all-even or all-odd subse-2~ quences i~ 5.
The (0,3/5) code is designed for a speciric partial response (P~) char.nel, namely ,he so-called "class-IV"
PR. Class-IV par_ial r~sponse refers to a channel re-sponse whose output wave-orm is described bv takins the ~s input wave~orm, and subtracting from it the same wa~eform dela~red by 2 bit intervals. This is desc~ibed disiLally in terms of a channel polvnomial, P(D). For class-IV
partial response: ~ ;
P(D) = (l-D ) The polynomial describes the effect of the channel on digital inputs. The D operator means~"delay one bit time", and D2 means "delay 2 bit times." Therefore, the class-IV channel produces output sample U at time t which `
is equal to the input W at time t, minus the input l~ at time t-2. In othe~ words:
,,, :
:
~.
S
1 308~ 1 1 t t Wt_2 (2) The modulation code is characterized by three param-eters d, k, and k1 written (d,k/kl). The parameters d and k represent the minimum and ma~imum run lengths of zeroes in the channel output code bit sequence, where a run length of zeroes may be regarded as a period of silence in the detection proc:ess. The parameter k1 represents the maximum run length of zeroes in the par~
ticular all-even or all-odd subsequences. In the present invention, d equals 0 since a minimum run length of zeroes is inapposite in the context of PRML channel. The value of k is set to three and the value of kl is set to 5. A small value of k is desirable for accurate timing and gain control, and a small value of kl reduces the size of the path memory required in the ML detector.
A rate 8/9 RLL block code having (0,3/5) constraints provides at most 251 9-bit codewords from 8-bit data bytes. Two hundred fifty six codewords can be derived by excluding the all-ones codeword and adding ~ state depen-dent codeword pairs for two state encoding. The states 1 and 2 are identified by the value of the last bit of the previous codeword concatenation. Thus, 256 codewords of 9 bits each can be defined where all catenations of such codewords comply with the d,k/kl constraint and two state encoding is used. The code provides for specific assign-ment of 8-bit data bytes to 9~bit codewords which creates partitions of bytes and codewords with similar structure.
The partitions of bytes are uniquely identifiable and overall mapping of the codewords is produced by gating partition bits according to simple boolean functions.
If Y denotes a 9-bit codeword in the (0,3/5) code, then Y lYl' Y2' Y3~ Y4. Y5, Y6, Y7, Y8, Yg] (3) The constraint k = 3 in the overall coded sequence can be produced by eliminating 9~bit sequences with run lengths of 3 zeroes at the left end thereo, run lengths of 2 zeroes at the right end thereof, or run lengths of 4 zeroes within each 9-bit sequence. Such a constraint is given by the following boolean relation:
(Yl+Y2~Y3) (Y2+Y3+Y4+Ys) (Y3+Y4+Y5+Y6) (Y4~Y5~Y6~Y7) S (Y5+Y6+Y7+Y8) (Y8+Y9) = 1 (~) Similarly, the constraint k1 = 5 is described by the following two equations for the sequence of all odd-bit positions and the sequence of all even-bit positions, respectively, in Equations (5) and (6) given below.
lo (Yl+Y3+Y5) (Ys+Y7+Yg) = 1 (5) : (Y2+Y~+Y6~y~) = 1 (6) Two hundred fifty one valid 9-bit binary sequences satisfy Equations (4), (5), and (6), the decimal equiva-lents for which are given in Table III.
5: Referring now to Fig. 1, an 8-bit binary data byte, denoted X, and its assigned 9-bit codeword, Y, are given by: :
X [Xl~ X~, X3, X4, X5, X6, X7, X8] (7) y [Y1, Y2, Y3, Y4, Ys~ Y6~ Y7~ Y8~ Yg] (8) The first:partition of codeword assignments, denoted~
M, comprises the set of data bytes in which the first and : last four bits of the 8-bit binary data bytes can be : mapped without change into the first and last four bits, respectively, of the 9-bit codeword, YO The middle bit, i.e. the fifth bit position, of the 9-bit codeword in this partition is always 1. Thus, partition M comprises : ~:;
: 162 codewords which can be identified by the relation:
M1 = ~X1~X2~X3~): (9~ :
: `
M2 tX7+X8) : (10) ..
-:
:
~.~
1 308~ 1 1 3 ( 2 X4 X5 X7) (11) M = M1M2M3 (12) The remaining codeword assignments are divided into 1' Rl, S1~ N2~ R2 and S2, which identify 24 25, 9, 10, 20 and 6 codeword assignments, respectively.
These assignments are given by the following structures - of the bits in X:
N1 - M2(~1+X3)Y~4 (13) Rl = ~l2(X2+~-5X6)~ 1 3 4 (14) lo 1 2( 2 5 ~)( 1 3) 4 (15) N2 = M1[';g+X6)X5 (16) R2 M1(X8+~6)~`~ (17) 52 = ~l3~Xl+x3 )xa ( 18) The six state-dependent codewords, together with decimal equivalents of the possible values, are given in Table IV.
To avoid an all ones coded sequence, the middle bit, Y5, is changed to zero which, in turn, creates another valid codeword. The par~ition E derines the ail-ones codeword as follows:
: -E = XlX2X3X4X5X6X7X8 (19) The lo~ic equations for encoder 100 of Fig. 1 are given ln Tab]e I.
The decoder function of Fig. 2 identifies the same partitions as those in the encoder, using the exclusive structures of bit patterns in the 9-bit sequence Y to obtaîn logic equations ~or the components of X. Decoder equations for the decoder 300 of Fig. 2 are provided in Table II.
Referring now to Fig. 1, encoded variables, X1-X8 enter encoder 100 at receiver lines X1 to X8 of encoder ~~ 8 l 3 n88ll 100. The receiver lines X1 to X8 are coupled to encoder gates 102-274. In response to such variables, codewords are produced by encoder gates 102-274 in the following manner. Encoder gates 102-146 produce codeword parti-~ Nl, Rl, Sl~ N2, R2, S2, and ~ respectively-Finally, encoded variables Y1-Yg are produced by encoder gates 148-164, 166-182, 184-194, 196-204, 206-~10, 212-220, 222-234, 236-254 and 256-274, respectively.
Coded variables, Yl-Yg, enter decoder 300 at receiv-er lines Y1 to Yg as shown in Fig. 2. The receiver lines Yl to Yg are coupled to decode:r gates 302-426. Backward reading, codeword partitions, E, M, Nl, R1, and S1, for recreating uncoded variables, i.e. the data, are produced by decoder gates 302-322, respectively, in response to coded variables Yl-Yg. Similarly, partitions N2, R2 and S2 are produced by decoder ga-tes 324-328, respectively.
Finally, the data, ~l-X8, is provided by decoder gates 330-340, 342-348, 350-364, 366-374, 376-390, 392-410, 412-418 and 4~0-426, respectively.
The code described in this specification is an optimum code in that k cannot be decreased without de-creasing the rate. Similarly, k1 cannot be decreased without increasing k, decreasing the rate, increasing the codeword length, or increasing the number of encoder states. This modulation code provides a reduced k param-eter (k=3) relative to the (0,4/4) code ~k=4) for im-proved timing and gain control information, and it achieves this without increasing the k1 parameter as much as the (0,3/6) code (kl=5 versus k1=6). The kl parameter directly influences the hardware requirements in the Viterbi detector path memory, as well as the size of the most probable error bursts. The maximum error propagation of the (0,3/5) code is the same as that of the tO,3/6) code.
While the invention has been particularly shown and described with reference to a preferred embodiment there-of, it will be understood by those skilled in the art that various changes in detail may be made therein with-out departing from the spirit, scope and teaching of the invention. For example, a software implementation of the S~9-86-013 ,.. ~
encoder ancl decoder circuit functions is possible.
Accordingly, the apparatus and method herein disclosed are to be considered merely as illustrative, and the invention is to be limited only as specified in the claims.
-- lO 1 3088 1 1 TABLE I
(0,3/5) Encoder Partitions:
Ml =(Xl + X2 X3) Nl = M2(Xl ~ X3)X4 2 ( 7 x8) N2 = Ml~X8 + X6) 5 3 (X2 ~ X4 + Xs -~ X7) 1 M2(X2 + X5X6)(Xl + X3)X4 M = MlM2M3 R2 = Ml(Xg + X6) 5 E = XlX2X3X4X5X6X7X8 Sl = M2(X2 + X5X6)(Xl + X3)X4 S2 = M3(Xl + X3)X8 Encoding Functions:
1 ( l)Xl RlX~ ~ R2(X4 + X7) ~ $1X3tXl + X6) y = (EM + Nl)X2 + R~X3 + R2(x4 -~_X7) SlXl 2( 3 ~ Nl)X3 + N2 + RlXl + R2(X4 + X7) + S
Y4 = (EM + Nl~)X4 + N2X4 + Rl 2 Y5 = EM + 52~PAsT) Y6 = (EM + N2)X5 + Rl + R2 S2 6 y = (M + N2)X6 + Nl(X5 + X6) + RlX6 + R2X8 1 2 Y = (M+N )X + Nl(X5 + X6~ + RlX5 + R2X6 ~ Sl( 1 6 2 1 y = ~EM + N2)X~ -~ Nl(Xs + X6) + RlX2 R2X5 1 5 2 3 Pa~t = Last digit; in:previous codeword (set PAST=0 for (0,3/6) code).
TABLE II
(0,3/5) Decoder Partitions:
E = YlY2Y4Y5Y6Yg Rl = M(Yl + Y2 3) 4 6 M = Y5(Yl + Y2 + Y3) + E R2 = M(Yl + Y2)Y4Y6 Nl = M(Yl + Y3)Y4Y6 S ~Y ~
N2 MYlY2Y3Y6 2 ( 1 Y3) Encoding Functions:
Xl ~ E + (M + Nl)Yl + RlY3 + SlY2 S2Y8 X2 = E + (M + Nl)Y2 Rl 9 X3 = (M + Nl)Y3 -~ RlY2 + Sl(Yl 2) 2 9 X4 = E + (M + Nl~Y4 + N2Y4 ~ RlYl R2YlY2 X5 = E + (M + N2~Y6 + NlYgYg ~ RlY8 + R2Y9 1 9 X6 = ~M -~ N2)Y7 + NlY7Yg + RlY7 + R2Y8 + Sl(llY2 Y8) 2 6 X7 = (M + N2)Y8 + R2Y2Y3 X8 = E + (M + N2)Yg + R2Y7 S2 " 12 l 3088ll TABLE III
List of 251 9-bit words (converted to decimal) which can be freely concatenated to form strings satisfying the (0,3/5) constraint:
71 73 75 77 78 79 ~32 83 86 87 89 90 91 93 94 95 g9 lOl 102 103 105 107 109 110 111 113 114 115 117 118 119 121 122 178 179 181 182 183 185 1~86 187 189 190 191 197 19~ 199 201 203 205 441 442 443 445 446 447 453 454 455 45'7 459 461 462 463 465 466 467 .. .
~. SA986-013 " 1 3088 1 1 TABLE IV
List of the six state-dependent codewords:
0 A 0 l.B 1 1 1 1 where A = ~ (PAST) B = (PAST) PAST being a binary variable that defines the state and is given by the last digit of the preceding codeword. The possible values of codewords which may result are:
State 1State 2 DATA (PAST~ PAST=0) 00100001 (33) 000110101 (53) 010100101 (165) 00100101 (37) 000111101 (61) 010101101 (173) 10000001 (129) 000110110 (54) 010100110 (166) 10000101 (133) 000111110 (62) 010101110 (174) 10100001 (161) 000110111 (55) 010100111 (167) 10100101 (165) 000111111 (63) 010101111 (175) . ~ ,, .
, ~1 3 .. ", , :
CROSS REFE~ENCE TO RELATED APPLICATION
The present invention is related to Canadian application S.N. 532,490 entitled "Method and A~paratus for Implementing Optimum PRML Cocles" filed April 14, 1987.
BACKGROUND OF THE INVENTION
Field of the Invention This invention relates to techniques for encoding data. More particularly, it relates to a Partial Response Maximum Likelihood technique for encoding a preselectable number of bits of binary data into codewords having a preselectable number of bits on a class-IV channel using a run length limited (RLL) code.
DESCRIPTION OF THE RELATED ART
Partial Response Maximum Likelihood techniques have long been associated with digital communication channels.
ML detection is typically used in PR class-IV channels (hereinafter, the acronym PRML is used to denote the combination of PR class-IV channels with ML detection).
Further, encoding data for use with recording channels is also known. The ~d,k~ cons-traints, which specify the minimum and maximum run lengths of zeroes, respectively, in RLL codes used in peak-detection systems, reduce intersymbol interferences (hereinafter, ISI) while maintaining self-clocking characteristics of the data signal. See, for example, IBM TECHNICAL
DISCLOSURE BULI,ETIN, Vol. 28, No. 5, October 1985, pp.
1938-1940, entitled "Improved Encoder and Decoder for a Byte-Oriented (0,3) 8/9 Code", IBM TECHNICAL DISCLOSURE
BULLETIN, Vol. 18, No. 1, June 1975, pp. 248-251, entitled "Encoder and Decoder for a Byte-Oriented ~0,3) 8/9 Code", and the above-identified related application S.N.
`~k -~ 1 3nssl 1 532,490 which discloses both a (0,3/6~ and a (0,4/4) PRML
method and apparatus.
In a PRML channel, a channel code can also be used to provide clocking and automatic gain control (AGC) information. Since the maximum run length of nominally zero samples must be limited, the k constraint is still appropriate when specifying the channel code requirements for PRM~ channels. However, RLL codes with d greater than zero are not necessary in PRML charmels because compensation for ISI is inherent in the ML detector.
Thus, there is no need to reduce interference by coding with a d constraint.
On the other hand, the k constraint is not the only constraint re~lired for the PRML channel. The kl constraint is an additional constraint that is used to limit both detector delay and hardware complexity. If a data sequence of the input signal is demultiple~ed into an even indexed sample subsequence and an odd indexed sample subsequence, and ML detection is applied to each subsequence independently, a constraint on the number of successive nominally zero samples in each subsequence adequately limits the detector delay and hardware. Thus, in terms of NRZI data representation, the required limitation is on the maximum number of sequential zexoes in both the even-indexed and the odd-indexed subsequences. The maximum number of sequential NRZI
zeroes in either subsequence is referred to as the kl constraint, and is analogous to the k constraint for the interleaved sequence of data.
Codes having run length constraints restrict the allowed code sequences to less than 2 to the power o~ n sequences possible, where n specifies the number of data symbols in a sequence. The rate of such a code is less than 1 data bit to 1 code bit, which can be expressed as a ratio of small integers. Thus, if an 8-bit data byte is mapped into a 9-bit codeword, the code rate is 8/9.
The (0,3/6) and ~0,4/4) codes disclosed by Eggenberger differ in the following manner. The k parameter is desirable for accurate timing and gain control.
. sAs86-013 `` 1308~1 1 Therefore, the (0,3/6) code disclosed by Eggenberger, which uses a smaller value of k (3) will provide more accurate timing and gain control than the (0,4/4) code.
However, it has a disadvantage relative to the (0,4/4) code in that it requires more hardware in the Viterbi detector path memory. Alternatively, a small k1 parame-ter will reduce the size of the path memory required in the ML detector. Therefore, the (0,4/4) code will re--- quire a smaller path memory t:han the (0,3/6) code.
Likewise, the (0,4/4) code has a disadvantage relative to the (0,3/6) code in that it ~oes not have timing and gain control equal to the (0,3/6) code. Since these codes cannot be simultaneously used, a design choice must be made depending on the relative importance of the advan-tages inherent in each code.
SUMMARY OF THE INVENTION
It is an object of this invention to implement a single class-IV PRML modulation code which has the timing and gain control advantages of the (0,3/6) PRML code, and the reduced Viterbi detector path memory hardware re-quirement advantages of ~he (O,4/4) PRML code.
This and other objects will become apparent when read in light of the accompanying specification and drawings. The above object is carried out by a ~0,3/5) ~5 modulation code suitable for class-IV PR channels employ-ing ML detection. The (0,3/5) code receives input data comprised of a preselectable number of bits of binary data which are encoded into sequences of codewords having a preselectable number of bits. The sequences of codewords are arranged into odd and even interleaved subsequences, each sequence having no more than three consecutive zero bits of binary data and each odd and even subsequence having no more than five consecutive zero bits of binary data. In like fashion, the codewords produced by the encoder can be used as input to a decoder. The decoder receives the codewords and produces sequences of binary data in response to the codewords.
_ , ~
.~.
:
S.~986-013 '1 DESCRIPTION OF TIIE DF~INGS
Fig. 1 is a schematic diagram of a PRML system modulation code encodcr for a code having rate 8/9 and run length constraillts (0,3/5) t constructed according to the principles of the present invention.
Fig. 2 is a schema~ic diagram of a P~L system modulation code decoder for a code having rate 8/9 and run length constraints (0,3/5), constructed according to the principles of the present invention.
DESCRIPTION ~F THE PP~EFERRED EMBODIMENT
In accordance with the present invention, a method and apparatus is disclosed for encoding and decoding a preselectable number of binary bits into codewords having a preselectable number of hits. The methcd and a paratus utilize a (0,3/5) P~IL modulation code to encode 8 bit binary data into codewords com~rised of 9 bit code se-quences. The maximum number or consecutive zeroes 21-lowed within a code sequence is 3, and the ma~imum number of consecutive ~eroes in the all-even or all-odd subse-2~ quences i~ 5.
The (0,3/5) code is designed for a speciric partial response (P~) char.nel, namely ,he so-called "class-IV"
PR. Class-IV par_ial r~sponse refers to a channel re-sponse whose output wave-orm is described bv takins the ~s input wave~orm, and subtracting from it the same wa~eform dela~red by 2 bit intervals. This is desc~ibed disiLally in terms of a channel polvnomial, P(D). For class-IV
partial response: ~ ;
P(D) = (l-D ) The polynomial describes the effect of the channel on digital inputs. The D operator means~"delay one bit time", and D2 means "delay 2 bit times." Therefore, the class-IV channel produces output sample U at time t which `
is equal to the input W at time t, minus the input l~ at time t-2. In othe~ words:
,,, :
:
~.
S
1 308~ 1 1 t t Wt_2 (2) The modulation code is characterized by three param-eters d, k, and k1 written (d,k/kl). The parameters d and k represent the minimum and ma~imum run lengths of zeroes in the channel output code bit sequence, where a run length of zeroes may be regarded as a period of silence in the detection proc:ess. The parameter k1 represents the maximum run length of zeroes in the par~
ticular all-even or all-odd subsequences. In the present invention, d equals 0 since a minimum run length of zeroes is inapposite in the context of PRML channel. The value of k is set to three and the value of kl is set to 5. A small value of k is desirable for accurate timing and gain control, and a small value of kl reduces the size of the path memory required in the ML detector.
A rate 8/9 RLL block code having (0,3/5) constraints provides at most 251 9-bit codewords from 8-bit data bytes. Two hundred fifty six codewords can be derived by excluding the all-ones codeword and adding ~ state depen-dent codeword pairs for two state encoding. The states 1 and 2 are identified by the value of the last bit of the previous codeword concatenation. Thus, 256 codewords of 9 bits each can be defined where all catenations of such codewords comply with the d,k/kl constraint and two state encoding is used. The code provides for specific assign-ment of 8-bit data bytes to 9~bit codewords which creates partitions of bytes and codewords with similar structure.
The partitions of bytes are uniquely identifiable and overall mapping of the codewords is produced by gating partition bits according to simple boolean functions.
If Y denotes a 9-bit codeword in the (0,3/5) code, then Y lYl' Y2' Y3~ Y4. Y5, Y6, Y7, Y8, Yg] (3) The constraint k = 3 in the overall coded sequence can be produced by eliminating 9~bit sequences with run lengths of 3 zeroes at the left end thereo, run lengths of 2 zeroes at the right end thereof, or run lengths of 4 zeroes within each 9-bit sequence. Such a constraint is given by the following boolean relation:
(Yl+Y2~Y3) (Y2+Y3+Y4+Ys) (Y3+Y4+Y5+Y6) (Y4~Y5~Y6~Y7) S (Y5+Y6+Y7+Y8) (Y8+Y9) = 1 (~) Similarly, the constraint k1 = 5 is described by the following two equations for the sequence of all odd-bit positions and the sequence of all even-bit positions, respectively, in Equations (5) and (6) given below.
lo (Yl+Y3+Y5) (Ys+Y7+Yg) = 1 (5) : (Y2+Y~+Y6~y~) = 1 (6) Two hundred fifty one valid 9-bit binary sequences satisfy Equations (4), (5), and (6), the decimal equiva-lents for which are given in Table III.
5: Referring now to Fig. 1, an 8-bit binary data byte, denoted X, and its assigned 9-bit codeword, Y, are given by: :
X [Xl~ X~, X3, X4, X5, X6, X7, X8] (7) y [Y1, Y2, Y3, Y4, Ys~ Y6~ Y7~ Y8~ Yg] (8) The first:partition of codeword assignments, denoted~
M, comprises the set of data bytes in which the first and : last four bits of the 8-bit binary data bytes can be : mapped without change into the first and last four bits, respectively, of the 9-bit codeword, YO The middle bit, i.e. the fifth bit position, of the 9-bit codeword in this partition is always 1. Thus, partition M comprises : ~:;
: 162 codewords which can be identified by the relation:
M1 = ~X1~X2~X3~): (9~ :
: `
M2 tX7+X8) : (10) ..
-:
:
~.~
1 308~ 1 1 3 ( 2 X4 X5 X7) (11) M = M1M2M3 (12) The remaining codeword assignments are divided into 1' Rl, S1~ N2~ R2 and S2, which identify 24 25, 9, 10, 20 and 6 codeword assignments, respectively.
These assignments are given by the following structures - of the bits in X:
N1 - M2(~1+X3)Y~4 (13) Rl = ~l2(X2+~-5X6)~ 1 3 4 (14) lo 1 2( 2 5 ~)( 1 3) 4 (15) N2 = M1[';g+X6)X5 (16) R2 M1(X8+~6)~`~ (17) 52 = ~l3~Xl+x3 )xa ( 18) The six state-dependent codewords, together with decimal equivalents of the possible values, are given in Table IV.
To avoid an all ones coded sequence, the middle bit, Y5, is changed to zero which, in turn, creates another valid codeword. The par~ition E derines the ail-ones codeword as follows:
: -E = XlX2X3X4X5X6X7X8 (19) The lo~ic equations for encoder 100 of Fig. 1 are given ln Tab]e I.
The decoder function of Fig. 2 identifies the same partitions as those in the encoder, using the exclusive structures of bit patterns in the 9-bit sequence Y to obtaîn logic equations ~or the components of X. Decoder equations for the decoder 300 of Fig. 2 are provided in Table II.
Referring now to Fig. 1, encoded variables, X1-X8 enter encoder 100 at receiver lines X1 to X8 of encoder ~~ 8 l 3 n88ll 100. The receiver lines X1 to X8 are coupled to encoder gates 102-274. In response to such variables, codewords are produced by encoder gates 102-274 in the following manner. Encoder gates 102-146 produce codeword parti-~ Nl, Rl, Sl~ N2, R2, S2, and ~ respectively-Finally, encoded variables Y1-Yg are produced by encoder gates 148-164, 166-182, 184-194, 196-204, 206-~10, 212-220, 222-234, 236-254 and 256-274, respectively.
Coded variables, Yl-Yg, enter decoder 300 at receiv-er lines Y1 to Yg as shown in Fig. 2. The receiver lines Yl to Yg are coupled to decode:r gates 302-426. Backward reading, codeword partitions, E, M, Nl, R1, and S1, for recreating uncoded variables, i.e. the data, are produced by decoder gates 302-322, respectively, in response to coded variables Yl-Yg. Similarly, partitions N2, R2 and S2 are produced by decoder ga-tes 324-328, respectively.
Finally, the data, ~l-X8, is provided by decoder gates 330-340, 342-348, 350-364, 366-374, 376-390, 392-410, 412-418 and 4~0-426, respectively.
The code described in this specification is an optimum code in that k cannot be decreased without de-creasing the rate. Similarly, k1 cannot be decreased without increasing k, decreasing the rate, increasing the codeword length, or increasing the number of encoder states. This modulation code provides a reduced k param-eter (k=3) relative to the (0,4/4) code ~k=4) for im-proved timing and gain control information, and it achieves this without increasing the k1 parameter as much as the (0,3/6) code (kl=5 versus k1=6). The kl parameter directly influences the hardware requirements in the Viterbi detector path memory, as well as the size of the most probable error bursts. The maximum error propagation of the (0,3/5) code is the same as that of the tO,3/6) code.
While the invention has been particularly shown and described with reference to a preferred embodiment there-of, it will be understood by those skilled in the art that various changes in detail may be made therein with-out departing from the spirit, scope and teaching of the invention. For example, a software implementation of the S~9-86-013 ,.. ~
encoder ancl decoder circuit functions is possible.
Accordingly, the apparatus and method herein disclosed are to be considered merely as illustrative, and the invention is to be limited only as specified in the claims.
-- lO 1 3088 1 1 TABLE I
(0,3/5) Encoder Partitions:
Ml =(Xl + X2 X3) Nl = M2(Xl ~ X3)X4 2 ( 7 x8) N2 = Ml~X8 + X6) 5 3 (X2 ~ X4 + Xs -~ X7) 1 M2(X2 + X5X6)(Xl + X3)X4 M = MlM2M3 R2 = Ml(Xg + X6) 5 E = XlX2X3X4X5X6X7X8 Sl = M2(X2 + X5X6)(Xl + X3)X4 S2 = M3(Xl + X3)X8 Encoding Functions:
1 ( l)Xl RlX~ ~ R2(X4 + X7) ~ $1X3tXl + X6) y = (EM + Nl)X2 + R~X3 + R2(x4 -~_X7) SlXl 2( 3 ~ Nl)X3 + N2 + RlXl + R2(X4 + X7) + S
Y4 = (EM + Nl~)X4 + N2X4 + Rl 2 Y5 = EM + 52~PAsT) Y6 = (EM + N2)X5 + Rl + R2 S2 6 y = (M + N2)X6 + Nl(X5 + X6) + RlX6 + R2X8 1 2 Y = (M+N )X + Nl(X5 + X6~ + RlX5 + R2X6 ~ Sl( 1 6 2 1 y = ~EM + N2)X~ -~ Nl(Xs + X6) + RlX2 R2X5 1 5 2 3 Pa~t = Last digit; in:previous codeword (set PAST=0 for (0,3/6) code).
TABLE II
(0,3/5) Decoder Partitions:
E = YlY2Y4Y5Y6Yg Rl = M(Yl + Y2 3) 4 6 M = Y5(Yl + Y2 + Y3) + E R2 = M(Yl + Y2)Y4Y6 Nl = M(Yl + Y3)Y4Y6 S ~Y ~
N2 MYlY2Y3Y6 2 ( 1 Y3) Encoding Functions:
Xl ~ E + (M + Nl)Yl + RlY3 + SlY2 S2Y8 X2 = E + (M + Nl)Y2 Rl 9 X3 = (M + Nl)Y3 -~ RlY2 + Sl(Yl 2) 2 9 X4 = E + (M + Nl~Y4 + N2Y4 ~ RlYl R2YlY2 X5 = E + (M + N2~Y6 + NlYgYg ~ RlY8 + R2Y9 1 9 X6 = ~M -~ N2)Y7 + NlY7Yg + RlY7 + R2Y8 + Sl(llY2 Y8) 2 6 X7 = (M + N2)Y8 + R2Y2Y3 X8 = E + (M + N2)Yg + R2Y7 S2 " 12 l 3088ll TABLE III
List of 251 9-bit words (converted to decimal) which can be freely concatenated to form strings satisfying the (0,3/5) constraint:
71 73 75 77 78 79 ~32 83 86 87 89 90 91 93 94 95 g9 lOl 102 103 105 107 109 110 111 113 114 115 117 118 119 121 122 178 179 181 182 183 185 1~86 187 189 190 191 197 19~ 199 201 203 205 441 442 443 445 446 447 453 454 455 45'7 459 461 462 463 465 466 467 .. .
~. SA986-013 " 1 3088 1 1 TABLE IV
List of the six state-dependent codewords:
0 A 0 l.B 1 1 1 1 where A = ~ (PAST) B = (PAST) PAST being a binary variable that defines the state and is given by the last digit of the preceding codeword. The possible values of codewords which may result are:
State 1State 2 DATA (PAST~ PAST=0) 00100001 (33) 000110101 (53) 010100101 (165) 00100101 (37) 000111101 (61) 010101101 (173) 10000001 (129) 000110110 (54) 010100110 (166) 10000101 (133) 000111110 (62) 010101110 (174) 10100001 (161) 000110111 (55) 010100111 (167) 10100101 (165) 000111111 (63) 010101111 (175) . ~ ,, .
, ~1 3 .. ", , :
Claims (9)
1. Apparatus for encoding a preselectable number of bits of binary data into codewords having a preselectable number of bits, said apparatus com-prising:
receiver means for receiving the preselectable number of bits of binary data; and encoder means, coupled to the receiver means, for producing sequences of codewords each having at least two interleaved odd and even subsequences in response to said bits of binary data;
said sequences of interleaved subsequences having no more than three consecutive zeroes therein; and said odd and even subsequences each having no more than five consecutive zeroes therein.
receiver means for receiving the preselectable number of bits of binary data; and encoder means, coupled to the receiver means, for producing sequences of codewords each having at least two interleaved odd and even subsequences in response to said bits of binary data;
said sequences of interleaved subsequences having no more than three consecutive zeroes therein; and said odd and even subsequences each having no more than five consecutive zeroes therein.
2. Apparatus as in claim 1 wherein the ratio of the number of bits in the encoded binary data to the number of bits in the codewords is 8/9.
3. Apparatus as in claim 1 wherein the number of codewords are increased by having each codeword establish a state dependency on selected bits in the previous codeword.
4. Apparatus as in claim 1 wherein:
the encoder means includes a plurality of gating means for producing the codewords as partitions and output gating means for combining the partitions of codewords into the sequences of codewords.
the encoder means includes a plurality of gating means for producing the codewords as partitions and output gating means for combining the partitions of codewords into the sequences of codewords.
5. Apparatus as in claim 1 further including decoding means for decoding a preselectable number of codewords into a preselectable number of bits of binary data, said decoding means comprising:
receiver means for receiving the codewords; and decoder means, coupled to the receiver means, for producing sequences of binary data in response to said codewords.
receiver means for receiving the codewords; and decoder means, coupled to the receiver means, for producing sequences of binary data in response to said codewords.
6. Apparatus as in claim 5 wherein the decoder means includes a plurality of gating means for producing the partitions of binary data and output gating means for combining the partitions of binary data into the sequences of binary data.
7. A method for encoding a preselectable number of bits of binary data into codewords having a preselectable number of bits, said method comprising the steps of:
receiving the binary data; and encoding the binary data by producing sequences of codewords each having at least two interleaved odd and even subsequences from said binary data;
said sequences of interleaved subsequences having no more than three consecutive zeroes therein; and said odd and even subsequences having no more than five consecutive zeroes therein.
receiving the binary data; and encoding the binary data by producing sequences of codewords each having at least two interleaved odd and even subsequences from said binary data;
said sequences of interleaved subsequences having no more than three consecutive zeroes therein; and said odd and even subsequences having no more than five consecutive zeroes therein.
8. The method as in claim 7 wherein the ratio of the number of bits in the encoded binary data to the number of bits in the codewords is 8/9.
9. The method as in claim 7 wherein the number of codewords are increased by having each codeword establish a state dependency on selected bits in the previous codeword.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US78,731 | 1987-07-28 | ||
| US07/078,731 US4786890A (en) | 1987-07-28 | 1987-07-28 | Method and apparatus for implementing a PRML code |
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| CA1308811C true CA1308811C (en) | 1992-10-13 |
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| CA000572185A Expired - Fee Related CA1308811C (en) | 1987-07-28 | 1988-07-15 | Method and apparatus for implementing a prml code |
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| US (1) | US4786890A (en) |
| EP (1) | EP0301191B1 (en) |
| JP (1) | JPH01119120A (en) |
| CA (1) | CA1308811C (en) |
| DE (1) | DE3888418T2 (en) |
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| US4888779A (en) * | 1988-03-18 | 1989-12-19 | International Business Machines Corporation | Matched spectral null trellis codes for partial response channels |
| US4888775A (en) * | 1988-03-18 | 1989-12-19 | International Business Machines Corporation | Trellis codes for partial response channels |
| EP0413076B1 (en) * | 1989-08-16 | 1995-01-18 | International Business Machines Corporation | Data coding for fast start-up of PRML receivers |
| US5220466A (en) * | 1991-05-21 | 1993-06-15 | International Business Machines Corporation | Method and apparatus for digital filter control in a partial-response maximum-likelihood disk drive system |
| US5243605A (en) * | 1991-07-11 | 1993-09-07 | Storage Technology Corporation | Modified viterbi detector with run-length code constraint |
| US5327440A (en) * | 1991-10-15 | 1994-07-05 | International Business Machines Corporation | Viterbi trellis coding methods and apparatus for a direct access storage device |
| US5196849A (en) * | 1992-01-31 | 1993-03-23 | International Business Machines Corporation | Method and apparatus for implementing PRML codes with maximum ones |
| US5257272A (en) * | 1992-04-15 | 1993-10-26 | International Business Machines Corporation | Time-varying modulo N trellis codes for input restricted partial response channels |
| JP2648554B2 (en) * | 1992-08-13 | 1997-09-03 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Asynchronous gain adjustment method and apparatus for PRML disk drive system |
| US5255131A (en) * | 1992-08-13 | 1993-10-19 | International Business Machines Corporation | Asynchronous servo identification/address mark detection for PRML disk drive ssytem |
| US5260703A (en) * | 1992-08-27 | 1993-11-09 | Quantum Corporation | Data encoding and decoding within PRML class IV sampling data detection channel of disk drive |
| US5343340A (en) * | 1992-12-31 | 1994-08-30 | International Business Machines Corporation | Digital servo signal demodulation method and apparatus utilizing a partial-response maximum-likelihood (PRML) channel in a disk file |
| US5424881A (en) | 1993-02-01 | 1995-06-13 | Cirrus Logic, Inc. | Synchronous read channel |
| US5353170A (en) * | 1993-05-19 | 1994-10-04 | International Business Machines Corporation | Error recovery data storage system and method with two position read verification |
| JPH07220398A (en) * | 1994-02-03 | 1995-08-18 | Fujitsu Ltd | Method and device for recorded signal reproducing |
| US5619539A (en) * | 1994-02-28 | 1997-04-08 | International Business Machines Corporation | Data detection methods and apparatus for a direct access storage device |
| DE19549399B4 (en) * | 1994-03-18 | 2004-03-04 | Fujitsu Ltd., Kawasaki | Phase synchronization circuit |
| US6002538A (en) * | 1994-03-18 | 1999-12-14 | Fujitsu, Ltd. | PRML regenerating apparatus having adjusted slice levels |
| US5544178A (en) * | 1994-06-10 | 1996-08-06 | Cirrus Logic, Inc. | Method and apparatus for encoding data in a PRML class-IV digital communication channel |
| US5576707A (en) * | 1994-06-10 | 1996-11-19 | Cirrus Logic, Inc. | Method and apparatus for detecting and decoding data in a PRML class-IV digital communication channel |
| US5671252A (en) * | 1994-09-21 | 1997-09-23 | Analog Devices, Inc. | Sampled data read channel utilizing charge-coupled devices |
| JP3456781B2 (en) | 1995-02-06 | 2003-10-14 | 富士通株式会社 | Demodulation circuit of magnetic recording / reproducing device |
| DE69535160T2 (en) * | 1995-09-18 | 2007-06-28 | Hitachi Global Storage Technologies Netherlands B.V. | DEVICE AND METHOD FOR NOISE PROMISE MAXIMUM PROBABILITY DETECTION |
| US5790571A (en) * | 1995-12-11 | 1998-08-04 | Seagate Technology, Inc. | Coding data in a disc drive according to a code having desired algebraic characteristics |
| US5949831A (en) * | 1997-05-21 | 1999-09-07 | International Business Machines Corporation | Method and apparatus for data detection for PRML data channels |
| KR100450782B1 (en) * | 1997-08-27 | 2004-11-16 | 삼성전자주식회사 | Encoding and decoding method of a prml code for a high-density data storage apparatus, especially in connection with magnetically recording and reproducing digital data without interference between signals |
| KR100281738B1 (en) | 1998-07-13 | 2001-02-15 | 이계철 | Encoding and decoding method of nibble inversion and block inversion code, code and decoder |
| US6158027A (en) * | 1998-08-31 | 2000-12-05 | International Business Machines Corporation | Enhanced noise-predictive maximum likelihood (NPML) data detection method and apparatus for direct access storage device (DASD) |
| US6175457B1 (en) | 1998-10-06 | 2001-01-16 | International Business Machines Corporation | Dual polarity thermal asperity detector for direct access storage device (DASD) |
| US6137643A (en) * | 1998-10-06 | 2000-10-24 | International Business Machines Corporation | Thermal asperity detection with long magnet rejection for direct access storage device (DASD) |
| US6430713B1 (en) | 1999-06-30 | 2002-08-06 | International Business Machines Corporation | System and method for constructing low complexity block coders |
| IT1316796B1 (en) * | 2000-03-09 | 2003-05-12 | St Microelectronics Srl | CIRCUIT DEVICE TO RECOVER THE SYMMETRY OF AN ANALOGUE SIGNAL OBTAINED FROM A READING OF DATA FROM MAGNETIC MEDIA |
| KR100384886B1 (en) * | 2000-10-10 | 2003-05-22 | 주식회사 케이티 | Apparatus and Method for Using Nibble Inversion Code |
| US7142134B2 (en) * | 2005-02-01 | 2006-11-28 | Hitachi Global Storage Technologies Netherlands B.V. | Techniques for generating modulation codes using running substitutions |
| JP6768739B2 (en) | 2018-05-22 | 2020-10-14 | 矢崎総業株式会社 | Waterproof connector and waterproof connector structure |
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| US4567464A (en) * | 1983-01-28 | 1986-01-28 | International Business Machines Corporation | Fixed rate constrained channel code generating and recovery method and means having spectral nulls for pilot signal insertion |
| JPS6048645A (en) * | 1983-08-29 | 1985-03-16 | Sony Corp | Information converter |
| JPH0721942B2 (en) * | 1984-10-11 | 1995-03-08 | ソニー株式会社 | Channel coding method |
| US4707681A (en) * | 1986-04-24 | 1987-11-17 | International Business Machines Corporation | Method and apparatus for implementing optimum PRML codes |
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1987
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| EP0301191B1 (en) | 1994-03-16 |
| DE3888418D1 (en) | 1994-04-21 |
| EP0301191A2 (en) | 1989-02-01 |
| DE3888418T2 (en) | 1994-10-06 |
| US4786890A (en) | 1988-11-22 |
| EP0301191A3 (en) | 1990-07-04 |
| JPH0319735B2 (en) | 1991-03-15 |
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