CA1311287C - System and process to control the flow of packets - Google Patents

Abstract

ABSTRACT

A system and process for controlling the flow of packets carried by asynchronous time multiplexers (EPACi). The packets from one communication link are identified by their label and the identity of the multiplexer which carries them.
The process is comprised of allocating for each communication a predetermined clock rate and a predetermined threshold value, measuring the difference between the number of packets entering belonging to the communication and the number of pulses generated by the clock, lower bounding this difference, and, if the difference reaches a predetermined threshold, triggering a signal (DEP) which causes the detection of packets belonging to the communication in question as long as the difference is not less than the predetermined threshold. The signal (DEP) is used by the control means of a switch (XPAC) which transmits to the source of the communication in question a message requesting it to reduce its rate, when this is possible, and, in any event, a message warning it of a loss of packets.

Description

01 The present invention concerns a packet 02 flow control syste~ for packets carried by 03 asynchronous time multiplexers.
04 The routing of whatever flows on, and the 05 sharing of the same transmission resources constitutes 06 the principal concern of asynchronous time 07 techniques. In fact, asynchronous time multiplexing 08 allows the transmission on the same support, that is, 09 asynchronous time multiplexing of packets belonging to different virtual circuits. Each packet is made up of 11 a label identifying the virtual circuit to which it 12 belongs and an information block. The maximum number 13 of virtual circuits on a multiplexer is determined by 14 the length in bits of the label.
~owever, the allocation of these resources 16 usually relies on the activity statistics of the 17 different transmitting sources and as such there is a 18 non-negligible risk of loss of information if the 19 queueing files overflow due to instantaneous overloads. We must obviously minimize these losses, 21 but the solution is not easy since the flow generated 22 by the different sources is of a discontinuous 23 character and is sporatic.
24 One purpose of the present invention is to provide a method allowing the improvement, in real 26 time, of the management of flow. In accordance with 27 this method, we observe the flow of one, a number or 28 all the virtual circuits established on one or the set 29 of input time multiplexers to a switch in order to prevent bottleneckiny and resulting saturation of 31 network resources to consecutive overloads due to 32 abnormal operation, or not respecting the E]ow 33 threshold level to which each communication was 34 established.
In accordance with the invention, the 36 process is comprised of measuring the flow of packets 37 of each communication and, when it is found to be ~ 3 ~ 7 01 greater than a maximum flow threshold, called peak 02 flow, triggering a signal which caues the elimination 03 of packets above the peak flow for the communication 04 concerned before -they get processed by the switching 05 machine.
06 The value of the peak flow is singular to 07 each communication and is set during the setting up of 08 the link, in concurrence with its control mechanism, 09 that is the network control unit:
- by the user, in the case where the 11 source he inserts into the network has a variable -flow 12 and when he knows the peak flow of this source, or ~3 - by the network control unit, in the 14 case of constant flow sources, or variable flow sources where the control unit can determine the 16 average and maximum ~lows.
17 In accordance with the invention, the 18 signalling mentioned above can be used by the control 19 mechanisms o~ the switch which transmits to the source of the communication concerned a message requesting it 21 to reduce its flow, when this is possible, and, in any 22 case, a message warning it of the loss of packets.
23 In accordance with another characteristic 24 of the invention, an up-down counter is provided whose down counting input receives pulses at the rate of the 26 peak flow allocated to the communication concerned and 27 whose up counter input receives a pulse upon the 28 transmission o~ each packet belonging to the 29 communication concerned, the maximum counting output o~ the up-down counter generating, when it is enabled, 31 the said signalling.
32 In accordance with another characteristic, 33 the said up-down counter can ~e formed of a ~irst 34 storage registerj a second storage reyister, an incrementing adder, a counter, a first subtractor, a 3~ second subtractor, and a peak value detection circuit, 37 the input o~ the counter receiving pulses at the rate 3~ - 2 -~ 3 ~

01 of the peak flow allocated to the communication 02 concerned a~d the output of the counter being 03 connected, on one hand, to the loading input of the 04 first counting register and to the first operand input 05 of the first subtractor whose other operand input is 06 connected to the output of the -first counting 07 register, the input of the adder being connected to 08 the output of the second storage register, the outputs 09 of the adder and of the first subtractor being connected to the operand inputs of the second 11 subtractor whose output is connected to the loading 12 input of the second storage register and to the input 13 of the peak value detection circuit whose output 14 generates the said signalling, each ~ransmission of a packet belonging to the said concerning communication 16 triggering the transfer of the contents of the counter 17 and of the first storage register to the operand 18 inputs of the fi.rst subtractor, the transfer of the 19 contents of the second storage register into the adder, then the transfer of the contents of the adder 21 and of the first subtractor to the operand inputs of 2~ the second subtractor, and, finally, the loading oE
23 the first and second storage registers, once the 2~ second subtraction has been done.
In accordance with another characteristic, 26 the said up-down counter is associated with a packat 27 identification receiver circuit for the packets 28 carried by asynchronous time multiplexers entering a 29 switch, to a memory containing as many messages as identifications of links established through the 31 switch, the said identifications constituting the 32 addresses of the said memory, each message being made 33 up of a number of words, two of which are used as the 3~ first and second storage registers of the said up-down counter, a ~ime base containing a number o~ counters, 36 a selector to selecti~ely switch one output of the 37 said counters to the first operand input of the first 2 ~ 7 subtractor, sach message containing a third word being used to carry out the said sel~ction.
In accordance with another characteristic, the up-down counter comprises also a selectable ratio divider between the output of the first subtract:or and the corresponding operand input of the second subtractor, each message of the said memory containi.ng a fourth word defining the ratio of the divider.
An embodiment of the inventiorl is a process for controlling the flow of data packets carried by asynchronous time multiplex channels of a system comprising an up-down counter apparatus having a down counting input which receives pulsas of the communication at a maximum peak rate that is allocated to the perti:nent communication and having another counting input which receives a pulse upon the transmission of each data packet belonging to the pertinent communication, each of the data packets from any one communication carried by the channel being identified by its label and by an identity of the multiple channel which carries it; the process is comprised of the steps of (a) allocating to each communication a predetermined clocX frequency and a predetermining threshold value representing a particular difference between a number of entering data packets and a number of clock pulses generated at the predetermined clock frequency, and operating the up-down counter apparatus in response to the received data packets; (b) determining an actual differenc~ between a number of entering data packets belonging to the communication and a number of pulses generated at the predetermined clock frequency, (c) setting a boundary for this difference determined in step (b); and (d) if the difference reaches the predetermined threshold, triggering a signalling process which starts a deletion of data packets belonging to the pertinent communication until the difference : - 4 -returns to a value which does not reach the predetermined threshold, a maximum count output of the up-down counter apparatus generating a signalling requesting a reduction in rate of the received pulses of the communication.
S The characteristics of the above-mentioned invention, as well as others, will appear clearer upon reading the description of a realization example of the invention, the description being carried out in relation to the attached drawings, among which:
Figure 1 is a block diagram :illustrating a first embodiment o~ a flow control circuit associated with a packet switch, Figures 2a to 2c are timing diagrams illustrating the operation of the circuit of Figure 1, Figures 3a to 3b are curves illustrating in a different way the operation o~ the circuit of Figure 1, Figure 4 shows a block diagram of a second embodiment of the flow control circuit; more complete than that of Figure 1, Figure 5 is a schematic block diagram of the control module used in the circuit of Figure 4, Figure 6 illustrates the structurP of message from the memory used in the module of Figure 6, Figure 7 is a schematic block diagram of the time bas circuit of Figure 4, Figure 8 is the schematic of the pulse generator in the time base of Figure 7, : Figures 9.1 to 9.10 are timing diagrams illustrating the signals generated in the time base of Figure 7, Figures 10.1 to 10.4 are the timing ~4a -p ~

01 diagrams of other signals generated in the circuits of 02 Figure 7 and 8, and 03 Figure 11 shows the timing diagrams 04 illustrating the operating cycles of the module of 05 Figure 5.
06 In Figure 1, we have shown a packet switch 07 XPAC with it input junctions EP~C, its output 08 junctions SP~C and its time base BT. The switch XPAC
09 is controlled and ordered by a control unit UX which establishes the virtual circuits between the input 11 junctions and the output junctions. For the sake of 12 an example, the junctions EPAC and SPAC can transmit 13 time multiplexers such as that which is described in 14 the document EP-A-0 108 028 and the switch XPAC can be of the type described in the document EP-A-0 113 639, 16 the control unit UX thus including the control unit 17 UCC which is part of this autoswitch.
18 As a shunt on one of the input junctions 19 EPAC, namely EPACi, iS connected a framing circuit CCAD which can frame ~he packets carried by the 21 junction EPACi and remove their labels. The output of 22 circuit CCAD i9 connected to the f irst input of a 23 comparator CETI whose second input is connected to the 24 output of a register RETI in which is stored the label corresponding to a virtual circuit to be monitored~
26 The cixcuit CCAD is, for example, the circuit 27 described in the document EP-A~0 113 307 and it has a 28 clocking input f3 connected to a corresponding output 29 of the time base BT of the switch XPAC. We recall that the signal f3 triggers the exiting, out of 31 circuit CCAD, of the first byte of a packet, that is 32 the label.
33 The output of comparator CETI is connected 3~ to the + counting input of an up-down counter DETD of capacitor ~ whose - down counting input is connected 36 to the output of a time base BTC. In practice, the 37 capacity N is selected less than the storing capacity 01 of the switch XPAC queueing files. In practice, the 02 storing capacity of the queueing files gives the 03 switch some flexibility which allows i-t small 04 instantaeous traffic overloads. We -thus understand 05 ~hat it suffices that N be less than this capacity.
06 On the other hand, N should not be selected too small, 07 because the system would not even allow the flow of 08 small trafEic overloads.
09 The overflow output DEP of up-down counter DETD is connected to a corresponding input of the 11 control unit UX, which also has an output connected to 12 the write input of register RETI and one output 13 connected to the frequency control input of the time 14 base BTC. In the remainder of the description, we will indicate that the control unit UX can modify the 16 value of the label contained in the register RETI and 17 that the time base BTC generates a-t the - input of 18 up-down counter DETD periodic pulses IC whose 19 frequency is controlled by the control unit UX.
The circuit shown in Figure 1 operates as 21 follows. The control unit UX has established a 22 virtual connection between the junction EPACi and one 23 of the output junctions SPAC for a link of whlch all 24 the packets have the label Z. Afterwards, for example, from an exchange of signalling with the 26 source of the communication, it has established a peak 27 flow for the link. The control unit UX thus writes 2~ into register RETI the word Z and controls, in 29 relation to this peak flow, the frequency of the time base BTC. Each time that the comparator CETI detects 31 a coincidence of words at its two inputs, it applies a 32 pulse IP to the ~ input of up-~own counter DETD.
33 The timing diagram of Figure 2 illustrates 34 the pulses IC, the diagram of Figure 2b illustrates the pulses IP and Figure 2c indicates the successive 36 values of the contents of up-down counter DETD. In 01 Fiyure 2c, we have assumed that the initial value of 02 the contents was 5 and that the capaclty N of the 03 up-down counter DETED was equal to (24-1). Each time 04 that -the overflow value 15 is reached, the up-down 05 counter DETD transmits a signal DEP to the control 06 unit UX. In accordance with the invention, the 07 control unit UX thus orders the switch XPAC to delete 08 the packets having the label Z and coming from the 09 junction EPACi. Eventually, the control unit UX
enters into communication with the source concerned to 11 advise it that some packets have been deleted and that 12 it should reduce its rate for the link in question.
13 The diagram of Figure 3a illustrates, in 14 an analog manner, how the flow of the source in question evolves over a period of time, while the 16 diagram of Figure 3b shows how the contents of up-down 17 counter DETD varies with time. It appears that as 18 long as the flow from the source dR is less than the 19 peak flow dC, as shown in part I of the curves of Figure 3a, the contents of DEDT is zero. During part 21 II of the curve, after crossing the ordinate dC, the 22 contents of up-down counter DETED goes .rom 0 to N, 23 that is from 0 to 15, in relation with the diagrams of 24 Figures 2a to 2c. During part III of the curve, the up-down counter DETD is held at ~=15, which brings 26 about the deletion of packets. Finally, during part 27 IV of the curve, the flow dR returns to a value less 28 than dC and the contents of the up-down counter 29 decreases to zero. The diagram of Figure 3b thus illustrates that for a given period of time, between 31 the points Sl and S2 all the packets arriving from the 32 source in question are deleted. We observe that the 33 diagrams of Figures 2a to 2c correspond to parts II, 34 III and IV of the curve of Figure 3a.
The circuit of Figure 1 has allowed us to 36 describe the basic operation of the packet flow 37 control system in accordance with the invention, but 3~ - 7 -2 ~Y~
01 it does not apply to a single link. In practice, a 02 really efficient control system must allow control of 03 the flow of a set of input mul-tiplexer EPAC from a 04 packet switch and, in each multiplexer EPACi, all the 05 virtual circuits established. For the sake of an 06 embodiment of the invention, a basic module capable of 07 monitoring 16 entering multiplexers from a switching 08 matrix such as that shown in Figure 8 of document 09 EP-A-0 113 639 is provided. Thus, there will be as many basic modules as there are switch matrices in the 11 first stage of a packet switch.
12 Figure 4 illustrates a basic module MOB
13 associated with a switching matrix XPAC with 16 14 entering multiplexers EPAC and 16 exiting multiplexers SPAC, such as mentioned above, the basic module MOB
16 being controlled by the control unit with processor 17 UX. In the matrix XPAC, we have shown the input 18 circuits CE of the entering multiplexers EPAC, the 19 input rotation matrix MRE, the packet buffer memory MP, the output rotation matrix MRS, the output 21 circuits p/s, the central control unit UCC, the 22 routing circuit ACE including the label translation 23 memory MC, the time base CTS and the local byte clock 24 H.
Between ~he matrix XPAC and the module 26 MOB, we have shown the links Dl, e, H and DEP. The 27 outgoing link Dl from XPAC successively generates the 28 different packet labels ETIj which enter into the 29 matrix XPAC. We recall that, according to the document EP-A-0 113 638, the link Dl is connected to 31 the first output of the rotation matrix MRE which 32 generates the labels ETIj to the memory MC. The link 33 e coming from the time base CTS, is used to identify 34 the number of the entering muItiplexer which carries the packet with label ETIj, the information e carried 36 by this link ha~ing the same role in the matrix XPAC.
37 The link H transmits the internal byte clock H used in ~ ~L~

01 the matrix XPAC. The link DEP goes from the basic 02 module MOB to the unit UCC which deducts the command 03 to transmit to the memory MC to no longer process a 04 particular label ETIj coming from a particu]ar 05 entering multiplex.
06 Between the basic module MOB and the 07 control unit U~, a bidirectional data bus DEO-DElS and 08 a write request wire SEL are provided. The bus 09 DEO-DE15 allows the control unit UX to transmit to the basic module MOB at the same time addresses and data.
11 When a packet switch has a number of input matrices, 12 such as XPAC, we provide as many modules MOB as 13 matrices, such that wires AD0-AD2 are necessary, at 14 the output of unit U~, to select, for example, one module from eight.
16 Finally, between the control units UX and 17 UCC, is provided a data exchange link lL through which 18 the control unit UCC transmits to the unit UX data 19 concerning the peak rate of a newly established link which is identified by its label ETIj and the entering 21 multiplex e which carries it. These data will be 22 described below.
23 ~he basic module shown in Figure 5, 24 comprises a memory MDET, a time base BTC, write multiplexers MUXl to MUX3, buffer registers BUFl to 26 BUF4, an adder ADD, two subtractors SOUl and ~OV2, a 27 divider PlV, two comparators COMPl and COMP2, a logic 28 control circuit CLC and basic logic circuits such as 29 gates Pl to P4.
As we shall see below, the adder ADD and 31 the subtracter COU make up, with the buffer BUFl, an 32 up down counter DETD fulfilling the same role as that 33 of Figure 1.
3~ The memory MDT is organized into K words.
There are as many words as possible connections 36 through the switching matrix XPAC, here this is ~096 37 (16x28) words since this matrix has 16 entering 3~ _ 9 _ 01 mul-tiplex EPAC and processes packe-ts whose label 02 occupies one byte (eight bits). Thus, the word ETIj 03 from one label and the identity word e of the entering 04 multiplex EP~C together define the complete address of 05 one word in the memory MDET.
06 Each word of memory MDET, Figure 6, is 07 broken down into a number of fields Cl, C2, C3 and C4.
08 The -field C1 is a four b:it memory being 09 used to store the contents mCl of up--down counter DETD between two readings of the word in question-11 The field C2 is a four bit memory 12 containing the division ratio mC2 r of the peak 13 reference flow chosen for the connection in question, 14 this division ratio being used in the divider DlV.
The field C3 is a 2 bit memory containing 16 the selection address mC3 of an associated counter 17 among the four counters Cc0 to Cc3 of the time base 18 BTC which generates the peak flow reference.
19 The :Eield C4 is a sixteen bit memory being used to store the current state mC4 of the associated 21 counter Cc0 to Cc3 selected in the time base BTC.
22 The addressing input of memory ~DET is 23 connected to the output of buffer BUF2 of whic`h one 24 input is connected to the output of multiplexer and the other input to the output of multiplexer MUX2.
26 The first inputs of multiplexers MUXl and MUX2 are 27 connected to links e and Dl, respectively, while their 28 second inputs are connected to corresponding outputs 29 of buffer BUF3, respectively.
The first input of multiplexer MUx3 is 31 connected to the output of buffer BUFl and its second 32 input to a corresponding output of buffer BUF3.
33 . The control inputs of multiplexers MUXl, 34 MVX2 and MUX3 are connected to the output of comparator COMPl whose first input is connected to 36 link Dl and second to the output of a register Z0 37 containing the byte of an empty packet label, also ~. 3 ~ 7 01 called the null label. The comparator COMPl also has 02 an enable input connected to the output of the write 03 control logic circuit CLC. This enable input is 04 enabled when the control unit with microprocessor UX
05 has loaded the buffer BUF with addressing data and 06 data to be written in the memory DETD, then enabled 07 the circuit CLC. Note that upon establishing a link 08 communication, the control unit UCC transmits throuyh 09 link LL, to the control unit UX the contents o~ fields C2 and C3 of the word in memor~ MDET which is at 11 address ETIJ.e identifying the said commmunication 12 link.
13 The corresponding write input to fields C1 14 of memory MDET is connected to the output of multiplexer MUX3. The write inputs of fields C2 and 16 C3 are connected to corresponding outputs of buffer 17 BUF3 respectively. The write input of fields C4 is 18 connected to the output of buEfer BUF4.
19 The four read wires of field Cl are connected, on one hand, to the B operand input of an 21 adder ADD and, on the other hand, to the inputs of a 22 ~AND gate Pl whose inverted input is connected to the 23 A operand input of adder ADD. Thus, upon each reading 24 of a word from the memory MDET, the adder ADD adds one unit to the contents mCl of the corresponding field 26 Cl, except if the content mCl is already equal to 15 27 (in binary 1111). The four read wires of fields C2 28 are connected to the control input of divider DIV.
29 The two read wires of fields C3 are connected to a selection input SDC of the time base BTC in order to 3I do the selection of one counter from four, as we shall 32 show in the sequel. Finally, the sixteen read wires 33 of fields C4 are connected to the B operand input of 34 subtractor SOV2 whose A operand input is connected to the selected output SCS of time base BTC. The sixteen 36 wires of output SCS supply the signal Vc, Figure 11 37 and are also connected to the input of buffer B~F4.

' ' .

~J~ ~6~j7 01 The subtractor SOU2 calculates the 02 difference between the sixteen bit words Vc and mC4 03 applied to its ~ and B inputs respectively and 04 generates to the divider DlV a sixteen bit difference 05 word Ve. It carries out a division of the difference 06 word by 2mC2, which corresponds to a left shift of 07 mC2 steps. From the sixteen output wires of divider 08 DlV, the first four, which carry the least significant 09 bits making the word x, are connected, on one hand~ to the B operand of subtractor SOUl and, on the other 11 hand, to the second input of comparator COMP2. The 12 twelve other output wires of divider DIV are connected 13 to the twelve inputs of an OR gate P2.
14 The four wire output of adder ~DD is connected, on one hand, to the A operand of subtractor 16 SOUl and, on the other hand, to the first input of 17 comparator COMP2. The four output wires of subtractor 18 SOUl, supplying the word z, Figure 11, are connected, 19 on one hand, to the inputs of buffer BUFl and, on the other hand, to the inputs of an AND gate P3 whose 21 output generates the signal DEP.
22 The output of OP gate P2 is connected to 23 one input of an OR gate P4 whose second input is 24 connected to the output of comparator COMP2 and whose output is connected to the CLR input of buffer BUFl.
26 Before describing the operation of the 27 module MOB of Figure 5, we will describe in detail the 28 time base BTC whose block diagram is shown in Figure 29 7. The time base BTC comprises a pulse generator GEN, four counters Cco to Cc3 and sixteen multiplexers MUY0 31 to MUY15.
32 The pulse generator GEN, Figure 8, 33 comprises a four stage binary counter whose signal 34 input receives from a source HL a local clock signal h at the rate of 280 Mbit/s and whose zero reset CLR
36 input receives the signal H or byte clock from the 37 matrix XPAX. The four outputs 11 to 14 of counter ~ 3 ~ 7 01 CPTl generates the signals de~ignated by the same 02 references, the frequencies of which are 140, 70, 35 03 and 17.5 Mbit/s respectively. These signals h and 11 04 to 14 are shown in Figures g.l to 9.5. We note that 05 the period of the signal 11 is 7 ns.
06 The outputs 12 to 14 are connected to the 07 inputs oE a decoder DECl which generates the signals 08 Bu, Vv, Bw and Tx whose waveforms are shown in Figures 09 9.6 to 9.9. In practice, the decoder DECl is a logic circuit which resolves the following logic equations:
11 Bu = 12/.13/.14/
12 Bv = 12.13/.13/
13 Bw - 12/.13.14/
14 ~x = 12.13.14/
We observe that each of these signals is 16 at the high level for one period of 11, -then at the 17 low level for the next three periods. The high level 18 times are phase shifted from one signal to the next.
19 The signal 13 is also applied to an invexter INV which generates a signal Bz/ shown in 21 Figure 9.10.
22 Finally, the signal 13 is applied to the 23 input of a second binary counter CPT2 with three 24 stages and three outputs ml and m3 generating signals which are applied, with the signal 13, to a decoder 26 DEC2 which generates 16 signals t0 to tl5 which are 27 shown in Figure 10.1. The decoder DEC2 resolves logic 28 equations similar to those mentioned above, but with 29 four terms on the right instead of three. We note that each of the signals t0 to tl5 is at the high 31 level during one half period of signal 13, then stays 32 15 half periods at the low level. The high level 33 times are shifted rom one signal to the next. Note 34 that the signal 13, which is periodic, corresponds to a rate of 35 Mbit/s.
36 The generator GE~ comprises also three OR
37 gates P4 to P6. The OR gate P4 has seven inputs which 01 are connected to the outputs tl, t3, t5, t7, t9, tll 02 and tl3 o decoder DEC2 respectively. Its output 03 generates the signal nl which is shown in Figure 04 10.2. We note that this signal, which is not 05 periodic, corresponds to an average rate of 30.6 06 Mbit/s with an average period of 32.7 ns.
07 rrhe OR gate P5 has six inputs which are 0~ connected to the outputs tl, t3, t7, t9, tll and tl5 09 of decoder DEC2 respectivel~. Its OlltpUt generates the signal n2 shown in Figure 10.3. This signal, 11 which is not periodic, corresponds to an average rate 12 of 26.2 Mbit/s with an average period of 38 ns.
13 The OR gate P6 has ~ive inputs which are 14 connected to the outputs tl, t5, t7, tll and tl5 of decoder DEC2 respectively. Its output generates the 16 signal n3 shown in Figure 10.4. This signal, which is 17 not periodic, corresponds to an average rate of 21.87 18 Mbit/s with an average period of 45.7 ns.
19 The signals 13 and nl to n3 are applied to the signal inputs o~ sixteen stage binary counters 21 Cc0a to Cc3 respectively.
22 Each multiplexer MUYi has four signal 23 inputs which are connected to the ith order outputs o~
24 counters Cc0 to Cc3 respecti~ely. ~ach multiplexer MUYi has two control wires connected to the two input 26 wires of the selection control SDC respectively.
27 Thus, upon receiving a two-bit selection word, the 28 setup consisting of the multiplexers MUY0 to MUY15 2~ retransmits the state of one of the counters Cc0 to Cc3. The outputs of multiplexers MU~0 to MUY15 are 31 connected to the sixteen wire output SCS.
32 With reference again to Figure 5, it 33 appears that upon reading a word in the memory MD~T, 3~ th wires SDC are enabled, such that the sixteen bit word Vc is generated to the A operand of subtractor 36 SOU2. Simultaneously, the reading of field C4 37 produces the sixteen bit word mC4 applied to the B
38 - 14 ~

01 operand o-E subtractor SOU2, which generates the 02 di-fference (A-B) in the form of a sixteen bit word Ve 03 to the divider DlV. In the divider, the reading of 04 field C2 will control the number of shifts mC2 to the 05 left in order that the four least significant bits, 06 making the word x, ~e used in the subtractor SOUl.
07 Finally, at the time of writing in the memory MDET, 08 the contents of buffer BUF4 will refresh the contenks 09 mC4 of field C4 by writing into it the word supplied by the outputs SCS of the time base BTC. It i5 11 understood that at each reading of a word from the 12 memory MDET, the subtractor SOU2 supplies the number 13 of the counter CcO to Cc3 selected by SDC to increment 14 since the previous reading. The use of the four counters CcO to Cc3, with the divider DlV, allows a 16 considerable economy of means. In fact, we could have 17 multiplied the number oE counters of the time base BTC
18 up to sixteen and remove the divider. But this 19 solution requires multiplexers with more inputs. On the other hand, it may be seen that the signals nl to 21 n7, even if they are not strictly periodic, do not 22 have any large gaps between two adjacent pulses.
23 However, the multiplication of these signals would 24 lead to the introduction of very large gaps.
It follows from the above that the four 26 least significant bits of the output word of divider 27 DlV represent the number x of pulses IC, by taking 28 again the notations of Fig. 2a which were ~iven since 29 the previous reading of the word in question. Thus this word is read when its address is transmitted by 31 the buffer BUF2 to the addressing inputs of memory 32 MD~T, that is when Dl transmits the label of the word 33 and that e identifies the entering multiplex in 34 question. The reading of the words brings about the transfer of the con-tents mCl of four bit field Cl to 36 the B operand of adder ADD. If this content mCl is 37 less than 15, the gate Pl transmits to the A operand a ~ t~3 7 01 1 which represents a pulse IP of Figure 2a. The adder 02 DD thus generates the value (mCl+l). If the contents 03 mCl of field Cl is already equal to 15, the gate Pl 04 generates a 0 and the adder ADD generates the value 05 mCl, equal to 15.
06 The subtractor SOUl subtracts from mCl or 07 (mCl~l) the value x and generates either (mCl-2) or 08 (mCl+l-x). This value z is transmitted to the buffer 09 BUFl for writing at the same address in the memory.
MDET where it becomes the new content mCl of field 11 Clo Furthermore, if this value is equal to 15, the 12 A~D gate P3 transmits through its output the signal 13 DEP which causes the deletion of the packets in 14 question in the matrix ~PAC, as mentioned earlier.
In other respects, if the time interval 16 between the arrivals of two packets regarding a 17 particular communication, that is the time interval 18 between two readings of the same word, is very large, 19 it is possible that the value of the output word of divider DIV be greater than 15. In this case, the 21 value x is without meaning, but since at least one of 22 the most significant bits is at 1, the OR gate P2 23 transmits, through OR gate P4, a CLR signal to buffer 24 BUFl. The new value mCl written in field Cl of memory MDET will thus be 0.
26 In the case where the value applied to the 27 B operand of subtractors SOUl is greater than that 28 applied to its A operand, the subtractor SOUl 29 transmits a zero ~alue to buffer BUFl. If the applied values are equal, the comparator COMP2 also transmits 31 by OR gate P4, a CLR signal to buffer BUFl.
32 It is apparent that the set consisting of 33 the adder ADD, the subtractor SOUl and the bufEer BVF
34 fulfills the same purpose as the up-down counter DED~
of Figure 1.
36 The timing diagrams of Figure 11 37 illustrate the unfolding of the read-write cycle of 38 ~ - 16 -~:L~37 01 memory MDET allowing the execution of the operations 02 which have just been described. We find diagra~s of 03 the signals 11, Bu, Bv, Bw, Bx and Bz whose generation 04 was described in relation with the Figures 8, 9.2 and 05 9.6 to 9.10. The diagrams of -the signals Bx/ and Bw/
06 are also shown. The signal Bx/ is applied to buffer 07 BUF2. The signal ~w/ is applied ~o the read-wri-te 08 control of memory MDET. The signal Bv is applied to 09 bu~fers BUFl and BUF4.
The timing diagram ETI represents the 11 succession of words e applied to multiplexers MUXl and 12 MUX2 respectively, coming from the matrix XPAC. When 13 this word is different from a null label, which is 0 14 in Figure 11, it triggers a flow control cycle and, when it is equal to that of a null, which is 0 in 16 Figure 11, it gives to the control unit UX the 17 possibility to write in the memory MDE~.
18 The timing diagram AD shows the instance 19 at which a new read address, deducted either from the word Dl,e, or from data provided by the unit UX, is 21 validated, by Bx/, in buffer BUF2. The timing diagram 22 mC to mC4 of fields Cl to C4 respectively are 23 available for reading to the adder ADD, the control 24 input of the divider DIV, the input SDC and the B
operand of subtractor SOU2 respectively.
26 The timing diagram BTC shows the instance 27 where the counters Cc0 to Cc3 change state in the time 28 base BTC, this instance being defined by the signal 29 Bz.
The timing diagram Vc shows the instance 31 where the multiplexers MUY0 to MUY15 are controlled to 32 give the value Ve of the A operand to subtractor 33 SOU2. The timing diagram Ve shows the times when the 34 calculation of (A-B) is finished in the subtractor and the timing diagram Div the moment when the division in 36 divider DIV is compIete to give the B operand to 37 subtractor SOUl.

r~ i~

01 The timlng diagrams Mcl-~ and z show the 02 times when the addition operation is complete in adder 03 ADD and when the subtraction operation is complete in 04 subtractor SOUl respectively. The timing diagram DCl 05 shows the times at which the output values of buffers 06 BUFl and BUF4 are given, controlled by Bv.
07 We must note that the leading edge of 08 signal Bw/ triggers the writing o the values present 09 in BUFl and BUF4 to the fields Cl and C4.
It is apparent that a cycle is described ll starting with the following addressing ETIj and e, 12 which allows the reading of the fields Cl to C4, then 13 the carrying out of the operations on the contents 14 mCl, mC4 and the selections by the contents mC2 and mC3, and, finally, the writing of the new values of 16 mCl and mC4, before the new addressing which 17 retriggers a cycle.
18 When an empty packet appears on an 19 entering junction EPAC, its label is recognized in the comparator COMPl which switches the multiplexers MOXl 21 to MOX3 and, on the other hand, inhibits the reading 22 of the memory MDET. One write cycle is thus open in 23 which the microprocessor of the control unit UX causes 24 the writing at an address contained in buffer BUF3, the data which is also written in the buffer BUF3. A
26 person knowledgeable in the field would easily 27 determine that it has the same duration as the cycle 28 previously described, which i8 why it appeared 29 pointless to describe it in detail. As soon as such an update has taken place, the cor.trol unit prepares a 31 new writing through buffer BUF3 and the circuit CLC
32 re-enabled by the link SE~.
33 - 1~3 -

Claims (5)

1. A process for controlling the flow of data packets carried by asynchronous time multiplex channels of a system comprising an up-down counter means having a down counting input which receives pulses of the communication at a maximum peak rate that is allocated to the pertinent communication and having another counting input which receives a pulse upon the transmission of each data packet belonging to the pertinent communication, each of the data packets from any one communication carried by said channel being identified by its label and by an identity of the multiple channel which carries it, said process comprising the steps of:
(a) allocating to each communication a predetermined clock frequency and a predetermining threshold value representing a particular difference between a number of entering data packets and a number of clock pulses generated at said predetermined clock frequency, and operating said up-down counter means in response to said received data packets;
(b) determining an actual difference between a number of entering data packets belonging to the communication and a number of pulses generated at said predetermined clock frequency;
(c) setting a boundary for this difference determined in step (b); and (d) if said difference reaches the said predetermined threshold, triggering a signalling process which starts a deletion of data packets belonging to the pertinent communication until said difference returns to a value which does not reach said predetermined threshold, a maximum count output of the up-down counter means generating a signalling requesting a reduction in rate of said received pulses of said communication.

2. The process in accordance with claim 1, and the further steps of: sending a signal to a source transmitting the pertinent communication in order to request it to reduce its rate of transmission, and for transmitting a message warning said source that there may be a loss of data packets during transmission.

3. The process in accordance with claim 1, and the further steps of: sending a signal to a source transmitting the pertinent communication in order to request it to reduce the clock frequency rate of transmission, and for transmitting a message warning said source that there may be a loss of data packets during transmission at said reduced rate.

4. The process in accordance with claim 1 and the added step of occasionally receiving empty packets, identifying empty packets upon the arrival thereof responsive to an empty packet label carried by said packets in order to inhibit an addressing of the memory during reading.

5. The process in accordance with claim 4, and the added step of triggering an access authorization to the memory during a writing period for the control unit in response to said identifying an empty packet.