CA1312955C - Apparatus for real time data compressor - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

High speed computing apparatus is provided for performing real time data compression of analog voice data or digital data to be transmitted over a data link. The incoming data stream is divided into blocks of digital data and the blocks are subdivided into digital samples or elements to be compressed. Each sample is analyzed individually to determine its estimated variance and the marginal return to be gained by alloting the sample one or more of the bits to be employed to define the block of digital data. The bits are assigned to the samples having the highest estimated variance factor so that an optimum allocation of bits to individual samples is achieved with variable ratio data compression. The allocated bits are employed to encode the samples during real time data compression and transmission.

Description

~3~ 2~5~

APPARATUS FOR REAL TIME: DATA COMPRESSOR

BACKGROUND ~F THE INVEN~ION
~. Field of the Invention This invention relates to ~igital apparatus and a method for compres~ing analog or digital data ror transmission by standard commercial data links using adaptive transform coding (ATC) to achieve an optimal allocation of the compressed digital bits to be transmitted. More specifically, the present invention relates to hardwars for achieving fast allocation of bits to define blocks of information which permit real time data compression and transmission.

2. Descri~tion of the Prior Art Digital signalling formats are superior to traditional analog formats in many ways. As a result there is a trend to convert analog telephone networks to all digital networks.
High grade speech occupies a bandwidth of about 32QO hertz in analog form. A present way Or converting khis analog speech to digital format is to sample the speech in blocks of 8000 samples per second and assign a digital value to each sample using eight bits per sampleJ This typical eonversion requires 2~ 3 bandwidth wh~ch will support transmission of 64 Kbps to reproduce a speech waveform with telephone quality when decoded. This is a most important reason that standard digital data-telephone phone links have been standardized at 64 ~bps data rates.

`

. ~

. :

` ~3~2~

S~andard di~ital speech phone lines capable of transmitting sixty-four thousand bits per second are commonly used ~or telephone voi~e ~ommunication. When digital telephon~
lines are employed, all 64 ~bps capaci~y is available to the user to use in any manner desirable. ~t ~s possible to use such a standard telephone data link line to transmit up to eight voice channels digitally on the same data link line with understandable, though somewhat degraded, voice quality. It is also possible to ~ompress the digital data representations by a ratio of four to one and transmit four voice Ghannels on one digital data speech phone line with very little voice degradation. Heretofore, the delay in achieving such speech compression has mitigated against its use for real time transmission.
Transcontinental digital speech phone lines rent or lease for over ~40,000 per month. If the voice information to be transmitted is compressed at a ratio of four to one, the use-will achieve saving of over $120,000 per month.
For over twenty-five yeans scholarly articles have been presented proposing different ways of compressing voice information, however, there is not presently available commercially any apparatus to take advantage of the aforementioned possible savings when transmitting compressed voice information.
Huang and Schulthiess in their paper "Block Quantization of Correlated Gaussian Random Variables", IEEE Tran.-Comm. Sys.
vol. CSll, pp. 286-296, Sept. 1963, suggested that blooks of digital information could be encoded on a sample by sample basis and further suggested that digital bit allooation could ' ~312~
be employed to define the block of information to achieve data compression. The sllocation of bits suggested by this paper is sub-optimal because the optimal distribu~ion of bits b( j) is not a linear function of the variance 2(~) and requires a non-integer assignment of bits which rarely results in a realdistribution of the available bits.
Adrian Segall in his paper "Bit Allocation and Encodin~
for Vector Sources", IEEE Trans Inform Theory vol. IT-22, pp-162-1699 March 1976, reviewed the different ways of allocating 1~ digital bits to achieve data compression of blocks of digital information. Further, this Segall article suggested an algorithm for the optimum allocation of discrete bits to achieve data compression of blocks of digital information.
While this paper suggests an optimum allocation of bits, the implementation would require approximately sixty thousand separate computer operations. To perform the same optimum allocation of bits the present invention only requires approximately 7,560 operations which can be performed as simple operations in real time.
Richard V. Cox and Ronald Crochiere of Bell Labs in their paper "Real Time Simulation of Adaptive Transform Coding", IEEE
Trans. on Acoustic, Speech and Signal Processing, vol. ASSP 29, No. 2, April 1981 suggested Adaptive Transform Coding ~ATC) as an effective means of digitally encoding speech at low bit rates (9.6-16 Kpbs) for transmission on voice lines at 64 Kbps.
Actual telephone conversations were data compressed and transform encoded. The encoded data was transmitted and then transfsrm decoded from the compressed form at the receiving end. This Cox et al article further teaches an ATC encoder and decoder emp~oying a fast processor intended to enable real time data compression transmission.

, .. . . .

~: . .

12~

It would be extremely desirable to provide in a single hardware package a sys~m which w~uld transmit and/or receive two, four or more channels of voice information on a single standard Gommercial data link channel without noticeable distortion.

It is a principal object of the present invention to provide a system for Q~mpressing digital voice data for transmission on standard commercial data link lines.

It is another principal object of the present invention to provide a high speed Adaptive Transform Coding (ATC~ encoder capability of multi~hannel compression of digital voice data for real time transmission.
It is another prin¢ipal obje~t of the present invention to provide a high speed system for compressing digital voiGe data at compression ratios of approximately four to one with optimum allocation of digital b1ts.
It is yet another obje~t of the present invention to provide a ~ingle hardware package that may be ~onnected to a plurality of individual telephones for transmission Or voice data oYer a single data link.
It is a general ob~ect of ~he present invention to provide a system for performing optimum bit allooation used with Adaptive Transform Coding (ATC).
It is another general ob~e~t to provide apparatus for performing optimum bit allocation used with ATC whi~h aohieves high quality reproduction of all classes of signals.

: " ~

_5 13~2~

It is a general object of the present invention to provide apparatus for performing ATC at higher speeds than heretofore achievable.
It is a general object of the present invention to provide an economical system for data oompression which will promptly pay for itself in practioal ~ommercial use.
According to these and other objects of the present invention~ there is provided a high ~peed system for compressing digital voice data which permits the system to receive blocks of digital data in real time and to process the blo~ks of information and transmit oompressed digital repli~ations in real time. Blocks of incoming data are received by a high speed processor and stored as block sa~ples in a high speed memory at designated addresses. The stored digital data samples are processed by performing frequency domain transforms (FDT) on the blocks of sample information and a linear prediGted coding ~LPC) model of the transformed block Or data is ~reated. The (FDT) and the (LPC) model information is stored in the high speed memory and then employed to create a magnitude estimate of the ~arianoes of the transformed data sample by sample. The value representations of the estimated variances are then employed to allo¢ate portions of a predetermined number of bits designated to define the blocks of inco~ing data. Once all of the available bits are allo~ated to describe the block of trans~ormed data they are encoded and transmitted along with the (LPC) model whi~h allows the transmitted model to decode the bits at the re¢eiver.

-6- ' ~3~2~
BRIEF DESCRIPTION OF THE DRAWING

Figure 1 is a schematic block diagram showing a generic prior art encoding scheme;
Figure 2 is a blo~k diagram showing a prior art form of adaptive transform coding (ATC);
Figure 3 is a iogic flow diagram illustrating the preferred embodiment pointer method o~ bit allocation employed to achieve optimum high speed data oompression;
Figure 4 is a schematic diagram illustrating how the preferred embodiment pointer system is executed ~ perform high speed bit allocation;
Figure 5 is a logic diagram illustrating a modification of the preferred embodiment in Figure 1 using a marker method of allocation to aohieve optimum high speed data compression;
Figure 6 is a graphi¢ representation of the magnitude of the estimated variance data of a transformed block of data showing how marginal return data is related to the magnitude estimates;
Figure 7 is a block diagram showing how the high speed compression system may be utilized for digital or analog data;
Figure 8 is a simplified block diagram of the preferred embodiment high speed data Gompression system employed for illustration purposes only; and Figures 9Aand 9~ are a more detailed descriptive blook diagram of the Preferred embodiment invention of Figure 8 showing a system ~apable of performing frequency domain transform (FDT) and for generating a linear predictive Qoding (LPC) model and for calculating magnitude estimates of the variances from the (LPC) model and for allocating bits based on marginal return oalculations.

: . , ,.. . ~ j .

7 1 3 l2 9~r3 DESCRIPTION OF THE PREFERRED EM~ODIMENT

Before explaining the drawings in detail it shouid be mentioned that the data lines to be used are ~locked at a rate of 64 Kbps by phone companies and the data to be transmitted must conform to this clook rate.
To simplify the explanation of the present invention he~ein, the ~locks of data to be ~ompressed will be explained as being divided into two hundred snd fifty-six samples, each of which are defined by twelve bits on the line entering the data compressor. This effectively represents a bit rate of 96 ~pbs which can be output processed to provide an output data rate of 64 Kbps. The present invention system is also capable of input and output data rates at the hardware data Gompressor at 96 Kpbs even though the output per ohannel will be 16 Kpbs.
If each of the samples were defined using only six bits instead twelve bits, the six bits when transmitted would effectively cause a two to one ~ompression of the data.
Because voice data has an extremely complex spectrum, the bits employed to define each sample cannot be equally allocated to samples and requires an analysis of the voice spectrum. The present in~ention is concerned with an optimum allocation of the approximate 400 bits which will be used to define the 256 samples of the block of incomlng data and will be retransmitted at an effect rate of 16 Kpbs per second to provide a four to one compression ratlo based on the da~a rate of the voice data link line which is 64 Kbps.

, , ~:
.

~. ~3~2~

- Refer now to Figure 1 showing the basic encoding scheme 10 disclosed in the aforementioned Adrian Segall IEEE Article.
The encoding procedure is designed to take advantage of then known coding schemes for soalar sources as applied to vector sources. The author describes ~he input X(i) on line 11 as the output from a disorete memoryless vector source formed as a sequence of independent identically distributed m dimensional random vectors having a jointly Gaussian distribution. The X(~) vectors are transformed by a nonsingular matrix S (12) into Y(~) vectors yielding uncorrelated components of the Y
vectors. ~he m ~omponents of Y vectors are separately encoded at encoders 13, 14, 15 by a source coding technique to provide discrete (individual) digital values Y which are transmitted through a discrete noiseless channel 16 to provide the digital values at the decoding utilization devioe.
The received digital ~alues Y on line 17 are inverse transformed by nonsingular matrix R (18) to provide X vectors on line 19 that approximate the original signal X(~) on line 1 1 .
Segall recognized that the sour¢e information on line 11 to be transmitted through channel 16 would have a limited number of digital bits and that each component or sample of a source word or block was to be processed separately. The problem was to find to optimal allocation of the available bits to the individual components or elements in order to maximize the overall mean-squared error between the source information X~) and the reproduoed sequence X0 .

9 ~3~2~

Segall suggest a procedure for obtaining an optimum allocation of available bits. First, a value of marginal return P(b,k) is calculated for each sample. The marginal return values are then arranged in decreasing order. The sam?le having the highest marginal return is assigned one bit and the decreased marginal re~urn value P(b,k) is again figured for the sample receiving ~he bit. The samples are then rearranged in de¢reasing order of marginal return value and the next bit is assigned to the next sample having the highest marginal return. The process is repeated until all of the bits available are assigned. The assigned bits are then employed to encode the samples whiGh are transmitted as a block in digital format and are de~oded at the receiver. It can be shown that this procedure will require approximately sixty thousand sorting and merging, etc. operations to allocate four hundre~
bits over 256 samples using a preferred transform operation.
Refer now to Figure 2 showing a bloGk diagram of adaptive transform ooding 21 disolosed in the aforementioned prior art Cox and Crochiere IEEE article. The data stream X(~) on line 22 is stored in blocks in buffer 23. The X(~) vectors are frequency domain transformed (FDT) at block 24 being quantized and enooded at block 25 for transmission over noiseless channel ~7 after being multiplexed at block 26.
Side information is computed and quantized at block 28.
The side information on bus 29 is applied to multiplexer 26 for transmission over channel 27 and is also employed to construct a spectral estimate of the charaoteristics of the block of information. Bit allo¢ation and assignment to Yndividual .
.

.

~3~ 29~
~o--quantized samples is made at block 31. The assigned bits for each samples are then enooded at encoder 25 and step size values ~ k are applied to the encoded ~its before being applie~
via bus 32 to multiplexer 26.
Refer now to Figure 3 which is a logic flow diagram illustrating a preferred embodiment pointer method of bit allocation. The incoming data is prooessed in block 33 to provide estimated variance data ~ (k) necessary to allocate the bits. The estimate variance data is stored for each of the samples and is pro~ided to the system ~rom memory to enable the system to sort in block 34 the estimated variance data in diminishing order of magnitude as will be explained in greaten detail hereinafter. ~he information from the sort is also stored in memory and is available to permit the system to set a lS predetermined number of pointers to the top of the estimated variance data as indicated by block 35. She system then runs a simple calculation using the estimated variance data to deter~ine the largest marginal return, defined as P(b,k) for eaGh magnitude or value being pointed at by the pointer as shown by block 36. 8lock 37 shows that one of the 400 bits to be allocated is assigned to the magnitude or value for only the pointers having the highest marginal return. Block 38 is employed to show that the pointer is now moved to the next to the highect (next lowest) magnitude or value of the estimated varianoe. Block 39 illustrates that the system determines if all of the 400 bits to be allooated have been allocated and if not line 41 shows that the logic returns to block 36 and recalculates the highest or largest marginal return. The system again assigns another bit to the highest marginal return ~: , "., , ' .................. .

" ~3~29~ ~

value at blook 37 and moves the pointer to the next lowest estimated varianoe value in block 38. The system again determines whether ~ll of the bits to be allo~ated have been allocated and returns in the loop via line 41 until such time that all of the bits to be allocated are allocated and the system stops the allo~ation of bits at block 42. Effectively, the pointer 3ystem allocates more bi~s to the magnitudes or values of the estimated varian~e that are the largest which effeGtively ~aximizes or optimizes the ability of the system to define the block of information to be transmitted.
As an example of the operation of logic flow diaBram Figure 3, the marginal return or marginal error can be theoretically determined for the increase of one or more bits from the equation:
P(b,k) - ~-(k)[~(b~ (b)~
where b represents the number of bits assigned and k is the coefficient index a?plicable.
Or~k)is the estimated variance for the kth ~oefficient.
~(b) is the mean-squared error obtained when quantizing a Gaussian random variable of variance one using (b) bits.
The term [~b-1)-p(b)] is a Gonstant for each bit (b) and is calculated and stored in a memory or look up table for fast access. When the estimated varian¢e $s normalized or made unity by dividing the transform coefficient y(~) by the estimated varian~e ~ (k), the marginal return is ¢alculated by multiplying the estimated varian~e ~ by the mean squared error term, whîch has been pre¢omputed for each bit (b). The mean squared error term is called the ~¢umulative gain" be¢ause it is representative of the amounts of gain resulting from raising ..

. , . .... ~ .

-~2- ' ~3~2~
or improving the marginal return P(b,k) by one additional bit b. An example of the Bain from raising the number of bits from zero to one, from one to two and from two to three, eto. is as follows:
No. of Bits ~B) Cumulative Gain (BK ~-3K) ~ ~ 0.6366 1 to 2 0.2446 2 to 3 0.0~14 3 to 4 0.02586 4 to 5 D.00805 etc. _ _ _ The marginal return for the samples in Figure 3 must be oalculated in block 37 in order to assign a new bit to the largest or highest marginal return value. The marginal return for any ~oeffi~ient k when the number of bits (b) is zero is e~ual to the variance. Thus, P(o,k) = ~2(k).
If the samples are arranged in a diminishing order of estimated variance ~ (k), the bits may be assigned or allocated without the need fQr reordering and merginB the sorted estimated variance values.
Refer now to Figure 4 showing a schematic diagram 43 of variance ~2 as would occur in memory and at block 34 of Figure 3. Originally all of the pointers were set to the top of largest estimated ~arianoe data as shown in blook 35. The ten pointers are numbered 1 to 10 in squares with arrows pointing to the aforementioned ~amples. The number in the squares also represent the number Or bits assigned to the individual sample. The amount of Bain derived from assigning any sample one more b t may be expressed by the Bain term G _ X (BK 1-BK) ~, , . .

.

.

_ ' ~1 6~'1 2~

where the cumulative gain term is precalculated and store~ in memory. All of the pointers s~art at the top of the ordere~
sample list, and the samples maintain the initially sorted order throughout the allo~ation process. Thus, any sample or element whi¢h receives its first bit before other elements in the order, also receives its second bit before the same othe:^
elements in the order.
Figure 4 illustrates tha~ ~he element (sample) at the top of the estimated variance (~ ) list have all re~eived no less than six bits because the six bit pointer has moved down to element 2 indicating that all elements above pointer 6 have been assigned 6 bits. When elemeht 0 receives its seventh bi~, pointer 7 will move down to element 1, thus, the effect of moving the pointer 7 to element 1 is to assign 7 bits to lS element 0. The pointers are moved one at a time until all bits are allocated. After all bits are allo~ated the vectors.Y(~) may be quantized and encoded with the bits available for encoding as explained with regards to Figure 2.
Refer now to Figure 5 showing a logic flow diagram illustrating the preferred embodiment marker method for allocating bits to samples within the blocks. Again the incoming data is processed in block 33 to provide the estimated variance o-2~k~ data and sorted in block 34 in a diminish order of Yalue or magnitude of the estimated va-iance data.
The system calculates a reference value in terms of the estimated variance in block 44 for purposes of allo~ating bits as will be explained in greater detail hereinafter and need not be a marker value.

'' -` -14- ~3~29~
A seoond ~alculation is ~ade in block 45 to pr~Yide a value of a new marker associated with several bits to be allo~ated to a set or group of values of estimated variance whi~h fall in a group or set together. The se~ond ~alculation is made in block 45. After ~alculating where to position the marker9 as relate.d ~y marker ratios, ~he marker is now position~d in blook 46 and a determination is made in block 47 whether the maximum number of markers to be positioned have been positioned. If all of the markers have not been positioned, Shen the answer is N0 and the logi~ enters the loop at line 48 and continues the ~alculation of new marker values displa¢ed or related by known ratios until all of the markers have been positioned as shown in block 47. When all markers are positioned, the system calculates the markers that are noh positioned. After this calculation is made, it is neces~ary to check in blo~k 51 to determine if the previous oalculation allocated all of the bits to be allocated. If the answer is N0, then the system enters the loop on line 52 and returns to calculate a new reference magnitude of value for the estimated ~ariance at block 44, then ~ontinues through the loop until it exits to block 53 which results in the oompletion of the allocation of bits and nauses the system to stop at block 54.
As an example of the operation of the marker method, refer now to Figure 6 showing in graphic form magnitudes or values of the estimated varian~e as the ordinate versus samples of the data ~hich ~onstitute a block of data as ~he absoissa.
Bars 55 to 67 are representative of the ordered values Or the estimated variance of samples which have been sorted into a ~iminishing order of magnitude and whose new addresses are 3n numbered from 0 through 255 for purposes of showing that 211 . 256 samples are represented on ~his ~hart or graph.

-15- ~3129~

The numbers of the sorted addresses are shown in both new and original position addresses below the bars 55 through 67 to indicate that the original positions of the sa~ples of data have been rearranged and that the original data samples still maintain their associated original ~equential addresses in memory. A second axis or ordinate scale is shown superimposed on the gain scale whiQh is representat~ve of the marginal return ratios at Y axis 68. The values shown on the marginal return ratios are in terms of bit markers or pointers employing the same terminology used with regards to the logic or flow diagrams o~ Figures 3 and 5. It will be noted that bar 55 falls between an 8 bit marker and a 7 bit marker and is designated within the range below an 8 bit marker value as an estimated varian~e magnitude which receives 7 bits. Each of the bars 56, 57 and 58 fall in the range in whi¢h the estimate variance magnitude would receive 6 bits. Bars 59 and 61 are shown at the highest poink within the range for 5 bits and 4 bits respectively and would receive the lesser value of bits to be assigned. It will be understood that the value of the magnitude`s of the estimated varianoes ~an vary for different forms of incoming data. The s~ale for the marginal return ratios 68 has fixed but nonuniformed ratios between the bit markers or bits adjusted to cover all samples. Thus, the marker method ef~eotively adjust the marginal return ratio s~ale 68 so as to allocate all of the bits to be allocated by ad~usting the sGale 68 rather than attempting to ad~ust the magnitude of estimated Yariance of the individual samples as explained hereinbefore with re8ard to the distribution of pointer~.

' ~ ' -16- ~31~

It will be a~knowledged that prior art algorithms existed fo. allocating bits to magnitudes similar to the estimated varian-ces employed in the present invention. However, the equations and methods were so complex and lengthy that they could not be performed in real time. One su~h allo~ation of bits systems is revealed in the Segall paper reference~
hereinbeforeO Further, other at~empts were made to allocate bits employing suboptimal algorithms or te~hniques in order to overcome the length of time required to make the bit allocation determination such as the aforementioned Cox et al reference whi¢h employed the Haugh and Shortill method, which also produ~es a ~uboptimal result.
The present invention provides a simple and efficient method of allocating all of the bi~s in an optimum manner employing the logic explained hereinbefore regards to Figures 3 and 5.
Refer now to Figure 7 which is a simplified blo~k diagram showing the environment in which the present invention higl speed data compression hardware is utilized. Analog data, ~o including voice data on line 69 is oonverted to digital data in a~d converter 71 to provide digital data on line 72 at a 96 Kilobits per second (Kpbs). The first in and first out buffer 73 provides a block of data on line 74 to the hardware data oompression 75 for pro¢essing . The data rate on the line 74 to the hardware data ¢ompression 75 is preferably at 96 Kpbs.
After the data is processed in the data oompressor 75 i~ is transmitted to a data link on line 76 at 16 Kpbs when a data oompression ratio of four to one is desired. It will be ~nderstood that the allocation of the number of bits may be ' ~ 7~ ~3 ~2~ ~

inGreased or de~reased so as to ~hange the compression ratio of the analog data to be processed. Since ~he present system is capable of processing digital information as well as analog information on a digital input lnformation line is shown at line 77 The data sent over the data link is re~eived on line 78 at 16 ~pbs per second and is applied to the hardware decompressor 79. The de~ompressed output is stored on a first in and first out buffer 81 via line 82. The buffered information in buffer B1 is clo~ked out on line 83 at 96 Kpbs and is ~onverted from digital to analog form in d/a oonverter 84 to provide an analog output on line 85 which is a ^decompressed replica of the original input information on line 69. Since the present data compressor 75 and decompressor 79 . are capable of handling either digital or analog data, output line 86 is shown for the output of digital data.
Refer now to Figure 8 whioh is a. simplified block diagram representative of the data compressor 75 of Figure 7. The digital data on data input line 74 is applied to a multiplexer 87 an~ applied via line 88 to buffer 89 of ALU 91. Multiplexer 87 illustrates that the present embodiment system is capable of handling four data input lines 74 which could be used for four different phone lines and the information transmitted over one datà link line. ALU 91 and buffer 89 are.adapted to re~eive blocks of inooming information which are transferred via bus 92 and holding ~egister 93 to memory 94 via b~s 95. The samples to be pro~essed are stored as digital information first in memory 94 before any processing ocours. The address generator 96 ao~esses the information in memory 94 via bus 97 to retrieve copies of samples of the digital data whi~h is transferred to .

-18- ~2~

the holding regis~er 93 and processed in the ALU 91 employing constant value information stored in look-up table 98 to calculate the estimate variance and marginal return data mentioned hereinbefore.
The esti~ated varian~e data so cal~ulated is again stored in high speed ~emory 94 ~ith its asso~iated memory address to enable fast a¢cess and to prooess the information. The processed information is now sorted employing the ALU 91, the holding register 93 and somparator 99. All of aforementioned l~ calculations are programmed in program memory portion 101 of the oontrol blook 1020 Sequencing and timing are logical fun~tions of the oontroller 102 ~hich presents controlling and timin~ information on bus 103 to all of the blo¢ks shown in Fi~ure 8. The ~ommands on ~ontrol bus 103 are preferably 135 bit control words which simultaneously oontrol all portions of the data compressor 75. The only information required to be supplied to the controller in order for it to ~omplete its program and sequencing and proper timing is the status of information from the ALU 89 on line 104, the oomparator 99 on line 105 and the address generator 96 on line 106. In the preferred embodiment data processor 75 there is provided a biseotion address generator 107. This generator is not used in the aforementioned pointer sys~em which was desoribed with regards to Figure 3, but is employed in the preferred embodiment bit marker allocation system explained with regards to Figure 5 at block 47.
~ata is oompressed one blook at a time in data ~ompressor 75 and transmitted on output line 108 via multiplexer 109 to data output line 111 similar to data link 76.

.

.
~ ' ' ', ; . .
, . .

,9 ~3~2~5 3 Refer now to Figure g showing a ~ore detailed des~ription of the preferred embodiment data ~ompressor 75 shown in ~igures 7 and 8. The buffered samples are presented on lin~ 38 to ALU
91 where the sample is converted from an integer representation to a floating point representation of the digital sample. The floating point sample on line 113 where it is applied to an .
input line 112 of the holding register 93L. T~e floating point representation in digital form is transferred from holding register 93 to the high speed memory 94 via line 95 where it is stored in sequential address order. Once all of the samples are stored in high speed memory 94, they are sorted by comparing the individual sa~ples in ~omparator 99 as they are transferred via line 95 from the high speed memory 94 to the holding register 93. Based on a deoision made at oontroller 102, the in~ividual samples are transferred back to high speed memory 94 based on their diminishing order of estimated varian~e as explained hereinbefore.
When the ALU 91 is performing the pointer method operation explained hereinbefore, the ad~ress generator 96 is providin~ addresses on line 97 to access the estimated variance from the memory 94 whi~h is supplied through the holding registers 93 to the ALU 91. Cumulative gain factors which were previously calculated and stored are accessed by address generator 96 via line 97 and pipeline register 114 which supplies an address on line 11~ to the look-up table 98. The constants in look-up table 98 are supplied via line 116 to bus 92R which enables bus 92R to supply the right side 91R or the left side 91L of the ALU 91. When the left side of AL~ 91 is being supplied, the bus 92R is ~onnected through the ALU buffer -20- ~3~2~

117 to the left side bus 92L which is connected into the ALU
91L. The magnitude of variance multiplied by the cumulative ~ain G resuits in the marginal return figure which was explained hereinbefore.
Since there are only 10 ~alues of marginal return to be compared, ~he highest order of marginal return can be calculated in the ALU, but could be calculated employing the comparator 99 if a large number o~ comparisons needed to be made, When the largest marginal return is found for a particular pointer, the address associated therewith, and contained in address generator 96, is incremented to the next low~ t estimated variance value as explained hereinbefore which is effective to assign one bit to the sample above the pointer. The effect of moving the pointer is to assign one l~ more bit to the elements or the samples having the highest marginal return defined by the pointer addresses. Effectively, the process of system 75 is at block 37 of figure 3 and the marginal gain or return is reduced for the sample which received the one bit. The pointer has been moved to the next 2~ lowest estimated variance and the process 91 under control of the program memory 101 now makes the decision to determine if all the bits have been allocated and lf not, the program again ~igures the marginal return P(b,k) for the pointers in the sublist. Agaln, the sample at the pointer which has the 2~ lar~est marginal;return receives the assignment of one bit.
Its pointer is then moved to the next lower estimated variance and the marginal return associated with that pointer is calculated using the newly pointed to estimated variance. The decision is then made as to whether all bits have been ,, ~

-21- ~3~29~
allocated. The marginal return ~al~ulation need only be made for the updated pointer ~orresponding to the sample which receives ti~e last bit, because the other pointers still have the same marginal return. Thus, the ~alGulations proceed until all the bits are allo~ated and the allocation of bits is completed. When the bit allo6ation is ~omplete, the data in the high speed memory 94 is quantized by taking the information in high speed memory into the holding register's 93 and performing a quantizing operation in the ALU 91. The quankized information is transmitted sample by sample or element by element and the lnformation to be transmitted is presented on write line 113 from the left side of ALU 91L. Before the information is transmitted on line 111 via line 113, the ~ ~loating point representations are converted back to integer representations in ALU 91L. While the oalculations have been explained as being made on the left side of ALU 91L, it is to be understood that the ALU 91R also performs caloulations to process a block of information during real time. The assignment of duties of the two ALUs 91L and 91R are basi~ally a function of the programmed memory 101 and do not require further explanation.
Whe`n the quantization calculation was made, the final bit allocation was stored in high speed memory 94. The input data and the bit allocation is transferred on line q5 to the ALU
91. The bit allocation is used as an address to address the constants in look-up table 98. During ~his operation, the ALU
to address generator buffers 117 and 118, are employed to 8enerate the addresses necessary to ac~ess the look up table 98 by producing addresses on line 119. Line l19 connects to the bus 121 from control 102 and ~upplies the addresses to address generator g6.

-22~ ~3~2~
Whenever a divide operation is performed in ALU 91, a pair of division look-up tables 122 and 123 are provided, which are external to the ALU~s 91, for purposes of speeding up the operation. A~cordingly, the look-up data from table 122 is used for the exponent and the look-up data from ~able 123 is used for the mantissa. It will be understood that the look-up tables 122 and 123 are loaded with inverse numbers which avoi~
lengthy oyclioal operations in the ALUs.
In addition to the address generator 96, there is provided in output line 9~ a pipeline register 124 and a buffer register 125 which assists in speeding up the address operation of the addresses being supplied to the high speed R~M 94 via line 37.
Refer naw to Figures 5 and 9 and the bisection address 1~ generator 107. As previously explained in blook 44 of Figure 5, a calculation is made of a reference value. The marker values are ~alculated based on the reference value and the predetermined ratios between markers and the referen~e value.
Those marker values are used to place or position the markers within the sorted data ~n order to provide a bit allo~ation.
The marker pla~ement is aa~omplished by loading the marker value into the comparator 99 and ~omparing that value with values whose addresses are designated by the address generator 96 in oonjunation with the bise~tion address generator 107.
When all of the markers have been placed 9 $t is possible to determine if all of the bits have been properly allo~ated using the predetermined marker ratios and the Gurrent reference value.
If the bit allo~ation is too high, the program in oontrol nauses the generation of a new referen~e value. Conversely, if the bit allocation is too low, a new hiBher rererenoe value is , . .

.

~ 3~2~

calculated. The process is repeated until the correct number of bits has been allocated due to the markers~ position. By refining the reference value employing successively smaller steDs, and repeating the correction loop, the process converges on an optimum placement of marker, and thus, proper allocation of the bits to be used.
In the ease the optimum bit allocation is not unique, the optimum allocation is performed for those bits where a unique solution does exist and the remaining bits are allocated lO arbitrarily among the equally deserving samples.
The control lines 104 from ALU 94, 105 from comparator 99 and 106 from address generator 96 are shown being connected to the selector-status block 126 of the control 102. A control address generator buffer 127 provides an address output on bus 121 to address register 96 from the aforementioned program memory 101. The program control bus 103 is preferably 136 bits wide and is connected to each of the units in Figure 9 being controlled rather than having the program operated from the AL~
91 as occurs in most minicomputers and small processors.
Having explained a preferred embodiment apparatus for performing real time data compression in the form of a pointer system and a second preferred embodiment in the form of a marker or reference value system, it will be understood that the difference in time required for making the optimum bit 2~ allocation does not vary substantially for 400 bits and that the optimum allocation of bits to the samples is the same in both cases. Thus, the method of allocating bits as well as the structure employed results in being able to accept either digital or analog blocks of data and perform the operation of data compression within 30 milliseconds and transmit the , -24- ~312~
compressed data in digital f~rm while performing optimum bit allocation for data compression. The receiving apparatus for decompressin~ the compressed data is highly simplified in that the data on line 113 or line 76 also includes the information needed to decode the samples being transmitted and the system is less complex than that shown in Figure 9.
~ 'hile the preferred e~bodiment system has been explained employing adaptive transform coding, other forms of transform coding may be employed without having to modify the hardware and method for performing the optimum allocation of bits for data compression which is the crucial factor in obtaining the speeds necessary for real time data compression.
It will be understood that the method explained hereinbefore was directed to performing a four or two to one data compression on voice or speech data. The identical method and apparatus can be employed to perform data compression at other preferred ratios. For example, on systems where the quality of speech is not an important factor and transmission of larger amounts of voice data is important t the compression ratio has successfully been raised to a value of B to 1 with no loss of voice data. The higher ratio is accompanied by a degradation of the quality of the voice data being transmitted. Where real time considerations are not important, other forms of lossless data compression are available which perform data co~pression at ratios up to 10 to 1 with no loss of data. Thus, large masses of repetitive digital data may be transmitted either faster or ~ore economically than the present system and invention. However, the present invention provides the highest reprod~ction quality of any known system capable of compressing both voice and ~odem signals for real time transmission over commercially available data links at the bit rates between 9.6 Kbps and 32 Kbps.

.. ..-, ' .
-,

Claims (15)

1. Apparatus for performing real time data compression of blocks of digital or analog data of the type having an input data stream converted to a desired digital format data stream of time domain estimated variance samples comprising:
high speed computing means coupled to said digital data stream for allocating a digital bit to individual estimated variance samples and calculating marginal return values for said samples;
comparator means;
high speed storage means coupled to said high speed computing means and to said comparator means;
look-up table means coupled to said computing means for storing predetermined mean-squared error constants employed for computing the highest marginal return for said digital data samples;
address generation means coupled to said high speed storage means and to said look-up table means; and control means coupled to said computing means, said comparator means and said address generation means for presenting a sequence of commands to provide a real time stream of blocks of compressed data samples from said computing means, said blocks of compressed data each having;
a predetermined number of bits to be allocated for each block of compressed data;
each said block of compressed data having an optimum allocation of bits to the highest marginal return samples; and a minimum bit error rate and the highest average marginal return for each block of compressed data.

2. Apparatus for performing real time data compression as set forth in claim 1 wherein said high speed computing means is programmed by said control means to store said estimated variance for each digital data samples of said input data stream as input data into said high speed storage means.

3. Apparatus for performing real time data compression as set forth in claim 2 wherein said high speed computing means is programmed by said control means to sense and compress a predetermined number of said samples of digital data representative of which define a block of incoming data.

4. Apparatus for performing real time data compression as set forth in claim 3 wherein said digital data samples are individually examined by said high speed computing means and compressed at variable compression ratios to provide a predetermined data compression ratio for said block of compressed data by allocation of different numbers of bits to different samples.

5. Apparatus for performing real time data compression as set forth in claim 3 wherein said high speed computing means is programmed to calculate estimated variances of said samples of data to be compressed and to arrange said estimated variance samples of a block of data in a diminishing order of magnitudes.

6. Apparatus for performing real time data compression as set forth in claim 5 wherein said high speed computing means is programmed to calculate marginal return values for each of said samples of a block of data and to determine the sample having the highest Marginal return by multiplying said estimated variance by a constant stored in said look-up table means.

7. Apparatus for performing real time data compression as set forth in claim 6 wherein said high speed computing means is programmed to assign one bit of said bits to be allocated to the sample having the highest marginal return and to recalculate the marginal return of the sample then having the highest marginal return.

8. Apparatus fox performing real time data compression as set forth in claim 7 wherein said high speed computing means is programmed to assign one bit at a time of said bits to be allocated to the sample having the highest marginal return value until all bits to be allocated are assigned to said samples to provide an optimum allocation of bits to the highest marginal return values.

9. Apparatus for performing real time data compression as set forth in claim 8 wherein said high speed computing means is programmed to encode each of said samples employing the number of bits assigned to each sample whereby samples are compressed at different compression ratios in the same block of samples.

10. Apparatus for performing real time data compression as set forth in claim 1 which further includes a plurality of division look-up tables containing estimated inverse values coupled to said computing means for performing high speed division by multiplication.

11. Apparatus for performing real time data compression as set forth in claim 1 which further includes a bisection generation means coupled to said address generation means and to said comparator for performing bisection pointer address calculations.

12. A method of performing real time data compression of an input stream of data comprising the steps of:
dividing said input stream of data into blocks of digital data;
dividing said blocks of digital data into samples of digital elements;
calculating an estimated variance for each digital element sample;
arranging said samples of digital data into a diminishing order by magnitude of said estimated variances;
examining each sample to determine the sample having the highest marginal return;
reducing the marginal return of the sample having the highest marginal return by allocating one bit of a predetermined number of bits to be allocated to define said block of digital data;
moving a pointer representative of the number of bits allocated to the particular sample which had the highest marginal return to the next lowest sample in the order of samples;
repeating the steps of determining the sample having the highest marginal return and reducing the marginal return of the sample having the highest marginal returns by allocating one bit and moving a pointer representative of the number of bits allocated to the particular sample until all bits to be allocated are allocated; and encoding each said sample with the number of bits so allocated to each individual sample in real time.

13. A method of performing real time data compression as set forth in claim 12 which further includes the steps of:
predetermining in advance the total number of bits to be allocated to define a block of digital data of greater bits thus defining the compression ratio of data compression.

14. A method of performing real time data compression as set forth in claim 13 which further includes the step of determining side information defining the spectral energy content characteristics of said block of digital data and wherein the step of encoding each sample further includes encoding each sample employing said side information.

15. A method of performing real time data compression of an input stream of data comprising the steps of:
dividing said input stream of data into blocks of digital data;
dividing said blocks of digital data into samples of digital elements;
examining each sample of digital data to determine the energy content of each sample;
sorting said samples in a diminishing order of energy content;
determining the cumulative gain related to the energy content applicable to defining any one sample with one or more bits in order to digitally define said sample;
determining the maximum number of bits to be employed to define any one sample;
positioning a reference marker and other markers which have a fixed ratio relative thereto to the sorted samples;
assigning bits to samples between markers in said sorted order to provide an optimum allocation of bits;
checking to determine if the total number of bits allotted to define a block of digital data have been allocated; and encoding each said sample of elements of said block of digital data employing an optimum allocation of digital bits.