CA1324192C - Controlling responding by users of an intercommunications bus - Google Patents
Controlling responding by users of an intercommunications busInfo
- Publication number
- CA1324192C CA1324192C CA000583478A CA583478A CA1324192C CA 1324192 C CA1324192 C CA 1324192C CA 000583478 A CA000583478 A CA 000583478A CA 583478 A CA583478 A CA 583478A CA 1324192 C CA1324192 C CA 1324192C
- Authority
- CA
- Canada
- Prior art keywords
- bus
- arbitration
- subunits
- access
- subunit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000004044 response Effects 0.000 claims abstract description 33
- 230000000977 initiatory effect Effects 0.000 claims abstract description 12
- 238000012544 monitoring process Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 11
- 230000000694 effects Effects 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 230000008520 organization Effects 0.000 description 3
- 241001508687 Mustela erminea Species 0.000 description 2
- 101000860173 Myxococcus xanthus C-factor Proteins 0.000 description 2
- 239000000872 buffer Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 241000324343 Causa Species 0.000 description 1
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 1
- 101100368708 Homo sapiens TACSTD2 gene Proteins 0.000 description 1
- 102100027212 Tumor-associated calcium signal transducer 2 Human genes 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 239000003999 initiator Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/378—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a parallel poll method
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Time Recorders, Dirve Recorders, Access Control (AREA)
Abstract
ABSTRACT OF THE INVENTION
Each user of an intercommunication bus is associated with a distinct channel of an arbitration bus and maintains a priority record indicating its current priority status against each other user. During a contention interval each user then seeking to use the intercommunication bus bids for use of it by transmitting a bus request signal and makes an analysis of the signals to ascertain if it has a dominating priority for initiating a transaction on the bus, and access is granted accordingly. During the use-signal interval a user then using the intercommunication bus transmits an in-use signal used to update priority records with the effect of giving the last using user lowest priority. For transactions which require a response form a user other than the one initiating the transaction, a second round of bidding is conducted to determine whether any user is qualified to respond and if so which will be enabled to do so. When the response bidding shows no bidders the system immediately initiates bidding for a new transaction.
Each user of an intercommunication bus is associated with a distinct channel of an arbitration bus and maintains a priority record indicating its current priority status against each other user. During a contention interval each user then seeking to use the intercommunication bus bids for use of it by transmitting a bus request signal and makes an analysis of the signals to ascertain if it has a dominating priority for initiating a transaction on the bus, and access is granted accordingly. During the use-signal interval a user then using the intercommunication bus transmits an in-use signal used to update priority records with the effect of giving the last using user lowest priority. For transactions which require a response form a user other than the one initiating the transaction, a second round of bidding is conducted to determine whether any user is qualified to respond and if so which will be enabled to do so. When the response bidding shows no bidders the system immediately initiates bidding for a new transaction.
Description
~ 3 ~ 2 CONTROLLING RESPONDING BY USERS
OF ~N INTERCOM~UNICATIONS BUS ~:
Brief Summary of the Invention Computer systems may be organized with a plurality of / processors operating concurrently in parallel. In 3 such systems, the several processors operate yuasi 1 5 independently, but from time to time need to transfer , information between processors or ~etween a processor !~ and other system components such as input output devices. In order to ef~ect these in~ormation transfers, an intercommunication bus is provided :l 10 connecting to the processors and to other system s component, the bus being capable of transferring information from any user to any other. Such a bus is very flexible in its operation, but it is n~cessary to have some procedure to as~ure orderly 5 use of the intercommunicatiorl bus. This invention r lat es t o controlling access to an intercommunication bus shared ~y several users so as to pro~ide orderly use of the bus by a plurality of users. ~;.
20 The invention features a multi-channel arbitration ~; bus with each u~er as~ociated with a distinct channel thereof and a priority record for each user indicating current priority status of the associated user against each other user. A contention interval 25 and a use-signal in~erval are defined by a state ~, , ,"~;
~2~1~2 machine associated with each user. During the contention interval each user then seeking to use the in~ercommunica~ion bus bids ~or use of it by transmitting a bus request slgnal. Each user makes an analysis of ~he bus request signals to ascertain if it has a dominating priority for use of the intercommunication bus for a transaction iand access is granted accordingly. Duriny the use-siynal interval a user then using the intercommunication bus transmits an in-use slgnal. The in-use signal is used by each user to update its priority record with the effect of giving the lQ last using user a priority subordinate to all others for the next bidding to inltiate a transaction.
For transactions which require a response form some system user oth~r than the one initi.ating the tran~iaction, a Y second round of hidding is conducted to de~ermine whether any user ;`~ is qualified to respond and if so which will be enabled to do so.
When the response bidding shows no bidders the system immedlately initiates bidding for a new transaction; when there are one or more qualified responders, one is selected and enabled to respond.
According to a broad aspect o~ the invention there is ¦ 20 provided, in a computer sys~em having a multiplicity of subunits connected to a shared bus, distributed bus arbitration apparatus co~prlsin~:
an arbi~ration bus with means for carrying a mul~ipliclty of substantially simultaneous bus request signals; and a multlplicity o~ arbitration means, each coupled to ~he shared bus, the arbitration bus and a correspondiny one o~ the subuni~s, for determlning the relative priorities by which said ,"
, ., ,., ,,~ ., " ,,, ' ,, ., ' , :, ,, ; , ," ' ; ! ' , , 3 2 ~
2a 61051-2234 : subunits shall access said shared bus; each said arbitration means determining only whether said subunit coupled to said arbitration means is to be granted access to said shared bus;
each sa~d arbitra~ion means including:
status means for storlng status signals denoting which ones of said subunits have higher priorlty than the subunit corresponding to said arbitration means;
bus requesting means coupled to said arbitration bus for asserting a bus re~uest signal on said arbitration bus; and access control means, coupled to said arbitration bus and :
I said status means, for receiving bus request signals asserted on sald arbitration bus and for granting said corresponding subunit access to said shared bus only when said bus requestin~ means has asserted a bus request sigSnal and none of the received buæ request signals were asserted by the arbitration means of subunits denoted by said status means as having higher priority than said ~:
,l corresponding subunit;
~ characterized by:
.
a plurality o~ said subunits includlng means ~or ini~iating transactions which require a response by another of said subunits; --said bus requesting means including, in a plurality of said ~:
l arbl$ration means, means for asserting a bus request signal in i : response to the initiation of a transaction by one of said j subunits; and ~l said arbltration means includings state machine means coupled to said bus requestlng means, access control means, said shared bus and æaid arbitration J"'r~ ' ,:`
~ ' ~1 32~2 ..
2b 61051~2234 bus, for controlling the operation of said arbitration means, including meani for detecting when one of siaid subun.lts initiates a transaction which requires a response by another one of said subunits, for ~onitoring saicl arbitration bus for bus request signals and for aborting said transaction when no bus request signals are detected by said monitoring means.
According to another broad aspect of the invention there is provided~ in a computer system having a multiplicity of siubunits in a computer system having a multipliclty of subunits .
interconnected by an arbitration bus with means for carrying a multiplicity of substantially simultaneous bus request signals, a method o~ arbitrating access by said subunits to a shared bus, the ~ steps of ~he method comprising: -`j storing, for each subunit, a distinct set of sta~us signals denoting which ones of said subunit,s have higher priority than said subunit;
asserting on siaid arbitration Ibus a separate bus request signal for each of those subunits w'hich need access to siaid shared ¦ bus, and substantially simultaneously, at each one of said subunits which asserted a bus request signal, comparing said bus request signals asserted on said arbitration bus with said stored status signals ~or said subunit and yranting said subunit access to said .. -~.
shared bus only if none of sald bu~ reques~ signals correspond to ~.
subunit% denoted by said stored status slgnals as having higher :.-' prioxity than said subunit; ~
; -,.:
'' ~C ';~' 1324~
2c 61051 ~234 said method characterized by the s~eps, performed substantially simultaneously at each of said subunits, of:
detecting when one of said subunits initiates a transaction which xequires a response by another one of said subunits;
asserting on said arbitration bus a bus request signal for : each subunit which responds to the initiation of said transactlon;
-' monitoring said arbitration bus for bus requ~st signals, and then aborting said transaction if no hus re~uest signals are detected by said monitoring step.
Brie~ Description Qf the Dra~inq ,, .
Figure 1 shows schematically an access control system controlling responding by a plurality of bus users of an , intercommunica~ion bus according to the invention.
~I Figure ~ shows in block diagram form an access ;l controller used in the responæe control sys~em of Figure 1. -.
Figure 3 shows details o~ khe priority state store and the arbitration logic used in the access controller of Figure 2.
.'~
~3 .
I
~ 3 ~ 3 2 Figure 4 shows in detail the constructi~n of interconnect keys used in the access c~ntrol system of Fig. 1.
Figure 5 shows timing signals used in the access control system of Fig. 1.
Figure 6 sh~ws the operations of a stat~ machine u~ed in the invention.
Figure 7 shows the connections of update circuitry of the access c~ntroller of Fig, 2.
,~
Figure 8 shows the connection scheme of the ~interconnect keys of thP access control system of :~Fig. 1.
,,~ .
Detailed DescriPtion With reference to thP Figures, access control system ~15 10 according to the invention controls use o~
`~int~rcommunication bus 14 ~y ~proc~ssor users 12, 13, and i/o dçvice 16. Information is transferred on the in~ercommunication bus in predefined related ~equential or parallel operations denominated a 20 transaction. ~here may be several types of transaction with distinct operations such as reading or writing ts~ the cache memory o~ another processor, `~acknowledgement o~ interrupts, and reading or writing to input-output devices. Certain transac:tions, ~25 notably ~nterrupt acknowledg~ and memory read, are ,~inil:ialted by one user an~ require a response from another user.
,~ .
Ac~ess control ~ystem 10 as ~hown particularly in Fig~ 1, includes arbitration bUs 21, having n 30 channels, control bu5 22, and bus system clock 23.
~ Bus system clock generates and propagates t~ all bus ,~
user~ timing signals ~hich define definite time increments which synchronize the whole bus system.
The clock propagates to all bus stations a primary periodic signal (the A clock) the rising edge thexeof defining the start of a new time increment. The clock also propagates a secondary ~ignal (the B
clock) phase shifted from the A clock, the rising edge of which define~ a time towards the end o~ each time incre~ent. The B ~-lock is generally USRd to admit signals into latches after propagation ~ transients have subsided. The clock signals are ; diagrammed in Fig. ~. :
.1 RPpresPntative user 12 is connected to associated access controller 17 by bus request line 19, by 15 response ready line 50l by grant line 20 and by ~ response enable line 51, and to intercommunication ; but 14, control bus 22, and bus system clock 23.
Access controller 17 is connec:ted directly to control :~l bus 22 and bus system c.lock 23, and through J 20 interconnect key 24 to arbitration bu5 21. User 12, together with its access conlroller 17 is connected ~;~ to interconnect key 24, initialize key 38 and . intercommunication bus 14 through standard poxt 47.
: User 13 and further u~ers inc~uding i/~ ~evice 16, : 25 are connected as is user 120 ~ Access controller 17` includes transmit line 25, :.~7, (n - 1) monitoring lines 26, control circuitry 27, drive circuitry 28g priority ~tate ~tore 29, ~;~' arbitration logic 30, acces~ grant cir¢uitry 31 with grant latch 37, update circuitry 32, no-bid circuitry , 33, initializ~ gate 39 and update gate 34, ~'; intQrconnected as shown in Fig. 2.
Fur~her details of priority state store ~9 and .. arbitration loyic 30 are shown in Fig. 3~ Priority : .
,. .
. ,~,, .
r ' ~
~ 3 ~
state store 29 includes (n - 1) two-state storage elements 35, advantageously flip~flops. From storage elements 35 outputs pass in parallel to (n - 1) AND
gates 36. Monitor lines 26 also pass in parallel to AND gates 36. Outputs of AND gates 36 ar~ combined with the signal T on transmit line 25 as shown to produce the signal P.
~ Update circuitry 32, as shown particularly in Fig. 7, I connects kransmit line 25 to the set inputs of each ., 10 of two state storage elements 35 and connects the monitor lines 26 respectively to the reset inputs of each of the storage elements 35. These connections are made through update gate 34. The output lines 40 from initialize key 38 are connected through ~, 15 initialize gate 39 to the set and reset inputs of torage elements 35.
Control circuitry 27 includes a cycling state machine 46 which controls the operation of ac~ess controller 17 and keeps track o~ what is happening on the intercommunication bus. The operation of this state . machine is diagrammed in Fig. 6 and will be further discussed in connection with the system operatinn.
' ., Access c~ntroller 18 and further access c~ntrollers are identical to access controller 17.
1 :
~25 Turning to the op~ration of the system, a user .~typically operates quasi-independently processing instructions, u~ing it~ own local cache memory and .~.
with its own synchronizing clock which is not that of `~the bus or other users. From time to tim2 the '~30 computations per~ormed will generate a re~uirement t~
exchange information with another system component.
.~Typical events requiring information exchange are need for data ~tored in another usar's cache mPmory, . "~. . , _6_~32~2 need to update data stored in another users memory,and need to obtain information from an i/o device in order to proces~ an interrupk. Information is exchanged over the intercommunication bus in a transaction. Th~re may be several types of transaction but each will have a defined format specifying what is transmitted on which bus component .and in what ~rder. In the system dPscri~e here, the format calls for signals identifying the transaction type to pas~ on the control bus and detailed ~,information such as addresses and data to pass on the ::
intercommunication bus. When a user has need to communicate over the bus system it loads output ~,buffers with the information to service a transaction '.15 and then transmits to its access controller 17 a bus ~request signal R on bus reguest line 19 indicating -ilthat it seeks to u~e the intercommunication bus and is ready to initiate a transactionO When a grant ~,signal G is received from ac:cess controller 17 on grant line 20 the user begins a bus transaction.
A user also continually monitors the buses to detect signals indicating that a transaction initiated by another user requires the monitoring user to provide a response~ When it detects such a signal, it loads 25 the response into output buffers and when these are -~
ready it emit~ a response ready signal ~' on line 50 to it5 controller 17. Then when a respon~e enable signal ~ is received on line 51, it begins ~tran~mission o~ the respon~e~ :.
,~ ..
~h~ operation of acce~s controller 17 is organizPd by ,.;.control circuitry 27 which can be und~rstood with reference to its skate machine diagrammed in Fig. 6.
~Thi~ state machine passes from state to sitate through -~ilocps with no particular ~tarting point. It .,, :.
,,`' .
-7~ ~32~2 transfers from one state to the next with t~e onset of each time increment marked by the A clock.
.
~It will be. conveni~nt to follow the operation of the :,ætate machine from a point when it has just entered .5 into the state C at the top of the diagram. The existence of the ~tate machine in state C defines a contention interval, and during this interval control CirGuitry 27 emits an active C signal which, as shown in Fig. 2, is applied to drive circuitry 28, access grant circuitry 31, and n~-bid circuitry 33~ At the end o~ the time increment marked by the A clock, if control circuitry 27 has received an active n~-bid signal X from no-bid circuitry 33 it reenters state C; absent the no bid signal it shifts to state U.
The C and clock signals are shown in Fig. 5.
,.
The existence of the state machine in state U defines a us~-signal interval, and during this interval, control circuitry 27 emits an active U signal as shown in Fig. 5. The U signal, as shown in Fig. 2, is applied to access grant ciLrcuitry 31 and update gate 34. During the time increment when the state machine exists in the U ~tate, control circuitry receives from control bus 22 signals indicating which typ of transaction is being initiated by one o~ the users 12. In accordance with these rec~ived signals, at the end of the period the ~tate machine branches to one of se~eral transaction completion states, denominated Z, each corre~po~ding to one of the pr~de~ined transaction types. :.--l ..
l30 The transaction types A, B are representative of -.~rather simple transaction6 such as ef~ecting transfer o~ data from the ~nitiating user to an input-output device. L~nger and more complex transactions may also be defined and use as illustrated by transacti~n -8~ ~ 3 ~
type C. For all transactions the state machine continues through a chain o~ successive transaction completion states as may be required to complete the particular transaction type which is in progress.
When the state machine reaches the end of whatever chain it is following it reverts to state C and beyins another contention interval.
The Type D branch chain is of particular relevance to the present invention. Such a transaction is exemplified by an interrupt acknowledge transaction which may occur when a processor-user wishes to service an interrupt and initiates a Type D
transaction to obtain needed information. On branching according to a Type D transaction, the ~ 15 state ma.chine enters state C'. ~he existence of the ;l state machine in state C' defines a response bid interval, and during this interval control circuitry 27 emits an active C' signal which, as shown in Fig. 2, is applied to drive circuitry 28, access j 20 grant ~ircuitry 31, and no-bid circuitry 33.
¦ At the end of the time increment for existence in 3l- ~tate C' (marked by the A clock), if control ~' circuitry 27 has received an active no~bid ~ignal X
~ ~rom no-bid circuitry 33 it reenters state C; absent ;~ 25 the no-bid signal it shif~s ~o state V.
The existence of the state machine in the V state ~ de~ine~ a respon~e enablement interval, and during .~ this interva~ control circuitry 27 emits the V
.~ ~ignal, which, as shown in Fig. 2, is applied to ac~s grant circuitry 31.
~, At the end of its period in the V state the state machine returns to state C shown at the top of ~ Fig. 60 '~
9 ~ 3 2 ~ 2 Control circuitry 27 also is responsi~e to a l'waik"
signal received from the control bus during any o~
; the ~tates to cause th~ ~tate machine to reenter a state r,ather than progressing to the next state.
This feature permits any user that is unready to keep up with the standard transaction pace to delay the advance of state machines in all controller~. by transmit ing the wait signal on the control bus.
It may be noted that while the operation of the state machine is contin~ent on signals received from the sontrol bus, it is indifferent to which user is emitting these signals. As a result the state machines of the several access controllers are in step keeping independent but identical records of the 1 15 state of the intercommunication bus.
i ~onsider now the interactions o~ the signals emitted ~ by the ~ontrol circuitry with other e,lements of the ;l access controller. To ~acilita~te this discussion the signals on the (n 1~ monitor lines will be 20 designated Mi with i running 1 to (n - 1~. The signals of the storage elements 35 will be designated ~, Si with the index of the storage element 3~ corresponding to that ~f the monitor line connected to the ~ame one of ~ND gates 36.
, Z5 When the . ~ignal emitted by the control circuitry :~ durin~ a ¢o~tention interval i~ applied to drive 3, circuitry 28, it causa~ user 12 has signalled on ~ line 19 that it ~eeks to use the intercommunication -~ll bus, the transmission o~ a bu~ contention signal through interconneck key 24 to the arbitration bus channel associated with the user.
,~, Also during a contention interval any ~ontention signals transmitted onto the arbitration bus are .
3, -;, .
.~
- 10 ~ 3 2 ~
applied to arbitration logic 30, wherP they are logically analyzed with the signals out of priority state store ~9 to produce the signal P indicative of whether the user 12 has a dominating priority. If an active condition on an arbitration bus channel is denominated 1 and an inactive 0, and i~ the two states of the ~torage elements Si of the priority state ~tore are similarly denomina~ed, the loyical operation of the arbitration logic may be described in terms of modulo 2 arithmetic as P = T (M1S1 ~ 1) (M2S2 + ~ (Mn-1Sn-l + 1)-~, The C signal together with the B cloc~ applied to access grant circuitry 31 effect the capture of the P
signal i.nto grant latc~ 37 during th2 later part of 15 the contention interval. The contention signals from ~, the arbitration bus are also applied to and logically analyzed in the n~-bid circuitry 33, the r,esult being ~ emitted as the X signal by the application of the C
-~ ~ignal and the B clock. ~e X signal provides ¦ 20 control circuitry ~7 with the criterion for ;! immediately restarking ~ contention interval. ~:.
The U signal emitted by the control circuitxy during a use-signal interval is ap]plied to access yrant circuitry 31, and if the W signal ~u~ ~f the grant 25 latch 37 is asserted, this causes the G signal to be sent to user 12 on line 20. The G signal in turn - cause~ the emi~ting o~ the ~ signal from drive :~ circuitry 28. The U ~ignal together with the B clock . i~ also applied to update gate 34 to eff8rt the 30 updatlng of the priority ctorage elem~nts during the later part of the use-~ignal interval.
ij Control circuitry 27 is also responsive to an initialize ~ignal received on the control bus to J enable the trans~er o~ signals ~rom initialize key 38 . , "':
.,. ., .: . ,, . . . , . ~. . ....... : : . . , . : ..... .
~', i ', "" '' ' ,' ' ' . ' ' ' ', ' ' ',' , '" ' ' .' '' .~ ,; ,',. ' ` ' , '"' ~32~
~11--to priority state store 29 throuyh initialize gate When the C' signal emitted by the control circuitry during a response bid interval is applied to drive circuitry 28, it causes, if user 12 has signalled a response ready si~nal R' on line 50 indicating that it is ready to respond on the intercommunication bus, the transmission of a rssponse bid signal through interconnect key 24 to the arbitration bus channel ; lO associated with the user.
, I
Also during a response bid interval any response bid signals transmitted onto the arbitration bus are applied to arbitration logic 30, where they are logically analyzed with the signals out of priority ' 15 st~te s~.ore 29 to produce ~he signal P indica~ive of :~ whether the user 12 has a dominating priority, the analysis being as described in connectlon with the ~, contention interval.
.1 -~ The V signal emitted by the control circuitry during a response ~nablement interval is applied to access grant circuitry 31, and if the W signal out of the yrant latch 37 is at this tim~e asserted, this caus~s ;, the ~ signal to be sent to user 12 on line 51.
:;1 '' We now consider the global organization through which the several access controllers interact with each ~:,.. J other. It should be noted that the several controll~rs are all identical ln construction and operation. The only .distinctions between one controller and another lie in the interconnec~ keys 30 through which the controllers are connected to the arbitratiQn bus, in the information content of the priority state stores, and in the initialize keys ..
' Il~ ' ~ , 1 ' ' ' .. . .. . . . . . . . . . .
~32~2 which e~tablish initial values of the priority state stores.
Interconnect keys 24 interconnect arbitration bus 21 with access controllers 17 as shown particularly in 5 Fig. 4. In contrast to the controllers 17, which are all alike, the interconnect keys and the initialize keys are distinct and organized in a pattern on a global basis. Each key on its bus side has n connections connected to the n arbitratisn bus ~l 10 channels (which will be designated A1~ A2, ........ An)-J Each interconnect key on its contxoller side connects to the transmit line 25 (signal T) and to the ~n - l) monitor lines 26 (signals Mi) of its associated controller. A first interconnect key (designated K1) ~ 15 has internal connections connecting Al to its ¦ transmit line and the ~n - 1) bus channels other than A1 to the (n - l) monitor lines o~ its controller; a second interconnect key K2 has internal connections . connecting A2 to the transmi~: line and the (n - 1) 20 bus channels other than A2 to the ~n - l monitor lines o~ its controller; and so on through the interconnect keye. In particular/ the transmit line . : of each controller is connected through keys Ki to a distinc~ bus channel Ai. Thle connection scheme is 25 illustrated in Fig. 8.
Th~ initialize keys 38, a~ ~hown particularly in Fig. 4, generate slgnals from the voltage supply (O
and +) which are applied in direct or inverted order through initialize gate 39 to the ~t and reset 30 inputs of ~torage element~ 35 o~ priority ~tate store ~ 29.
:
`j In the ~irst nitialize key Il, (associated with access controller l and interconnect key ~ the :¦ connections ar~ ~uch as to apply the ~ voltage to the ~J
~2~
set inputs of none and the reset inputs of all of the storage elements, so that when the initiali~e gate 39 of access controller 1 admits the~e signals all its storage elements will be reset to 0O
In the second inikialize key I2, he conn~ctions are such a~ to apply the + voltage to the set input of the first storage element and the reset inputs of all of the higher indexed storage el~ments, ~o that when .the initialize gat~ 39 of acces~ controller 2 admits I10 these signals, the ~irst of its storage elements will be set to 1 and the higher indexed storage elements ~will b~ reset to 0, (The indexing of the storagP
,~felements is that of the associated monitor line and signal as assigned in the discussion of the interconnect keys.) iIn the third initialize key I3, the connçc~ions are 1such as to apply the ~ voltage to the ~et input of -~the first and second storage element~ and the reset :-~inputs of all of the higher indexed storage elements, ~!20 so that when the initialize gate 39 of access :~controller 3 admits the~e signals, the first and second o~ it~ storage elements will be set to 1 and the higher indexed storage elements will be reset to O.
.~
.. ~ . .
~25 The connection pattern continu~s to the higher -;~indexed ini~ialize keys, with the switching po~iti~n belQw which the ~ voltage is ~pplied to the s~t input increa~ing progressively ~or the higher indexed initialize Xey~. The nth initialize key has the ;~30 switching position above the highest indexed storage ~lement with the result that all it~ ~torage elements will b~ ~et7 The general pattern is illustrated in ~5the ~ollowing table:
.'~ ,,.
;
..
i .
, . ,, , ", , .. .. . ~ .. ~ . , .. : .. ..
32~ ~2 Initialize K~y Switch position between -, Storag~ Plements ______ _______ ______~ ___;:________ _ ~
~1 ... ~
Ij For purposes of a discussion of the global aspects of 10 the operation of the invention it will be convenient to use a different conv~ntion for identifying khe signals of the storage elements of priority state ~tore 29 tha~ that used in discussing the internal operation of a single controller. The storage 15 elements signals will be denominated with reference to their connections to the arbitration bus. Each ~d storage element i~ associatesl (in di~ferent way~) with two distinct bus channels. ~ 6torage element ~ignal will be designated ~ with the meaning that ; 20 it is in the ~ccess contro:Ller whose T line is ~,i conne~ted $hrough it~ interconnect key to bus channel i Ai, and is associated with channel Aj by being ,, con~ect~d to the ~ame AND ~ate 36 as channel Aj.
~, Since ~ND gates 36 are never connected to the same r 25 bus channel a~ T, the Sij are constrained by the c~ndition i not egual to j.
`'.'' ~he signals ~tored ~n the priori~y ~ta~e s~ore o~
~ each controll~r e~sentially indicate the curre~t : : priority of the controller against ~ach other 30 controller. That is, when S13 is 1, it indicates to ~-~
. controller l that controller 3 has a dominating -:
`~ priority. ~hile any combination of values may occur ::
in the (n ~ orage elements of a ~ingle , controlIer, not all global combinations of values of ::~
35 the n(n ~ ystem elements are compati~le with an ,.,:~ :
''~i , .
.~ , .
132~ 2 ordered priority ranking of the controllers. The global conditions that must be met by the stores to reflec~ an ordered priority ranking o~ ~he controllers are that Sij be not e~ual to Sji and that the numbsr of ones in ~ny controller store be : di~ferent from that in any vther. The organization of the initialize keys ensures that th~se conditions are met at the start of operations, and the organization of the interconnect keys ensures that all updating changes maintain the required conditions O
From a system viewpoint, each controller keeps track , in its priority state store of its priority status against each other controller. Then at the beginning ~ 15 sf the contention interval each controller, if it i seeks to initiate a transaction on the interco~munication bus, promulgates a bid to all 1 others by transmission on its proper arbitration channel (thak is, the one with which it is uniguely associated by connection through its interconnect key). Towards the end o~ thl2 contention interval, each controller through its arbitration logic ; analyzes the bid signals to det;ermine what controller ,~ is to be granted access to the intercommunication busç In the succ0eding use-sis~al interval the . bidding contro~ler which has been granted access ~nables its user to initiate a transactisn on the intercommunication bus and alæo announces this use to l all other controllers by ~mitting the T signal on its i~ 30 proper channel. Towards the end o~ the use signal interval (at the time of the B clock~ the ~ignals on the arbitrakion bus indicating which controller has u~ed the intercommunication bus are passed through the update gates and used to update the priority record. The using controller revises its record to show that every other controller now dominates it;
.~
~ 3 ~ 2 -16- .
each non-using controller records that the usiny controller i5 now subordinate to itself. The result of these revisions is to move the last using controller ~rom its previous position to the bottom of the priority order while otherwise leaving the priority order unchanged.
The system operation thus implements a policy o~
making the last initiator of a transartion go to the end of the priority line.
.j ~, 10 In dealing with certain transactions requiring a ~3 response and where there may be one, several, or n qualified responders, a respsnse bid interval occurs in which each quali~ied responder indicates that it ~l is ready to respond by transmission on its proper Y 15 arbitration channel of a response bid signal. These any signals placed on the arbitration bus during the response bid interval are analyzed to determine whether ~here is any bidding respond~r, and if SD
¦ which one has priority. I~ there is no qualified 20 responder the system without delay restarts the ,~ c3ntention for a new transacti.on; if there ar~ one or msre a quali~ied responders one is enabled to make the response. The operation during the rssponse bid ~ interval ~ollows the pattern o~ that during the '~ 25 contention interval and uses th~ same acce5s ~ controller circuit~y with advantag~s o~ economy. By , immediately rest~rting the primary contention for a new transaction when there is no bid for respons~, the sy~tem avoids tying up the buses waiting for a 30 reply that will never come.
.~ The response bidding operation does not make any ~-! reSvi~ion o~ the priority store in~ormation and so :~ does not inter~ere with the priority policy for :~ awarding most ancient user priority in initiating a ~1 ~J
~17-transaction. In most of the preceding discussion it has been assumed that a full complement of users was bidd.ing for the use of the intercommunication bus ~-that is that there are n actively bidding llsers for a system with n arbitration channels. The ~ystem works equally well if there are fewer than n users or if some users are passive, participating in transactions but nev~r initiating any. In such cases the nominal priority of the passive or non-exi~tent users will rise to the top ranks, but since these u~ers never bid for the intercommunication bus, the bus grant will always be to the highest rankiny bidding user.
The described 6ystem ~acilitates interchangeability of operating users on an intercommunication bus because the controllers are identical. Thus an intercommunication bus may ~e designed with the unique connect and initialize keys terminating in ~tandard ports to which a controller ~nd user can be connected. Users with different fun~tions can then be attached to any port indi~criminately.
,' ' .
OF ~N INTERCOM~UNICATIONS BUS ~:
Brief Summary of the Invention Computer systems may be organized with a plurality of / processors operating concurrently in parallel. In 3 such systems, the several processors operate yuasi 1 5 independently, but from time to time need to transfer , information between processors or ~etween a processor !~ and other system components such as input output devices. In order to ef~ect these in~ormation transfers, an intercommunication bus is provided :l 10 connecting to the processors and to other system s component, the bus being capable of transferring information from any user to any other. Such a bus is very flexible in its operation, but it is n~cessary to have some procedure to as~ure orderly 5 use of the intercommunicatiorl bus. This invention r lat es t o controlling access to an intercommunication bus shared ~y several users so as to pro~ide orderly use of the bus by a plurality of users. ~;.
20 The invention features a multi-channel arbitration ~; bus with each u~er as~ociated with a distinct channel thereof and a priority record for each user indicating current priority status of the associated user against each other user. A contention interval 25 and a use-signal in~erval are defined by a state ~, , ,"~;
~2~1~2 machine associated with each user. During the contention interval each user then seeking to use the in~ercommunica~ion bus bids ~or use of it by transmitting a bus request slgnal. Each user makes an analysis of ~he bus request signals to ascertain if it has a dominating priority for use of the intercommunication bus for a transaction iand access is granted accordingly. Duriny the use-siynal interval a user then using the intercommunication bus transmits an in-use slgnal. The in-use signal is used by each user to update its priority record with the effect of giving the lQ last using user a priority subordinate to all others for the next bidding to inltiate a transaction.
For transactions which require a response form some system user oth~r than the one initi.ating the tran~iaction, a Y second round of hidding is conducted to de~ermine whether any user ;`~ is qualified to respond and if so which will be enabled to do so.
When the response bidding shows no bidders the system immedlately initiates bidding for a new transaction; when there are one or more qualified responders, one is selected and enabled to respond.
According to a broad aspect o~ the invention there is ¦ 20 provided, in a computer sys~em having a multiplicity of subunits connected to a shared bus, distributed bus arbitration apparatus co~prlsin~:
an arbi~ration bus with means for carrying a mul~ipliclty of substantially simultaneous bus request signals; and a multlplicity o~ arbitration means, each coupled to ~he shared bus, the arbitration bus and a correspondiny one o~ the subuni~s, for determlning the relative priorities by which said ,"
, ., ,., ,,~ ., " ,,, ' ,, ., ' , :, ,, ; , ," ' ; ! ' , , 3 2 ~
2a 61051-2234 : subunits shall access said shared bus; each said arbitration means determining only whether said subunit coupled to said arbitration means is to be granted access to said shared bus;
each sa~d arbitra~ion means including:
status means for storlng status signals denoting which ones of said subunits have higher priorlty than the subunit corresponding to said arbitration means;
bus requesting means coupled to said arbitration bus for asserting a bus re~uest signal on said arbitration bus; and access control means, coupled to said arbitration bus and :
I said status means, for receiving bus request signals asserted on sald arbitration bus and for granting said corresponding subunit access to said shared bus only when said bus requestin~ means has asserted a bus request sigSnal and none of the received buæ request signals were asserted by the arbitration means of subunits denoted by said status means as having higher priority than said ~:
,l corresponding subunit;
~ characterized by:
.
a plurality o~ said subunits includlng means ~or ini~iating transactions which require a response by another of said subunits; --said bus requesting means including, in a plurality of said ~:
l arbl$ration means, means for asserting a bus request signal in i : response to the initiation of a transaction by one of said j subunits; and ~l said arbltration means includings state machine means coupled to said bus requestlng means, access control means, said shared bus and æaid arbitration J"'r~ ' ,:`
~ ' ~1 32~2 ..
2b 61051~2234 bus, for controlling the operation of said arbitration means, including meani for detecting when one of siaid subun.lts initiates a transaction which requires a response by another one of said subunits, for ~onitoring saicl arbitration bus for bus request signals and for aborting said transaction when no bus request signals are detected by said monitoring means.
According to another broad aspect of the invention there is provided~ in a computer system having a multiplicity of siubunits in a computer system having a multipliclty of subunits .
interconnected by an arbitration bus with means for carrying a multiplicity of substantially simultaneous bus request signals, a method o~ arbitrating access by said subunits to a shared bus, the ~ steps of ~he method comprising: -`j storing, for each subunit, a distinct set of sta~us signals denoting which ones of said subunit,s have higher priority than said subunit;
asserting on siaid arbitration Ibus a separate bus request signal for each of those subunits w'hich need access to siaid shared ¦ bus, and substantially simultaneously, at each one of said subunits which asserted a bus request signal, comparing said bus request signals asserted on said arbitration bus with said stored status signals ~or said subunit and yranting said subunit access to said .. -~.
shared bus only if none of sald bu~ reques~ signals correspond to ~.
subunit% denoted by said stored status slgnals as having higher :.-' prioxity than said subunit; ~
; -,.:
'' ~C ';~' 1324~
2c 61051 ~234 said method characterized by the s~eps, performed substantially simultaneously at each of said subunits, of:
detecting when one of said subunits initiates a transaction which xequires a response by another one of said subunits;
asserting on said arbitration bus a bus request signal for : each subunit which responds to the initiation of said transactlon;
-' monitoring said arbitration bus for bus requ~st signals, and then aborting said transaction if no hus re~uest signals are detected by said monitoring step.
Brie~ Description Qf the Dra~inq ,, .
Figure 1 shows schematically an access control system controlling responding by a plurality of bus users of an , intercommunica~ion bus according to the invention.
~I Figure ~ shows in block diagram form an access ;l controller used in the responæe control sys~em of Figure 1. -.
Figure 3 shows details o~ khe priority state store and the arbitration logic used in the access controller of Figure 2.
.'~
~3 .
I
~ 3 ~ 3 2 Figure 4 shows in detail the constructi~n of interconnect keys used in the access c~ntrol system of Fig. 1.
Figure 5 shows timing signals used in the access control system of Fig. 1.
Figure 6 sh~ws the operations of a stat~ machine u~ed in the invention.
Figure 7 shows the connections of update circuitry of the access c~ntroller of Fig, 2.
,~
Figure 8 shows the connection scheme of the ~interconnect keys of thP access control system of :~Fig. 1.
,,~ .
Detailed DescriPtion With reference to thP Figures, access control system ~15 10 according to the invention controls use o~
`~int~rcommunication bus 14 ~y ~proc~ssor users 12, 13, and i/o dçvice 16. Information is transferred on the in~ercommunication bus in predefined related ~equential or parallel operations denominated a 20 transaction. ~here may be several types of transaction with distinct operations such as reading or writing ts~ the cache memory o~ another processor, `~acknowledgement o~ interrupts, and reading or writing to input-output devices. Certain transac:tions, ~25 notably ~nterrupt acknowledg~ and memory read, are ,~inil:ialted by one user an~ require a response from another user.
,~ .
Ac~ess control ~ystem 10 as ~hown particularly in Fig~ 1, includes arbitration bUs 21, having n 30 channels, control bu5 22, and bus system clock 23.
~ Bus system clock generates and propagates t~ all bus ,~
user~ timing signals ~hich define definite time increments which synchronize the whole bus system.
The clock propagates to all bus stations a primary periodic signal (the A clock) the rising edge thexeof defining the start of a new time increment. The clock also propagates a secondary ~ignal (the B
clock) phase shifted from the A clock, the rising edge of which define~ a time towards the end o~ each time incre~ent. The B ~-lock is generally USRd to admit signals into latches after propagation ~ transients have subsided. The clock signals are ; diagrammed in Fig. ~. :
.1 RPpresPntative user 12 is connected to associated access controller 17 by bus request line 19, by 15 response ready line 50l by grant line 20 and by ~ response enable line 51, and to intercommunication ; but 14, control bus 22, and bus system clock 23.
Access controller 17 is connec:ted directly to control :~l bus 22 and bus system c.lock 23, and through J 20 interconnect key 24 to arbitration bu5 21. User 12, together with its access conlroller 17 is connected ~;~ to interconnect key 24, initialize key 38 and . intercommunication bus 14 through standard poxt 47.
: User 13 and further u~ers inc~uding i/~ ~evice 16, : 25 are connected as is user 120 ~ Access controller 17` includes transmit line 25, :.~7, (n - 1) monitoring lines 26, control circuitry 27, drive circuitry 28g priority ~tate ~tore 29, ~;~' arbitration logic 30, acces~ grant cir¢uitry 31 with grant latch 37, update circuitry 32, no-bid circuitry , 33, initializ~ gate 39 and update gate 34, ~'; intQrconnected as shown in Fig. 2.
Fur~her details of priority state store ~9 and .. arbitration loyic 30 are shown in Fig. 3~ Priority : .
,. .
. ,~,, .
r ' ~
~ 3 ~
state store 29 includes (n - 1) two-state storage elements 35, advantageously flip~flops. From storage elements 35 outputs pass in parallel to (n - 1) AND
gates 36. Monitor lines 26 also pass in parallel to AND gates 36. Outputs of AND gates 36 ar~ combined with the signal T on transmit line 25 as shown to produce the signal P.
~ Update circuitry 32, as shown particularly in Fig. 7, I connects kransmit line 25 to the set inputs of each ., 10 of two state storage elements 35 and connects the monitor lines 26 respectively to the reset inputs of each of the storage elements 35. These connections are made through update gate 34. The output lines 40 from initialize key 38 are connected through ~, 15 initialize gate 39 to the set and reset inputs of torage elements 35.
Control circuitry 27 includes a cycling state machine 46 which controls the operation of ac~ess controller 17 and keeps track o~ what is happening on the intercommunication bus. The operation of this state . machine is diagrammed in Fig. 6 and will be further discussed in connection with the system operatinn.
' ., Access c~ntroller 18 and further access c~ntrollers are identical to access controller 17.
1 :
~25 Turning to the op~ration of the system, a user .~typically operates quasi-independently processing instructions, u~ing it~ own local cache memory and .~.
with its own synchronizing clock which is not that of `~the bus or other users. From time to tim2 the '~30 computations per~ormed will generate a re~uirement t~
exchange information with another system component.
.~Typical events requiring information exchange are need for data ~tored in another usar's cache mPmory, . "~. . , _6_~32~2 need to update data stored in another users memory,and need to obtain information from an i/o device in order to proces~ an interrupk. Information is exchanged over the intercommunication bus in a transaction. Th~re may be several types of transaction but each will have a defined format specifying what is transmitted on which bus component .and in what ~rder. In the system dPscri~e here, the format calls for signals identifying the transaction type to pas~ on the control bus and detailed ~,information such as addresses and data to pass on the ::
intercommunication bus. When a user has need to communicate over the bus system it loads output ~,buffers with the information to service a transaction '.15 and then transmits to its access controller 17 a bus ~request signal R on bus reguest line 19 indicating -ilthat it seeks to u~e the intercommunication bus and is ready to initiate a transactionO When a grant ~,signal G is received from ac:cess controller 17 on grant line 20 the user begins a bus transaction.
A user also continually monitors the buses to detect signals indicating that a transaction initiated by another user requires the monitoring user to provide a response~ When it detects such a signal, it loads 25 the response into output buffers and when these are -~
ready it emit~ a response ready signal ~' on line 50 to it5 controller 17. Then when a respon~e enable signal ~ is received on line 51, it begins ~tran~mission o~ the respon~e~ :.
,~ ..
~h~ operation of acce~s controller 17 is organizPd by ,.;.control circuitry 27 which can be und~rstood with reference to its skate machine diagrammed in Fig. 6.
~Thi~ state machine passes from state to sitate through -~ilocps with no particular ~tarting point. It .,, :.
,,`' .
-7~ ~32~2 transfers from one state to the next with t~e onset of each time increment marked by the A clock.
.
~It will be. conveni~nt to follow the operation of the :,ætate machine from a point when it has just entered .5 into the state C at the top of the diagram. The existence of the ~tate machine in state C defines a contention interval, and during this interval control CirGuitry 27 emits an active C signal which, as shown in Fig. 2, is applied to drive circuitry 28, access grant circuitry 31, and n~-bid circuitry 33~ At the end o~ the time increment marked by the A clock, if control circuitry 27 has received an active n~-bid signal X from no-bid circuitry 33 it reenters state C; absent the no bid signal it shifts to state U.
The C and clock signals are shown in Fig. 5.
,.
The existence of the state machine in state U defines a us~-signal interval, and during this interval, control circuitry 27 emits an active U signal as shown in Fig. 5. The U signal, as shown in Fig. 2, is applied to access grant ciLrcuitry 31 and update gate 34. During the time increment when the state machine exists in the U ~tate, control circuitry receives from control bus 22 signals indicating which typ of transaction is being initiated by one o~ the users 12. In accordance with these rec~ived signals, at the end of the period the ~tate machine branches to one of se~eral transaction completion states, denominated Z, each corre~po~ding to one of the pr~de~ined transaction types. :.--l ..
l30 The transaction types A, B are representative of -.~rather simple transaction6 such as ef~ecting transfer o~ data from the ~nitiating user to an input-output device. L~nger and more complex transactions may also be defined and use as illustrated by transacti~n -8~ ~ 3 ~
type C. For all transactions the state machine continues through a chain o~ successive transaction completion states as may be required to complete the particular transaction type which is in progress.
When the state machine reaches the end of whatever chain it is following it reverts to state C and beyins another contention interval.
The Type D branch chain is of particular relevance to the present invention. Such a transaction is exemplified by an interrupt acknowledge transaction which may occur when a processor-user wishes to service an interrupt and initiates a Type D
transaction to obtain needed information. On branching according to a Type D transaction, the ~ 15 state ma.chine enters state C'. ~he existence of the ;l state machine in state C' defines a response bid interval, and during this interval control circuitry 27 emits an active C' signal which, as shown in Fig. 2, is applied to drive circuitry 28, access j 20 grant ~ircuitry 31, and no-bid circuitry 33.
¦ At the end of the time increment for existence in 3l- ~tate C' (marked by the A clock), if control ~' circuitry 27 has received an active no~bid ~ignal X
~ ~rom no-bid circuitry 33 it reenters state C; absent ;~ 25 the no-bid signal it shif~s ~o state V.
The existence of the state machine in the V state ~ de~ine~ a respon~e enablement interval, and during .~ this interva~ control circuitry 27 emits the V
.~ ~ignal, which, as shown in Fig. 2, is applied to ac~s grant circuitry 31.
~, At the end of its period in the V state the state machine returns to state C shown at the top of ~ Fig. 60 '~
9 ~ 3 2 ~ 2 Control circuitry 27 also is responsi~e to a l'waik"
signal received from the control bus during any o~
; the ~tates to cause th~ ~tate machine to reenter a state r,ather than progressing to the next state.
This feature permits any user that is unready to keep up with the standard transaction pace to delay the advance of state machines in all controller~. by transmit ing the wait signal on the control bus.
It may be noted that while the operation of the state machine is contin~ent on signals received from the sontrol bus, it is indifferent to which user is emitting these signals. As a result the state machines of the several access controllers are in step keeping independent but identical records of the 1 15 state of the intercommunication bus.
i ~onsider now the interactions o~ the signals emitted ~ by the ~ontrol circuitry with other e,lements of the ;l access controller. To ~acilita~te this discussion the signals on the (n 1~ monitor lines will be 20 designated Mi with i running 1 to (n - 1~. The signals of the storage elements 35 will be designated ~, Si with the index of the storage element 3~ corresponding to that ~f the monitor line connected to the ~ame one of ~ND gates 36.
, Z5 When the . ~ignal emitted by the control circuitry :~ durin~ a ¢o~tention interval i~ applied to drive 3, circuitry 28, it causa~ user 12 has signalled on ~ line 19 that it ~eeks to use the intercommunication -~ll bus, the transmission o~ a bu~ contention signal through interconneck key 24 to the arbitration bus channel associated with the user.
,~, Also during a contention interval any ~ontention signals transmitted onto the arbitration bus are .
3, -;, .
.~
- 10 ~ 3 2 ~
applied to arbitration logic 30, wherP they are logically analyzed with the signals out of priority state store ~9 to produce the signal P indicative of whether the user 12 has a dominating priority. If an active condition on an arbitration bus channel is denominated 1 and an inactive 0, and i~ the two states of the ~torage elements Si of the priority state ~tore are similarly denomina~ed, the loyical operation of the arbitration logic may be described in terms of modulo 2 arithmetic as P = T (M1S1 ~ 1) (M2S2 + ~ (Mn-1Sn-l + 1)-~, The C signal together with the B cloc~ applied to access grant circuitry 31 effect the capture of the P
signal i.nto grant latc~ 37 during th2 later part of 15 the contention interval. The contention signals from ~, the arbitration bus are also applied to and logically analyzed in the n~-bid circuitry 33, the r,esult being ~ emitted as the X signal by the application of the C
-~ ~ignal and the B clock. ~e X signal provides ¦ 20 control circuitry ~7 with the criterion for ;! immediately restarking ~ contention interval. ~:.
The U signal emitted by the control circuitxy during a use-signal interval is ap]plied to access yrant circuitry 31, and if the W signal ~u~ ~f the grant 25 latch 37 is asserted, this causes the G signal to be sent to user 12 on line 20. The G signal in turn - cause~ the emi~ting o~ the ~ signal from drive :~ circuitry 28. The U ~ignal together with the B clock . i~ also applied to update gate 34 to eff8rt the 30 updatlng of the priority ctorage elem~nts during the later part of the use-~ignal interval.
ij Control circuitry 27 is also responsive to an initialize ~ignal received on the control bus to J enable the trans~er o~ signals ~rom initialize key 38 . , "':
.,. ., .: . ,, . . . , . ~. . ....... : : . . , . : ..... .
~', i ', "" '' ' ,' ' ' . ' ' ' ', ' ' ',' , '" ' ' .' '' .~ ,; ,',. ' ` ' , '"' ~32~
~11--to priority state store 29 throuyh initialize gate When the C' signal emitted by the control circuitry during a response bid interval is applied to drive circuitry 28, it causes, if user 12 has signalled a response ready si~nal R' on line 50 indicating that it is ready to respond on the intercommunication bus, the transmission of a rssponse bid signal through interconnect key 24 to the arbitration bus channel ; lO associated with the user.
, I
Also during a response bid interval any response bid signals transmitted onto the arbitration bus are applied to arbitration logic 30, where they are logically analyzed with the signals out of priority ' 15 st~te s~.ore 29 to produce ~he signal P indica~ive of :~ whether the user 12 has a dominating priority, the analysis being as described in connectlon with the ~, contention interval.
.1 -~ The V signal emitted by the control circuitry during a response ~nablement interval is applied to access grant circuitry 31, and if the W signal out of the yrant latch 37 is at this tim~e asserted, this caus~s ;, the ~ signal to be sent to user 12 on line 51.
:;1 '' We now consider the global organization through which the several access controllers interact with each ~:,.. J other. It should be noted that the several controll~rs are all identical ln construction and operation. The only .distinctions between one controller and another lie in the interconnec~ keys 30 through which the controllers are connected to the arbitratiQn bus, in the information content of the priority state stores, and in the initialize keys ..
' Il~ ' ~ , 1 ' ' ' .. . .. . . . . . . . . . .
~32~2 which e~tablish initial values of the priority state stores.
Interconnect keys 24 interconnect arbitration bus 21 with access controllers 17 as shown particularly in 5 Fig. 4. In contrast to the controllers 17, which are all alike, the interconnect keys and the initialize keys are distinct and organized in a pattern on a global basis. Each key on its bus side has n connections connected to the n arbitratisn bus ~l 10 channels (which will be designated A1~ A2, ........ An)-J Each interconnect key on its contxoller side connects to the transmit line 25 (signal T) and to the ~n - l) monitor lines 26 (signals Mi) of its associated controller. A first interconnect key (designated K1) ~ 15 has internal connections connecting Al to its ¦ transmit line and the ~n - 1) bus channels other than A1 to the (n - l) monitor lines o~ its controller; a second interconnect key K2 has internal connections . connecting A2 to the transmi~: line and the (n - 1) 20 bus channels other than A2 to the ~n - l monitor lines o~ its controller; and so on through the interconnect keye. In particular/ the transmit line . : of each controller is connected through keys Ki to a distinc~ bus channel Ai. Thle connection scheme is 25 illustrated in Fig. 8.
Th~ initialize keys 38, a~ ~hown particularly in Fig. 4, generate slgnals from the voltage supply (O
and +) which are applied in direct or inverted order through initialize gate 39 to the ~t and reset 30 inputs of ~torage element~ 35 o~ priority ~tate store ~ 29.
:
`j In the ~irst nitialize key Il, (associated with access controller l and interconnect key ~ the :¦ connections ar~ ~uch as to apply the ~ voltage to the ~J
~2~
set inputs of none and the reset inputs of all of the storage elements, so that when the initiali~e gate 39 of access controller 1 admits the~e signals all its storage elements will be reset to 0O
In the second inikialize key I2, he conn~ctions are such a~ to apply the + voltage to the set input of the first storage element and the reset inputs of all of the higher indexed storage el~ments, ~o that when .the initialize gat~ 39 of acces~ controller 2 admits I10 these signals, the ~irst of its storage elements will be set to 1 and the higher indexed storage elements ~will b~ reset to 0, (The indexing of the storagP
,~felements is that of the associated monitor line and signal as assigned in the discussion of the interconnect keys.) iIn the third initialize key I3, the connçc~ions are 1such as to apply the ~ voltage to the ~et input of -~the first and second storage element~ and the reset :-~inputs of all of the higher indexed storage elements, ~!20 so that when the initialize gate 39 of access :~controller 3 admits the~e signals, the first and second o~ it~ storage elements will be set to 1 and the higher indexed storage elements will be reset to O.
.~
.. ~ . .
~25 The connection pattern continu~s to the higher -;~indexed ini~ialize keys, with the switching po~iti~n belQw which the ~ voltage is ~pplied to the s~t input increa~ing progressively ~or the higher indexed initialize Xey~. The nth initialize key has the ;~30 switching position above the highest indexed storage ~lement with the result that all it~ ~torage elements will b~ ~et7 The general pattern is illustrated in ~5the ~ollowing table:
.'~ ,,.
;
..
i .
, . ,, , ", , .. .. . ~ .. ~ . , .. : .. ..
32~ ~2 Initialize K~y Switch position between -, Storag~ Plements ______ _______ ______~ ___;:________ _ ~
~1 ... ~
Ij For purposes of a discussion of the global aspects of 10 the operation of the invention it will be convenient to use a different conv~ntion for identifying khe signals of the storage elements of priority state ~tore 29 tha~ that used in discussing the internal operation of a single controller. The storage 15 elements signals will be denominated with reference to their connections to the arbitration bus. Each ~d storage element i~ associatesl (in di~ferent way~) with two distinct bus channels. ~ 6torage element ~ignal will be designated ~ with the meaning that ; 20 it is in the ~ccess contro:Ller whose T line is ~,i conne~ted $hrough it~ interconnect key to bus channel i Ai, and is associated with channel Aj by being ,, con~ect~d to the ~ame AND ~ate 36 as channel Aj.
~, Since ~ND gates 36 are never connected to the same r 25 bus channel a~ T, the Sij are constrained by the c~ndition i not egual to j.
`'.'' ~he signals ~tored ~n the priori~y ~ta~e s~ore o~
~ each controll~r e~sentially indicate the curre~t : : priority of the controller against ~ach other 30 controller. That is, when S13 is 1, it indicates to ~-~
. controller l that controller 3 has a dominating -:
`~ priority. ~hile any combination of values may occur ::
in the (n ~ orage elements of a ~ingle , controlIer, not all global combinations of values of ::~
35 the n(n ~ ystem elements are compati~le with an ,.,:~ :
''~i , .
.~ , .
132~ 2 ordered priority ranking of the controllers. The global conditions that must be met by the stores to reflec~ an ordered priority ranking o~ ~he controllers are that Sij be not e~ual to Sji and that the numbsr of ones in ~ny controller store be : di~ferent from that in any vther. The organization of the initialize keys ensures that th~se conditions are met at the start of operations, and the organization of the interconnect keys ensures that all updating changes maintain the required conditions O
From a system viewpoint, each controller keeps track , in its priority state store of its priority status against each other controller. Then at the beginning ~ 15 sf the contention interval each controller, if it i seeks to initiate a transaction on the interco~munication bus, promulgates a bid to all 1 others by transmission on its proper arbitration channel (thak is, the one with which it is uniguely associated by connection through its interconnect key). Towards the end o~ thl2 contention interval, each controller through its arbitration logic ; analyzes the bid signals to det;ermine what controller ,~ is to be granted access to the intercommunication busç In the succ0eding use-sis~al interval the . bidding contro~ler which has been granted access ~nables its user to initiate a transactisn on the intercommunication bus and alæo announces this use to l all other controllers by ~mitting the T signal on its i~ 30 proper channel. Towards the end o~ the use signal interval (at the time of the B clock~ the ~ignals on the arbitrakion bus indicating which controller has u~ed the intercommunication bus are passed through the update gates and used to update the priority record. The using controller revises its record to show that every other controller now dominates it;
.~
~ 3 ~ 2 -16- .
each non-using controller records that the usiny controller i5 now subordinate to itself. The result of these revisions is to move the last using controller ~rom its previous position to the bottom of the priority order while otherwise leaving the priority order unchanged.
The system operation thus implements a policy o~
making the last initiator of a transartion go to the end of the priority line.
.j ~, 10 In dealing with certain transactions requiring a ~3 response and where there may be one, several, or n qualified responders, a respsnse bid interval occurs in which each quali~ied responder indicates that it ~l is ready to respond by transmission on its proper Y 15 arbitration channel of a response bid signal. These any signals placed on the arbitration bus during the response bid interval are analyzed to determine whether ~here is any bidding respond~r, and if SD
¦ which one has priority. I~ there is no qualified 20 responder the system without delay restarts the ,~ c3ntention for a new transacti.on; if there ar~ one or msre a quali~ied responders one is enabled to make the response. The operation during the rssponse bid ~ interval ~ollows the pattern o~ that during the '~ 25 contention interval and uses th~ same acce5s ~ controller circuit~y with advantag~s o~ economy. By , immediately rest~rting the primary contention for a new transaction when there is no bid for respons~, the sy~tem avoids tying up the buses waiting for a 30 reply that will never come.
.~ The response bidding operation does not make any ~-! reSvi~ion o~ the priority store in~ormation and so :~ does not inter~ere with the priority policy for :~ awarding most ancient user priority in initiating a ~1 ~J
~17-transaction. In most of the preceding discussion it has been assumed that a full complement of users was bidd.ing for the use of the intercommunication bus ~-that is that there are n actively bidding llsers for a system with n arbitration channels. The ~ystem works equally well if there are fewer than n users or if some users are passive, participating in transactions but nev~r initiating any. In such cases the nominal priority of the passive or non-exi~tent users will rise to the top ranks, but since these u~ers never bid for the intercommunication bus, the bus grant will always be to the highest rankiny bidding user.
The described 6ystem ~acilitates interchangeability of operating users on an intercommunication bus because the controllers are identical. Thus an intercommunication bus may ~e designed with the unique connect and initialize keys terminating in ~tandard ports to which a controller ~nd user can be connected. Users with different fun~tions can then be attached to any port indi~criminately.
,' ' .
Claims (7)
1. In a computer system having a multiplicity of subunits connected to a shared bus, a distributed bus arbitration apparatus comprising:
an arbitration bus with means for carrying a multiplicity of substantially simultaneous bus request signals; and a multiplicity of arbitration means each coupled to the shared bus, the arbitration bus and a corresponding one of the subunits, for determining the relative priorities by which said subunits shall access said shared bus; each said arbitration means determining only whether said subunit coupled to said arbitration means is to be granted access to said shared bus;
each said arbitration means including:
status means for storing status signals denoting which ones of said subunits have higher priority than the subunit corresponding to said arbitration means;
bus requesting means coupled to said arbitration bus for asserting a bus request signal on said arbitration bus; and access control means, coupled to said arbitration bus and said status means, for receiving bus request signals asserted on said arbitration busand for granting said corresponding subunit access to said shared bus only when said bus requesting means has asserted a bus request signal and none of the received bus request signals were asserted by the arbitration means of subunits denoted by said status means as having higher priority than said corresponding subunit;
characterized by:
a plurality of said subunits including means for initiating transactions which require a response by another of said subunits;
said bus requesting means including, in a plurality of said arbitration means, means for asserting a bus request signal in response to the initiation of a transaction by one of said subunits; and said arbitration means including:
state machine means coupled to said bus requesting means, access control means, said shared bus and said arbitration bus, for controlling the operation of said arbitration means, including means for detecting when one of said subunits initiates a transaction which requires a response by another one of said subunits, for monitoring said arbitration bus for bus request signals and for aborting said transaction when no bus request signals are detected by said monitoring means.
an arbitration bus with means for carrying a multiplicity of substantially simultaneous bus request signals; and a multiplicity of arbitration means each coupled to the shared bus, the arbitration bus and a corresponding one of the subunits, for determining the relative priorities by which said subunits shall access said shared bus; each said arbitration means determining only whether said subunit coupled to said arbitration means is to be granted access to said shared bus;
each said arbitration means including:
status means for storing status signals denoting which ones of said subunits have higher priority than the subunit corresponding to said arbitration means;
bus requesting means coupled to said arbitration bus for asserting a bus request signal on said arbitration bus; and access control means, coupled to said arbitration bus and said status means, for receiving bus request signals asserted on said arbitration busand for granting said corresponding subunit access to said shared bus only when said bus requesting means has asserted a bus request signal and none of the received bus request signals were asserted by the arbitration means of subunits denoted by said status means as having higher priority than said corresponding subunit;
characterized by:
a plurality of said subunits including means for initiating transactions which require a response by another of said subunits;
said bus requesting means including, in a plurality of said arbitration means, means for asserting a bus request signal in response to the initiation of a transaction by one of said subunits; and said arbitration means including:
state machine means coupled to said bus requesting means, access control means, said shared bus and said arbitration bus, for controlling the operation of said arbitration means, including means for detecting when one of said subunits initiates a transaction which requires a response by another one of said subunits, for monitoring said arbitration bus for bus request signals and for aborting said transaction when no bus request signals are detected by said monitoring means.
2. The distributed bus arbitration apparatus of claim 1, further characterized by:
said state machine means including state denoting means for denoting a first state during which said bus requesting means may assert a bus request signal, a second stats during which said access control means may grant access to said shared bus, a third state denoting the initiation of a transaction by one of said subunits which transaction requires a response by another one of said subunits, a fourth state during which said bus requesting means may assert a bus request signal in response to the initiation of a transaction by one of said subunits; and a fifth state during which said transaction takes place;
said state machine further including means for monitoring said arbitration bus for bus request signals and for returning from said fourth state to said first state when no bus request signals are detected by said monitoring means.
said state machine means including state denoting means for denoting a first state during which said bus requesting means may assert a bus request signal, a second stats during which said access control means may grant access to said shared bus, a third state denoting the initiation of a transaction by one of said subunits which transaction requires a response by another one of said subunits, a fourth state during which said bus requesting means may assert a bus request signal in response to the initiation of a transaction by one of said subunits; and a fifth state during which said transaction takes place;
said state machine further including means for monitoring said arbitration bus for bus request signals and for returning from said fourth state to said first state when no bus request signals are detected by said monitoring means.
3. The distributed bus arbitration apparatus of claim 1, said arbitration means further including:
use asserting means coupled to said arbitration bus for asserting a use signal on said arbitration bus when said access control means grants access to the corresponding subunit; and status updating means coupled to said status means for storing a status signal denoting low priority for each subunit granted access to said shared bus, and for resetting said status signals to a predefined state when said corresponding subunit is granted access to said shared bus;
whereby said multiplicity of arbitration means maintain distinct but consistent status signals in their respective status means.
use asserting means coupled to said arbitration bus for asserting a use signal on said arbitration bus when said access control means grants access to the corresponding subunit; and status updating means coupled to said status means for storing a status signal denoting low priority for each subunit granted access to said shared bus, and for resetting said status signals to a predefined state when said corresponding subunit is granted access to said shared bus;
whereby said multiplicity of arbitration means maintain distinct but consistent status signals in their respective status means.
4. The distributed bus arbitration apparatus of claim 1, said arbitration means further including:
use asserting means coupled to said arbitration bus for asserting a use signal on said arbitration bus when said access control means grants access to the corresponding subunit; and status updating means coupled to said status means for storing a status signal denoting low priority for each subunit granted access to said shared bus, and for storing high priority status signals for ail other subunits when said corresponding subunit is granted access to said shared bus.
use asserting means coupled to said arbitration bus for asserting a use signal on said arbitration bus when said access control means grants access to the corresponding subunit; and status updating means coupled to said status means for storing a status signal denoting low priority for each subunit granted access to said shared bus, and for storing high priority status signals for ail other subunits when said corresponding subunit is granted access to said shared bus.
5. In a computer system having a multiplicity of subunits interconnected by an arbitration bus with means for carrying a multiplicity of substantially simultaneous bus request signals, a method of arbitrating access by said subunits to a shared bus, the steps of the method comprising:
storing, for each subunit, a distinct set of status signals denoting which ones of said subunits have higher priority than said subunit;
asserting on said arbitration bus a separate bus request signal for each of those subunits which need access to said shared bus; and substantially simultaneously, at each one of said subunits which asserted a bus request signal, comparing said bus request signals asserted on said arbitration bus with said stored status signals for said subunit and granting said subunit access to said shared bus only if none of said bus request signals correspond to subunits denoted by said stored status signals as having higher priority than said subunit;
said method characterized by the steps, performed substantially simultaneously at each of said subunits, of:
detecting when one of said subunits initiates a transaction which requires a response by another one of said subunits;
asserting on said arbitration bus a bus request signal for each subunit which responds to the initiation of said transaction;
monitoring said arbitration bus for bus request signals, and then aborting said transaction if no bus request signals are detected by said monitoring step.
storing, for each subunit, a distinct set of status signals denoting which ones of said subunits have higher priority than said subunit;
asserting on said arbitration bus a separate bus request signal for each of those subunits which need access to said shared bus; and substantially simultaneously, at each one of said subunits which asserted a bus request signal, comparing said bus request signals asserted on said arbitration bus with said stored status signals for said subunit and granting said subunit access to said shared bus only if none of said bus request signals correspond to subunits denoted by said stored status signals as having higher priority than said subunit;
said method characterized by the steps, performed substantially simultaneously at each of said subunits, of:
detecting when one of said subunits initiates a transaction which requires a response by another one of said subunits;
asserting on said arbitration bus a bus request signal for each subunit which responds to the initiation of said transaction;
monitoring said arbitration bus for bus request signals, and then aborting said transaction if no bus request signals are detected by said monitoring step.
6. The bus arbitration method of claim 5, said method further characterized by:
said detecting step including the steps of denoting a first state during time periods in which a bus request signal may be asserted, denoting a second state during time periods in which said access may be granted to said shared bus, denoting a third state when one of said subunits initials a transaction which requires a response by another one of said subunits, denoting a fourth state during time periods in which a bus request signal may be asserted in response to the initiation of a transaction by one of said subunits; and denoting a fifth state during which said transaction takes place;
said aborting step including denoting said first state when no bus request signals are detected by said monitoring step while said fourth state is denoted.
said detecting step including the steps of denoting a first state during time periods in which a bus request signal may be asserted, denoting a second state during time periods in which said access may be granted to said shared bus, denoting a third state when one of said subunits initials a transaction which requires a response by another one of said subunits, denoting a fourth state during time periods in which a bus request signal may be asserted in response to the initiation of a transaction by one of said subunits; and denoting a fifth state during which said transaction takes place;
said aborting step including denoting said first state when no bus request signals are detected by said monitoring step while said fourth state is denoted.
7. The bus arbitration method of claim 5, said method further characterized by:
said granting step further including the step of asserting a use signal on said arbitration bus when said subunit is granted access to said shared bus;
and said storing step further including the steps of storing a status signal denoting low priority for each subunit granted access to said shared bus, and storing high priority status signals for all other subunits when said corresponding subunit is granted access to said shared bus.
said granting step further including the step of asserting a use signal on said arbitration bus when said subunit is granted access to said shared bus;
and said storing step further including the steps of storing a status signal denoting low priority for each subunit granted access to said shared bus, and storing high priority status signals for all other subunits when said corresponding subunit is granted access to said shared bus.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US123,382 | 1987-11-23 | ||
| US07/123,382 US4920486A (en) | 1987-11-23 | 1987-11-23 | Distributed arbitration apparatus and method for shared bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1324192C true CA1324192C (en) | 1993-11-09 |
Family
ID=22408371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000583478A Expired - Fee Related CA1324192C (en) | 1987-11-23 | 1988-11-18 | Controlling responding by users of an intercommunications bus |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4920486A (en) |
| EP (1) | EP0318221B1 (en) |
| JP (1) | JPH061458B2 (en) |
| CA (1) | CA1324192C (en) |
| DE (1) | DE3853574T2 (en) |
Families Citing this family (54)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5038274A (en) * | 1987-11-23 | 1991-08-06 | Digital Equipment Corporation | Interrupt servicing and command acknowledgement system using distributed arbitration apparatus and shared bus |
| US5237696A (en) * | 1988-04-13 | 1993-08-17 | Rockwell International Corporation | Method and apparatus for self-timed digital data transfer and bus arbitration |
| US5218703A (en) * | 1988-07-07 | 1993-06-08 | Siemens Aktiengesellschaft | Circuit configuration and method for priority selection of interrupts for a microprocessor |
| US5210871A (en) * | 1988-07-15 | 1993-05-11 | The Charles Stark Draper Labroatory, Inc. | Interprocessor communication for a fault-tolerant, mixed redundancy distributed information processing system |
| JPH0282343A (en) * | 1988-09-20 | 1990-03-22 | Hitachi Ltd | Interrupt handling method for multiprocessor system |
| US5274774A (en) * | 1989-01-31 | 1993-12-28 | Wisconsin Alumni Research Foundation | First-come first-serve arbitration protocol |
| US5155854A (en) * | 1989-02-03 | 1992-10-13 | Digital Equipment Corporation | System for arbitrating communication requests using multi-pass control unit based on availability of system resources |
| US5313620A (en) * | 1989-04-06 | 1994-05-17 | Bell Communications Research, Inc. | Selective receiver for each processor in a multiple processor system |
| US5151994A (en) * | 1989-11-13 | 1992-09-29 | Hewlett Packard Company | Distributed fair arbitration system using separate grant and request lines for providing access to data communication bus |
| US5506989A (en) * | 1990-01-31 | 1996-04-09 | Ibm Corporation | Arbitration system limiting high priority successive grants |
| IL96808A (en) | 1990-04-18 | 1996-03-31 | Rambus Inc | Integrated circuit i/o using a high performance bus interface |
| US6751696B2 (en) | 1990-04-18 | 2004-06-15 | Rambus Inc. | Memory device having a programmable register |
| JP2511588B2 (en) * | 1990-09-03 | 1996-06-26 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Data processing network, method for acquiring lock and serialization device |
| US5282272A (en) * | 1990-12-21 | 1994-01-25 | Intel Corporation | Interrupt distribution scheme for a computer bus |
| US5261109A (en) * | 1990-12-21 | 1993-11-09 | Intel Corporation | Distributed arbitration method and apparatus for a computer bus using arbitration groups |
| JP2855298B2 (en) * | 1990-12-21 | 1999-02-10 | インテル・コーポレーション | Arbitration method of interrupt request and multiprocessor system |
| US5613128A (en) * | 1990-12-21 | 1997-03-18 | Intel Corporation | Programmable multi-processor interrupt controller system with a processor integrated local interrupt controller |
| JP2561759B2 (en) * | 1991-03-29 | 1996-12-11 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Multiprocessor system and message transmission / reception control device thereof |
| US5546587A (en) * | 1991-05-30 | 1996-08-13 | Tandem Computers Incorporated | Decentralized bus arbitration system which continues to assert bus request signal to preclude other from asserting bus request signal until information transfer on the bus has been completed |
| US5371863A (en) * | 1991-05-30 | 1994-12-06 | Tandem Computers Incorporated | High speed processor bus extension |
| US5265223A (en) * | 1991-08-07 | 1993-11-23 | Hewlett-Packard Company | Preservation of priority in computer bus arbitration |
| US5359715A (en) * | 1991-09-16 | 1994-10-25 | Ncr Corporation | Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfaces |
| US5269005A (en) * | 1991-09-17 | 1993-12-07 | Ncr Corporation | Method and apparatus for transferring data within a computer system |
| US5848297A (en) * | 1991-12-30 | 1998-12-08 | Apple Computer, Inc. | Control apparatus for maintaining order and accomplishing priority promotion in a computer interconnect |
| JPH05257851A (en) * | 1991-12-30 | 1993-10-08 | Apple Computer Inc | Device for controlling order of transfer of data |
| US5640599A (en) * | 1991-12-30 | 1997-06-17 | Apple Computer, Inc. | Interconnect system initiating data transfer over launch bus at source's clock speed and transfering data over data path at receiver's clock speed |
| US5410677A (en) * | 1991-12-30 | 1995-04-25 | Apple Computer, Inc. | Apparatus for translating data formats starting at an arbitrary byte position |
| US5257385A (en) * | 1991-12-30 | 1993-10-26 | Apple Computer, Inc. | Apparatus for providing priority arbitration in a computer system interconnect |
| US5887196A (en) * | 1991-12-30 | 1999-03-23 | Apple Computer, Inc. | System for receiving a control signal from a device for selecting its associated clock signal for controlling the transferring of information via a buffer |
| ES2131065T3 (en) * | 1992-03-27 | 1999-07-16 | Cit Alcatel | ACCESS CONTROL PROVISION. |
| US5265212A (en) * | 1992-04-01 | 1993-11-23 | Digital Equipment Corporation | Sharing of bus access among multiple state machines with minimal wait time and prioritization of like cycle types |
| US5301283A (en) * | 1992-04-16 | 1994-04-05 | Digital Equipment Corporation | Dynamic arbitration for system bus control in multiprocessor data processing system |
| US5307466A (en) * | 1992-04-30 | 1994-04-26 | International Business Machines Corporation | Distributed programmable priority arbitration |
| US5488693A (en) * | 1992-06-24 | 1996-01-30 | At&T Corp. | Protocol with control bits and bytes for controlling the order of communications between a master processor and plural slave processors |
| US5313591A (en) * | 1992-06-25 | 1994-05-17 | Hewlett-Packard Company | Computer bus arbitration for N processors requiring only N unidirectional signal leads |
| US5463753A (en) * | 1992-10-02 | 1995-10-31 | Compaq Computer Corp. | Method and apparatus for reducing non-snoop window of a cache controller by delaying host bus grant signal to the cache controller |
| US5553248A (en) * | 1992-10-02 | 1996-09-03 | Compaq Computer Corporation | System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal |
| US5535395A (en) * | 1992-10-02 | 1996-07-09 | Compaq Computer Corporation | Prioritization of microprocessors in multiprocessor computer systems |
| US5353415A (en) * | 1992-10-02 | 1994-10-04 | Compaq Computer Corporation | Method and apparatus for concurrency of bus operations |
| US5553310A (en) * | 1992-10-02 | 1996-09-03 | Compaq Computer Corporation | Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems |
| JPH06205313A (en) * | 1992-12-28 | 1994-07-22 | Sony Corp | Av system |
| JP2821345B2 (en) * | 1993-09-29 | 1998-11-05 | 北海道日本電気ソフトウェア株式会社 | Asynchronous I / O control method |
| SG67906A1 (en) * | 1993-12-16 | 1999-10-19 | Intel Corp | Multiple programmable interrupt controllers in a multi-processor system |
| KR0155269B1 (en) * | 1995-01-16 | 1998-11-16 | 김광호 | Bus arbitrating method and its apparatus |
| US5842025A (en) * | 1996-08-27 | 1998-11-24 | Mmc Networks, Inc. | Arbitration methods and apparatus |
| US5991841A (en) * | 1997-09-24 | 1999-11-23 | Intel Corporation | Memory transactions on a low pin count bus |
| US6157970A (en) * | 1997-09-24 | 2000-12-05 | Intel Corporation | Direct memory access system using time-multiplexing for transferring address, data, and control and a separate control line for serially transmitting encoded DMA channel number |
| US6131127A (en) * | 1997-09-24 | 2000-10-10 | Intel Corporation | I/O transactions on a low pin count bus |
| US6119189A (en) * | 1997-09-24 | 2000-09-12 | Intel Corporation | Bus master transactions on a low pin count bus |
| US6026459A (en) * | 1998-02-03 | 2000-02-15 | Src Computers, Inc. | System and method for dynamic priority conflict resolution in a multi-processor computer system having shared memory resources |
| US7010050B2 (en) * | 2001-08-30 | 2006-03-07 | Yamar Electronics Ltd. | Signaling over noisy channels |
| US7890686B2 (en) * | 2005-10-17 | 2011-02-15 | Src Computers, Inc. | Dynamic priority conflict resolution in a multi-processor computer system having shared resources |
| US8032678B2 (en) * | 2008-11-05 | 2011-10-04 | Mediatek Inc. | Shared resource arbitration |
| DE102011007437A1 (en) * | 2010-11-15 | 2012-05-16 | Continental Teves Ag & Co. Ohg | Method and circuit arrangement for data transmission between processor modules |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4063220A (en) * | 1975-03-31 | 1977-12-13 | Xerox Corporation | Multipoint data communication system with collision detection |
| US4320457A (en) * | 1980-02-04 | 1982-03-16 | General Automation, Inc. | Communication bus acquisition circuit |
| FR2513407B1 (en) * | 1981-09-24 | 1987-01-16 | Finger Ulrich | ARBITRATION SYSTEM FOR REQUESTS FOR ACCESS OF MULTIPLE PROCESSORS TO COMMON RESOURCES, THROUGH A COMMON BUS |
| US4536839A (en) * | 1982-03-30 | 1985-08-20 | Mai Basic Four, Inc. | Memory request arbitrator |
| US4633394A (en) * | 1984-04-24 | 1986-12-30 | International Business Machines Corp. | Distributed arbitration for multiple processors |
| US4656627A (en) * | 1984-11-21 | 1987-04-07 | At&T Company | Multiphase packet switching system |
| US4719622A (en) * | 1985-03-15 | 1988-01-12 | Wang Laboratories, Inc. | System bus means for inter-processor communication |
| US4760515A (en) * | 1985-10-28 | 1988-07-26 | International Business Machines Corporation | Arbitration apparatus for determining priority of access to a shared bus on a rotating priority basis |
-
1987
- 1987-11-23 US US07/123,382 patent/US4920486A/en not_active Expired - Lifetime
-
1988
- 1988-11-18 CA CA000583478A patent/CA1324192C/en not_active Expired - Fee Related
- 1988-11-21 DE DE3853574T patent/DE3853574T2/en not_active Expired - Fee Related
- 1988-11-21 EP EP88310954A patent/EP0318221B1/en not_active Expired - Lifetime
- 1988-11-21 JP JP63294451A patent/JPH061458B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0318221A3 (en) | 1991-09-11 |
| DE3853574T2 (en) | 1996-01-25 |
| US4920486A (en) | 1990-04-24 |
| JPH021037A (en) | 1990-01-05 |
| DE3853574D1 (en) | 1995-05-18 |
| EP0318221B1 (en) | 1995-04-12 |
| JPH061458B2 (en) | 1994-01-05 |
| EP0318221A2 (en) | 1989-05-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1324192C (en) | Controlling responding by users of an intercommunications bus | |
| CA1078524A (en) | Destination selection apparatus for a bus oriented computer system | |
| EP0162050B1 (en) | Improved access-arbitration scheme | |
| US4754398A (en) | System for multiprocessor communication using local and common semaphore and information registers | |
| EP0343770B1 (en) | Multi-bus microcomputer system with bus arbitration | |
| US4034347A (en) | Method and apparatus for controlling a multiprocessor system | |
| US4797815A (en) | Interleaved synchronous bus access protocol for a shared memory multi-processor system | |
| US4050097A (en) | Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus | |
| US4030075A (en) | Data processing system having distributed priority network | |
| US6014729A (en) | Shared memory arbitration apparatus and method | |
| US4817037A (en) | Data processing system with overlap bus cycle operations | |
| EP0369264B1 (en) | Multiprocessor system having distributed shared resources and deadlock prevention | |
| US4796176A (en) | Interrupt handling in a multiprocessor computing system | |
| CA1221173A (en) | Microcomputer system with bus control means for peripheral processing devices | |
| US4006465A (en) | Apparatus for control and data transfer between a serial data transmission medium and a plurality of devices | |
| US5253347A (en) | Centralized arbitration system using the status of target resources to selectively mask requests from master units | |
| US4482954A (en) | Signal processor device with conditional interrupt module and multiprocessor system employing such devices | |
| US5119480A (en) | Bus master interface circuit with transparent preemption of a data transfer operation | |
| JPS6024499B2 (en) | Distributed multiple data processing equipment system | |
| GB1572972A (en) | Data processing apparatus | |
| JPS6048779B2 (en) | Modular data processing equipment | |
| US4236203A (en) | System providing multiple fetch bus cycle operation | |
| JPS62266642A (en) | Data processor | |
| US5038274A (en) | Interrupt servicing and command acknowledgement system using distributed arbitration apparatus and shared bus | |
| KR900001120B1 (en) | Distributed priority network logic for allowing a low priority unit to reside in a high priority position |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |