CA1324193C - High speed half duplex modem with fast turnaround protocol - Google Patents

Abstract

"HIGH SPEED HALF DUPLEX MODEM WITH FAST
TURNAROUND PROTOCOL"
Abstract of the Invention A modem with improved signal processing and handshaking capabilities as described. Two digital signal processors are used to perform independent, concurrent operations so that a faster execution rate is obtained and more precise calculations are made possible. The modem also uses an improved handshaking technique which allows the modem to maintain compatibility with existing 1200 and 2400 bps modems while allowing for negotiation for 4800 and 9600 bps communications. The modem also incorporates an improved baud clock recovery circuit which dynamically adjusts the actual sampling point in a manner dependent upon the difference between the actual sampling point and the optimal sampling point. This allows the actual sampling point to converge upon the desired sampling point at a high rate while minimizing filter around the optimal sampling point.

Description

~32~1~3 -. .

"HIGH SPE~ED HALF DUPlLEX MODEM~ WITHl ~FAST
TUR~AROUND PROTOC(3L,"
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Technical Field The preserlt invention relate~ to data communications and transfer and particularly describes a high :1 15 speed, half duple~ modem having a high speed handshaking :~
, procedllre and a half duple~ ~as~ line tllrnaround protocol.

lBackground o~ the Inverltioll ~he widespread use o~eomputing devices in t~e ;1, 20 llome and ~e o~fice created a need ~or a means whereby data could be quickly and convenlien~ly trarls~rred iFrom one :
computiIlg device to a~other eomputi~g device. Modems ;~. (modulator-demodula~or), in conjunction with the public ~elephoIle ne~work, subs~antially fill~ill ~is need. Modems co~ver~ ~e digital da~a used by a eomputing device into an analng signal capa~le of being transmit~ed over ~e public telephonesy~tem. : :
Full duplex operation (the abllity ~o send and ::
receive at the same time~ is typically preferred. Also, as ~e 3~ unt of data to be trans~r~ed from one device to another is `1 : increased~ highe~ data raltes (in bits per seeond) are gcnerally ;~ desired in order to reduce connection time and telephone ~ eharge~, especially where long distance communica~ions are -~ ;nvolved. However, a typical telephone line has a limited 35 bandwidth, approximately three kiloHertz, and this limited ~, .. . .

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.,.. , . , . ,, . .. , . .. , . , . . , , , . " , , , ., ~ . . , 1 32~3 - bandwid~, in conjunction wi~ background noise, cross~alk, and transmission line phase and amplit~lde distortion, places ~n upper limi~ on the rate a~ which data can be successfully transferred over ~he ~elephone line.
II1 the United Sta~es, communica$ion da~a rates up to 2400 bits per second (bps) are typically full duplex communications and comr~unication da~ ~te~ in excess of 2400 bps are typically hal~ duplex Gomm~nica~ions~ i.e.9 a modem can send or receive but not bo~ at the same time.
0 Some modems can communicate at a data ratc of up to 1200 bps, o~er moderns can communica~e up to 2400 ~ps~
and some modems can commT~nieate up to 9600 bps. In order for one modem to commurlicate with ano~er modem, the ~wo modems must agree upo;n a con~on data ra~e. The me~od hy which the two modems agree UpOIl the da~a rate is commonly called "handshaking". Recommendation V.22 bis of ~he Intema~ional Telegraph and Telephone Consul~ative Commit~ee (CCIlT~ recommends a handshaking proeedure which allows two modems to negotiate whether data will be trans~erred at 2~ 12û0 or 2400 bps. H[owever, there is no corresponding ~ecommendation w~i h allows ~e modems ~o negotiate whe~er ~e data will be transfPrred at 1200, 2400, 4800 or 9600 bps.
Therefor~ ~ere is a need for a hands~aking procedure whieh supplemen~s CCIl~ V.22 lbis so as to provide a uniform 2 5 handshaking me~od ~or data trans~er ra~es up to 9600 bps.
Full duplex commu~ications are generally avail~le where the data trans~er rate is 2400 bps or less.
However9 where ~e dat:a trans~r rate is in excess of 24~ bps, ~ull duple~c comrnunications devices are o~ten e~pensive and half 30 duplex operation becornes desirable. YYitlh half duplex operation, it becomes desirab~e for a f;rst modem to instruct a second modem ~at ~e ~st modem is dlrough transmi~ing and l! is now ready to receive. CCIIT recommendation X.25 $ provide~ a frame iFormat ~or dle e~cchange of data and control 35 information. However, the X.25 format provides more ~
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3 ~32~1~3 information and control bits than are absolutely necessary.
Since these bits must be transm;tted with each frame then some of the time which could be used to transmit data is was~ed transmitting unnecessary or unused control and information bits. Therefore, ~ere is a need ~or a half duplex forrnat which uses a minimum numbe~ of control and in~ormation bits, especially for a control ~ame where a ~Irs~ modem is advising a second modem ~hat it has no data ~o trans~er.
Most modems use one or two microprocessors to e~ecute the rnodem functions. HoweYer, at a 9600 bps communication rate, instruction e~ecutioIl time may become a limiting ~actor. Of course, ~ very high speed microproc~ssor ~:, could be used if the additional cost, power consumption, and localized heat generation can be accommodated. Lower speed, less expensive microprocessors could be used provided ~hat their ~uIIGtions were divided so as to be concurrent and :~ nonoverlappin~ and provided there was a means OI
communicating data between the two microprocessors.
-~ Therefore, there is a need for a me~hod for splitting the 2 0 exeeution tasks betwee~ the two mic~oprocessors arld a mearls or allow:ing t~e two microproGessors ~o exchange tlhe necessary da~.
Although a communication rate may be described ~ as, f~r e~ample9 9600 bps, dle bandwidth limitatiolls of ~e -1 25 telephorlle line prevent indiv;dual bits ~rom being serially ~ - ~ansmitted a~ 9600 bps. In order to achieve an effectiYe data ;~ ra~ of 9600 bps a series of bits is grouped toge~er to fo~m a set j~; Of b;tso 0ne e~ample of such a set is a quadbit (four bits). The !-~ quadbit is ~en used ~o modulate ~e phase alld amplitude sf ~e ' 30 carrier signal. The qua~bit is updated at a frequeIlcy known as :1 ~e baud rate. Therefo~3 if the e~fectil~e communications rate is 9600 bps, and ~quadbits are used, then the baud ra~e is 9600J4-2400 baud. However, in order to accurately recover i~ the quad~it, it is necessary to sample the incoming sagnal at approximately the same place in each baud. This is !

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'~ . :'~' 4 ~32~3 accomplished by processing a signal to recover ~e baud clock.
Typically, an oscillator is set to appro~imately the baud clock frequency and the incoming signal is used to adjust the ~reguency and phase of this oscilla~or ~o exactly ma~ch the transmitted baud clock. The oscilla~or phase is often adjusted, by ~lxed increments, to match the baud cloek phase o~ the iIlcoming signal. However, if the f~ed incremen~s are too large therl ~e oscillator will not be able to precisely track the baud clock and ~erefore baud elock jitter will occur. Conversely, i:f ~e increment size is too small~ then it will take ~he oscillator an excessively long period to loc~ OIl to ~e ~ansn~it~ed baud clock.
. Therefore, ~ere is a need ~or a b~ud clo~ recovery circui~
which allows the ~covered baud clock oscillator to ~ickly and precisely lock on to ~e ~ansmitted baud clo~.
~ 1 5 ~¦ Summary of the Invention The present invelltion provides a modulator-demodulator (modem) with improved signal processing capability, handshaking and protoc~l techniques, and an 2 0 improved baud cloclc ~ecovery circuit.
Broadly stated, the present invention may be characterized as a modem whic,h divides the signal processing task ~tweerl two digital signal processors so ~hat independent operati~ns may bP perfo~ed in parallel, ra~er ~an in series, 2s and a ~aster exesution rate obtained. More particularly described, the present invention may be charaeterized as a metfhod and apparatus whereby two microprocessors ean exchange informatioll by using a common random access memory (RAM).
0 The present irlvention also may be characterized as a 9600 bif~s per second (bps~ modem which uses a handshaking ,1 ~ technique which is compatible with many eurren~y existing `:3 1200 and 2400 bps modcms.
Also, the present inYelltion may be characterized as ~1 35 a modem which uses an improved training sequenee which ' .

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~ 3 ~ 3 reduces the phase rota-tion effec-t when switching from the training mode of operation to the data exchange mode of operation.
Also, the present inven-ti.on may be characterized as a modem which uses a fas-t line turnaround protocol so that, when operating in the half duplex mode, a minimum of time is used in turning control of the line over to a first modem when the second - modem has no data to transfer.
The invention in one aspect provide a V.22 bis ~ 10 compatible handshake method for an originating modem -for 3 establishing communications with an answering modem at a selected `~ speed of 1200 bits per second (bps), 2400 bps, or greater than 2400 bps, comprising (a) sending a first sequence for a first predetermined period, (b) sending a second sequence for a second , 15 predetermined period while listening for the first sequence from i the answering modem, (c)(l) if the first sequence from the l answering modem was not heard, commencing communications with the ¦ answering modem at 1200 bps, (2) if the first sequence from the answering modem was heard, sendin~ a third sequence for a third predetermined period while listening for the second sequence from the answering modem, (dj(l) if the second sequence from the answering modem was not heard, continuing to send the third I sequence for an additional period of time and then commencing .-, training and communications with the answering modem at 2400 bps, 1~ 25 and (2) if the second sequence from the answering modem was;~ heard, commencing training and communications with the answering modem at a speed greater than Z400 bps.
¦ Further the invention provides a V.22 bis compa-tible `~ handshake method for an answering modem for establishing communications with a calling modem at a selected speed of 1200 bi-ts per second (bps), 2400 --bps, or greater than 2400 bps, comprising (a) l.istening for a first sequence from the calling :3 modem, (b)(l) if the first sequence from the calling modem was not heard, commencing communications with the calling modem at 1200 bps, (2) if the ~irst sequence from the calling modem was ~ detected, sending the -first sequence to the calling modem and `! listening ~or a second sequence from the calling modem, (c)(l) if : ':
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5A ~ 3 the second sequence from the calLing modem is not heard, commencing training and communications at 2~00 bps, (2) if the second sequence from the calling modem was heard, sending the second sequence and commencing training and communica-tions at a , 5 rate greater than 2400 bps.
Another aspect of the invention comprehends a fast line ' turnaround method for transferring data in the half-duplex mode, comprising (a) a data transfer protocol comprising (1) sending a , carrier for a first predetermined period, (2) sending a first idle signal for a second predetermined period, (3) sending at least one of a predetermined flag, (4) sending a data frame, the data frame not e~ceeding a predetermined number of bits, (5) repeating steps (a)(3) and (a)(~) until available data has been sent, sending a second idle signal for a -third predetermined lS period and (b) a no-data line turnaround protocol, comprising (1) ~ sending a carrier for a fourth predetermined period, (2) sending ;~ the first idle signal for a fifth predetermined period, (3) sending at least one of the predetermined flag and (4) sending the first idle signal for a sixth predetermined period.
~j 20 Still further the invention provides a method for ¦ correcting for a loss of equalization in an e~ualizer in a i calling modem for use with a calling modem engaged in half-duplex communications with an answering modem. The calling modem 1 procedure comprises detecting the loss of equalization in the ~S equalizer in the calling modem, waiting until the ans~ering modem has completed transmitting, sending a carrier for a first predetermined period, being silent for a second predetermined period, sending a training sequence to the answering modem for a third predetermined period, and reoeiving the training se~uence from the answering modem and using the training sequence to adjust the e~ualizer in the calling modem. The answering modem procedure comprises detecting the carrier sent by the calling modem, being silent during the second predetermined period, being silent during the third predetermined period and sending the 3S training sequence to the calling modem for the third predetermined period.
i The above characteristics and other improvements : ~1 .

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provided by the presen-t invention will become apparen-t from a reading of the Detailed Description below.
Brief Description of the Drawings Figures lA and lB are an illus-tra-tion of -the preferred embodiment o-f the improved handshaking technique.
Figure 2 is an illustration of the phase amplitude constellation used in the preferred embodiment.
Figure 3 is an illustration of the retraining request ~ sequence used in the preferred embodiment.
; 10 Figure 4 is an illustration of the communications I protocol used in the preferred embodiment.
Figures 5A and 5B are a schematic diagram of the p re f e r red emb od imen t .

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:1 , -~32~93 Figure 6 is a schematic diagram of an alternative embodiment ~or controlling the memoly.
Figure 7 is a schematic diagram of the preferred embodiment of ~he disride-by-1.5 divider.
Figure 8 is an illust~tion of the wave forms in the preferred embodiment oiF ~e divide-by-l .S divider~
shown with Figure 6.
Figure 9 is a blook diagram of ~e preferred embcdimen~ of ~e receiver baud clock phase lock loop control o circuit Figure 10 is a flow char~ of the process used by ~e preferred embodiment to calculate ~e lead~ag step size.

Detailed Description ^ TurIling now to the drawings, in which like numerals represen~ like compo:rlen~s ~roughout the several figll~S9 ~e preferred embodiment of ~e present invention will be described~ Pigures lA and lB are an illus~ration of the :! preferred hands~aking seguence. ~ the preferred embodiment, a calling modem 10 initia~es a call to and conducts :~ 2() commu~ications with an answering modem 12 over a standard .1 telephone line 11. Each modem 10, 12 is de~ned as havLng a transII~itter section (T~ which places si~als on telephone line 11 d a receiver seetion ~R) which ~istens for and detects signals on telephone line 11. The transmit~er section and receiver section of a modem may operate simultaneously, as in the full duplex mode, or altennately, as in ~e half duplex mode. The -~ callLng modem 10 therefore operates in ~e full duplex mode for sequences 13A ~rough 13E and 14A ~ough 14E9 and opera~es in the half duplex mode for sequences 30A ~rough 30I.
~j 30 Similarly9 ~e answeling modem 12 opera~es in ~he full duple~
mode for seqllences l5A ~rough 15F and 16A d~ough 16D, and operates in ~e half duple:~ mode for sequences 31A ~hrough 31~I.
¦ A.lthough the primary purpose of the illustrated .~ 35 i~andshaking se~quence is to dete~e whe~er communications ~ . .

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'.;,'' . ' ~ ' , ' . . . , : ' 7 ~ ~ 2 ~ 3 should be conducted at 4800 or 9600 bi~s per second ~bps), it is desirable to be able to comrnunicate with modems which can only operate at 300, 1200 and/or 2400 bps. ~herefor~, the first part of the handshake sequence inco~pora~es par~ of ~e CM~T
V.22 bis handshake se~quence recommenda~i{)n. ~e ~ransmitter section (T) of calling modem 10 places ~h~ call 13A and ~en erl~ers a period o:f silence 13B. The receiver section (R~ of calling modem 10 wa;ts 14A while the call is being placed and ~en lis~ens for and detects ~e answer tone 14B.
The receiver section (R) of ~e answering modem 12 waits 16A while the transmitter section ~T) first has a period of sileIlce 15A, ~en sends the 2100 Hz answer tone lSB and ~en en~ers a short periQd of silence lSC. A~ ~e lend of t~e shor~
period of silence lSC the transmitter section ~T) sends 15D the BCl sequence while ~e receiver section R lis~ens for and detects the presellce o~ the Sl seglllence. In accordance with recommendation V.22 bis sequence BCl is an unscrambled '1 binary 1 at 1200 bps and sequence Sl is unscrambled double 11ïbits 00 and 11 ~ 1200 ~ps.
A~ter dle receiver sectioIl lR of calling modem 10 has dete~ted 14C ~e BCl sequence i~rom ~swe~ng modem 12 -1 ~en ~e ~ansmit~er section T sends 13C the Sl sequence. Also, if c~lling modem 10 recognizes a sile~ answer l~y answering ; modem 12 ~eIl, after th~ silence period 13B, calling modem 10 will send 13C ~e Sl sequence. Normally, following ~e V.22 bis recornmerldation, ~e n~t act of ~e transmit~er sec~ion T of calling modem 10 would be to send se~en~e BC2. However, in ~e preferred embodiment, ~e transn~itter section T sends 13D
i3 sequence S2 before sending 13E sequence BC2. Seguence S2 is an unscrambled binary 0 at 1200 bps. Sequence S2 is of a suf~iciently short duration so as not to be detected as an interruption or cause problems wi~ handshakillg with a conventiorlal 1200 and/or 24~ bps modem.
7~ In an alternative embodiment, se~ence S2 is the same as sequeIlce Sl: unscrambled double dibits on and 11 at , . .

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8 ~2~3 1200 bps. CCII~ recommendation V.22 bis specifies $ha~
sequence Sl shall be 100 ~/- 3 milliseconds. In ~his alternatiYe embodiment sequence S2 is a continuation or prolonging of se~ueneç Sl. An answering modem 12 which is no~ capable oiF
S sp~eds in excess of 24()0 bps will not respond to the longer double dibit sequence. However, an answering modem 12 capable of speeds in e~cess of 2400 bps w;ll recognize the prolonged double d;bit se~quence as being the Sl sequence and ~e S2 sequence and respond accordingly.
Similarly, answering modem 12 ;x sending 15E
seguence Sl while listening for 16C sçquence S2 from the calling modem 10. If answering modem 12 detects 16C ~e S2 sequence then answering modem 12 responds lby sending 15F
~e $2 sequence. Calling modem 10, a:~ter send~g 13D ~e S2 seguence begins sending 13E ~he BC2 sequence while listening 1, 14E ~or the S~ seg~ence from answe~ing modem 12. At this il point 22 calling modem lû and ansYvering modem 12 are ready to enter ~e half duplex mode and begin ~e 48~ ~s ~nd 9600 bps handshaking sequ~nces.
It will be no~ed that if, at point 20, answering modem 12 has no~ detected ~e $1 sequence ~en, in accordance wi~ V.22 bis answering modem 12 co~i~ es wi~ ~e V.22 bis 12~3 ~ps 3handshake se~nce. Similarly, if ~e calling modem ~' 10 doe~ ~ot detect 141~ e Sl seque;nce ~en, at point 21, calling 2 s modem 10 will cont~ue wi~ e V.22 bis 1200 bps handshake sequen~e.
I:f answerillg modem 12 detects 16B the Sl sequence ~t does not detect l~C ~dle S2 se~ence ~en, at point 2:1, answe~g modem 12 will continue wi~ e V.22 bis 2400 bp~ handshaki~g sequence. Likewise, if calling modem 10 has detected 141D ~e Sl sequence but has not detected 141Ei ~he S2 sequellce t~hen~ a~ pOillt 22, calling modem 10 will continue with ~e V.22 bis 24010 bps hallds~laking sequence. Therefore, ~e preferred handshakin~ sequence maiIltains V.22 bis compatibility ~or communications with 1200 ~d 2400 bps ., .

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modems. It will be noted that the BC2 se~uence 13E has been sent by the calling modem lO so ~hat, in the event the S2 sequence is not returIled by the answering modem, the calling modem 10 will already have lbegun ~e iE3C2 se~quence required S to maintain compatibility with and handshaXe wi~ a ~1.22 bis 240() bps modem.
~he answering modem 12 ~lso maintains compatibility wi~ V.22 bis modems by sending ~e Sl and S2 sequences oIlly in response to detection of ~he Sl and S2 sequences, respectively, being se~ by ~e ealling modem 10 There~ore, ~e use of ~e S2 sequence allows compa~ibility wi~
existing V.22 bis modems to be maintained as well as providing a signal3ng scheme to indicate to a cormes~ted modemL ~a~ higher ~peed (g~eater ~an 2400 b~s3 operation is available.
- 15 Assuming now that calling modem 10 and answering modem 12 have indicated to each o~er ~at a data rate in excess of 2400 bps is desired and ~a~ ~ey a~e a~ point 22 prepanng to e~;t ~rom the full duplex mode to ~he half duplex mode. At ~irs$, bodl nnodems are silent. The calling modem is ;~ 2 0 silent 30A and ~en begins sending 30B ~he first training signal llRN1 s7vhile ~e answeriIlg modem 12 listens ~r ~d receives ~e TRN1 tralniIIg sequence and begins coarse training and adjus~nent ~ its equalizer. Tra~Ling sequence TRN1 is a non-phase encoded scrambled binary 1 at 4800 ~ps. T~e non~phase 2 5 encoded scrambled binary 1 is simil~, but no~ identical, to that de~ed by CCITT recommenda~ion V.32, Section 5.2.3 arld Figure 1. After the cornpletioIl of training sequence TRN1 ~, calling modem 10 theIl sends 30C a preferred communication speed rate request RR1. IiF calling modem 10 prefers communica~ns at 4800 bps thcn ~1 is a scrambled b~y 1 at J~ 480Q bps. However, if calling modem 10 prefers communication at 9600 bps, ~hcn RR1 will be a scrambled binary dib;t 01 at 4800 bps. When calling modem 10 has ~mished sending 30C rate request RRl it ceases transn~it~ing.
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~ 3 ~ 3 Answering modem 12,11p3Il detecting the end of transmission of the rate re~quest RRl, begills sending 31C the ~rst traLnillg sequence TRNl. Accordingly, callLtlg modem 10 receives 30D dle f;rst train~ng sequence TRNl and begins the coarse training and adjustment of its equalizer. Upon comple~ion of sequence TRNl answering modPm 12 sends 31D
rate request RR2. If ~1 ~es~ed 48~ bps ~en RR2 will simply aç~nowledge ~e 4800 bps request. However, if 3~Rl was a ~quest ~or 9600 bps ~en RR2 may be a confirmation of ~e o 9600 bps reqllest, ill whi~ case co~nunicati3ns will be at 96 bps, or a denial of the 9600 bps ~ques~, in which ease communicatiolls will commence at the 4800 bps rate. (:alling modem lû receives 30E ~e rate re~quest RR2 from t~e answerillg modern 120 X:P RRl or 1~R2, or bodl, designated 4800 15 bps, ~en, at point 33, modem~ :lO and 12, have completed ~e handshaking and can commence to corr~nunicate at 4800 bps.
E~owever, if RR1 and ~2 bo~ reguested 9600 ~ps, ~en, at point 33, modems 10 an.d 12 will co~nence the 9600 ', bps traiDing sequences.
~ 2 o After ~swering modem 12 has ~ased sending 31D
:i its rate request RR2 ~en calling modem 10 beg~s sending 30Fse~ond t~a;nin~ seq~lence TRN2. Sesuence TR~2 is a ~on-phase encoded bin~ry 1 at 9600 b:ps. For T~2 the output of ~e scrambler is grouped into quadbi~s and the last dibits o~
succe~sive quadbits are encoded into ~e A,B9C and D signal .~ states ~igure 2). While calling modem lû is sending 30F
sequellce TRN2 the answering modem 12 is receiving 31E
sequence ~2 and training its equalizer.
. After c~lling modem 10 has completed sending sequence lrRN2 it ~en sends 3~ sequence BC3. SequeIlce BC3 a scrambled binary 1 transmit~ed at 9600 bps. Answe~g rnodem 12 receives 31F~ se~quence BC3 and per~o~ms ~e final adjus~snen~ and training of its equalizer. As soon as calling modem 10 ~in~shes send~ng sequence 13C3 answer~ng modem 12 ~gins sending 31G sequence TRN2 so ~a~ calling modem 10 , ' ' .~ ~
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11 ~3~93 - can receive 30H the seguence and begLtl tra1ning its equalizer.
A:~ter sending se~quence TRN2 answering modem 12 sends 31H
the final seqllence BC3. Calling modem lû receiYes 30I
sequence BC3 and performs dle ~inal adjustment and training of its equalizer. After dle comple~ioIl of sending sequence BC3 by answe~ g modem 12 the modems are ready to begin half duple~
co~munications at 96~) bps. In ~e pre~rred embodiment, at sta~es 30I and 31F, the receiving modem must de~ect a~ least 32 consecutive b~ary l's. Xf ~is mumber is not detected, t~en dle 0 ~ceiv~rlg modem will request ~at sequences TRN2 and lBC3 be se~t again. This reque~t is ~e same as ~at used to ~dica~ a los~
of equalization. The periods of silenee and of sending a particular sequence are ~orninal and some variation is allowable wi~hout di~turbing ~e handshaking seguence.
l~e pr~sent invention i~ also compatible with 300 bps fre~ency shift keyed (FSK) modems. If answering modem ^~ 12 in a 300 bps modem or is set to answer a~ 300 bps, then answenng modem 12 will not send dle answer tone or ~e BCl, Sl, S2 sequence, but wi~l send a marl~ idle signal at 22~0 Hz.
Therefore, at point 22, caLIing modem 10 will, by default, switch to ~e !FSK mode to conrlect with a:n~we~n~ modem 12.
However, if answering rnodem 12has speed ~ up capability ~; and is set to allow ~ ups then, in response to the Sl,S2 and :~ BC2 sequences iFrom calling modem 10~ answering modem 12 2 5 will send ~e BCl, Sl and S2 sequences, as appropriate, and as ~1 ~ described a~ve~ to allow ~ connection at speeds greater ~an 3~) bps.
Likewise, iiP callLng modem 10 is a 300 bps modem or is set to orig~nate at 300 bps ~erl calling modem 10 will not 1l 30 send the Sl, S2 or BC2 sequences but will send a mar~ idle :~ signal at 1270 Hz. There~ore, if by point 20, answering modem12 has not de~ected the Sl or BC2 sequences answering modem 12 will look ~r the ma~k signal. If ~e mark signal is present answering modern 12 will switch to the FSK mode, send the 3 5 ma~k signal at 2250 Hz and ~en connect wi~ calling modem 10 !
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at 300 bps. However, if calling modem 10 has speed ~all-up capability and is se~ ~o allow fall-up t~en, in ~esponse to ~e lBCl sequence sent by answering modem 12, calling modem 10 will send dle Sl, S2 and BC2 sequellces, as descri~d above, ~o allow S the conrlect;on at speeds grea~er ~n 300 bps.
Figure 2 is an illustration oiF the pre~erred signal states for 4800 and 9600 bps eomrnunica~ions. ~ ~e preferred embodiment~ the 32 pOiIlt signal stxucture with trellls coding, as depicted in Figure 2 of V.32, is used ~r 9600 bps comlrmmication. Also, Ln ~e pre:~erred embodiment~ signal s~ates A, B, C, and I3 are used for 4800 bps training and communicatioIls. D~ s 00, 01, 105 and 11 co~respond to signal states A,B,C and D, respec~ively. As previously sta~ed, 1~1 and TRN2 are non-phase Pncod~d meaning ~a~ di~erential s ~quadrant encoding is not used. It will be appreciated tha~ ~e A, B, (: and D points are a 4 poin~ subset of ~e 32 point signal structlure. MakiIlg dle 4 point ~ai~ g struc~ure a subset of ~e 32 p~in~ sigrlal s~ructure r~duces the rotation effect when :, chan~ing ~r~m a 4 point decision process (training) to a 32 point decision process (9600 bps communicatioIls). The CCIlT
recomm~DLdatioIl V.32 training ]points are ~own as A', B', C' ~, and D' in Figure 2. It will be notçd ~at ~e V.32 t~aining poLnts e~ are not a precise subset of the 32 point signal struc~re and therefore the equalizer must compensate ~or the rotation effect 2 5 encou~tered when switching fronn the 4 point training pro~ess to dle 32 poi~t decislon process.

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NON-PHR~SE EIYCODED SIGNAL STATE~
.__ ~0 ~ (-3,-2) 01 B (~2,-3) ~ (~3.
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., T~ellis codiIlg is preferred because of its error detecting an~ correcting capability. In an alternative embodiment, trellis codiIlg is not used for 9600 bps 15 communicat;ans. In ~is alte~na~iYe embodimen~, ~he 16 poin~
signal s~ructu~, and ~e 4 point subset thereof, of Figure 1 of -~
CCI~Y recommendation V.32 is used iF~r training, 4800 bps communications, and 9600 bps comm~cations.
Turn now to Figure 3, which is an illustration of the loss of equalization/retra~n reque~t sequence. AssuIne that ~, the answering modem 12 is sending 51A data ~ e calling - :
modem 10, and ~at dle calliIlg nnodem 10, a~ter receiving SOA
a iE~r ~ penod of tiI~le7 undergoes a loss of equalization 50B.
When answering modem 12 ~mishes sending ~lA the data and 25 swi~ches to the receive mode 51B tihe calling modem 10 will ~, detec~ ~ end of ~e data and send 50C a Tl seque~ce. ~he Tl seqllence is de~Lned as a 150 millisecond burs~ of a 320 Hz tone.
The Tl sequence advises answeriIlg modem 12 ~at a loss of equaliza~ioll has oecurred and th~t retrainirlg is re~guested.
3a An~wering modem 12 ~hen confi~ns ~e ~equest by sending 50D
a 150 millisecond burst of the 320 Hz tone. At this poLnt, both the calling modern 10 and the answering modem 12 enter wait periods 50:1E, 511:~, respectively, which, in thei preferred env;romnent, are 250 milliseconds. At ~he end of the wait :-~
periods 50D, 51C, the modems go ts point 33 of :Pigure lB

, :

"" ' ' ' . '" .. . " ' ' " '" ' ' ' '' ' .' , ',''. ' ' ' "' ' ~ .' i ' ' ' . "".' ," .` . '' ', " , ` ' . . ' ' .~.', . , .,' .. ' ' . . '. ', ," 1, " , , , , . , , , , . , ,, . ~., , . j, ., , ., '; ' .' ~., ", . .1 ; ', ', , , ,. , ' , " " , ,' ,., ",' ", ', . . .

1~ ~3~ 9~

whereupoll the calling modem 10 begins sending 3ûF training se~uerlee TRN2.
A sirnilar operation occurs if the answering modem loses equal;zation. After ~he calling modem eompletes sending 52A the data and enters ~he rec~ive mode 52B, thel[l, if ~he answering modem 12, while reeeiving 53A da~a, has suiF~ered a loss of egualization 53B7 ~en answering modem 12 will send 53(: ~e Tl se~ence. l~e calling modem 10 will receive 52B
~e Tl sequence and coNfi~n the r~quest by sending 52C ~e Tl se~quence. Both modems will then enter the wait state 52D9 53E
and then go to point 33 in Figure lB to begin retraining sequence. It will be noted tha~ either modem can request retrain~g sequence but l~at9 a~er ~e wai~ sta~ 50E7 5113~ 52D, 53E~ ~e retrain sequence will begin at pOillt 33 in Fi~re lB and ~e calling modem will send ~e training sequence ~Irst. Algo, if cor~FirmatioIl of the request is not received the requesting modem w;ll repeat ~he Tl sequence until corlfirmatioIl is obtained or a time-out discolmeet occurs.
Tu~ now to Figure 4 whieh ls an illustration of -i 20 two ~ypes of ha~f duple~ communication~ be~weeIl ~e modems:
a da~ e~hangeg and a mlll exch~ge. In a data exchange, ~e transmitting modem, w~c}L may be ei~er ~e ca~ling modem 10 or ~e answe~ing modem 12, first places a start-up sequence 60 ;~' onto li~e 11 for a start-up per:iod, typically 15 milliseconds.
~' 2 5 During ~is start-up period 60, the trans~tter provides ~e ~our poimt constellation training se~quencst T~l~ TRN2, ~or 4800 bps or 9600 bps9 respec~ively, for appro~imately 15 :::
millisecond~. Ihis ~aining sequeIlce allows ~e recei~rer baud clo~ in ~e receiving modem to lock on, and Can7 if desired, be used to begin updating of dle adaptive equali~er u)ef~lcients in ~e receiving modem. This is followed by a ~ millisecond period 61a of the mark idle signal (scrambled lts using 32 poin~
constellation). The receivin~ modem b~gins looking ~r the mark idle signal 61a approximately 10 milliseconds a~ter the start of reception of startup sequence 60. The transmitting ,', ,:
: . :~ .

.,,~ ., . - . , .. . , , . , , ~ , . , , , , . . .; . . . . . ..

-1~ ~32~

modern then sends the flag 62a followed by a first da~a ~rame 63a. Flags 62 are the sequence 01111110. The receiving modem mllst detect 16 consecutive marks in dle mark idle s~ignal 61a before looking for flag 62a. Data ~ame 63a is followed ~y ano~ler flag 62b and a data frame 63b. C3ata frame 63b is ~ollowed by flag 62c and ~en data *ame 63c. Ihis flag/data ~rame process is repeated until ~e transmi~ting modem has sent ~e last data ~rame 63n and the last flag 62n~ e transmit~ing modem ~en sends rnark idle signal 61b wlhich acts as a line - 1 0 turnaround signal. ~e recçiving modem must detec~ at least 7 consecllt;ve marks in mark idle signal 61b to recognize marl~
idle signal 61b as ma~ing ~e end of ~e data e~changç. At ~is pOiltlt, sLnce this is a ha~ duplex operation, the transmitting moclem now enters ~e receiv~g sta~e and ~e modem which was ~he receiving modem now eI ters the transmitting state and transmits elements 60 through 63.
A data ~rame 63a comp~ises a l;nk layer header 63aa, a packet header 63ab, a variable leng~ da~a stream ~3ac, and a eheek~um 63ad. ~e data string 63ac is lpre~erably ~' 25 complessed data, ~ may be l;~comp~essed data. (:heeksum 63ad preferably eIlcomLpa~se~ parts 63aa, 63ab and 63ac, bult :may, if ~esired, encompass onl~y a se1eeted one or two of ~ese part~. Checsksum 63ad is used, ~ a mamler well known to Sdlose kil1ed in the art, to detect transmission e~rors in the ~'i 2s encompassed parts, 63aa, 63ab and 63ac. In ~e pre~erred embodiment, ~ k layer header 63aa con~o~ms to the protocol requirements speci~led for LAP-B headers, and checksum 63ad Si uses the HI:)LC/SDI.C cyclic redundaIlcy check (CRC) :1 : algo~ithms.
The packet header 63ab ear~ies sontrol ~: info~mation. One use of ~der 63ab is to designate whe~er s data string 63ac contains dat~ or instructions (for e~ample, dle "break" lnstructlon). There~~ y character cSan b~ used in sl data string 63ac to convey data or, if desired, to convey ( 35 , . . .
.~, ' .:

1~

instructions. Header 63ab is also used to transmi~ flow control information.
A data ~rame 63a need no~ con~ain packet header 63ab or data 63ac. lFor example, a supervisory data ~rame 63a which is used for link establishrnent, or an acknowledgement of a da~a reception, widl no r~tum dat:a, would consist only of link layer header 63aa and ehecksum 63ad. Link layer header 63aa speeifies whe~er a packet header 63ab exists.
~e presence or absenee of data 63ac is de~elmined in an inverse fashion. The data ~rame 63a is de~lned as that information between flags, sueh as flags 62a and 62bo A data ~rame~ such as 63a~ always colltains link layer header 63aa and ehecksum ~3ad, and header 63aa specifies whether packet ~ader 63ab exists. Ther~ore, wlhen ~e :flag at ~e end of frame 63a is de~ected, any information be~ween header 63ab and ehecksum 63ad is defined as data 63ac. The result is that the l.ongth of an indivi~al data ~rame~ such as 63a, will be depe~dent upon the con~o~L and/~r data information trans~e~ed.
Assume that a first device ~not shown~, connected ~o modem 10, can output da~a at a very high rate and a second d~viee (no~ shown~, cormected to modem 12~ can accep~ data at a s1ower rate. If modem 10 is allowed to transfer data ~o modem 12 as ~ast as ~e ~lrst device can output ~e data, dle buffer in dle seeorld d~Yice wil1 even~ually overflow and da~a will be lost.
There~re, ~e reeeiving modem, modem 12 in ~is exannp1e, send~ a credit or a pe~it to dle sendLng modç~m, modem 10 in this e~ample7 a~vising modem 10 how many data ~ames or packets 63a that the serldirlg modem may transmit. In the preferred emboclimen~, as explained below, a Inaximllm of 3~ seven da~a frarnes 63a is permitted. If modem 12 sends modem 10 a credit of four then9 once modem 10 has sent four data ~rames 63a, modem 10 camlot send any more data frames until modem 12 proYides modem 10 with ano~er credit figllre.
Therefore, if the second device advises modem 12 that its bu~fer is fu11 or substantia11y fu11, modem 1~ w;11 not send any ..
.
..

, ;,.- ~ ~ .; ,, . , , , ; ~ ; . 1 17 ~32~ 93 addi~ional credits to modem 10. Modem lû will ~en advise the first device to stop outputting data. OrLce the buf~er ;n t~e second device has room :for more data the second device will advise modem 12 t~at it is ready ~o accept more dat~. Modem 12 will send a credit to nmodem 10, and rnodem 10 will advise the :~irst device to send more data to modem 10 for transmission to modem 12. ~his process is ~epeated until ~e ~lrst devi~ has no more data to output.
Link layer header 63aa also contains imCorma~ion on ~e number of ~e ne~t frame expected to be received. If ~e receiving modem ~eceives a fsame wi~ a mlmber dif:~erent ~an that e~pec~d, the receiving modem will advise dle transmitting modem that an error has occu~red and provide the frame number expected to be received. l~e tlransmittiIlg modem will ~en ~ebrarlsmi~ the data, beginning wi~ ~is fr~ne num~er. : :
In dle preferred embodimentl ~he maximum data transmission leng~ for ~he series of ~lags 62a to 26n~1 and data frames 63a to 63n is approximately 9~ bytes. Also, ~e length of each individual data ~r~ne 63 is limited to approximately 128 by~es, and there carl be up ~o seven data ~rames 63 ~ a data exchan~e. At 96~ bps ~is yields a maximurn transmission time oP lLess ~an 1 second. Therefore~ o~e modem can only retain ,l con~ol of dle line for less ~an 1 second be:~ore relinquishing coIltrol ~o ~e other modem. l~is prevents the users from 2 5 havL~g to wait ~o~ an excessive period befor~ being able ~o send a new instruc~ion or addi~ional data. 'rhis limitation on the :-transmission length also assures that the transmittin~ modem penodically receives da~a so tlhat the r~ceiver carrier cloek and receiver baud clock timing recovery circuits are periodically 3c~ resyrlchroI~ized to the clocks in ~e o~er modem.
Also, ~he null e~change can be sent in appro~imately 77 milliseconds so that, when nei~her modem has da~a to send and ~hen one of ~e modems has data to send, dle modem widl data ~o send car~ quickly o~tain control of the line.
;s 35 1~ ~ 3 ~ 3 In aecordance with X.25 LAPB procedure, each transmission is acknowledged by use of header 63aa. HoweYer7 situa~ions frequently arise whereLn neither modem has data to transfer but it is desired to maintain the connectioll over S telephone line 11. In such situations it is also desirable to minimize the ~urnaround ~ime and protocol so tha~ when one nnodem has data to transfer there is no~ a long wait while the .~ other modem is still sending the no data line tu~arolmd protocol. Th~ mlll e~change meets these requirements. The null exchange comprises a c~rier s~up sequence 60, typ;cally 15 milliseconds, 5 milliseconds of mark idle 61a signal9 ~lve flags 62a-62e, and 15 milliseconds of ma~k idle 61b signal. The flags 62 are, aga~a ~e sequence 01111110. Also, as above, ~e rece;ving modem must detect at least 16 conseclltive l's in mark idle signal 61a and 7 collsecutive l's in mark id,le signal 61b. It will be appreci~ted ~hal: ~e null ex~hange is s~ilar to ~e data exc~ange but does not have clata frames 63a-63n or flags separating ~he da~a frames.
The null exchange may also be used to indicate an error condition. In the pre~erlred embodiment, if a modem :1 sends data, other ~an an acknowledgement, and gets a null ~Challge re5ponse3 ~en ~e sending mo~em will assume ~a~ the data was lost. T~ sending modem will dlen queIy the reeeiving modem ~o determine which ~ne ~e receiving modem expects 2 5 to receive next. The sending modern then begins retransmission, s~arting wi~ ~e indicated frame. lhe query and retrarlsmissioll are similar to the LAP-B protocol speci~lcations.
In an alternative embodiment, each modem 3Q measures9 or is programmed to assume, the period of time between the end of its transrnission and the beginning o:~ the receipt of ~dhe transmission from the other modem. This period . ~TpT3 includes the roundtrip propagation time and the tu~naround time of the other modem. A~ter period TpT is measured for several data transi~er cycles, the rlull exchange is , ;
., .: .

32~3 not sent bu~, after the end of a transmission, ~e transmitting modem waits ~r period TpT plus a sa~ety factor period (TSF3.
If nothing has been received at ~e end of ~PT ~ TSF~ ~en ~he transmitting modem presllmes ~a~ th~ receiving modem received ~e da~a correctly and has nothing ~o send. The ~ransmitting modem then resumes transmissioIl. Therefore, the turnaround time is reduced and ~e da~a ~roughput is increased by eliminating ~e time required to send a null exchange.
In order to veriiFy ~at ~e co~ec~ion between ~he modems is s~ill valid, ~Le ~ransmittiIlg modem periodically polls the receiving modem and, in response, ~e receiving modem sends a response, such as ~e null exchange. Alternatively, the receiving modem periodieally sends anL advisory~ such aLs t~e null e~change, to advise ~Le transmitt;ng modem that t~e lS rec&iving modem is still connelcted. If ~he response or the advisory is not received, then ~e transmittinLg modem assumes ~Lat ~he conn~ction has been brol~en and accordirlgly advises ~e device to WkLi~h it is co~nLected (SULCh as a computer).
Operation at di~erent speeds is also provided. For examLple~ the ca~ g modem 10 and the answering modem 12 ~ may ~nitially agree to commu~Lcate at 9600 b~s. Ass~nLe nLow at the noise level of telephone 1 Le 11 substantially increases for commllLnications in ~e direetion ~rom modem 10 to modem 129 but does not increase for conr~nunicat;ons from modem 12 to modem lLO. Communications in bo~h ~irections eould be dropped to 4800 bps9 but dlis does not t~e advantage of ~e fact ~at 9600 lbps çom~nunieations a~e still possible in one direction.
Therefore, in one alterna~ive embodimen~, each modem sends, preferably as part of packet header 63ab, a one 3~ bit indication of ~e ~eceived sigIlal quali~.
For example, a logic 1 for ~is bit indica~es that 9600 bps receptioII is good, a~d a logis O indica~es ~at ~600 bps .¦ recep~ion is no~ good. lhe other modem ~hetl ~lspects ~is bi~ to determine whether its transmission should be at 4800 bps or '~ 35 9600bps, andtransmits accordingly.

:, ,j .
~ . .

20 ~ 9 3 '~is allows the two modems to communicate at different speeds. In the example above9 calling mode~ 10 would transmi~ ~t 4800 bps and receive at 9600 bps, and answering modem 12 would ~ansmit at 960û bps and receive at 480() ~s. '~erefore, telep~one line 11 is used to its maximum capacity. ~e received signal quality is, of course, determined by ~e receiving modem. Means of measuring received signal for example, by measuring ~e received data error rate, are well :~ known to ~ose skilled in ~e art.
0 The above is not limited to 4800 or 9600 bps selection but, by using two or more bits, can also be used to allow speed fallup and speed ~allbacl~ for 300, 1200, 241)09 4800 and 9600 bps.
'l'here may be cases where ~e n~ise level is so 15 seYere as to prevent either modem from receiving ~allback instructions from dle o~er modem. ~ such cases9 ~e ~ailure to receive a speed instruetion will, after a predeterm~ned timeou~
period, :~r example, 250 milli~eeonds, eaus~ ~e modem to automatically fall back to the ~e~t lower speed until 2 ~ communica~ions are reestablished, ~nodler timeout oceurs, or a `'' disco~ect oceurs. Therefore, ~le modem falls back ~rom 9600 b~s to 4800 bps, ~en 4800 bp~ to 2400 bps~ and so ~ordl.
~ ~e preferred embodiment, to achieve fast line ~:
turnaroulld? ~e received data baud cloek is updated, even ~1~ 2 s ~ough not used, when transmitting in the hal~-duplex mode.
Likewise7 ~he transmit data baud clock is upda~d, even ~ough not used, when receivillg in dle hal~-duplex mode. This allows the baud clocks ~o free-run when not lbeing used so ~at, when ~e line is t~rned a~ound, ~e baud clocks will not be starting at 30 all arbitrary position but will have rema~ned, wi~in ~e clock ~:, accuracy tolerance, in 3ynchronization. Likewise, ~e transmit data carrier and receiver demodulation carrier are updated, even when not in use, so that as ~e modem altemates between ~he ~ransmit and receive modes, a minimum of adjustrnent is 3~ :

.:
.

~2~93 required to maintain synchroniza~ion with the connected modem.
Main~aining ~e clocks and carriers in ~is marmer allows a fast line turnarouIld rate to be achieved since minimal time is reguired for synchronization be~weeIl the modems.
~, Also, the egualizer coefficients are ~rozen while in ~e tr~nsmit mode. When returning to the receive mode, t~e eqllalizer coefficients a~ not updated ~or at about 24 milliseconds. This delay allows time for the transmitter of the o~er modem to stabilize and prevents ~e eqllali~er coef~lcients from being incorrectly updated. Thi~ techni~e also assists in achieving a ~, fas~ line tumaround rate. The r~sult of ~e high speed (4800 or -` 9600 bps), the ~as~ line tumarourld capability, and the specified maximum trans2nission lerlgth is to provide half-duplex opera~ion which closely sim~lates ~e per~orman~e obtainable from ~11 duplex operation.
l~e trailing mark idle 61b provides for detection of end of trarlsmission and is used by the receiving modem as a signal ~o change the operation of adaptive c;rcuits, such as:
~recze ~e equalizer ~ap coeffilcients, and begin free-running the receiver baud olock phase loe~d loop. This prevents these adaptive circuits from trying to adapt to the no-signal condition oecurr~ng a~ter ~e o~er modem ceases transmit~ g.
In ~he preferred embodiment, the master 2s microproce~sor and ~e slave microprocessor generate the above clocks, earriers, and equ~lizer coef~lcients.
I~ will be apprecia~ed that, espeeially at 9600 bps, ~e modem mus~ process ~e transmitted and received data signals at a very high speed. ~ a pre~erred embodiment, in order to process the data at the required speeds, two Texas ~i~ Instruments TMS 320lO digital signal processors a~e used in a -~ masterlslave relat;onship. Table 2 lists ~e differerlt funetions perfolmed by the master processor and the slave processor.
i *Trademark ~32~1~3 TABL~E 2 MASl[ER ANI) SLAVE FUNC:TIONS

s MAST~ __ M~I~E FUNCIION FUNCTION
__~
V.29 TRANS Phase enc~g, l~une pulse shap~g, ~lltenng, modulation.
____~ .
10 V.29 RCVR Automa~c gain con~l FIactionally spased (AGC), balld ~ming and adap~ve equalize~, ~ec~very9 Hilber~ trans~m ~ualize~ decision, demodula~on, ~ans- equilize~ e~r calcula-f~ring data to the other ~on, upda~ng adap~e modern circuits, sending equali~r coefficients, . . -data to ~e slave. phase ~acking ~nd phase 1 5 __ ~ d~
Y.32 TRANS Phase and Trellis encoding, None pulse shaping, filte~ing, modulation.
V.32 RCVR Autc(natic gain cctnl~ol, _ _ _ baud tLmillg and resl~very, adap~ve equalizer, Hilbe~t trans~o~ demodu- equalize~ decision, 2 0 ladon, Viter~ decoding, e~uali~er ~or calcula-phase decoding. ~n, upda~ng adapt;ve f eqll~iz~ coe~ficients, . phase tracking.
V.22,V.22 Phase encc~ing, pulse N~e ,i bis ~ B~Il shaping, filtering, and i 212 l~NS modulation.
~ ~ _ V.22, v.æ Aut~n~atic gain control~ F~actionally spaced :
:: ~ bis & BELL baud ~min~ and recovery, adap~ve equalizer, 7:12 R~VR~ ~EIil~i~t tr~nsform demodu- equaliær d~cision, lationj trans~erring da~a eqllalize~ error calcula- ::
~om ~he slave to the other ~on, up~ating adap~ve : ~.
modem circuits, sendin~ ~qualizer coeifficients, data to dle slave. phase ~racking and phase :~
3 0 decodin~.
V.21 &BE~LL A~m ~ ~ mm m~ Nm~
103A TRANS au~oco~relation, low pass ~: R~R filtering, mark/space decision, ~enerating /~ m mm~ m m .. ...
. .

~" .
.:
'''.

~, ~- " . .. , .. , ,, , . . , i, .. . . . ... . . . .. .. . .. .... .. . . . . . ... . .. ..

23 ~32~ 3 It will be noted :from Table 2 that one of ~he functions of the master processor is to transfer data between the slave processor and the o~er modem circuits. 17herefore~ it is necessary ~at ~e slave processor be able to exchaIlge data wi~
the master processor, aIld the mas~er processor be able to exchange data wi~ both ~e slave processor and with the other modem circuits.
Figures 5A and 5B are a schematic diagram of ~he preferred embodiment showing the connection between ~e master microprocessor, the slave microprocessor, ~d ~e other modem circuits. The o~er modem s~ircui~s 80 is connected to telephone line 11. O~er modem circuits 80 also has an RS-232C interface~ par~ of which is shown as transmit data (lXD) cvnd!uctor 81, reeeive data (RXD) conduetor 82, and data ca~er detect (DCD) conductor 83. The use of ~e TXD and RXD signals is straightforwarfl. However, in ~e preferred em~odiment, the DCD signal does not precisely reflect t~e presence or absence of ~e da~a carrier ln ~e half duplex modes.
It will be appreciateid that, in ~e ha~f duplex mode, :~ 2 0 ~ere i~ no recf~ived data c,arrier when the modem is transmi$ting. l[here~ore, if ~e I)CD signal precisely reflected ~e p~esence or absence of a data carrier t~en ~e DCD signal would indicate no carrier w~enever ~e modern was in the ~ transmit mode. This c~ callse problems wit~ some e~temal : ~ 2 5 devices (not show~) which treat ~e abxence of dle data carrier as a discormect or end of com~nunication signal. The~or~, in ~he preferred em~odiment, when operating in the half duple7 mode, orlce the data carrier is detected the DCD signal will :, become and remain active until the o~er modem circuits $0 0 have discsnnected ~rom ~lephone line 11. l~e DCD signal will also remaill active dur~ng momentary signal dropoutsl and requests for retraining. There:fore, the external device (not ;~ shown) is not advised of an absence of carrier until the cor~ullication wi~ the offler modem ~las been terrninated.

. ~ .
.,, . . .. .. .. . ., .. . ~ . ... . .. . . . . . . .
,; . . .. . . . ,-;; .,, .. : ; " ; - . ,. , , . , . i .. , ,, ,. , ~ . , , , ,, , , . , . " . .. .. . ..
.. , - - .. . ... . .. ~ , , . , ; . .... . . - , ~ , , " , : . .. , . , . ., , : .

132~19~

Other than those functions listed in Table 2 the other modem circuits 80 perform most of the ~emaining modem functions~ A few of those remaining functions are scrambling, descrambling, line interfacing, answer and guard tone g~neration, etc.
Means of constr~lction. of the other modem circuits 80 are well known to those skilled in the art. Also, means of construction and operation of other modem ci~cuits 80, and of interfacing other modem circuits 80 with ma~ter microprocessor 87 are described in CDN Patent Application Serial Number 521,043 filed October 21, 1986, now CDN Patent NoO 1,260,102 granted SeptPmber 26, 1989, by Jeffrey Inskeep and George R. Thomas, entitled n Improved Modem Controll~r~, and in CDN Patent Applicati.on Serial Number 541,519 file,d July 7, 1987 by Sweitzer, Nash, Correa, Easley, Tjahjadi, Pan~lla, Thoma~ and Martin, entitled "Modem With Impro~ed Digital ,~ Signal Processorn~
Th~ nega~d poLled iIlterrup~ r~quest ~NP~) ou~ut O~ ~e o~er modem circuits 80 i~; colmested by eon~uctor 84 to one input of a two input AND-ga~te ~5. The outpu~ of gate 85 is ::
conneçt d by eonduetar 86 to the negated pollcd interrupt request (NBI(~I~ input of microprocessor 87. In ~e preferred embodiment, microprocessor 87 is a type TM~* 32010 ::
z5 mar~factured by Te~as Instru:ments, ~c., Houston, Texas.
Details of operation and programming of ~e TMg~32010 have beeIl published by the manufactu~r and are available Up re~quest.
In ~e pre~rred em~odiment, ~ere are two types ~: 30 of polled interrupts: a memory 160 control turnaround9 -:
explained below, and a ring sigIlal. When a ring signal is ::
present on telephone line 11 ~e other modem circuits 80 will place an altematLng logic 0/logic 1 signal on conductor 84.
~en a ring signal is not present, ~e other modem circuits ~0 3s will place a logic 1 onto conductor 84. Also9 ~s explained , below9 NSINT conductor 95 will have a logic 0 on it when slave - . micropr~cessor 122 ~as control over RAM 160, and a logic 1 on 3 ~ :J6~ ::
~ ` *Trademark ::

.

i~ when microprocessor 122 turns control over RAM 160 back to master microprocessor 87.
Microprocessor 87 knows whether the polled interrupt is from the other modem circuits 80 or from microprocessor 122 by the mode of operation. If comznunications are not in progr~s, ~en slave microprocessor 122 will be idle, and dle internup~ mus~ come from ~e o~her modem circuits 80. Likewise, once communic~tioIls are in :' progress, ~en ~ere will be no r~nging signal on telephone line 1 0 11 so the interrupt must come from slave microprocessor 122.
.( l~e negated iIlterrupt request (NIN'rR) output of :~ ~e o~er modem circuits 80 is connected by con~ctor 90 to ~e D-input of flip-flop 91. The clock output (CLKOIJT) of microprocessor 87 i5 connected by conductor 93 to the clock inpult of flip-itlop 91. The Q ou~ut of flip-flop 91 is connected by conductor 92 to ~e negated inte~pt (NINT~ input of microprocessor $7. M;croprocessor 87 ~erefore receives ~wo t:ype~ of interrupts from ~e o~er modem circuits 80: a polled interrupt (NBIO); and, via fllip-flop 91, a synchronized interrupt (NINT). ~ the pre~erred embodiment~ the other :~ modem cirGuits 80 generates and provides to microprocessor ~7~: 9600 r~ceiver interrupts per second and 9600 transmitter interrupts per second.
Microprocessor 87 communicates with the other 2 5 modem circllits 80 via a negated write enable (NWEN~ signal on conductor 96, a negated memQry enable (NMEN) signal on ~J conductor 94, a ~ourbit subset (MA0-MLA3~ ~e 12 bit (MA0 s ~11) add~ess b~s (MADDR), ~e lower byte (MD0-MD7) of ~ the 16 bit (M~0-~15) lbidirectional dal:a bus (MDATA), and :-, 3~ an e~ternally generated random aceess memory enable ? (RAMEN~ signal on conductor 107. The RAMEN signal :, conductor 107 is provided by ~e output of ~our-input NAND-gate 106 using address lines MA8, MA9, MA10 and MAl 1 of MADDR. T~ NMEN, RAMEN, and NMWEN signals are used to write data from mieroprocessor 87 to the other modem , !

~, ~6 ~2~ 3 - - circuits 80. Similarly7 the N~N and RAMEN signals are used ~o read data from odler modem circuits 80 to microprocessor 87. Sirlce only address lines MA0-MA3 are used, other modem ci~ui~s 80 has a 16 word latch or random access memory, each S word being 8 bits long (MD0-MD7).
Microprocessor 87 derives i~s ope~ating instructions and o~her parameters ~rom a 4K by 16 bi~ r~ad only memory ~ROl\I) 110. ~e NM~M signal from microprocessor ~7 is connected by conductor 94 to ~e input of inver~er :111.
~ ~ 1 0 The output of inYer~er 1 1 1 is conrlected to one input of a 2-inpu~
N~D-ga~ 112. The CLKOUT output oiFmie~oproeessor 87 is conrlected by conductor 93 to ~e other input o:F gate 112. The ou~ut of gate 112 is connec~d to ~e nega~ed ch:ip select 1 (CS1) input of memory 110. ~he RAMEN signal on eoIlductor 107 is co~ected to the chip select 2 (CS2~ input of memo~y 110. The chip select 3 (CS3) input of memlory 110 is connected to a lngic 1. The 16 bit da~a outpu~ of memory 110 is connected to Ml:)ATA bu~ 102. Data is trans~rred ~rom memoly 110 to microprocessor 87 when RAMEN conductor 107 and CLKOUT
2 conductor 93 are a logie 1 and NMEN conduc~or 94 is a logic 0.
Bodl the other modem circui$s 80 and memory 110 are loca~ed ~,: in ~e memo~y address space of processor 87. MADDR is not ~ully decoded, therefore memory address 000 through EFF
(HEX) point to memory 110, and memory add~sges P00 s 2 s tl~ough F~F (HEX) point to other modem circuits 80. It will there~ore be appreciated that only 3840 words of the 4096 words in m~mory 110 are accessible. Of course, more of memory 110 could be used, if desired, by ~ully decoding MADDR.
~, 30 Microprocessor g7 also exchanges da~a with microprocessor 1~2 via a lS word by 8 bit RAM 16û. The data input/ou~puts (D0-D7) of RAM 160 are connected by bus 161 to ~e B0-B7 inputs/outputs of bidirectional ~ree-state buffers 157 and 162. ~ ~e preferred embodiment, bui~fers 157 and 162 are SN7~ALS245A octal bus transcfeivers. The A0-A7 '',' "' ' : ,, : , . . . , . ~ , , ,,:

27 ~ 3 ~

inputs/outputs of buffer 162 are cormected to the lower byte (MD0-~7) of master data bus 102. ~e A0-A7 inputJoutputs of buf~er 157 are connected by bus 171 ~o ~he lower byte (SD0-SD7) of the slave data bus (SDATA) input/output of slave microprocessor 122. Slav~ microprocessor 122 is also a type TMS 32010. Buf~er 162 ~erefore allows microprocessor 87 to write da~a to and read data ~rom RAM 160, and swi~ch 157 allows microprocessor 122 to write da~ to and read data from RAM 160. Microprocessor 87 there&ore sends data to microprocessor 122 by writing the data into RAM 160, whereafter microprocessor 122 reads dle dat~ ~rom RAM 160.
Simila~ly, microprocessor 122 sends data to microprocessor 87 by writing ~e data into ~M 160, w~reafter microprocessor 87 reads ~e data from RAM 160 The direction of data iFlow through buffer 162 is controlled by its direction ~DIR~ input which is controlled by ~e NMDEN signal o~ conductor 97. When NMDEN is a logic 0 data is tr~sferred from RAM 160 to microprocessor 87.
Con~eTsely, when NMDE~N is a ll~gic 1, data is tr~s~err~d from microproçessor 87 to RAM 160. Similarly, the neg~ted data enable ~NDEN) output of mier~)roce~sor 122 is connected by eonduc~or lL25 to the DIR input of bu:f~er 157. A logie 1 on conductor 125 allows data to be transferred from lmicroprocessor 122 to RAM 1~0 and a logiç 0 a~ows data to be trans~erred from RAM 160 to ~croprocessor 122. It will be appreciated ~at ~e DIR signal mus~ be used in co~jlmction wi~
~e negated output enable (03~) ;nput~ of bu~ers 157 and 162.
l~e generation of ~e negated vutput enable Sigllal5 iS described ~low.
RAM 160 has ~ur address lines (A0-A3~, a negated write enable (WE) input and a negated chip select (cs) input. The nega~d chip select input is connected to a logic 0.
Three Qf ~e address lines7 A0-A2, and ~e negated w~i~e enable input are connect~d to the ou~uts of a 4 sec$ion 2:1 multiplexer (MUX) 146. MUX 146 detennines whe~er ~e MA0-MA2 , ., ~

~ 28 ~32~193 - address l~es from master microprocessor 87 or the SA0-SA2 address lines ~rnm slave microprocessor 122 are provided to the A0-A2 address inpwts, respectiYely, of lRAM 160 via conduc~ors 147~ 148 and 150, respectively. Also, MUX 146 determines whelther the negated master write enable signal (NM[WEN) on conductor 96 or the negated slave wlite enable signal (~VEN) on conductor 126 is provided to the negated write enable input of RAM 160 via conduc$or 151.
Ram 160 is located in the inputloutput (I/O) spaee of processors 87 and 122. However, when per~orming I/O
operations using the TMS 32010, only ~e ~ee least signi~lcant bits, MA0-MA2, SA0-SA2, can be used. This only allows access to eight words in RAM 160. In ~e pre~erred embodiment, mo~ than eight words are required to be ~ans~rred between , 15 processor 87 and processor 122. Ther~iFore~ dle A3 iIlpUt to RAM 160 was generated in a dif:~e~nt ma~ner. l~e MA0-MA2 address l~es of bus 101 are connected to ~e A0-A2 inputs, respectively, of a 3-to-B-decoder lOlD, such as ~e 74 HC 138.
The C51 input of decoder 100 ;s connected to a logic 1. The ~ 2~ negated second and third chip select inputs (CS2, CS3) are connected by conductor 97 to the ND~N output of microprocessor 87. In ~e pre~erred embodiment, only dle Y5 ~rough Y7 ou~uts of decoder 100 are usedO The NDEN signal on conductor 97 is used, in conjunction widl address lines MA0-2 s MA2, to cause ~ selected one of the outputs of decoder 100 $o become a logic 0. The negated YS output of decoder 100 is connected by NM5 conductor lL03 to the nega~id reset inpllt of flip-flop lL34. The negated Y6 output of decoder lûO is cormected by NM6 condllctor 104 to dle negated set of flip-~lop 134. There~ore, wheII microprocessor 87 causes the NM5 - signal OIl conductor 103 to become a logic 0, ~e Q outpu~ of ilip-flop 134 become~ a logic 0. When mlcroprocessor 87 ¦ causes ~e NM6 signal on conduc~or 104 to beicome a logic 0, ~e Q output of flip flop 134 becon?ies a logic 1.

,.,, . ,. ,, ,, - , . " . , , , ., , ,,; . ",; . . , ., ~ ,, .,, . ~ . . . .

29 ~.32~93 - Slave microproces30r 122, 3~to-8 decoder 123 and flip-flop 128 perform in ~ sirnilar fashion. The SAû-~A2 signals of SADDR bus 170 are connec~ed to dle A0-A2 inputs of decoder 123. The negated data enable ~NDEN) ou~q?ut of slave S microprocessor 122 is comlected by conductor 125 to the negated CS2 and CS3 inpllts of decoder 123. l[he CSl input of decoder 123 is connected to a logic lL. Th negated Y5 output of decoder 123 is co~ected by conductor 131 to ~e nega~d ~eset irlput of 1ip-flop 128. The negated Y6 olltpU~ of decoder 123 is connec~d by condllctor 130 to dle negated se~ i~lpUt of ~lip-iElop 128. Therefore, when slave microprocessor 122 ca~ses decoder 123 to place a logie O on its negated Y~ OUtpllt, the Q output of flip-flop 1128 becomes a logic 0. Also, when slave mieroprocessor 122 causes decoder 123 to place a log;c O on i~s nega~ed Y6 output, ~e Q output of flip-flop 128 ~comes a logic 1.
3 The Q output of 1ip-flop 134 is eo~lLnected by conductor 135 to one input of a two-input OR-gate 133. The Q
ou~pu~ of ilip-flop 128 is conne:cted by conductor 132 to the 21) other input of gate 133. The ou'q?ut of gate 133 is connected by conductor 13l5 ~o ~e A3 iIlpUt of :~M 160. T~erefore, if dle Q
output of fl;p-Ilop 134 or ~lip-~lop 128 is a logic 1, ~e A3 input :i of RAM 160 is a logic 1, ~e~eby addressing the higher order ;; eight words o~ RAM 160. When dle Q output of both flip-flop 2 5 134 ~nd flip-flop 128 are logic 0, ~e A3 input to RAM 160 is a s logic O the~by addr~ssing ~ lower order eight words in RAM
., 160.
It will ~ appreciated, from dle connections to OR-gate 133, dlat ~e Q ou put of ~ip-flop 134 lnust be a logic O if s 3 o sl~ve tnicroprocessor 122 is to be able to address ~e lower eight bytes of J~AM 160. Likewise, ~e Q ou~ut ~ flip-flop 128 mus~
be a logic O if master microprocessor 87 is to be able to address the lower eight bytes of E~AM 160. l~lerefore, when mas~er micr~processor 87 has completed its usage of RAM 160 and is s 35 prepared to turn control of RAM 160 over to slave s ., - .

30 ~ 3 ~ 3 microprocessor 122 ~en master microprocessor 87 will c~use a logic O pulse to be present on NM5 conductor 103, thereby reset~ing flip-:flop 134. Likewise, when slave microprocessor 122 has completed its usage of l~M 160 ~nd is prepared to turn control over to master microproeessor 87 then slave microprocessor 122 will cause 123 to place a logic O on coIlductor 131 ~e~by resetting flip-flop 128.
The negated Y7 output of decoder lûO (NM7 conductor 105) and the negated Y7 output of decoder 123 (conductor 127) are used to tr~er control of RAM 160 betweeIl rnaster microprocessor 87 and sl~ve microprocessor 122. NM7 eonductor lOS i~ colmected to the clock input of flip-flop 120 and ~e negated sct input of ~ip-flop 140. The data ~D) input of ~lip-flop 120 is co~ecteld to a logie 0. l~e Q ou~pu~ of flip-flop 120 is connected ~o ~e Idata (D~ input of ~ip-ll~ 121 The Q output of ~lip-flop 121 is coImected by negated slave in~errupt (NSINT3 c~nductor 95 to the negated interIupt input (NINT) of slave microproeessor 122 and to ~c other input of AND~ga~e 85. The negated Y7 output of decoder 123 is connected by conductor 127 to ~le negated set input of flip-flop 120 ~nd ~he clock input of flip-~Lop 140. The data ~1:)3 input of flip-flop 140 i~ conn~cted to a logic 00 T~e Q olltput of flip-flop 140 is connected ~ conductor 141 ~o ~e n gated A/B (NAJB) inpu~ ~f ~aJ~ 145.
The transi~er of control of RAM 160 between master microprocessor 87 and slave microprocessor 122 is as ~llows. WheIl master microprocessor 87 is prepared to reliIl~guish con~rol ~o slave microprocessor 122 master mieroprocessor 87 causes decoder 100 to place a logic O pulse on NM7 conductor 105. The rising edge of ~is logic O pul3e eloeks a logic O in~o the Q ou~put of flip~ p 120. On ~he rising edge of the CLKOUT signal from slave microproeessor 122 on conductor 124 thls logic O is then clocked onto the Q outpu~
(NSINT conductor 95) of ~lip-flop l 21. The logic O on NSINT
conductor 95 interrupts slave microprocessor 122. ~his , .

~32~9~

elTupt means that slave microprocessor 122 may take con~ol of RAM 160. The logic 0 pulse on NM7 corldllctor 105 also causes the Q output of flip-flop 140 ~o place a logic 1 onto condllctor 141. Conductor 141 is co~ected to ~e NA/B input of MUX 146 and ~o one input of a two-inpu~ NAND-gate 154.
The logic 1 on its NA/B input causes MtJX 146 to co~ect add~ess lines SA0-SA2 to RAM 160 add~ess inputs A~-A2 ~d to connect the NWEN signal on coIlductor 12,~ from sl~ve microprocessor 122 to ~e negated wn~e enable lnput of RAM
160. ~e negated Q output of ~lip-flop 140 is connected by conductor 142 to on put of a ~ree-i~ut NAND-gate 143.
'rhe output of gate 143 is connected by corl~uctor 144 to ~e negated outpu~ enabl (OE) input of bu~er 162. The lngic 0 -. pulse on NM7 conductor 105 causes flip-flop 140 to place a logic 0 onto conductor 142 and ~lere~re gate 143 placcs a logic 1 onto conduc~or 144 which dis~les the outputs of bu~~r 162 ~ereby preventing microprocessor 87 from tralns~erring data to or ~rom RAM 160.
The negated data enable (NDEM) output s)f slave J 20 mieroprocessor 122 is also connectcd by conductor 125 to one input of a two inpu~ AND-gate 15S and to ~e di~ection cvntrol (DIR) input of buffer 157. When slave microprocessor 122 places a logic O onto NDEN conductor 125 ~e output of gate 155 ~comes a logic 0. ~he OU~pllt of ga$e 155 is comlec~ed by 2 5 conductor 156 to ~he ne$ated output enable (OE) input of bu~r 1S7. The logic Q on conductor 156 ~e~efore enables the out~suts of buffer 157. Also, ~he logic 0 OIl NDEN condurtor 125 is provided to the DlIR comtrol input of bu~r 157. The logic 0 on -1 conduc~or 125 and ~e logic 0 on collductor 156 ~re~ore cause .~. 3 o buffer 157 to transfer data - ~rom RAM 160 to slave microproces~or 122.
Data ls transfe~Ted from slave microp~cessor 122 ~! to RAM 160 by causing microprocessor 122 to place a logic 1 onto NDEN conductor 125 and placing 1ogic 0 onto NWEN
3s . conductor 126. 1['he logic 0 on NWFN conductor 126 passes :'.

32 ~. 3 ~ 3 - through MUX 146 and places a logic 0 onto conduc~or 151, which is connected to ~e negated write enable input of RAM
160. Conduc~or lSl is also connected to the input of inver~er 152. The ou$put of inverter 152 is connected to ~e other input of ga~ 154. Since conductor 151 has a logic û on ilt, ~e output of inverter 152 on conductor 153 will be a logic lo I~ will be recalled that the Q ou~ut of flip-flop 140 on conductor 141 is also a logic 1. T~erefore, ~e oul:put of ~gate 154 will be a logic 0 and ~e output o:f gate lSS on conductor 156 will also be a logic 0. Therefore, ~e DIR input to buffPr 157 is a lLogic 1 and dle negated output ena~le input is a logic 0 SQ ~lat bu~fer 157 ~ans~rs data from microprocessor 122 to RAM 160.
Slave microprocessor 122 r cei~es its operating 5 ins~ctions and ce~aLn parame~rs from an external ROM 167.
In ~e preferred embodiment7 memory 167 is a two kilowor (2K) by 16 bit memory. The CS2 and CS3 ehip selec$ inputs of memory 167 are connected to a logic 1. The SA0-SA10 lines of SADDR addr~ss bus 1170 are conne~cted to ~e SA0-SA10 address i~puts of memo~r 167. T~e SD0-SD15 lines of SDAT~ bus 171 are connected to ~e SD0-SD15 i~nput/outputs of memory 167.
The Ilegat d memory enable NMFN outpu~ OI slave microprocessor 122 is cormected by conductor 163 to the input ofinverter 164. The Ollt put ofinverter 1~4 is coImected to one ~nput o~ a ~wo-~npu~ N A N D-gate 165. Slave nnic~oprocessor 122 aa~o provides ~he C L K o~rr signal on cond~ctor 124 to ~he o~her ~nput of gate l65. llhe ou~put o~ gate 165 is connected by conductor 166 to the nega~ed ch~p select(CSl~ ~nput of R O M
167. l~he tra~s~r of data ~ro m R O M 167 to microprocessor 122 is ~herefor~ synchronizedto ~he C LK O U T signal.
Assu me now ~hat slave microprocessor 122 has connpleted its erans~er of data wi~h respectto R A M 160 and is ready to ~ansfercon~ol of R A M 160 to nnaster micropr~cessor 87. Slave nnicropr~cessor 122 wi~ ~here~ore cause decoder 123 to place alogic 0 pulse on conductor 127. llhelogic 0 pulse on conductorl27 set~ ~he Q ou~putof ~ip-~op 120 to alogic 1. On 33 ~32~93 the next positive transition of ~e CLKOUT signal on conductor 124 d~is logic 1 is clocked through flip-flop 121 and appears on NSINT conductor 95. This resets the intemlpt ~o slave microprocessor 122 and, via gate 85, resets (lngic 1) the polled interrupt request input INBIO) of master microprocessor 87. It will be recalled ~at NSINT conductor 95 becomes a logic 0 on the rising edge of a logic 0 pulse on NM[7 conductor 105.
ThereiEore, input NBIQ will be a logic 0 once master microprocessor 87 has trans~erred control to slave rnicroprocessor 122 and remain a logic 0 un~il slave microprocessor 122 transfers control back to mastgr microprocessor 87 by placing a logic 0 pulse on con~uctor 127.
When the NBIO ~put becomes a logic 1 again thell master microprocessor 87 knows ~at slave microprocessor 122 has finished trans~e~ng data to/from RAM 160 and therefore master microprocessor 87 car~ ~ans~er data to/~rom RAM 160.
It should also be noted ~at upon ~e rising edge of ~e logic 0 pulse on c~nductor 127 a logic 0 is clocked onto d~e Q
output of flip-flop 140 and a log:ic 1 is clocked onto the negated Q output of ~lip-flop 140. The: logic 0 on conduc~or 141 (Q
OUtpllt) :~es the output of gal:e 154 ~o a logic 1. VVhen the output of gate 154 is a logic 1 ~ate 155 acts simply a~ a noninverting buffer. Then, when the NDEN signal from slave ~c~opr~cessor 122 on conductor 125 is a lojgic 1 ~he outputs of buffer 157 will be disabled. However, if NDEN conductor 125 ~as a logic 0 placed on it by microp~ocessor 122 then ~uffer 157 will allow data ~o be trans~erred ~rom bus 161 to microprocessor 122. 'rhis particular ~eature ls not used in the preferred embodiment.
l~e logic 0 on conductor 141 a~so causes MUX 146 ltO connect the MA0-MA2 ~ddress lines from master microprocessor 87 to ~he A0-A2 address inputs of RAM 160, and to connect the NMYVEN output from micropr~cessor 87 to the negated wri$e enable input of RAM 160. Therefore, RAM
160 is now under ~e control of mas~er microprocessor 87.
,. ~

.. , ., .. . , ,, . . . , -., .. , , ; ......... ..

3~ ~ 3 ~ 3 , .
- The negated Q output of flip-flop 140 is connec~ed by conductor 142 to one input of a three-input NAND-gate 143.
A logic O on conductor 142 there~ore disables gate 143 and a 1ogie 1 enables gate 143. NMDEN conductor 97 is corLnected to ~I the input of inverter 98. ~e output o:f inverter 98 is connec~ed -~ to one input of two-input OR-gatc 145. ~e Z output of MUX
1l 14~ on conduc~or 151 is conneeted to the input of inverter 152. -;
The olltpU~ of iIIverter 152 is connected to ~he o~er ~put of gate 14~. The ou~qput of gate 145 is co~ected to another input of gate 143. I~MEN conductor 107 is also eQnnected to an input of gate 143. The ou~ut of gate 143 is conneeted by ~onductor 14a, ~o ~e negated ou~put ena~le in~ut o~ r 162. Data is ;j trans~erred ~rom RAM 160 to master microprocessor 87 by causing master mieroprocessor 87 to place a logic 1 onto 1l 1 5 RAMEN conductor 107 and NMWEN conductor 96 aIld a logic :1 0 pulse onto NMDEN conductor 97. l~is callses a logic 1 pulse :~ to appear at the gate of 145, a logic 0 pulse to appear at ~he output of gate 143, and ~he Oll~lltS of ~u~fer 162 ~o be enabled.
l[~e logic 0 on NMDEN con~ucts)r 97 also causes bu:ffer 162 to y 2 trans~er data in ~e direction ~rom RAM 160 to ~croprocessor - 87 at dle time ~he outpugs are enabled.
Data i~ ~rans~erredl ~rorn microprocessor 87 to RAM 16~ by causi~g microprocessor 87 to place a logic 1 onto ,~ RAMEN conductor 107 and NMDE3N conductor 97 while :~ 2 5 p~cing a logie 0 pulse onto NM~YEN conductor 96. The logic 0 ;~ pulse on NM~YF,N conduc~or 96 causes a logic 0 pulse a~ the ~t~ nega~ed writP eIIable input of RAM 1~0, c~uses a logic 1 pulse to~, app~ar at ~he output of illve~er 1;529 causing a logic 1 pulse toappear at ~he output of gate 145, and the logic û pulse to appear at the output of gate 143. The lo~ic 0 pulse ~rom gate 143 : ~
enables the output of buffer 162. The loglc 1 on NMDEN ~: :
condllctor 97 causing buf~er 162 to be activated in a mamler to ~ransfer data ~rom microprocessor 87 toward ~M lS0 during ~e logic 0 pulse when its outputs ar~ enabled. ;~

. . - .

132~

- Tum now to Figllr~ 6 which is a schema~ic diagram of an alternative embodiment of ~e RAM address circuit. The altemative embodiment requires two additional gates 180 and 182 but has ~:le advarltage in ~hat processors 87 and 122 are no~
re~ired ~o reset flip-flops 134 and 12~39 respectively, before transfe~ng control to the alternate m;croproces~or. In this alte~ative embodiment, the Q vu$pu~ of ~lip-flop 134 is ~, connected by conductor 135 to one iIlpUt of a two-inpu~ ~ND-gate 180. The negated Q ou~put of flip-flop 14~ is co~ected by conductor 14~ to ~e odler input oiF gate 180. The output of gate 180 is connected by conductor 181 to GIle pUt of two-input OR-gate 133. The output of gate 133 is eonrleeted by conductor 13Ç ~o ~e A3 input of ~M 160. The Q output of flip-flop 128 is cormected by conductor 132 to one input of a ~o-inpw~ ANI)-S gate 182. The Q output of flip-flop 140 is connected by conductor 141 to ~e other input of gate 1~2. 'rhe ou~cput of gate 182 ;s connected by conductor 183 to ~e other input of gate 133. It will be recalled ~at when master microproeessor ~7 has control the Q output of flip-flop 140 is a logic 0 and the negated 20 Q OUtpllt is a logic 1. This means that, when master 'i microprocessor 87 has control, ~gate 182 will be disabled andgate 18lf3 enabled. ''I'here~fre, the A3 input of RAM 160 will ff correspond to ~e Q ou~ut of flip-flop l~f4, regardless of ~e f state of t~e ou~pu~ of flip-~lop 128. Similarly, when slave microproce~sor 122 has control the Q out~put of flip-flop 140 will be a logi~ 1 and ~e negated Q ou~?u~ will be a logic 0. Ln 9 ease ga~e lL80 will be disabled and ga~ 182 will be enabled.
Now ~e A3 i:nput to RAM 160 corresponds to ~e Q output of flip~ op 1289 regardless of the state of flip-flop 134.
3 t) There~re, the addition of gates 180 and 182 has elim~nated the reguirement ~or resetting flip-flops 128 and 134 prior to transferring çorltroL
~cluded in the o~er rnodem circuits 80 are a codec aIld clock generator for driving the codec~ In ~e preferred embodiment, ~e clock ~or ~e codec is generat~d by dividing : ;
. , .

,,. ,, . ,. . , ~ , ~ , . . . . , ~ ; , .

36 ~.32~93 :
- another readily available clock by 1.5. Mos~ conventional divide-by-1.5 circuits use one or more feeclback pulses so that ~he input to dle first stage of ~e divider has a higher ~requency than the reference clock fre~uency. This means that one or more stages of the divider chain must be able ~o rlm at a ~requency which is higher ~an ~he reference clock frequency or ~he desired clock frequency. T~is higher input frequency, and , ~e circuit required to accommodate it, typically mean higherlo costs, greater power requirements, and greater decoupling .~' requi~ements.
TUIn now to ~igu~e 7 which is a sclh¢matic diag~n of a divide-by~1.5 circuit used ~ o~er modem circuits 80 of ~e p~eferred embodiment. In the divider s~own in Figure 7 ~ere i, are no feedback clock pulses and ~ere~ore it is adequate for ~e dev}ces Ln ~e divider chain ~o be capable of operating at ~e refe~ence clock frequency. Reset conductor 2~) is connected ~
the reset ~R~ input of flip-flop~ 201, 202, 2039 204, 205, and 206. I'he reference clock ~(: I,K~ on conduetor 207 is provided `~ to ~e clock inputs of flip-flops 201, 2027 and 203, and to the 2 0 inpu~ of inverter 210. The out:pu~ of inverter 210 is ~e inverted clock and is connected by con~lctor 211 to ~he ~ lock inpllts of ip-flops 204, 205a and 206. The Q oul3put of flip-flop 201 is connected by conductor 212 ~o t~e D input of ilip-flop 202 and to ons ~pu~ of a ~wo-input NOR-ga~e 213. 'rhe Q outpu~ of flip-flop 202 is connected by condllctor 214 to ~e other i~put ~ gate 2139 the D input of flip-flop 203, one input of a three-input i, NAND-gate 217 and one input of exclusive-OR ~XOR) ga~e 216.
~1 The output oP ga~ 213 is connected by conductor 215 to ~e D
input of flip-flop 201. The Q output of flip-flop 203 is connected by conductor 224 eo one input of XOR-ga~e 226.
Q output of flip-~lop 204 is connected by conductor 220 to ~e D input of flip-flop 205 and a second input of gate 217. The Q output of flip-flop 205 is connected by conductor 221 to the D input of flip-flop 2069 thie o~lier input of gate 216, and ~e ~dhird input of gate 217. Thie output of gate 217 ., .1 .
... .
i 37 :.32~L93 - is connected by eollductor 222 ~o ~e D input of flip-~lop 204.
The Q output of flip-flop 206 is cor~ected by conduc~or 225 to ~e other input of g~te 226. The output of gate 216 on ronductor 223 is ~e reference clock ~requenry OIl conductor 207 divided by 1.5. The ou~put of gate 226 on conductor 227 is also the clock on conductor 207 divided by l.S bu~, because of flip-flops 203 and 206, lags behind ~e si~ll on conductor 223.
Turn now to Figure 8 which illustrates the wave i~ ~orms present in ~e circuit o:f Figur~ 7. It will be seen ~at ~e circuit formed by flip-flops 201 and 202 and ga$e 213 ~rm a divicle-by-3 divider. Alss:~9 if one d;sregards the input to gate 217 ~From ~p-iFlop 202 ~en ~e circuit ~ormed by flip-flops 204 and 205 and gate 217 forms a divide-by-3 divider.
Furt]he~more, ~om an lnspection of the wave form on conductor 221 it will lbe appreciated tha~ the output of flip-flop 20S still coITesponds to a divide-by-3. There~vre~ ~e input to gate 217 :~om flip-flop 202 pro~vides a synchroniza~ion signal whereby the operatioIl of ~e circuit ~ormed by components 204, 205, and 217 is synchronize~d ~o ~e opera~ion of ~e circuit ~ormed by components 2~1, 202', and 213. The divide-by-1.5 opera~ion is achieved by e~clus;ve-ORirlg the outpu~s of flip-flops 2û2 and 205. The phase difference between ~e ou~tputs of flip-flop~ 202 and 205 pro~rides the di~ide-by-1.5 OlltpUlt as shown on con~uc~or 223.
2 5 By using two additional flip-flops 203 and 206, and ez~clusive-OR gate 226 a phae delayed version of the divide-by-1.5 ~ignal on conductor 223 is obtaine~ on conduc~r 227. Flip-~ops 203 and 206 merely delay ~he outputs of flip-flops 202 and 205l respcctively, by one re~ererlce clock cycle (condu~or 207).
3 o From an Lnspection of the wave foIms in Figure 8 it will be appreciated ~at there are no ~eedback pulses present w~ich would requ~re a device, such as a ~lip-flop, to operate at a speed higher ~an ~e re~er~nce elocl~ (~onductor 207~
Widlout ~he com~ection between :flip-flop 202 and 3 5 gate 217 ~e Ollt ?uts of gates 216 and 226 would still be divide-.

- by-l .S as long as ~e upper and lower half half circuits remained in sync. However, i:f a noise pulse should occur and cause the ~` two halves to lose sync with respect to one ano~her, then the :. output would no longer be a divide-by-1.5. Fur~ermore, ~he ? 5 two halves would remaill out of SyTlC until ~set. Conne ~ing tl~
. ~utput of flip-flop 202 to ~e ~put of gate 217 sync~onizes theupper and lower half circuits so t~at, if eYen synchronization between the upper and lower half circui~ is inte~upted lbec~use of a noise pulse~ dhe t~o halves will automat;cally resynchronize 1 0 and the out3?uts of gates 216 and 226 will agam be divide-by-1.5.
- Tum now to Figure 9 which is a block diagram of an improved baud clock recovery circllit. In the pre~rred embodiment, components 250 ~ough 260 are not separately implemellt.ed but are implemented by microprocessors 87 and 122. Sampling circuit 20 samples the incoming sigI~al on conductor 249 at 9600 samples per second. Sampling circu;t 250 is contr~lled over eoncluctor 248 ~ ~e receiver b~ud clock phase locked loo~ (not showtl). The outpu~ of samplLng circuit 250 is provided to two Hilbert filters 251 ~nd 252 whcrein ~e I
and Q components, respec~ive:ly, of ~e sampled signal are reco~ve~d~ The output of filter 251 is provided to demodula~or 253 and to arl absolute value ci~,cuit 254. The OUtpllt of ~lter '; 252 is also provided to demodula~or 253 and to an absolu~e value circuit 2S5. The output of circu its 254 and 255 are cor~ected to ~e inputs of adder ~56~ The output of adder 2S6 is then provided to the input of a 2400 hertz b,andpass filter 257. The -~ output of bandpass ~llter 2$7 is then provided to a lead,/lag calculator 260. l~he output of the lead/lag calculator 260 is provided to ~e reeeiver baud clock phase lock loop (not shown~
', 30 to adjust ~e timing of ~e sarn~ling points.
The ou~put nf bandpass filter 257 will be ~e J recovered baud c.lock. ~n one application, dle baud clock will be 400 Her~ and ~e r~icovered baud clock wavei~orm 261 will be as shown in ~e inset. ~n order to m~ize dle data error rate, it 3 ~ is desi~ed dlat the sampling of ~e i~comin,g signal on eon~uctor ., .~ .

.~r - - ~- .- , . . .. ... .. . ...

~ 3 ~

- 249 be synehronized with the zero crossirlg points P of the recovered baud clock. This is accomplished by determining - which quadrant the primary sampling point lies in and then adjusting the receiver lbaud clock phase lock lo~ so ~hat the .! primary sampling point lies exaetly at point P. The quadran~ is determirled by eomparing ~e sign of the signal 261 oiF ~he primary sampling point with the sign of the signal at the p~ceding non-pnmary samplir~g point. Por example7 if the pnmary s~npling point is X~ and ~e immediately preceding non-primary sampling point is Xs l then the primary sampl~g point X~ is in ~e quadraIlt de~ined as CO However, if ~e p~ary sampling paint is Xs+l ~en ~e i:mmediately preceding no~-plimaly sampling point would be X~ and the~ ore, since ~e signs are ~e sarne and positive, ~e primary sampling point Xs~l would be in dle quadrant defined as 1[:3. Since ~e ~quadrant in which the p~imary sampling point lies is now determined lead/lag caleula~or 260 can ~en adjust the rece;ver baud clock ~j phase lock loop in ~e proper directioll to eause the primary sampling point to coineide with point P. For example~ if ~e 20 primary sampling point were point XS then ehe primary sampl~g point would be lagging po~n~ P ~nd i~ would be Ilecessary to advance ~e sampling po~ts. Similarly, if ~e p~ary sampling poin~ were point Xs.l ~en ~e primary :1 sampling point would be le~ding point P and it is necessary to 5 retard ~e t~ming of ~e san pling.
The position of ~e sampling poln~s i~ adjustcd by advancing or l~tardLng dle phase of the baud clock. This can be done in fi~ed iIlc~ments of, for example, one degree.
;, However, if a fi~ced increment size is used, ~en it 30 may læ impossible for the prima~y sampling poi~ ~o ~all exactly at point P and therefore ~he sampling point would oscillate -1 (jitter) around poin~ P as ~e step size caused ~e primary sampling poin~ to alternately lead and lag point P. To avoid ~his problem a small step size and a lock-on window eould be used 3 S but, if ~e primary sampling point ~ell in quadrants A or D, then -,~

~o ~ 9 3 .
- the small step size would require an excessively long time to move ~he sampling point ~rom quadrant A or D to point P.
In the preferred emlbodimen~, the step size necessary to move ~e primary samplLng point to point P is not ~Ixed but is calculated based upon the quadrant at which the primary sannpling point presently lies and ~he magnitlldes of bodl ~e primary sampling point and ~he immedia~ely preceding non-pIimary sampling point. 'I'here:~ore, ~e s~ep size llsed to 'i 10 move a primary sampling point lying at X~ tl would be greater~an ~e step size used to move a primary sampling point loeated at X~.
- Since ~e output of bandpass ~llter 257 is a 240() hertz signal 261 sampled at 9600 her~ ~sample/secolld) ~ere are ~ur sampling points per cycle of ~e signal 261. On staItup7 lead/lag calculator 260 dete~es which of these ~our sampling points is closest to point P and ~lerea~er ~is sampling point is designa~ed as the pIimary sampl:ing poin~. Thereafter, lead/lag calcula$or 260 adjusts th~ reeovered baud clock to eause ~he primary sampling point to occur at point P.
2 0 In the preferred embodiment, ~his, startup procedure is ~at descrilbed in dle above-referenced CDN Paten~
Application, Serial Numlber ~ 5 ~ l., 519 o In an altemative emb~diment, no attempe is made to detexmine w~ich sampling point lies closest to point P.
- 2 5 l~stead, one of ~e sampling points-~is simply designa~ed as d~e primary sampling point.
Turn now to Figure 10 which is a flow chart of the proeedure used by lead/lag calculator 260 to compute the step size after dle primary sampling point has been de~ ed. Since 3 o ~ere are ~ur samples per cycle of dle signal and only one of ~e sarnples is ~e p~ary sampling point, it is necessary to keep tra(k of ~e primary sampling point. This is done by using a baud clock counter (BC~ and incrementing it at eYery sample time. ~ Figure 10 it is assumed, or convenience, that it has 3 5 ~en previously defined that the primary sampling poin~ is ~e 2~93 ~`
sampling point at which the baud clock counter (BC) equals 1.
Therefore, BC is set to 1 Ln step 270. Then7 in s~ep 271, ~e next s~ple point Xn is obtained and BC is incr~mented. At decision point 272 BC is analyzed to determirle if ~e sample point Xn is ~ primary sampl~g point (BC-l). I~ no~ then decisioIl point `~ 273 detelmines whe~er eoun~er BC has r~ached its upper limit.
If so, ~hen BC is set to 0 in step 274. If BC was less than four, and also after step ~4 is e7~ecuted, thPn Xn is stored as Xn l in step 27S. The calculator ~hen ~etums to step 271, gets ~e nex~
1 0 value of Xn, and agaim increments B(: .
:; If BC eguals 1 ~en Xn is the p~ary sampling ;1 pOiIlt and ~e lead/lag step size ealcula~ion should be per~ormed.
Table 3 list~ ~e equations ~r t~ s~ep size calculation lby i, ~quadrant. K is a scale fastor and has a value of unity in ~e preferred ernbodiment. It will be noted ~at ~e equa~ions ~or all ~our quadrants haYe a common denomina~or. Therefore, step 280 calculate~ the co~non delmminat~r D. HoweYer~ since multiplicatiorl is ~aster than division, ra~her than dividing ~e .I numerator of ~e equatioll by the~ denomillator the step size S is 2 obta~ed by irlve~ing ~e denonninator and ~hen multiplying ~e ~I numerator by the inverted denominator. In the pre~erred ~: embodimellt, D is obtained by use of a look up table and is limited, ~or coIlverlience, to a~ 8 bit word. There~ore, in s~ep 280, after calculating the denominator D, the inverted :~ 2 5 denomiIla~3r M is calcula~ed. Decision points 281J 282 and 286 :~ determ~ne which guadrant ~e primary sample point Xn is located. If Xn is greater ~an zero and the preceding non-prima~ sampling poimt X~ l is greater than zero then ~he primary sampling pOiIlt is in quadrant ~ and ~e step size S is :, 3 0 calculated accordiIlg to t}le ~uation ~ step 2~7.

. .
.

';,' ~ :' : , ~2 ~32~1~3 ., .
~, _ TABLE 3 STEP SIZE EQU~TIONS
J

~ 5 : X~ X~; Qu~lls _ Step .
_ ~ ,, ~eg. Pos. A (Xn-2 (Xn-l)) K283 IXs~ fn-11 Neg. Neg B Xlt K 285 IXnl+lXn 11 ,1 _~ _ ~_ ~ ':
Pos. Neg. C Xn K 285 _ _ . . . ~ IXnl+lXn~ll ,1 1 S _~ , _ .
Pos. Pos. D (Xn ~2 (Xn-1)) K 287 .~ __. IXnl+lXn-ll _ _ 1 .
o If Xn i~ less ~ zero and Xn l is greater ~an zero t~en the primaly sample point has occurred in quadrant A and ~e step size ~ is calculated according to ~e e~ua~ion in step 283.
If Xn l is negative ~en ~e primary Samplillg pOillt Xn will be in quad~an~s B or C. ~er~fore ~e ~tep size S is calculated according to l:he equati~ in block 285, Af~er ~e 5t~p size S is calculated, according to steps 283, 285 or 287, as appropriate, ~en ~e step siz is output to the recovered baud clock phase lo~k loop hl s~ep 284. Frc;m step 284 lead/lag calculator 260 ~, returns ~o step 275 and ~en the process begins again. In ~e preferred embodiment, a step size S value ~1 co~responds to a 3~ change of ~pproximately 240 nanoseconds in ~e position of ~
primary sample pointO There~rc, the step size is dyn~nically adjusted accordirlg to ~he distance bet~ en the primary sampling point and poin$ P. As a result, ~he sampling point converges upon point P at a rate consistent wi~ a very large step size, and 3 ~

.~, ....... ,, .,, , , , . , , :

~3 ~32~ ~193 - locks onto point P with the stability and freedom from ji~er provided by a minimally small step size.
Although described with respect to the positive-going zero-crossing point P it will be appreciated ~at ~e above can be used for the negative-going zero-crossing point G by simply changing,~e sign of ~e step size computed according ~o Table 3 and Fj~ure 9.
~ lso, it will ~ appreciated that if ~e characteris~ic ~reqllency of signal 2~1 is 1200 Hertz, ~erl the sampling freguency would pre~erably be four times the characteristic ~, frequency, or 4800 E~ertz Furthermore, e~.ren if ~he 1200 Hertz signal 261 is sampled at, ~or example, 9600 Her~z, ~ above can be used by s~ply discarding every o~er sample.
Prom the above, it will lbe appreciated tha~
present invention describes a modem whic~ uses two digital signal p~eessing micr~processors and other techniques in order to e~fect savings in speed, processing ~ime, and memory r~quirements, achieve a ~ast hal-duplex line turnaround, and ;i maintain compatibili~ wit~ e~ist;ng 300, 1200 and 2400 bps modems while providing 48~ and 9600 ~3ps capa~ y. It will also be app~eciated ~at s~dard, well ,known techni~ques such as scrambling9 descrambling, frelquency synthesizing, power ~:
`~ supply constructioll7 telephone line in~erfacin$, etc., are '3 availablei in many printed publication~ and patents ~nd neeid not :' 2 5 ~ det~,iled herein.
Also, from ~e detailed description above, it will ~e -appreciated ~at many modifications and variations of ~e pre,~rr~d embodiment will become apparent to ~ose skilled in ~, the a~ herefore, the present inven~ion is to be limited only by 30, ~e claims below. - ~

;, '.-' i 35 .-. ~:

:f, ,~ ~ ,. . ,, , . , , . , . ,.,, . .. ,, .. , ; . : , .. , -i . . :.. ,; , . .. , , " ., . : , . . .. . . ..

Claims (54)

1. A V.22 bis compatible handshake method for an originating modem for establishing communications with an answering modem at a selected speed of 1200 bits per second (bps), 2400 bps, or greater than 2400 bps, comprising:
(a) sending a first sequence for a first predetermined period;
(b) sending a second sequence for a second predetermined period while listening for said first sequence from said answering modem;
(c) (1) if said first sequence from said answering modem was not heard, commencing communications with said answering modem at 1200 bps;
(2) if said first sequence from said answering modem was heard, sending a third sequence for a third predetermined period while listening for said second sequence from said answering modem;
(d) (1) if said second sequence from said answering modem was not heard, continuing to send said third sequence for an additional period of time and then commencing training and communications with said answering modem at 2400 bps; and (2) if said second sequence from said answering modem was heard, commencing training and communications with said answering modem at a speed greater than 2400 bps.

2. The method of Claim 1 wherein said first sequence is unscrambled double dibits 00 and 11 at 1200 bps.

3. The method of Claim 2 wherein said second sequence is an unscrambled binary 0 at 1200 bps.

4. The method of Claim 3 wherein said third sequence is a scrambled binary 1 at 1200 bps.

5. A V.22 bis compatible handshake method for an originating modem for establishing communications with an answering modem at a selected speed of 1200 bps, 2400 bps, 4800 bps, or 9600 bps, comprising:
(a) sending a first sequence for a first predetermined period;
(b) sending a second sequence for a second predetermined period while listening for said first sequence from said answering modem;
(c) (1) if said first sequence from said answering modem was not heard, commencing communications with said answering modem at 1200 bps;
(2) if said first sequence from said answering modem was heard, sending a third sequence for a third predetermined period while listening for said second sequence from said answering modem;
(d) (1) if said second sequence from said answering modem was not heard, continuing to send said third sequence for an additional period of time and then commencing training and communications with said answering modem at 2400 bps; and (2) if said second sequence from said answering modem was heard, then sending a fourth sequence followed by a rate request sequence;
(e) listening for said fourth sequence from said answering modem and training an adaptive equalizer in said calling modem in accordance with said fourth sequence;
(f) listening for said rate request sequence from said answering modem;

(g) (1) if said rate request sequence sent by said calling modem is different from said rate request sequence received from said answering modem, commencing communications at 4800 bps;
(2) if said rate request sequence sent by said calling modem and said rate request sequence received from answering modem both specify 4800 bps, commencing communications at 4800 bps; and (3) if said rate request sequence sent by said calling modem and said rate request sequence received from said answering modem both specify 9600 bps, commencing training and communications at 9600 bps.

6. The method of Claim 5 wherein said first sequence is unscrambled double dibits 00 and 11 at 1200 bps.

7. The method of Claim 6 wherein said second sequence is an unscrambled binary 0 at 1200 bps.

8. The method of Claim 7 wherein said third sequence is a scrambled binary 1 at 1200 bps.

9. The method of Claim 8 wherein said fourth sequence comprises a non-phase encoded scrambled binary 1 at 4800 bps.

10. The method of Claim 9 wherein said rate request sequence specifying 4800 bps comprises a scrambled binary 1 at 4800 bps.

11. The method of Claim 9 wherein said rate request sequence specifying 9600 bps comprises a scrambled binary 01 at 4800 bps.

12. The method of Claim 9 wherein said fourth sequence comprises 4 points of a 32 point phase-amplitude constellation, each point of said 4 points being displaced from the remaining 3 of said 4 points by an integer multiple of 90 degrees.

13. A V.22 bis compatible handshake method for an answering modem for establishing communications with a calling modem at a selected speed of 1200 bits per second (bps), 2400 bps, or greater than 2400 bps, comprising:
(a) listening for a first sequence from said calling modem;
(b) (1) if said first sequence from said calling modem was not heard, commencing communications with said calling modem at 1200 bps;
(2) if said first sequence from said calling modem was detected, sending said first sequence to said calling modem and listening for a second sequence from said calling modem;
(c) (1) if said second sequence from said calling modem is not heard, commencing training and communications at 2400 bps;
(2) said second sequence from said calling modem was heard, sending said second sequence and commencing training and communications at a rate greater than 2400 bps.

14. The method of Claim 13 wherein said first sequence comprises unscrambled double dibits 00 and 11 at 1200 bps.

15. The method of Claim 14 wherein said second sequence comprises an unscrambled binary 0 at 1200 bps.

16. A V.22 bis compatible handshake method for an answering modem for establishing communications with a calling modem at a selected speed of 1200 bits per second (bps), 2400 bps, 4800 bps, or 9600 bps, comprising:
(a) listening for a first sequence from said calling modem;
(b) (1) if said first sequence from said calling modem was not heard, commencing communications with said calling modem at 1200 bps;
(2) if said first sequence from said calling modem was detected, sending said first sequence to said calling modem and listening for a second sequence from said calling modem;
(c) (1) if said second sequence from said calling modem is not heard, commencing training and communications at 2400 bps;
(2) if said second sequence is heard from said calling modem, sending said second sequence and then listening for said third sequence from said calling modem;
(d) using said third sequence from said calling modem to train the adaptive equalizer in said answering modem;
(e) listening for a rate request sequence from said calling modem;
(f) (1) if said rate request sequence from said calling modem designates 4800 bps, sending said third sequence to said calling modem, sending said rate request sequence designating 4800 bps to said calling modem, and then commencing communications at 4800 bps;

(2) if said rate request sequence from said calling modem designates 9600 bps and said answering modem cannot accommodate 9600 bps then sending said third sequence, sending said rate request sequence designating 4800 bps, and commencing communications at 4800 bps; and (3) if said rate request sequence from said calling modem designates 9600 bps, and said answering modem can accommodate 9600 bps, sending said third sequence, sending said rate request sequence designating 9600 bps, and then commencing training and communications at 9600 bps.

17. The method of Claim 16 wherein said first sequence comprises unscrambled double dibits 00 and 11 at 1200 bps.

18. The method of Claim 17 wherein said second sequence comprises an unscrambled binary 0 at 1200 bps.

19. The method of Claim 18 wherein said third sequence comprises a non-phase encoded scrambled binary 1 at 4800 bps.

20. The method of Claim 19 wherein said third sequence comprises 4 points of a 32 point phase-amplitude constellation, each point of said 4 points being displaced from the remaining 3 of said 4 points by an integer multiple of 90 degrees.

21. The method of Claim 16 wherein said rate request sequence designating 4800 bps comprises a scrambled binary 1 at 4800 bps.

22. The method of Claim 16 wherein said rate request sequence designating 9600 bps comprises a scrambled binary 01 at 4800 bps.

23. A fast line turnaround method for transferring data in the half-duplex mode, comprising:
(a) a data transfer protocol comprising:
(1) sending a carrier for a first predetermined period;
(2) sending a first idle signal for a second predetermined period;
(3) sending at least one of a predetermined flag;
(4) sending a data frame, said data frame not exceeding a predetermined number of bits;
(5) repeating steps (a) (3) and (a) (4) until available data has been sent; and (6) sending a second idle signal for a third predetermined period; and (b) a no-data line turnaround protocol, comprising:
(1) sending a carrier for a fourth predetermined period;
(2) sending said first idle signal for a fifth predetermined period;
(3) sending at least one said predetermined flag, and (4) sending said first idle signal for a sixth predetermined period.

24. The method of Claim 23 wherein said first predetermined period is approximately 20 milliseconds.

25. The method of Claim 23 wherein said first idle signal is the mark idle signal.

26. The method of Claim 25 wherein said second predetermined period is approximately 1 milliseconds.

27. The method of Claim 23 wherein said predetermined flag is the binary sequence 01111110.

28. The method of Claim 23 wherein said predetermined number of bits is 128 bits.

29. The method of Claim 23 wherein said second idle signal is the mark idle signal.

30. The method of Claim 29 wherein said third predetermined period is approximately 15 milliseconds.

31. The method of Claim 23 wherein said fourth predetermined period is approximately 20 milliseconds.

32. The method of Claim 23 wherein said fifth predetermined period is approximately 15 milliseconds.

33. The method of Claim 32 wherein said sixth predetermined period is approximately 15 milliseconds.

34. For use with a calling modem and an answering modem engaged in half-duplex communications, a method for correcting for a loss of equalization in an equalizer in said calling modem, comprising:
a calling modem procedure comprising:
detecting said loss of equalization in said equalizer in said calling modem;
waiting until said answering modem has completed transmitting;
sending a carrier for a first predetermined period;
being silent for a second predetermined period;
sending a training sequence to said answering modem for a third predetermined period; and receiving said training sequence from said answering modem and using said training sequence to adjust said equalizer in said calling modem; and an answering modem procedure comprising:
detecting said carrier sent by said calling modem;
being silent during said second predetermined period;
being silent during said third predetermined period; and sending said training sequence to said calling modem for said third predetermined period.

35. The method of Claim 34 wherein said training sequence comprises a first sequence for coarsely adjusting said equalizer and a second sequence for finely adjusting said equalizer.

36. The method of Claim 35 wherein said first sequence comprises a non-phase encoded scrambled binary 1 at 9600 bps.

37. The method of Claim 35 wherein said second sequence comprises a scrambled binary 1 at 9600 bps.

38. The method of Claim 34 wherein said answering modem receives said training sequence from said calling modem during said third predetermined period and uses said training sequence to train an equalizer in said answering modem.

39. The method of Claim 38 wherein said third predetermined period is approximately 1.75 seconds.

40. The method of Claim 34 wherein said first predetermined period is approximately 20 milliseconds.

41. The method of Claim 34 wherein said second predetermined period is approximately 250 milliseconds.

42. The method of Claim 34 wherein said third predetermined period is approximately 1.75 seconds.

43. The method of Claim 34 wherein said tone has a frequency of 320 Hz.

44. For use with a calling modem and an answering modem engaged in half-duplex communications, a method for correcting for a loss of equalization in an equalizer in said answering modem, comprising:
an answering modem procedure comprising:
detecting said loss of equalization in said equalizer in said answering modem;
waiting until said calling modem has completed transmitting;
sending a carrier for a first predetermined period;
being silent for a second predetermined period;
receiving a training sequence from said calling modem and using said training sequence to adjust said equalizer in said answering modem; and a calling modem procedure comprising:
detecting said carrier sent by said answering modem;
being silent for said second predetermined period; and sending said training sequence to said answering modem for a third predetermined period.

45. The method of Claim 44 wherein said answering modem procedure further comprises sending said training sequence to said calling modem for said third predetermined period, and said calling modem procedure further comprises receiving said training sequence from said answering modem and using said training sequence to adjust said equalizer in said calling modem.

46. The method of Claim 45 wherein said third predetermined period is approximately 1.75 seconds.

47. The method of Claim 45 wherein said training sequence comprises a first sequence for coarsely adjusting said equalizer and the second sequence for finely adjusting said equalizer.

48. The method of Claim 44 wherein said training sequence comprises a first sequence for coarsely adjusting said equalizer and second sequence for finely adjusting said equalizer.

49. The method of Claim 48 wherein said first sequence comprises a non-phase encoded binary 1 at 9600 bps.

50. The method of Claim 48 wherein said second sequence comprises a scrambled binary 1 at 9600 bps.

51. The method of Claim 44 wherein said first predetermined period is approximately 20 milliseconds.

52. The method of Claim 44 wherein said second predetermined period is approximately 250 milliseconds.

53. The method of Claim 44 wherein said third predetermined period is approximately 1.75 seconds.

54. The method of Claim 44 wherein said tone has a frequency of 320 Hz.