CA1324444C

CA1324444C - Disk emulation system

Info

Publication number: CA1324444C
Application number: CA000606545A
Authority: CA
Inventors: Wade B. Tuma; George B. Tuma; Robert E. Warne
Original assignee: Disk Emulation Systems Inc
Current assignee: Disk Emulation Systems Inc
Priority date: 1988-07-26
Filing date: 1989-07-25
Publication date: 1993-11-16
Anticipated expiration: 2010-11-16
Also published as: WO1990001193A1; EP0428597A4; KR970003316B1; EP0428597A1; US5070474A; AU4057589A; KR900702456A; JP2933282B2; JPH04502826A

Abstract

DISK EMULATION SYSTEM

George B. Tuma Wade B. Tuma Robert E. Warne ABSTRACT OF THE DISCLOSURE
Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD interface convention and thus to the central processor and the SMD disk controller, the disk emulator appears as a disk with virtually a zero access time. In one embodiment, the primary systems of the disk emulator are a 66-bit shift register, a parity circuit, a latch circuit, a 66-bit parallel bus and a dynamic random access memory (DRAM) array. Each of these systems interface with control systems of the disk emulator which provide the signals required for the read and write operations of the disk emulator. An error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit.

Description

132~4~

~ISK EMULATION SYSTEM

George B. Tuma Wade B. Tuma Robert E. Warne 5 BACRGROI~ND OF TEIE INVENTION
Field of the Invention This invention rela~es generally to a digital computer subQy~tem for storing data, and more specifically, to a dynamic random access memory unit which functions as a hard 10 di_k storage unit without the latency limitations of a normal hard disk.

De~criDtion of the Prior Art ~-Ali co~puters regardless of sise are comprised of the same ba~ic subsy~tem~, a central proce_sing unit, a means 15 for displaying information, a means for entering informa- ` -tion, and a mean~ for storing data. Several mean~ for storing data currently exi~t including floppy diQk drives, ``
tape drives, and hard or fixed disk drives. Floppy disk drives have a limited storage capacity usually one megabyte ~ -20 or 1--8. T pe drives are useful for archiving and backing up d~ta, but tape drives are not appropriate for random access application~. The device mo_t commonly u~ed for storage of large amounts of data is the hard di~k drive.
~he total me ory capacity of a hard disk drive can range 25 from 5-1000 megabytes.
The hard dis~ drive haQ a rotating magnetic media, a disk, that can be magnetized in a certain pattern and a read/write head which flys above the surface of the disk.
Durlng a ~rite operation, the head creates data patterns on 30 the ~agnetic coating of the rotating disk which represent -;
the data, while in read mode the head reads these data ; ~;
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patterns. ln most high capacity hard disk drives, several disks are mounted above one another on a common spindle.
Each of the disks has at least one head/write head per surface, and commonly several read/write heads may be 5 utilized on each surface. Data is stored in tracks which are concentric circles on the disk surface. When a plurality of disks are used on a common spindle, the tracks on the disks are written at the same relative radial position on each di~k, that is track one on one disk is 10 directly above ~or below) track one on the adjacent disk.
The track locations may also be looked as cylinder locations since the location of track one on the stack of disks forms what is referred to as a cylinder which extends perpendicularly to the disk surfaces.
The data stored on the hard di~k is generally divided into files~ Each file represents a unit of data which is processed by the digital computer. The files are stored on tha rotating diak in sector~. The number of Qectors which are written in one revolueion of the rotating disk comprise 20 a track. While ehe number of sectors per track is a function of the disk drive and the disk controller, thirty-two ~ectors per track are common. Since a magnetic servo can position the read/write heads over the entire surface of the disk, the disk ~urface containQ a 25 ~ultiplicity of concentric data tracks. A typical disk has a track density of 1000 concentric tracks over a one inch radius.
The central proces~ing unit, the central processor, of a digital computer must be able to read and write data on the 30 hard disk upon command. The data must be written on the di~k 80 that it can be found when the central processor wants to the read the same data. Controlling a disk drive is a very involved operation and if the central processor were totally involved in disk drive control, the central `~
35 processor would not have adequate time for other operations 1 ~ 2 ~

such as mathematical eomputations or data processing.
Therefore, the central processor interfaces with the hard disk drive through a disk controller. ~he central processor issues a request for a ~ile to the disk controller and then goes on to other ~asks. The disk controller issues commands ~-to the disk drive, locates the sectors comprising the file on the disk, retrieves the file, and cue~ the central processor that the file is ready for use.
The disk controller acting as an interface between the lo central processor and the hard disk drive introduces another problem. Each computer has its own protocol, that is, each computer has a unique bus structure for interfacin~ the ~ ;
central processor with peripheral devices such as a hard disk drive~ To interface a hard disk drive with each of the 15 various buses for the central processing units of different computers would be a very cumbersome task. Accordingly, standard disk protocols have been developed for hard disk drives~ Thus, each central processor has its own convention for communication, but the disk controller translates this 20 convention into a standard disk protocol.
Control Data Corporation origina~ed one of the most wide}y used dis~ interface specifications, the Storage Module Device (SND) interface. The æMD interface uses bit serial digital data transfer, a parallel control bus, 25 differential signals, and incorporates error recavery Eacilities. The SND interface is widely applied and virtually all the major disk manufacturers build products ; 1 that comply with the SMD interface. Therefore, means are available for interfacing a hard disk drive with the central 30 processing unit of the digital computer, but hard disk `;
drives are still plagued with two very serious problems, seek time and latency.
Access time is defined as the time span between when the central processor requests information and that information 35 is made available by the disk controller. The major factor ~ 4 - 132~

in the access time is the large amount of time, the seek time, required to position a head over the desired track of the hard disk. A seek time of 100 milliseconds is not uncommon for hard disk drives. The magnetic servo can only 5 position the head near the desired track. Each sector in a track contains information about the head position, the track, and the sector number within the track. The controller reads this information and t~rough successive approximation between the current position of the read head 10 and the desired position of the read head, the desired track is found.
The 100 millisecond delay time is a significant delay for modern high speed computers, but several factors can make the delay time even qreater. After the track requested lS by the central processor iA located, another delay, rotational latency, may be imposed. A typical hard disk makes one complete revolution every 16 milliseconds. If the head is positioned on a track ju~t as the desired sector has gone past, t~e controller must wait another 16 milliseconds 20 before the desired sector can be read.
A large file may include hundreds of Qectors each filled w~th data. The disk controller can handle only several sectors at a time. Thus, the access time delay is imposed over and over again. Also if a large file i9 being used ~5 simultaneously by many different users of the digital computer, the disk controller is flooded with requests for - `
sectors located throughout the disk.
While these problems are widely recognized, the high speed rotation of the di~k, the ability to precisely position 30 the read/write heads, and the geometry of the disk severely limit the choices in addressing these problems. The options available for improving access time include increasing the rotation speed of the disk, increasing the storage density of the disk, or enhancing the Atorage efficiency on the disk.
To better understand the limitations of the current hard :

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disk dri~es, consider the information written in each sector on the hard disk by the SMD disk controller. AS shown in Fig. la, each sector 10 is comprised of several fields in addition to the data field. The first information at the 5 beginning of each sector is the head scatter field 11. ~his field 11, typically sixteen bytes long, is provided to ~" -compensate for the inability of a normal hard disk drive to go instantaneously from reading to writing. Immediately after the head scatter field 11 is the PLO sync field 12 10 which is typically ten bytes in length. The PLO sync 12 is -~
a sync signal that permits the controller to compensate for ~
variations in the disk speed from disk to disk or from time ;-to time. Next is the address field 13 of the sector 10 which comprises eight bytes and is further broken down as 15 shown in Fig. lb.
The address field 13 is a unique Eield for each sector on the disk. It provides information on the sync pattern 13a, flag status and logical unit 13b, the upper cylinder `; ``
13c, lower cylinder 13d and the head and ~ector 13e plus two `~
20 cyclic redundancy checkiny ~CRC) code bytes 13fr 13g.
Follo~ing t~e address field 13 i8 a write splice field 14 whic~ i~ typically one byte. This is followed by another PLO sync field 15 of ten bytes and a sync pattern field 1 of one byte.
After field~ 16 is the data field 17 in which the central processing unit may store data on the disk or read data from the disk. The data field 17 is followed by a two byte CRC field 18 and then the one byte end of record pad field 19, follo~ed by an eight byte end of sector field 20.
On a typical hard disk, only 81% of the storaqe capacity i8 actually u~ed for data storage. The remaining storage capacity is used to store the additional fields for each sector a8 shown in Pig. 1. Typically, only the 8 byte address field and the data field are unique to the sector.
35 The data in the other fields is similar for each of the :` ;,, .

6 1 3 2 ~ 4 ~ 1 sectors in a track.
In locating a desired sector, the disk controller issues a seek command. A conventional hard disk drive then issue8 a pair of signals, a sector pulse and an index pulse. The 5 sector pulse is issued to the controller at the beginning of each sector and the index pulse is issued once per revolution of the disk. The SMD disk controller issues a read gate signal immediately after receiving the sector pulse. The hard disk drive upon receipt of the seek command 10 positions the read/write heads. Upon receipt of the read gate signal, the disk drive reads the head scatter, PLO
sync, and the address fields of the ~ector over which the read head is currently positioned and sends the information to the SND disk controller. The SND disk controller always 15 dea~sert~ the read gate at the write splice field of the sector. Next, the controller initiate~ one of three actions;
1. If this is the sector to read, read gate is rea~serted. 0 2. If thi~ is the ~ector to write, write gate is a-~erted.
3. If thi~ is not the sector of interest, neither gate i~ asserted.
If it is not the correct track, the head moves to a new 25 location baged upon the current position and the position r~quested by the central proce~sor and reads again. This process continues until the correct track i8 found. A read gate or write gate signal is a~erted by the disk controller when the desired sector and track are found.
To overcome the problems associated with hard disk drives reguires eliminating or substantially reducing the acces8 time of the disk as well as providing better means for storage of data. The prior art has considered increasing the rotational speed of the hard disk, increasing 35 the storage density of the hard disk, and increasing the - 7 - 1 3 2 ~

efficiency of data storage on the hard disk as means for improving the performance of a hard disk drive. Another solution would be to replace the hard disk with solid state memory. Solid state memory has the advantages of a very fast access time and very good reliability because it is not an electromechanical device, but the SMD interface was conceived to control disks and rotating medium and not to control any type of solid state memory. Therefore to replace the hard disk with 301id state memory requires that 10 the solid state memory appear as a disk to the SMD disk ~`
controller. This invention overcomes the problems of the prior art by providing a means for directly interfacing a solid state memory with a SMD disk controller.

S~MAaY `` "
The disk emulator of thi~ invention i~ a solid ~tate system for significantly improving access time, i.e., improving both the seek time and the rotational latency.
The disk emulator complies with the SMD interface convention and thus to the central processor and the SMD disk controller, the disk emulator appears as a disk with vlrtually a ~ero ~ccesg time.
In one e~bodiment, the primary systems of the disk e ulator are a 66-bit shift register, a parity circuit, a latch circuit, a 66-bit parallel bus and a dynamic random acce88 memory (DRAM) array. Each of these systems interface ~ith control systems of the disk emulator which provide the signals reguired for the read and write operations of the disk emulator. ~hile different circuits are required to generate the signals necessary for the write operation and for the read operation, the use of the shift register, p~rity circuit and latch circuit in conjunction with the 66- -bit parallel bus and the DRAM array for both the read and write operations minimises the circuitry in the disk ~
~mulator. Consequently, both the cost and the size of the ~;
` "'' . .

disk emulator are reduced.
The 66-bit shift register receives serial data from the SMD disk controller and converts the stream of serial data into 66-bit words which are each passed over ~he 66-bit 5 parallel bus to the latch circuit where they are temporarily stored. For each 66-bit word a parity bit is alqo generated by the parity circuit. The stored word in the latch circuit and the associated parity bit are transferred to the DRAM
array over the 67 bit (that is 66 bits of data + 1 parity lo bit) parallel bus while another word is being serially supplied to the 66-bit shift register by the SMD disk controller.
In this embodiment, each track of data in the disk emulator may be comprised of thirty-two sectors, with each "
15 sector beinq comprised of si~ty-four 66-bit words. This word length allowQ the memory interface timing to be very conservative while still maintaining a very fast transfer rate to the S~D disk controller. An additional benefit of the 66-bit word is the economy oE parity. For a long word, 20 tbe ~tored parity bit i~ a small portion of the stored data.
To further reduce the memory requirements for the DRAM ` "`
~rr~y of the disk emulator, only the ~ector-specific data provided by the S~D disk controller are stored in the DRAM
array. In each sector on a disk, only the address field and 25 the data field are unique. Accordingly, the di~k emulator ne ds to store only address information and the data information and does ~o by making the zeroth word of the sector in the DRAM array the addre~s field and the first through sixty-third words of the sector in DRAM array the 30 data field. Since only t~e sector-specific data, the address field and the data field, are stored in the DRAM
array, approxim~tely 97~ of the ~RAM array is used for data storage while in a typical hard diQk only 81% of the disk is available for data storage. Hence, the ability of the disk 35emulator to store only sector-specific data significantly ~ ~
~ ' . .

1 3 2 `~
g . -enhances the utilization of the storage medium over priorart systems.
Another unique feature of the disk emulator concerns data integrity. Solid state memory errors can be divided 5 into two basic types, hard errors and soft errors. The SMD
disk controller corrects soft errors which are random, --single bit errors in the data retrieved from the DRAM
array. However, hard errors are the result of a catastropbic memory failure in the DRAM array and generally --10 affect many bits within the array. Hard errors require an error correction process to correct the stored data before the data are supplied to the SMD disk controller. Prior art error corre~tion process typically u~ed an 8-bit ECC code and a matbematical process which operated on the ECC code to 15 correct hard errors. However, an a-bit per word overhead would add significant cost to a disk emulator. Accordingly, a novel error correction process is incorporated in the disk emulator whicb corrects single bit hard memory errors using only a single parity bit.
In the error correction process, as each word is `-retrieved from the DRAM array of tbe disk emulator, a new parity bit is generated for tbe stored word. The new parity bit is cQmpared with the stored parity bit for the ~tored `~
~ord. If the two p~rity bits are the same, no error has 25 occurred and the normal read cycle for the di~k emulator is `
followed. ~owever, if the two parity bits are dif~erent, an error has occurred and the disk emulator uaes the novel error correction process to correct the word.
In tbe error correction process, the retrieved word i9 ` :.
30 inverted and latched in the latch circuit of the disk o~ulator. The inverted word is then written to the qame location in the DRAM array from which the original word was retrieved. Tbe inverted word is then again retrieved from tbe DRA~ array, inverted and latched in the latch circuit.
35 Then, at the appropriate time, the error corrected word is :: `
: "

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passed from the latch circuit over the 66-bit parallel bus to the 66-bit shift register from which the error corrected word is serially supplied to the SMD disk controller.
This novel READ/INVER~/WRI~E/READ/INVERT~WRI~E error 5 correction process, using only a parity bit, corrects a single bi~ hard memory error while the previous word is being serially supplied to the SMD disk controller. With the design of the latch circuit, i.e., the use of inverting latches, and this novel six step error correction process, lo the error correction process is completed in a time frame -~uch that the disk emulator can operate at data rates as high as 50 Megahertz. Thus, the new error corraction process not only conserve~ storage space in the DRAM over ~``
prior art proces~es, but also corrects errors with such 15 speed that the disk emulator operates at the highest freguency permitted by the SMD interface convention.
When the SMD disk controller wants to read data from the di8k e~ulator or write data to the disk emulator, the SMD
controller send~ a seek command to the di~k emulator. The 20 S~D di~ controller simultaneously provides the cylinder and head addres8 for the de8ired data over the SMD control cable. The co~bination of the cylinder and head address d~fines a unique track since each head can access predetermined cylinder8 on one di8k surface. Differential 25 current aode receivers in the disk emulator tran~late the differential signal~ $rom the SMD disk controller to logic signals.
The ROM translation circuit in the disk emulator instantaneously tran~lates the geometric addresses from the 30 5MD disk controller, the cylinder and head address, into higher order addresses for the DRAM array in the di~k e~ulator. In the disk emulator, higher order addresses refer to the addres~es $or the DRAM array which correspond ;
to the cylinder and head address from the SMD controller.
35 Lower order addresses are also used in the DRAM array and 132~

that term refers to the addresses in the DRAM array which correspond to the sector and the words within a sector.
Since the translation of the geometric address information from the SMD controller to the higher order 5 addresses is virtually instantaneou~, the microprocessor in the disk emulator can, upon receiving the seek command, immediately issue an index pulse to the SMD controller indicating that tbe desired head has been located over the :
desired cylinder, i.e., indicating that the track containing lo the desàgned sector has been located. The microprocessor then enters the rapid sector cycle. In the rapid sector cycle, the microprocessor initially generates the addreqs corresponding to the zeroth sector of the track specified by the SND disk controller. `
The inde~ pulse sent to the SMD disk controller is also used to initialize the disk emulator. The index pulse clears progra~mable counters, used to ~enerate timing ;
signals, the shift register and other components in the disk emulator. In addition, other programmable counters, used to 20 addr~sQ the words in a sector, are initialized such that the eroth word of the sector is addressed.
Sin~e the SND disk controller provided information which ``
wa~ tran~lated into the higher order addre~s and the disk emulator qenerated the lower order address for the zeroth 25 ~ord of the ~ero ~ector of the track specified by the SND
disk controller, the location in the DRAM array of the word that will initially be provided to the SMD disk controller is completely specified. Accordingly, the disk emulator fetches the reroth 66-bit word for the zeroth sector twhich 30 i8 the address field for the zeroth sector) in the track specified by the SMD controller plus the one parity bit for the eroth word and provides the word to the latch circuit and p~rity circuit on the 66-bit parallel bus.
At this time, the parallel terminals of the shift 35 register, which are also connected to the 66-bit parallel - 12 - 1 32 1 ~4~

bus, are tri-stated to prevent contentions on the 66-bit parallel bus between data in the shift register and the zeroth word being retrieved from the DRAM array. ~hus, the zeroth word from the DRAM array on the 66-bit parallel bus 5 is available only to the parity circuit and to the latch circuit. The parity circuit generates a new parity bi~ for the zeroth word on the 66-bit parallel bus and the error correction circuit compares the stored parity bit with the new parity bit and as described previously, the stored word lo is error correctea if the two parity bits are different.
Hence, after the seek command from the SMD disk controller and the index signal from the disk emulator, the zeroth word, the address field, for the zeroth sector of the track specified by the SND disk controller is loaded in the 15 latch circuit and is ready to be loaded into the shift regi~ter and serially transmitted to the SMD disk controller. ` "
Imoediately after the SMD disk controller receives the index pulse from the di~k emulator, the SMD disk controller 20 asserts the read gate signal to the disk emulator. At this time, the disk emulator starts to 8upply a series of zero ~`"
bits to the SMD disk controller which correspond to the first gap in the sector, i.e~, the region from the start of the sector to the address field of the sector.
The disk emulator counts the number of bytes supplied to the 5MD controller and precisely when the number of bytes in the sector prior to the addre~s field is reached, the disk ~ `
emulator load~ the address field from the latch circuit over the parallel bus into the ~hift regiQter which subsequently 30 ~erially shifts the address field to the SMD controller.
While the address field i8 being serially supplied to the SMD controller, the disk emulator retrieves the first word of the ~eroth sector from the DRAM array, error corrects the ~" "
word, and stores the word in the latch circuit.
After the SMD disk controller receives the address 132~

field, the controller deasserts the read gate at the write splice field of the ~ector and initiates one of three actions: (1) if this is a sector to be read, the SMD disk controller reasserts the read gate; (2) if this is a sector 5 to be written the SMD controller a~serts the write gate; or (3) if this is not the sector of interest, neither the read gate nor the write gate is asserted by the SMD disk controller.
Accordingly, the microprocessor of the disk emulator lo polls the read gate signal and the write gate signal from the SMD disk controller for a predetermined time after issuing the address field lin this case for the zeroth sector) and if neither the read gate nor the write gate signal is reasserted, this indicates that this is not the 15 sector which the SMD controller desires and a sector pulse i~ generated by the microprocessor and transmitted to the SMD disk controller. The microprocessor also increments the address of the DRAM array to the first sector in the track ~pecified by the SND disk controller. `:
The sector pulse initialises the disk emulator in a ~anner that i~ identical to that previously described for the index pulse. Hence, the zeroth word, the address field, for the first sector of the track specified by the SMD disk controller is retrieved, error corrected, and stored in the 25 latch circuie, In response to the sector pulse, the SMD disk controller asserts the read gate and the disk emulator again provides the ~ero bits for the first gap prior to the address field and aEter the first gap is finished the seroth word, the 30 addres- field, of the first sector of the track requested by the SMD disk controller is loaded into the shift register and serially provided to the SMD disk controller. While the addre~ field for the first sector is being provided to the S~D di8k controller, the disk emulator retrieves, error 35 correct~ and store~ the first word of the data field of the - 14 - 132~

first sector in the latch circuit.
~ he read qate signal and t~e write gate signal from the SMD disk controller are again polled for the predetermined time after the initiation of the sector pulse and address 5 field and if neither the read gate nor the write gate is reasserted, another sector pulse is generated by the microprocessor and the zeroth word for the second sector is --provided to the SMD disk controller in the same matter as described for the zeroth sector and the first sector. The 10 microprocessor continues in this rapid sector cycle mode to initiate a series of read cycles on the zeroth word of consecutive sectors in the track until the read gate or the write gate is asserted by the SMD disk controller~
Thus, the address fields are read by the SMD disk 15 controller at rapid intervals, typically about 10 ~icrosecond~, until the desired sector is found. If the deQired sector is the last one on the track, i.e., the -~
thirty-~econd sector, 320 micro~econds are required to locate thc sector. ~ conventional hard diQk drive can 20 require sixteen milliseconds to locate the correct sector after the track i~ located~ ~ence, the disk emulator of this invention reduces the average rotational latency by a factor of 500. Thi~ represents a Qignificant increase in the perfor~ance over a conventional hard disk drive and ~he 25 rotational latency of thè disk emulator i~ no longer the limiting factor in the response of the disk system. Now, ehe perfor~ance of the 5ND disk controller and the disk emulator is bounded by the response time of the SMD disk controller. Accordingly, to further improve the rotational `~-30 latency requires a change in the SMD interface convention.
~ hen the addres~ field provided to the SMD controller corresponds to the sector sought by the SMD controller, the D controller reasserts the read gate if the central proc-s~ing unit driving the SMD disk con~roller has 35 reguested the data stored in that sector. When the read - 15 - 1 3244~ 4 gate is reasserted, the microprocessor leaves the rapid sector cycle and the disk emulator provides a string of zeros, corresponding to the second gap in the sector which is the space between the address field (field 13) and the 5 first word in the data field, to the SMD disk controller.
At the precise time the number of bytes in the ~econd gap is completed, the error corrected first word of the data field is loaded into the shift register and serially ;
supplied to the SMD disk controller. While the first word 10 Of the data field is being supplied to the SMD disk controller, the second word of the data field i9 retrieved from the DRAM array, error corrected and stored in the latch circuit, and when the last bit of the first word leaves the shift register the second word is loaded into the shift 15 register and serially provided to the SMD disk controller.
This proceQs continues until the sixty-third word of the sector, which i~ the ~ixty-fourth and final word of the ~ector because the first word was the seroth word, is provided to the SMD disk controller. After the sixty-third 20 ~ord leave~ the shift register, the disk emulator is di8abled and provides a series of zero bits to the SMD
controller until another sector or index pulse is generated.
When the central processor, which drives the SMD
controller, wants to write data to the disk emulator, the 25 initial sequence of actions is identical to those in the read operation. The SMD disk controller issues a seek command and provides the cylinder address and head address to initiate a write to the disk emulator. The microprocessor upon receipt of the seek command and cylinder 30 and head addres-~ immediately isQues an index pulse and enters the rapid sector cycle. ~he initialization of the disk emulator and the retrieval of the zeroth word for the zero ~ector of the track requested by the SMD disk controller are identical to that previously described.
35 Accordingly the SMD controller again reads the zeroth word - 16 - 132~`14 and deas~erts the read gate at the write splice portion of the sector. Next the controller initiates one of two actions: (1) if this is the sector to write, the write gate is asserted; or (2) if this is not the sector of interest, 5 the write gate is not asserted.
If the write gate is not asserted, the microprocessor continues to rapidly supply the ~eroth word for the next sector (sector one) in the track and then polls the write gate and the read gate to determine whether either gate is 10 asserted as previously described. When the correct sector is located and the write gate is asserted by the SMD disk controller, serial data is clocked into the shift register and the microprocessor leaves the rapid sector cycle mode.
A comparator circuit in the disk emulator, which is 15 programmed to detect the data sync pattern prior to the addre~s field, monitors the data in the shift register~
When the dat~ sync pattern i8 detected, after two additional clock pulses to the shift register, a signal is generated which captureQ the first 66-bit word of the data field which 20 includes the data sync pattern in the latch circuit. The locations in the shift register, which are monitored by the co~parator circuit, are ~elected such that when the data sync p~ttern is detected, two additional clock pulses to the "~
8hift regi8ter are required to load the first full 66-bit `~
25 word of the d~ta field completely into the ~hift register.
While the next word is entering the shift register the 66-bit word stored in the latch circuit and the associated parity bit are written to the DRAM array over the 67-bit :
parallel bus which consists of the 66-bit data bus and the ~ -30 parity bit line, respectively. Also, the address for the DaA~ array i8 incremented to the next data word of the sector.
This sequence of operations is repeated for the second data ~ord through the si~ty-third data word of the sector. , 35 Thus, si~ty-four words are written to the DRAM array for . . , - 17 - 1 3 2`~f'~

each sector. In addition to the 66 bits of data information, a parity bit is generated by the circuitry in the disk emulator and is stored in the DRAM array as a 67th bit. After the sixty-fourth word is written to the DRAM
array, the disk emulator is disabled until the SMD disk controller issues another sector or index pulse.
Since the DRAM array of the disk emulator is a volatile memory storage element, ~he disk emulator contains back-up systems which protect the integrity of the data in the DRAM
10 array in the event that the power supply voltage is diQrupted .
The disk emulator of this invention significantly improves both the seek time and the sector rotational latency. Also, the data storage medium in the disk emulator 15 i~ used more efficiently than the data storage medium in a conventional hard disk. Pinally, since the disk emulator has no mechanical or moving parts and since the novel error correction process corrects hard memory failures, the reliability of the disk emulator should be significantly 20 better than the reliability of prior art hard diQk drives.

~RI~F DES~RIPTION QF TH~ DRAWINGS `
Fig. Ia and Fig~ lb illustrate the contents of a typical sector a~ defined by the SND interface convention.
Fig. 2 illu~trates a conceptual block diagram of the 25 architecture of the disk emulator of this invention.
Fig. 3 is a block diagram of the major circuits of the di~k emulator of the present invention.
Fig. 4, Fig. 5, and Fig. 6 are schematic diagrams of the interface between the SMD control cable, the SMD data cable 30 and the di~k emulator.
Pig. 7 and Fig. 8 are schematic diagrams of the differential current mode drivers which interface the ~elected lines in the disk emulator with the SMD data cable and the SMD control cable.
'',``,`~ .~

' - 18 - 132444~

Fig. ~ is a schematic diagram of input control circuit 801 of the disk emulator~ -Fig. 10 iS a schematic diagram of 66-bit shift register 802 in t~e disk emulator, and illustrates the intercor.nec-5 tions to input control circuit 801, 66-bit parallel bus 700, and AND gate Sg3 which are also shown.
Fig. 11 is a schematic diagram of latch circuit 803 of the disk emulator and illustrates the connections of latch circuit 803 to 66-bit parallel bus 700.
1~ Fig. 12 is a schematic diagram of parity circuit 80~ of the di_k emulator and illustrates the connections of parity circuit 80~ to 66-bit parallel bus 700.
Fig. 13 illustrates the connections to multiplexer 1125 used to provide read control signals and write control 15 signals to shift register 802 and latch circuit 803 in the `
dis~ emulator.
Fig. 1~ iQ a ~chematic diagram of comparator circuit 815 in the disk e~ulator.
Fig. 15 is a schemaeic diagram of write control circuit 2~ 806 ~n the d~sk emulator.
Fig. 16 i_ a ~chematic diagram of first gap counter circuit 808 and ~econd gap counter circuit 809 in the disk e~ulator.
Fig. 17 i8 a schematic diagram of byte clock circuit 813 25 in the di~k e~ulator.
Fig. 18 iQ a ~chematic diagram of read counter circuit 810 in the disk emulator.
Fig. 19 is a schematic diagram of the circuit of memory ~ord counter 807 in the disk emulator.
Fig. 20 i8 a schematic diagram of on-cylinder circuit 840 in the disk emulator. - `-Fig. 21 i8 a Qchematic diagram of microprocessor 816 in the disk emulator.
Figs. 2~a and 22b are a schematic diagram of ROM
35 trsnslation circuit 819.
`'`'`'",.'' " ' 132~

Figure 23 is a schematic diagram of sector/index circuit 817 of the disk emulator.
Fiqure 24 is a scheDatic diagram of writing flag clrcuit 811 in the disk e~ulator.
Figure 25 ls a sche~atlc dlagram of one of the slxteen DRAN controllers used in the disk emulator~
Flgures 26a and 26b are a block dia~ram illustratinq one of t~e sixteen DRAH cards in the disk e~ulator.
Figures 2~a throuqh 27d are a schematlc diagra~ of buffer clrcult 845 for the typical DRAH card in Pigures 26a and 26b. -F~gures 28a t~rouqh 28e lllustrate one storage block of the four storage blocks used ln each bank of à DRAN card ln the ~-dl~k enulator~
Fiqure 29 l~ a sche~ati~ dlagra~ of RFRQ clrcuit 841 in the dis~ e~ulator. ~ ;
Flgure~ 30a tbrough 30k illustrate the read slgnal~ and latch clock slgnal~ for reading the zeroth ~ord of a sector ~lthout error. ``
Figure 31 ls a schenatlc diagra~ of latch clock/error detectlon clrcult 805 ln tbe disk aaulator. :~
Figure 32 ls a scheuatlc dlagrau of the re~ot clrcult ln the dls~ aaulator.
Flgure 33 ls a ~cbeuatlc dlagrau of read~wrlte gate clrcult 812 ln t~e dlsk euulator.
Flgures 3~a throuqh 34z illustrate the slgnal response of read countar elreult 810 to the rollover of flrst gap counter . . . .
808. ;-;

~ ' , . ,. .- .
,', ' ..`'',.

u~ J ~ ~ ~

132~4~

Figures 3sa through 3sj on the sa~e sheet as Figures 30a through 30k, illustrate the sequence of signals for readlng of the first through sixty-third words of the sector without error Figure~ 36a through 36z illustrate the response of read counter circuit 810 to the rollover of second gap counter 809 and to read counter 810 Figures 37a through 37v illustrate the signal response ` -of ~rite eontrol circuit 806 after the data sync pattern is detected~
Flgures 38a through 38~ lllustrate the sequence of signals for ~rlting data to the disk emulator Figure 39 is a sche~atlc diagra~ of write B circu~t 814 ~ `
ln the dl~k emulator Flgures ~Oa through ~0~, on the sa~e sheet as Flgures ~;
38a tbrough 38~, illustrate the seguenoe~ of slgnal~ for a read ~itb error Flgure ~ a schematie dlagran of the unit select ` -circult in the di~k emulator~
Flgure ~2 1~ a sebenatlc diagram of the clock zero and tb~ clock one oircuit in the di~k emulator Figure ~3 1~ a schematlc dlagra~ of a flr~t portlon of -~
.. ..
SCSI back-up ~y~ten 101 ln the dl~k e~ulator Flgure ~ 18 a seheoatlc dlagraa of the second and ;`
ren-lnlng portlon of SCSI back-up ~y~tem 101 ln the dlsk emulator Figure~ ~5a through ~5d ldentlfy the indlvldual llnes lneluded ln the eables u~d ln the dl~k e~ulator Flgure ~6 1~ a sehematlc dlagram of SMD sector~lndex ... . .
elrcult 818 in the dl~k emulator ^~
..... :
. . .

~... ~ .

1324~
20a Figures 47a through 47c are a listlng of a BASIC
computer program used to generate the ROH translation table used in one embodiment of tbis invention.
Figure ~8 is a partial output listlng of the computer program of Figures 47a through 47c.
D~TAILFD DESCRIPTION OF THB INVENTION
The disk e~ulating system of this invention is a solid state syste~ for eli~inating latency. The disk emulator complies -with the SND lnterface convention and thus to the central :~
processor and the SMD disk controller the disk emulator appears as ~`
a disk drive with virtually a zero access time. A conceptual block diagra~ of the disk emulator ls sho~n ln Flgure 2.
Conceptually, a serializer~deserialiser 102, in Figure 2, ':'' :`' ~,;., ,';.'' ~ ~ , .

- 21 - 132~4~ -interfaces the solid state memory 104, a dynamic random access memory ~DRAM) array, of the disk emulator with the SMD disk controller 107. ~he serializer/deserializer 10~
functions in the deserializer mode and converts the serial 5 data stream on a write data line 115 from the SND disk controller into 66-bit parallel words that may be efficient-ly written into the DRAM array 104 over the parallel bus 112, 113. Conversely, when SND disk controller 107 reads data from the disk emulator, serializer~deserializer 102 lo functions in the serializer mode, converting the 66-bit parallel word, retrieved from solid state memory 104 over parallel bus 112, 113, into a serial data stream that is passed to the SMD disk controller over a read data line 11~. Also, serializer/de~erializer 102 generates a parity 15 bit Eor each 66-bit parallel word. As is described later, the parity bit is al~o stored in solid state memory 104 and is used for error correction.
In this embodiment, each track of data in the disk emulator is compri~ed of thirty-two sectors which are 20 de~ignated sector sero through sector thirty-one. Each sector i8 co~prised of sixty-Eour 66-bit words ~designated wlthin the ~ectors as word sero through word _ixty-three).
The ~eroth word in each sector is used to identify the sector and i~ the address for its respective sector. This 25 word length allows the memory Ee~ch timing to be very conservative while still maintaining a very fa~t transfer rate to the SMD disk controller. An additional benefit of the 66-bit word is the economy of parity. ~or a long word, the stored parity bit is a small portion of the stored 30 data. ~owever, in view of the description of the present invention, the design cf a disk emulator which utilizes a difEerent word length and/or sector length will be apparent to those skilled in the art.
When 5ND disk controller 107 wants to read data from the 35 disk emulator or write data to the diqk emulator, SMD disk . .~; . ' - 22 - 132~4~

controller 107 sends a seek command to control circuit 100 over an on-cylinder line 121. SMD disk controller 107 simultaneously provides the cylinder and head address for the desired data over cylinder/head address bus 108 to 5 addre~ translation circuit 106. Address translation circuit 106 converts the signals provided by SMD disk controller 107 into the hiqher order memory addresQes for ~he data the SMD disk controller wishes to read or write.
These addresses are provided to memory address selector 105 lo over higher order address bus 109. Unlike a typical hard disk which must hunt for the specified track, the disk emulator determines the address of the desired track instantaneously using address translation circuit 106.
Accordingly, addres~ translation circuit 106 eliminates the 15 head seek time a~sociated with locating the specified track in a conventional hard disk drive.
The control circuit 100, upon receiving the seek command, im~ediately issues an index pulse to SMD disk controller 107 indicating that the desired track has been 20 located and control circuit 100 enter~ the rapid sector cycle. In the rapid sector cycle, control circuit 100 begin8 by generaeing the address in solid ~tate memory 104 of the location of the seroth word in the zero ~ector ~which is the ~ddre~s of 8ector zero) of the track specified by SMD
25 disk controller 107 and that address i~ transmitted over addre~ bus 110 to memory address selector 105.
Since the SMD controller 107 provided the cylinder and head address information, which was translated by address translation circuit 106 into the higher order addresses, and 30 control circuit 100 generated the lower order addresses, the loc~tion of the word that will initially be provided to SMD
disk controller 107 is completely specified. Accordinglyr the disk e~ulator fetches the ~pecified 66-bit word plus 1 parity bit and provides that word to error correction 35 circuit 103 over parallel bu~ 112. Error correction circuit - 23 - 132~4~ ~

103, using the parity bit, analyzes the zeroth word (which is the address of sector zero) as described below, and if a bit of the 66-bit word changed while the word was stored, after storage or during a read in the solid state memory, 5 error correction circuit 103 corrects the hard error. I$
the error is not a hard error, error correction circuit 103, as described below, does not correct the error and so the error is passed to disk controller 107 which does correct the error.
Immediately after SMD disk controller 107 receives the index pulse from control circuit 100, 5MD disk controller 107 asserts the read gate signal on read gate line 119 to control circuit 100. Control circuit 100 then loads the error corrected ~eroth word, which is stored in error 15 correction circuit 103, into serializer/deserializer 102 over parallel bus 113. The 5ND disk controller 107 reads the eroth word which is provided serially on read data line 11~ by geriali8er/deserialiser 102. ` ` While the ~eroth word of sector zero is being read by 20 S~D disk controller 107, the disk emulator retrieves the .
fir~t word of the ~eroth #ector (which is a data word) from DRA~ array 10~ and provides the first word and the stored p rity bit to error correction circuit 103 on parallel bus 112. By loading the first word of sector zero into error 25 correction circuit 103 at thi~ time, if sector zero is the desired sector, the first word will be available as soon as it is reque~ted by SND controller 107.
The SMD disk controller 107 deasserts the read gate at the write splice field of the sector as shown in Fig. la, 30 and initiates one of three actions; (1) if this is the ~-sector to be read, the SMD disk controller reasserts the re~d gate; ~2) if this is the sector to be written in, the 5MD disk controller asserts the write gate; or l3~ if this i8 not the sector of interest, neither the read gate nor the 35 write g~te is a~serted.

':` ` , - 24 - 132~4~

Control circuit 100 polls read gate line 119 and write gate line 120 for a predetermined time after issuing a sector address and if neither the read gate signal nor the write gate signal is detected, a sector pulse is supplied by 5 control circuit 100 to SMD disk controller 107 over a sector pulse line la2. After the sector pulse, the zeroth word of the first sector (the address of sector one) of the track requested by SMD disk controller 107 is loaded into serializer/deserializer 102 in a manner identical to that 10 described for the zeroth ~ector and 5MD controller 107 reads thi~ address word. The read gate line 119 and write gate line 120 are polled again by control circuit 100 for a predetermined time after issuing the sector address and if the read qate or write gate i~ not detected, another sector 15 pulse is supplied to SMD disk controller 107 by control circuit 100 and the ~eroth word for the second sec~or is ~ent to SMD disk controller 107. Control circuit 100 continues in thi~ rapid sector cycle mode to initiate a serie~ of read cycles on the zeroth word of consecutive 20 ~ector~ in the track until the read gate or write gate is rea~#erted after the reading oE the seroth word.
When the read gate is reasserted by SMD disk controller 107 over read gate line 119, control circuit 100 loads the fir~t ~ord of the ~ector, which i8 stored in error 25 correction c~rcuit 103, into serialiser/deserializer 102 and then sequentially retrieves the second through sixty-third word of the sector from DRAM array 104. It will be recalled fro~ above that words one through sixty-three in each aector comprlse the data word~. As each word is retrieved, the 30 ~ord and the related parity bit are paa~ed over parallel bus 112 to the error correction circuit 103. Using the parity bit, error correction circuit 103 corrects any hard error which occurred and then the word is passed over the 66-bit parallel bus 113 to serialiser/deserializer 102.
35 Seriali2er/deserializer 102 provides the first through - 25 - 132~4~

sixty-third word of the sector serially to SMD disk controller 107 over read data line 114 so that all sixty-four words in the sector, the address field plus the sixty- -three words of data, are passed to the disk controller.
When the central processor, which drives SMD controller 107, wants to write data to the disk emulator, the initial sequence of actions is identical to those in the read operation. SMD disk controller 107 issues a seek command to initiate a write to the disk emulator~ Control circuit 100 10 upon receipt of the seek command immediately issues an index pulse and enters the rapid sector cycle. Control circuit 100 supplies the zeroth word for the zero sector Ithe ``
address of sector zero) oE the track requested by SMD disk controller 107. SND controller 107 again reads the seroth 15 word from Qerialiser/deserialiser 102 and deasserts the read gate at the write splice portion of the séctor. Next the controller initiates one of two actions (1) if this is the ~ector to write, the write gate is asserted; or (2) if this i8 not the ~ector of interest, the write gate is not 20 a~Qe:rted.
If the write gate is not asserted, control circuit 100 continues to supply the seroth word for the next sector in the track at a predetermined time, ten micro~econds in one e~bodiment, and then polls write gate line 120 to determine 25 whether the write gate is asserted. Control circuit 100 continues to is~ue successive sector address information and `~
poll write gate line 120. When SMD controller 107 receives the address of the desired sector, the write gate is as~erted by S~D disk controller 107, and serial data i5 30 clocked into serializer/deserialiser 102 over write data line 115. This is the firQt data word to be stored in solid ~tate memory 104. When an entire 66-bit word is in ~eriali~er/deserialiser 102, the word i_ passed over 66-bit parallel bus 113 to error correction circuit 103 where the 35 word is temporarily stored. While the next word is entering ., ~ .

,. ~' . . .

- 26 - 132~

serializer/deserializer 102 from SMD controller 107, a parity bit is generated for the 66-bit word stored in error correction circuit 103 and then this stored 66-bit word and the parity bit for that word are written to solid state 5 memory 104 over 67-bit parallel bus 113. This sequence is continued until a sector's worth of datar consisting of a 66-bit address word and sixty-three 66-bit data words, plus one parity bit for each word, is stored in the solid state memory 104.
In the read/write operation, the disk emulator converts ~ `
the geometric address data provided by SMD disk controller 107 into contiguous binary addresses and reads/writes the data at these addresses in solid state memory 104. This operation eliminates the seek time of a hard disk because a 15 data structure is generated that is easily and rapidly addres~ed when SMD disk controller 107 wants to retrieve or write data.
The solid state memory 104 of the disk emulator is a volatile memory storage e}ement. If the power to the disk 20 e~ulator were to fail, all the data ~tored in solid state me~ory 104 would be lost. Therefore, the disk emulator has several backup systems to ensure that this does not happen.
A battery backup module is a part of the solid state me~ory 10~. Should the line voltage fail, the battery 25 bac~up module can sUpport the memory structure for a time related to the battery capacity. The backup system also includes a SCSI hard disk 101. If control circuit 100 -senses that the battery power is failing, then the data stored in the solid state memory 104 are accessed by control 30 circuit 100 through serializer/deserializer 102 and the data are removed through the parallel path 118 and stored on SCSI
hard disk 101. Since SCSI hard disk 101 is a nonvolatile media, the data can effectively be warehouQed on the disk until the power i8 restored at which time control circuit 35 100 restores the data in solid state memory 104 via an . .

- 27 _ 132~

algorithm in software, which reprograms solid state memory 104 to the condition that existed when the disk emulator lost battery power.
While Fig. 2 illustrates the basic structure of the disk 5 emulator and is useful in conceptually visualizing the function of the disk emulator, Figs. 4-29, 31-33, 39, and 41-46 provide a circuit diagram of one embodiment of the disk emulator of this invention. In Figs. 4-29, 31-33, 39, and 41-46 are several integrated circuits. Several of the ~-10 integrated circuits are marked with a reference character as well as a second number. The reference character has four numerical digits or less, while the second number has either alphanumeric character~ or five numerical digits. The second number is generally the industry standard 15 identification number for integrated circuits. For example, IC indicated by reference character 1122 in Fig. 14 has a second number of F521 which i~ the identification nu,mber for a Series 7~ standard TTL integrated circuit. Similarly, in the specification Series 7~, standard T~L integrated circuit 20 identification is given for those integrated circuits not identified in the drawing~ For a detailed description of the specific integrated circuits, see for example, The T~L ``
Data_aook, Vol. 2, Te~as InQtruments, 1985. Two exceptions for the ~econd identification numbers are in Fig. 21 and 25 Fig. 25. In Fig. 21, integrated circuit indicated by reference character 1063 is an Intel 8051 microprocessor and in Fig. 25 integrated circuit indicated by reference character 8207 is an Intel 8207 DRAM controller. Since the circuit diagram, as shown in these figures, i~ complex, 30 Fig. 3 illustrates the major circuits in the disk emulator ~"`
as block diagram and ~hows the interconnections between the ma~or circuits. The general operation and interaction of the various circuits in Fig. 3 is considered first and then the integration of these circuits to perform read and write 35 functions is described in more detail.
, ~
`: `

- 28 - 132~

DIFFERENTIAL CURRENT MODE RECEIVERS
As shown in Fig. 3, the SMD disk controller sends data to the di~k emulator over the SMD data cable. Since ~he SMD
disk controller provides differential signals, each pair of 5 lines in the data cable is connected to a differential current mode receiver 800, only one of which is shown in Figure 3. Fig. 4, Fig. 5, and Fig. 6 are schematic diagrams of the interface between the lines in the SMD data cable and the SMD control cable and the lines in the disk emulator 10 system. The schematic for t~e interface between the lines J~-20, J~-8, which provide data from the SND disk controller, and the write data complement line 735 of the `
disk emulator is shown in Fig. 4. In this interface, which is also typical of the other interfaceQ shown in Fig. 4, :`; `
15 Fig. 5, and Fig~ 6, the differential signal on the lines J4-20, J~-8, which represent~ the data to be stored in the dis~ emulator, is coupled to a differential current mode receiver 547 in a ~C3~50 integrated circuit ~which is a generally available integrated circuit which may be `
20 purcbased by ordering by that part number) through a line te o inating resistor net~ork R54, R54-1 and the signal generated or. ehe output terminal of receiver 547 drives the ~rite data comple~ent line 735. In Fig. 4, Fig. 5, and Fig. 6 the si~e of the resistors in ohms is shown under the 25 identification lab-l.

INPUT CONTROL CI~CUIT
The ~rite data complement line 735 is one of the input lines to input control circuit 801 in Fig. 3. The schematic `~
for input control circuit 801 is illustrated in Fig. 9.
30 During nor~al operation, input control circuit 801 deterd nes the output signals on the serial data-in line 737 to ~hift register ao2 ~Fig. 10).
If the ~ignal on write gate line 704 is high, the input - 29 - 132~

control circuit in~erts the signals on wri~e data complement line 735 and provides the resulting signals to the serial data-in line 737. The SMD/SCSI complement line 725 and the SCSI serial data line 735 to the input control circuit 801 5 are used in the back-up operation of the disk emulator and so during normal operation of the disk emulator, the signal on line 736 is low, and the signal on line 725 is high. If the signal on write gate line 704 is low, the input control circuit generates a low signal on serial data-in line 737 10 irrespective of the signal level on write data complement line 735.

SHIFT REGISTER
Shift register 802 in Fig. 3 is a 66-bit shift register which performs the serialiser/deserialiser functions ``
15 described previously. Shift register 802 i~ comprised of eight 7~299 integrated circuits 1104-1111 and a 74194 integrated circuit 1121, as ~hown in Fig. 10. The 74299 integrated circuit (IC) i9 an eight-bit register having multiplexed parallel input/output terminals. Signals on the ~`
20 two function-select input terminals S0, Sl and two output-control input ter~inal~ G0, Gl of the 74299 IC determine the ode of operation of each register in the integrated circuit. The 7~19~ integrated circuit 1121 is a 4 bit bidirectional shift regi~ter~ Since integrated circuit 1121 25 does not have controlled parallel input/output terminals, the three state buffers 297, 298 in Fig. 10 are connected to the output terd nals QA and QB, respectively, of integrated circuit 1121.
In the write mode, when the shi~t register 802 functions 30 as a deserialiser, data are supplied to shift register 802 over serial data-in line 737 and the data are shifted through shift register 802 by clock pulses on shift register clock line 739 which i9 connected to each of the terminals CLR of integrated circuits 1104-1111, 1121 and to the output ~ 30 ~ 132~`1`1 terminal Y3 of multiplexer 1125. With the exception described below, as the data move through shift register 802, the data are simultaneously available on parallel bus 700. Accordingly, when a full 66-bit word is in shift 5 register 802, the 66-bit word is available to the other circuits in Fig. 3 which are on 66-bit parallel bus 700.
~owever, during the time inter~al when data are being -written into DRA~ array 822, a high signal on the shift register output control line 740 from multiplexer 1125 to 10 the terminals Gl, ~ of the integrated circuits 1104-1111 and the inverters on the control terminal of the three-s~ate .
buffers 297, 298 tri-states the parallel output terminals in `
the integrated circuits, and so during this time the signals in the register~ of shift register 802 are not on 66-bit 15 parallel bu~ ~00. While the parallel output terminals of shift register 802 are tri-state, da~a are still being ~hifted through shift register 802 on a serial data path.
In the read mode, when shift register 802 function-~ as a Qeriali~er a high signal on Sl line 741 from read counter ~o circuit 810 (shown in Fig~. 3 and 18) is applied to terminal~ Sl of integrated circuits 1104-1111, 1121. This hiqh ~ignal enables the parallel input terminals of shift regi~ter aO2 and consequently signals on parallel bus 700 are simultaneously parallel loaded into shift register 25 802. The 66-bit word i~ then shifted through the shift reg~ter onto serial data output line 738 by the clock pulses on shift register clock line 739. The sequence ànd generation of the control signals to shift register 802 are described in ore detail below.
The shift regi~ter 802 is cleared when the signal on sector/index complement line 711, which is connected to each terminal CLR of the IC's 1104-1111, 1121, goes low.

- 31 - ~321 LAT~H CIRCUI~
In writing to the disk emulator, the SMD disk controller provides data to shift register 802 at extremely high speeds since the disk emulator is desi~ned to operate at a clock 5 frequency of up to ~0 Megahert~. If the disk emulator operates at a speed of 25 ~egaherts, a 66-bit word exists on shift register 802 for only forty nanoseconds, and it is extremely difficult to write a 66-bit word from shift register 802 into ~RAM array 822 in this time frame. Thus, 10 at the precise moment a 66-bit word exists in shift register 802, latch clock/error detection circuit 805 (~ig. 3 and Fig. 31~ generates a clock pulse on latch clock line 743 which is connected to the terminal CP of each of integrated circuits 1112-1120 comprising latch circuit 803, shown in 15 ~ig. 11. This clock pulse captures in latch circuit 803 the 66-bit word from shift regi~ter 802 on parallel bus 700.
The latched 66-bit word is available to be written to DRAM
array 822, while the next word is filling shift register 802. ~ence, rather than requiring a write operation to the 20 DRAN array 822 in 40 nano~econds, the write simply must be performed within 2.6 microseconds.
After the data are latched in circuit 803, a ~ignal on 8hift register output control line 740, described above, from multiplexer 1125 tristates buffer 296 in Fig. 11 and 25 the parallel output terminals of shift register 802 which -`
are connected to parallel bu8 700. Simultaneously, a low signal i8 provided on latch output enable line 742, which is conneoted to terminal ~ of each integrated circuit 1112-1120 and to the output terminal Y4 of multiplexer 30 1125. Thus, the low signal on line 742 enables the output terminals of integrated circuits 1112-1120 and consequently provides the 66-bit word stored in the latches of latch circuit 802 to 66-bit parallel bus 700, because each line Dll)-D(66) of parallel bus 700 is connected to an output 35 terminal of one of the latches in integrated circuits .
''' -32- 1 32~

1112-1120, as shown in Fig. 11. At this time, the 66-bit word is also provided to parity circuit 804 (Fig. 3 and Fig.
12) and consequently parity circuit 804 generates a parity bit for the 66-bit word stored in circuit 803 on parity bit 5 line 744.
In the read mode, the word on 66-bit parallel bus 700 and the parity bit on line D(0), both from the DRAM array 822, are latched in latch circuit 803 by a clock pulse on latch clock line 743 from latch clock/error detection 10 circuit 805. When shift register 802 is ready to receive a new word, the signal on latch output enable line 722 to latch circuit 803 is low and the signal on Sl line 741, which connects each input terminal Sl of each of the integrated circuits 1104-1111, 1121 in shift register 802 to 15 the read counter circuit 810, goes high. Since the signal on input terminal S0 of each of the ICs 1104-1111, 1121 i9 high during normal operation of the disk emulator, the parallel input terminals of the ~hift register which are connected to 66-bit parallel bus 700 are enabled. Thus, the 20 66-bit word stored in latch circuit 803 i~ loaded into shift `
register 802 over 66-bit parallel bus 700. Prior to the parallel transfer of the ~6-bit word from latch circuit 803 to s~ift register 802, the 66-bit word is error corrected, a~ de~cribed below. The gener~tion and sequence of the 25 control signals to latch circuit 803 are also explained more fully below.
Since latch circuit 803 latches inverted data, the input ``
terminal of each register in latch circuit 803 is tied to the output terminal of the register. Then, after a word is 30 latched in latch circuit 803, a second clock pulse is applied to latch circuit 803 on latch clock line 743 while latch circuit 803 is in the enabled state. The second clock pulse causes latch circuit 803 to latch on the inverted data. The result is that latch circuit 803 ncw contains the 35 original word rather than the inverted word. This is true ~
: ,` . ' - 33 - 132~4~

in both the read and write modes.
As shown in Fig. 11, the latch circuit is comprised of nine 75534 integrated circuits 1112-1120. A 74534 integrated circuit is an eight bit edge triggered i~verting 5 register having the output line of ea~h re~ister coupled to a three-state output buffer. Accordingly, each of the latches referred to previously is a register in one of the integrated circuits 1112-1120.

PARITY CIRCUIT
The parity circuit 804 in ~ig. 3 and Fig. 12 is also on 66-bit parallel bus 700~ In the write mode, a~ previously described, after a 66-bit word is latched and inverted in latch circuit 803, the parallel-output terminals of shift ` ~-regi~ter 802 are tristated and the output terminals of latch 1~ circuit 803 are enabled. The inverted word is again inverted 80 a~ to obtain the original word in latch circuit 803. Consequently, the original 66-bit word stored in latch circuit 803 i8 on parallel bus line 700 and therefore the 66-bit word is input to the parity generation circuit 804.
20 T~e parity generation circuit provide~ an even parity signal on parity bit line 74~ to latch circuit ao3 which in turn passes the parity bit to DRAM array 822 over line DlO). The generation of the parity bit using the word in latch circuit 803 is one of the Eeatures of the disk emulator which 25 enable~ the disk emulator to work at clock frequencies as high as 50 M~.
In the read mode, the output Eunction of the parallel `
input/output terminals in shift register 802 are tri-state. ~hus, the 66-bit word on parallel bus 700 from DRAM
30 array 822 i8 only avai~able to latch circuit 803 and parity circuit 804. When latch circuit 803 captures the 66-bit word and the stored parity bit from DRAM array 822, parity circuit 80- provides a new parity bit on parity bit line `~
744, which corresponds to the parity of the word retrieved -~
:- :' ' ` ` ` ' - 34 - 1 3 2 ~

from DRAM array 822. The new parity bit is provided only to the first input terminal of Exclusive OR gate 302.
The stored parity bit from the DRAM array is provided to the second terminal of Exclusive OR gate 302 on line D10).
5 Thus, if the output signal from Exclusive OR gate ~02 is high, an error occurred while the word was stored, after storage, or during read in DRAM array 822 of the disk emulator and the error correction method, described below, corrects the error.
The parity circuit 804 in Fig. 3 is comprlsed of ten 74280 integrated circuits 109~-1103 which are interconnected -with each other and the parallel bus 700 a~ shown in Fig. 12.

MULTIPLEXER
lS ~he ~ultiple~er 1125 in Fig. 3 and Fig. 13 selects control ~ignals ~hich are applied to shift register 802 and latch circuit 803. ~ultiplexer 112S has two sets of input line~. The fir~t set of input lines, described below, provides read control ~ignals to shift regiQter 802 and 20 l~tch circuit 803 while the second set of input lines, also de-cribed belo~, provides write control signal~.
When the signal on writing line 709, which connects ~riting flag circuit 811 ~Fig. 3 and Fig. 24) to the input ter~inal ~7~ of multiplexer 1125 (Fig. ~ and Fig. 13) is 25 low, the first ~et of input line8 is coupled to the output terminals of multiplexer 1125. The signal on read B
cooplemene line 746 from latch clock/error detection circuit ``
805 (Fig. 3 and Fig. 31) is applied to the first output ter-inal of ~ultiplexer 1125; the positive supply voltage on 30 line 749 i8 applied to the second output terminal of ~ultipleYer 1125; the signal on clock zero line 728 is applied to the third output terminal of multiplexer 1125 and ` ~
the signal on read B line 745 from latch clock/error ~ ;
detection circuit 805 is applied to the fourth output ~ -,,,, . "' ', 132~4~

terminal of multiplexer 1125.
If the signal on writing line 709 is high, the second set of input lines is coupled to the output terminals. That is, the positive supply voltage on line 749, the signal on 5 write B line 747 from write B circuit 814 (Fig. 3 and Fig. 39~, the signal on write clock line 750, and the signal on write B complement line 748 from write B circuit 814 are applied to output terminals Yl to Y4 of multiplexer 1125, respectively.
The multiplexer 1125, as shown in ~ig. 13, is a 74157 integrated circuit~ The 7~157 integrated circuit is a ~uad two input multiplexer which selects four bits of data from two sources under the control of the signal on the input terminal ~7~.
The shift register ao2, parity circuit 804, and latch circuit ao8 ~re utilized both in reading data from DRAM
array 822 and in writing data to DRAM array 822. Thus, the~e circuit~ perfor~ a dual function and their mode of operation i8 determined by the additional circui~ry shown in 20 Fi~. 3. Utili~ing shift regi~ter 802, parity circuit 804 and l~tch circuit 803 for both read ~nd write operations min~m~zes the number of components in the disk emulator ~hich reduce~ both the cost and the size of the circuitry.

CO~PARATOR CIRCUIT
In the write operation, all the data which comes from the SND disk controller is not ~tored in DRAM array 822.
Only the address Eield and the data field of each sector, as ~ho~n in Fig. 1, are unique. Therefore, the disk emulator of this invention is desi~ned to strip away the nonsector-30 ~pecific dat~ fro~ the data provided by the SMD di~kcontroller and to store in the disk emulator's DRAM array 822 only the data which are sector specific. This approach al~o reduce~ the cost and size of the disk emulator, because the si~e of DRAM array 822 is reduced. However, more impor-13244~
` - 36 -.

tantly, as explained later, this approach significantly enhances the utilization of the storage medium in comparison to the utilization of the storage medium of a conventional hard disk drive.
The 64 sixty-six bit words stored by the disk emulator as a sector comprise a zeroth word which is the address field for the sector and the first word through the sixty-third word which comprise the data field of the sector. Accordingly, to capture only sector specific data 10 in the write mode, a mean~ is needed to ascer~ain when the address field is in shift register 802 and when each of the firse word through sixty-third words, comprising the data field, are in shift reqister 802, or, in terms of the pre~ious deqcription, the first clock ~ignal to the latch 15 circuit 803 on latch clock line 7~3 must be generated when ;~
the addre~ field is in the shift regiater and another clock " `
~ignal on latch clock line 743 must be ~enerated as each word of the data field fills shift register 802.
After the first word of the data field is detected, the 20 S~D dis~ controller provides a continuous stream of data so that a counter circuit which accumulated the number of clock pulses to shift register 802 and generated a clock signal to latch circuit 803 for each 66-bit word would capture the remaining words in the sector. Also, by counting the number 25 of clock pulse~ to latch circuit 803, the end of the sector ~`
can be determined. Comparator circuit 815, write control circuit 806, and memory word counter circuit 807 in Fig. 3 implement this conceptual approach.
The detection of the address field, the zeroth word of 30 the sector, and the first word of the data field is facilitated by the SMD interface convention. As shown in Pig. 1, the address field 13 and the data field 17 are each proceeded by a one byte sync pattern 13a, 16. The sync pattern~ 13a, 16 are usually the same, but in some embodi-35 ments of the SMD interface convention they are different.

~','`,''`,:'' 132~

Therefore, comparator circuit 815 has two comparators. The first comparator is programmed to detect the sync pattern in the address field on the 66-bit parallel bus 700 and the second comparator is programmed to detect the sync pattern 5 in front of the data field 17.
The comparator circuit 815 is comprised of two 74F521 integrated circuits 1122, 1123 and two eight poæition DIP
switches 291, 292, as shown in Fig. 14. The 74F521 integrated circuit is an eight bit identity comparator. To `
10 program the comparators, the lines D(10)-D(3) of 66-bit parallel bus 700 are connected to the input terminals P0-P7 respectively of comparator integrated circuit 1123 and to the input terminals P0-P7 respectively of comparator integrated circuit 1122. Notice that for lines D~3~-D~10~, 15 the number of the line does correspond to the bit of the word and in face, line D(3) carries the signal corresponding to the tenth bit of the word while line D(10) carries the signal corresponding to the third bi~ of the word.
Each of the input terminals Q0-Q7 of the comparator 20 ~ntegrated circuit 1123 i8 connected to the positive supply voltage throug~ a resistor in resistor package 294 and to ground throug~ one of the switches in the eighth position dip switch 291~ Similarly, the terminals Q0-Q7 o$
integrated circuit 1122 are connected to the positive supply 25 volt~ge through a resistor in resiator package 293 and to ground through one of the switches in the eight position dip ~itch 292. ~y openinq and closing the appropriate switches in the eight position dip switches prior to using the disk e~ulator, the signals on the terminals Q0-Q7 of comparators 30 1122, 1123 may be set 80 that the comparators will detect any 8 bit aync pattern used in implementation of the SMD
interface convention.
~ hen the comparator circuit 815 detects the programmed address sync pattern (block 13a in Fig. 1), a low signal is 35 generated on the addre8s sync detection complement line 752 . . .

132~

to write control circuit 806. Similarly, when tbe data sync pattern 116) is detected, a low signal is generated on the data sync detection complement line 753 to write control circuit 806 (Fig. 3 and Fig. 15).
To pre~ent spurious signals on line~ 752, 753 due to data patterns that look like sync patterns, memory word counter circuit 807 (Fig. 3 and Fig. l9) generates a signal on address zero detection complement line 754 which disables the address sync comparator except when the comparator is lO needed to detect the address sync pattern. Memory word counter 807 also generates a signal on address one detection `~
complement line ~55 which disables the data sync comparator except when the comparator i8 needed to detect tbe data sync `
pattern. The generation and timing of the8e signals are 15 discusQed more completely below.

WRITE CONTROL CIRCUIT :
~he ne~t clock pulse on the write clock line 750 after detection of the programmed addre~s sync pattern by coaparator circuit 815 shifts the one additional bit through 20 ~hift regiater 802 and in combination with the low signal on address sync detection complement line 752 enables write control circuit 806. The second clock pul~e on write clock line 750 after detection of the programmed address sync pattern shifts the data a 8econd additional bit through 25 8hift regi8ter 802 and write control circuit 806 generates a ~ ``
signal on load write latch line 717 to latch clock/error ~`
detection circuit 805. AQ will be de~cribed later, latch clock/error detection circuit 805 generates a clock pulse on latch clock line 7~3 when the ~ignal on load write latch 30 line 71~ i8 received. Hence, two clock pul~es after the detection of the address sync pattern the 66-bit word in shift register 802 i~ loaded into latch circuit 803.
The timing ~equence between the detection of the Qync pattern by co~parator circuit 815 and the generation of the ' " ` ' .... ..

- 39 - 1 3 2 ~

latch clock pulse dictates the location of the comparator circuit 815 on 66-bit parallel bus 700. If the number of clock pulses between the detection of the sync pattern and the generation of a clock pulse on latch clock line 753 is 5 n, then the comparators must be loca~ed at positions n~l through n+8 on the 66-b;t parallel bus 700 where the first poQition on the 66-bit parallel bus 700 is the most significant bit of the word and n=l.
After the write control circuit 806 (Fi~. 3 and Fig. 15 10 generates a signal on load write latch line 717, write control circuit 806 subsequently generates a high signal on the write line 716 to write B circuit 814 (Fi~. 3 and Fig. 39). The write B circuit 814 then generates signals on the write B line 747 and write B complement line ?48 to 15 aultipleYer 1125 ~Fig. 3 and Fig. 13), described previously. The low signal on write B complemen~ line 748 is al~o applied to input terminal WRB of the 8207 DRAM
controller~ 820 (Fig. 3 and Fig. 25) which in turn enables the area in the DRAM array 822 where the word from latch 20 circuit 803 and the associated parity bit on parallel bu~
700 ~re to be written.
After write control circuit 806 generates the signals whlch latch and write the fir~t word in the data field to the DRAM arr~y 822, write control circuit 806 generates a 25 8ign~1 on write counter clock line 715 to the first input ter~in~l of NAND gate ~06 ~Fig. 3). NAND gate 406 qenerates a ~ign~l which increments the counter in memory word counter circuit 807 (~ig. 3 and Fig. 19). Write control circuit 806 (Fig. 3 and Fig. 15) continues to generate a signal on load 30 write latch line 717, write line 716, and write counter line 715 for each 66-bit word of the data field.
~ emory word counter circuit 807 supplies a signal on word ~ddress 2-63 complement line 756 to write control circuit 806 which enable~ write control circuit ~06 to count 35 the second through sixty-third words of the data field.

, . ,. ,; . . , , , . ,~, , . . , , !,~ . . ' ~ , `

- 40 - 132~

When the signal corresponding to the sixty-third and last word of the data field is generated by write control circuit 806 on write counter clock line 715, memory word counter circuit 807 generates a sector full signal which is applied 5 to write control circuit 806 on sector full line 757. The signal on sector full line ?5? disables write control circuit 806.
The counter in write control circuit 806 is a sixty-six bit counter comprised of 74F161A integrated circuits 1027, `~
10 1028 as shown in Fig. 15. The 74F161A integrated circui~ is a synchronous four bit binary counter. The clear function for four bit binary counters 1027, 1028 is asynchronous and clears all four of the flip-flops in the counter to a low signal irrespective of the clock, load or enable input 15 signals.
The coun~ers 102~, 1028 are programmed to count sixty-six clock pulses on write clock line 750 and then roll over. The input terminal~ A, B, C, D of integrated circuit 1027 and input terminals A, ~ of integrated circuit 1028 are `
20 connected to ground. T~e input terminals C, D of integrated circuit 1028 are connected to the poQitive Qupply voltage.
T~e counterQ 1027, 1028 are casc~ded so that when the ripple carry output terminal of counter 1027 is high, counter 1023 i8 en~bled. A low signal on terminal LD of counter~ 1027, `
25 1028 disables the counters and on the next clock pulse on the write clock line 750 to terminal CLK of counters 1027, ~`
1028 the counter_ are loaded with the signals on their input terminals, irrespective of the signals on the terminals ENT, ENP. Thus, counters 1027, lQ28 comprise a counter that is 30 proqrammed to count sixty-six clock pulses on write clock line 750. "~

WRITING FLAG CIRCUIT
The writing flag circuit 811, illustrated in Fig. 3 and Fiq. 24, provideQ a high signal to the write control circuit `

132~

806 on writing complement line 710 which inhibits the operation of write control circuit 806 when the signal on write gate line 704 from R/W gate circuit 812 (Fig. 3 and Fig. 33) is low. Conversely, when the signal on write gate 5 line 704 is high, writing flag circuit 811 generates a low signal on writing complement line 710. The writing flag circuit also generates signals on writing line 709, which control multiplexer 1125, as previously described, and which inhibit operation of read counter 810 IFig. 3 and Fig. 18~
10 when data are written to the disk emulator. The signal on writing line 709 from writing flag circui~ ~11 also is used in latch clock~error detection circuit 805 (Fig. 3 and Fig. 31), a8 will be described more completely below, ~o gener~te the read control signals.

15 R~N GAT~ CIRCUIT
R~N gate circuit 812, illustrated in Fig. 3 and ~ig. 33, is coupled to writing flag circuit 811 by write gate line ~04 and also to input control circuit 801 ~Fig. 3 and ~ig. 9) by write gate line 704. Read/write gate line 705 20 couples R~N gate circuit 81S and microprocessor 816. The t~g-3 co~ple~ent line, bit-0 line and bit-l line from receivers connected to the SMD control cable are input lines to R/W gate circuit 812.
Nhen the SMD disk controller wants to write to the disk 25 emulator, the bit-0 line and the tag-3 line are used to assert the write gate, while for reading the bit-l line and th tag-3 line are used to assert the read gate. R/W gate circuit 812 generates the read gate, write gate and read/write gate signals based upon the signals received from 30 the 5~D di~k controller on the bit-0, bit-l and tag-3 lines.

READ CONTROL CIRCUIT
The read operation of the disk emulator is implemented u~ing the read control circuit (comprised of the first gap - 42 - 132~

counter 808, the second gap counter 809, and the read counter 810), latch clock/error detection circuit 805, and memory word counter circuit 807 in conjunction with micro-processor 816, DRAM array 822, shift register 802, latch 5 circuit 803 and parity circuit 804 (Fig. 3). To read from the disk emulator, the word is retrieved from DRAM array 822, placed in latch circuit 803, error corrected, and then ;
loaded into shift register 802 where the word is shifted out onto serial data output line ~38.
However, as described above, the entire sector is not stored in DRAN array 822 but rather, only the address field is stored as the 2eroth word of the sector and the data field is stored as the words one through sixty-three of the ~ector. Accordingly, since the S~D controller expects to 15 see the entire sector, as shown in Fig. 1, the disk emulator ~UQt recreate the information which was stripped away in the write operation, i~e., the first gap between the start of the sector and the address field and the second gap between :
the addre~ field and the data field. Thi~ is the first 20 function of the read control circuit. Read counter circuit 810 IFig. 3) clocks a series of sero bit~ to AND gate 593 (Fig. 3) over output zero complement line 730. The precise nu~ber of ~eros to be clocked is determined by first gap counter 808 and second gap counter 809.

25 P'IRST AND SEC~OND GAP COUNTER CIRCUITS `.
First gap counter 808 (~ig. 3 and Fig. 16) i~ comprised of counters 1013, 1014, which are 74Fl91 integrated circuits, and the six-position dip switch S2 as shown in ~ig. 16. The 74F191 integrated circuit iQ a synchronous 30 rever8ible up/do~n counter having four master-slave flip-flop~ that are triggered on a low-to-high tran~ition of the clock signal on the clock input terminal CLK if the enable input terminal G i~ held low. A high signal at the enable input terminal ~ inhibits counting. The counter~ are _ 43 _ 1 3 2 4 ~ 14 programmed by placing a low signal on the load input terminal LD and entering the desired data on the counter's input terminals. As shown in Fig. 16, the counters 1013, 1014 are cascaded, i.e., the output terminal RC0 of counter 5 1013 is tied to the enable terminal G of counter 1014 to permit a greater count capability.
To u~ilize the programma~le capability of counters 1013, 101~, the input terminals A, B, C, D of counter 1013 and the input terminals A, B of counter 1014 are connected to the 10 positive power supply voltage through a resistor and also to ground through a switch in the six-position dip switch S2.
The input terminals C, ~ of counter 1014 are connected to ground. The switcheæ in the six-position dip switch are open and closed to program the signals on the input 15 terminals of the counters so that after the counters are loaded, the counters count the number of bytes prior to the address field in the sector. Hence, the gap size is programmable.
T~e counter terminal D~U of counter~ 1013, 1014 is 20 connected eo the positive power ~upply voltage so that the gap counter-~ count down and roll over when the programmed nu~ber o~ bytes is reached. The second gap counter 809 ~Fig. 3 ~nd Fig. 16) is comprised of counters 1011, 1012 which are al80 7-F191 integrated circuits, and the input 25 ter~in~l8 of the counters are connected to ground and to the positive power supply voltage in a manner identical to that described for first gap counter 808.

aYTE CLOCX CI~CUlT
Bot~ fir~t gap counter 808 and second gap counter 809 are clocked by byte clock circuit 813 ~Fig. 3 and Fig. 17). The byte clock circuit is comprised of a 74Fl91 integrated circuit which has a byte clock output line 785 tied to its output terminal QC and is clocked by the clock pulses on clock zero line 728, as shown in Fig. 17. Thus, ~ , . .

_ 44 _ 1324~

the first clock pulse on byte clock line 785 occurs after eight clock pulses on clock zero line 728 and subsequent clock pulses on byte clock line 785 occur after every additional eight clock pulses on clock zero line 728.
The use of the byte clock and the programmable cascaded counters in the first gap counter 808 and the second gap counter 809 provides the maximum degree o~ flexibility in -settinq the gap size with a minimum number of components~
Since the number of bytes in the first and second gaps may 10 be dif~erent ~or different implementations of the SMD
interface convention, these circuits allow the user to easily modify the sise of the gaps so that the disk emulator is compatible with the version of the SMD interface on the user's computer. ``

15 READ QOVNTER CIRC~T
When first gap counter 808 counts down to zero from the nuaber of preset bytes, the counter generates a signal on line 722 to read counter B10 ~Fig. 3 and Flg. 18). This signal from first gap counter 808 causes the read counter 20 810 to cease the generation of zero signals on output sero co~plement line 730 to AND gate 593 and to simultaneously generate a signal on Sl line, i.e., line 741, to shift r~gister 802 which loads the word stored in latch circuit 803 into shift register 802. Also, a counter is started in 25 read counter circuit 810 (Fig. 3) which is ~sed to determine ~hen the 66-bit ~ord is shifted out of shift register 802.
While the word is being shifted out, read counter 810 `
generate~ a read signal on read line 733 to latch clock/error detection circuit 805 (Fig. 3 and Fig. 31) which `
30 caugeJ circuit 805 to provide a hiqh signal on read B line 745 to multiplexer 1125 and a low signal on read B
complement line 746 to multiplexer 1125 (Fig. 3 and Pig. 13). The low signal on read B complement 746 is also transmitted to 8207 DRAM controller 820 and the DRAM
'' '~:

13244~

controller 820 provides the next 66-bit word and the associated parity bit to a 67-bit parallel bus, i.e., 66-bit parallel bus 700 and line D(0) (Fig. 3). The 8207 DRAM
controller 820 also provides a signal to latch clock/error 5 detection circuit 805 which captures the word on the 66-bit parallel bus 700 in latch circuit 803. After this, the counter in read counter circu;t 810 generates another signal to the latch clock/error detection circuit 805 over read counter TC line 781 which inverts the word captured in latch 10 circuit 803, so that the word i`s in a normal mode. Read counter circuit 810 also generates a signal on read counter -line 732 to NAND gate ~06 (Fig. 3)~ The resulting output s;gnal from NAND gate 406 increments memory word counter circuit 807.
After t~e seroth word is shifted out of shift register 802, read counter circuit 810 again generates a serieQ of ~ero bit~ on the output sero complement line 730 until the second gap counter 809 lFi9~ 3) rolls over and generates a signal on second gap counter carry line 721 to read counter 20 810. The response of read counter 810 to the signal on line 721 is similar to the response deQcribed when the firqt gap counter 808 rolled over.
In fact, the read counter circuit 810 generàtes the same sequence of signal~ until memory word counter 807 determines 25 that t~e 6~ words (addres~ word plus sixty-three data words) comprisinq the sector have been read and generates a sector full signal on line 758 to read counter circuit 810 which disable~ re~d counter 810. During a write operation, when the read counter control circuit i8 not needed, the low 30 signal on writing line 709 from writing flag circuit 811 is used to inhibit read counter circuit 810.
The counter in read counter 810 i~ comprised of two 7~F163A integrated circuits 1022, 1023 as shown in Fig. 18 and the counter in memory word counter 807 is similarly 35 comprised of two 74F163A integrated circuits 1054, 1055 as - 46 - 132~

shown in Fig. 19. The 74F163A integrated circuit is identical to the 74F161A integrated circuit of write control circuit 806 described previously, except the clear function of the 74F163A inteqrated circuit is synchronous. ~ence, 5 counters 1022, 1023 and counters 1054, 1055 are both coupled and programmed in the same manner as previously described for counters 1027, 1028 in write control circuit 806. `

ADDRESSING TaE DRAM ARRAY
The previous description of the disk emulator explained lo in ~eneral terms how a word is passed between latch circuit 803, Qhift register 802 and the SMD disk controller. However, the disk emulator must locate and address the sector of the track requested by the SND disk controller. This is accompliQhed throug~ ROM tranQlation circuit 819, memory word 15 counter circuit 807 and microproces~or 816 in conjunction with 8207 DRAM controller 820 and DRAM array 822 (Fig. 3).
~ he SND disk controller is designed to interface with rotating data storage systems. The SMD disk controller addre~ses data only in terms of head, sector, track, and ~`
20 cylinder. Disk driveQ, unlike solid Qtate memory, address data ~e ory with this geometric structure. Solid state ~c~ory, i.e., the DRAM array of this invention, requires contiguous binary addresse~
~hen the S~D controller accesses a disk, the desired 25 head and trac~ data are usually provided as digital data.
Di~k controllers rarely provide contiguous binary addre8se~. Therefore, to interface the disk emulator with the SMD disk controller, the disk address information, the he~d and track data, provided by the SMD controller must be 30 translated into a binary structure suitable for addressing a solid seate memory.
Two different means are available for translating the geometrical form of the address information to the binary structure suitable for addressing _olid state memory. In '` `'',', ' - 47 - 1324~

the first method the portion of the computer operating system which interfaces with the disk emulator, i.e., the SMD disk controller, is modified. The modifications are made in the software disk driver that controls the disk 5 emulator. In this method, the software disk driver is configured so that the driven disk has a binary number of heads, sectors, and cylinders. Thus, the information presented by the disk controller to the disk emulator describes contiguous binary addresses. Accordingly, in this 10 method since the diQk controller has been modified to generate a contiguous binary sddresses, these addresses are simply used by the disk emulator to addresQ the Qolid state m~ory. ~ence, in this embodiment, ROM translator circuit 819 Inot shown) i8 comprised of latches which capture the 15 addresses provided by the SMD disk controller.
In a second method, RQM translation circuit 819 ~Fig. 3 and Figs. 22a and 22b) converts the disk related track and head information from the SMD disk controller into higher order address bits for DRAM array 822. A computer 20 ~lgorithm, shown in Figs. 47a to 47c, was used to develop the translation table which resides in a 256K x 8 ROM. The ROM translate~ the consecutive geometric addresses from the S~D disk controller to contiguou~ binary addresses which are U8ed to addre~s the DRAM array 822.
~ence, unlike an ordinary hard disk, where the head iteratively cros~è~ the disk to the desired track and waits for the aesired sector~ the disk emulator, using either the modi~ied disk controller or the translation table, instantaneously creates the effec~ of the head tracking 30 across the disk. Nhen the SMD disk controller issues a seek com~and~ the positioning within the disk emulator occurs vlrtually instantaneously.
The elimination of the seek time, associated with locating the track _pecified by the SMD controller i9 a 35 significant advantage of the disk emulator. On a conven-.....
..
....

1324~

tional dis~, the data sought by the SMD disk controller may be located on several tracks in different areas of the disk. Hence, the track location delay, the ~eek time, is imposed multiple times in locatin~ the data, but with the 5 disk emulator there is no delay time and hence the disk emulator is significantly faster than a conventional hard disk drive.

ROH TRANSLATION CIRCUI~
The head and track information is provided by the SMD
10 controller over the SMD control cable. ~he disk emulator uses a receiver for each pair of lines in the SMD control cable, as shown in Fig. ~, Fig. 5 and Fig. 6, which converts the differential signal on each pair oE lines to a logic signal which ~s processed by the disk emulator. ~he ~ignals ;
15 fro~ the receivers are translated in ROM translation circuit 819 and the addresseQ generated are latched in ROM
translation circuit 819. As used herein, higher order addresses mean the addresses for DRAM array 822 which correspond to the head and track address in a conventional 20 ~rd di8k and lower order addresse~ mean the addresses o~ `
DRA~ arr~y a22 which correspond to the sector of the track and the location within the sector.

DRAM CONTROLLERS AND DRAM ARRAY
The output siqn~l, corresponding to the highest order 25 address from ROM tranalation circuit 819, on the card ~elect line 792 enables one of the sixteen DRAM cards comprising the DRAM array 822 (Fig. 3). One DRAM card is illustrated in Figs. 26a and 26b and will be described fully herein-after. ~ach of the sixteen DRAM cards in DRAM array 822 30 interfaces with one of the ~ixteen 8207 DRAM controllers in DRAM controller circuit 820 and each card contain~ four banks of 256K DRAM integrated circuits. In one embodiment, the 8207 DRAM controller is physically located on the DRAM

_ 49 - 1 3 24 ~ A

card so that DRAM controller circuit 820 and DRAM array 822 in ~ig 3 are integrated together and comprise six~een DRAM
cards, with each card having a 820? DRAM controller and four banks of DRAN
Since each bank on a DRAM card stores a 66-bit word and the related parity bit and each bit of the 66-bit word and the related parity bit are stored in a separate DRAM
integrated circuit, each bank contains at least sixty-seven 256R DRAM integrated circuits This configuration on the 10 DRA~ cards limits the probability of a DRAM integrated circuit failure, for example, two bits of the same word are wrong and also provides a DRAM array configuration which functions at high speed Normally, the pre-charge effect of DRAM limits the qpeed ~
15 with which data may be written to or retrieved from DRAM `
~o~ever, in the disk emulator, the words are written consecuti~ely to the banks on a ~RAM card, i e the data is interleaved on a DRAM card Therefore, the pre-charge eEfect does not limit the performance oE DRAM array 822 ~hile the h~ghest order address from ROM translation circuit 819 selects one DRA~ card, the remaining higher ord~r ~ddresses from the ROM tran~lation circuit 81g are ~ppli~d to the higher order address terminals of the 8207 DRA~ controller on each of the sixteen cards However, -~
25 8ince only one of the sixteen cards is enabled, only the 820~ DRA~ controller on the enabled card actually addresses `
a location within DRAM array 822 Accordingly, as used herein, a r-ference to 8207 DRAM controller means the 8207 DRAM controller on the DRAM card which is enabled by the 30 bighest order addre~s frQm ROM translation circuit 819 ~ v-n though ROM translation circuit 819 (Fig 3) identifies the addresses in DRAM array 822 which corresponds to the he~d ~nd track position specified by the SMD disk controller, the sector informstion is not provided by the 35 S~D di~ controller because normally the disk simply .: .

- 50 - 13244~

positions the head over the track and waits for the right sector to move under the head. ~ence, the disk emulator must also generate a lower order address that corresponds to the desired sector within the track.
While the disk emulator is described as having 16 DRAM
cards and 256K DRAM integrated circuits, these characteris- -tics are illustrative and are not intended to limit the scope of the invention. The memory capacity of the disk emulator is determined by the storage capacity of the hard 10 disk drive whic~ the disk emulator is replacing. In view of this disclosure, one skilled in the art, using the principles of this invention, can vary both the size and nu~ber of DRAM integrated circuits on a card and t~e number of DRAM cards to achieve the necessary storage capacity.

15 ~ICROPROC~SSOR AND MEMORY WORD COUNTER
The lowest order addreæses, corresponding to a sector and each of the 67 bit words within a sector, are generated by meeory word counter circuit 807 and microprocessor 816 (Fig. 3). Wben the SND disk controller indicates that a new 20 8eceor of data i8 required by as~erting t~e seek command, the 8ee~ command i8 applied to one of the external interrupt input eer~in~ls of microprocessor circuit 816. The "
interrupt service routing of the microprocessor immediately initiates the rapid sector cycle. In the rapid sector 25 oycle, the ~icroprocessor set8 the sector address to zero on tbe P00 line through P04, lines 786-790 (Fig. 3), and issues an index pulse.
The index pulse initializes the word addres~ for the sector to rero in memory word counter 807 and latches the 30 signals on P00 through P0~ lines in memory word counter clrcuit 807 ~Fig. 3). Memory word counter circuit 807 generates signals on sector address bus 793 and the word address bus 79~ which are connected to the lower order ~ddress ter~inals of 8207 DRAM controller 820. The 8207 - 51 - 132~

DRAM controller 820 addresses the specified area in DRAM
array 822 over DRAM address bus 795 and the zeroth word of the seroth ~ector and the associated parity bit are supplied to 66-bit parallel bus 700 and the line D(0) respectively.
5 The line D(0) and the 66-bi~ parallel bus are a 67-bit parallel bus.
If this location corresponds to the track and sector requested by the SMD disk controller, the SMD disk controller as~erts either the read gate or write gate and 10 the remaining words of the sector are addressed by memory word counter circuit 807 over word address bus 794.
Accordingly, microprocessor circuit 816 polls the signal on read/write g~te line 705 to determine if ei~her gate is asserted within a predetermined ~ime, for example, 10 15 microseconds, after issuing the sector address. The actual length of the predetermined time is explained more completely below. If either gate i8 asserted within the predetermined time, microproces~or 816 immediately leaves the rapid sector cycle.
If the read qate or write gate wa~ not asserted, micro-processor 816 continue~, incrementing the sector address by one on P00 through P0~ lines 786-790, and i~sues a sector pulse. The sector pulae initializeQ memory word counter 807 in ~he s~me manner a8 the index pulse. Again, the 25 microprocessor waits a predetermined time and checks the g~tes.
Each sector pulse resets word counter circuit 807, so that the addresses of the zeroth word of each new sector are ~upplied to 8207 DRAM controller circuit 820 over word 30 addre~ bus 79~. Thus, the zeroth word of each sector is read by the SND disk controller at predetermined intervals until the desired sector is found. If the desired sector is the last one on the track, i.e. the thirty-~econd one, -`
assuming the predetermined time i9 10 ~sec, 320 microseconds ` `
35 (10 ~sec x 32) are required to locate the sector. Compared . .

132~

to the 16 milliseconds of uncertainty with a conventional hard disk drive, the disk emulator is soo times faster than ~he conventional hard disk drive. Accordingly, the latency related to locating the track and sector has been reduced 5 such that compared to conventional hard disk drives, the disk emula~or's latency is effectively zero, i.e., the --response is instantaneous. This represents a significant advance in the performance of disk storage devices.

ERROR CORRECTION
The final problem uniquely sol~ed within the disk emulator concerns data integrity. When the SMD disk controller is writing to the disk emulator, serial data from the controller is converted to parallel data, and before the data i~ written to memory, a parity bit is generated and 15 gtored as the ~7th bit, as previously described.
When the SND controller i~ reading, the process is rever~ed. Data i~ retrieved from memory and a new parity bit generated. The new parity bit is compared with the ~tored parity bit. If they are not the ~ame, then a bit has 20 changed either during storage, after storage or during the read indicating an error has occurred.
Solid state memory errors can be divided into two basic types, hard errors and soft errors. Soft errors are random single bit errors. These errors are not the result of 25 memory chip failure, and are corrected by the SMD disk controller. H~rd errors generally affect many bits within a meoory component. They are the result of catastrophic memory failure.
Error correction systems have long been in existence.
30 Uging a typical prior art error correction system in the disk emulator requires storage of an 8 bit ECC code along with the 66 bit word. A hard or soft error could be corr-cted through a mathematical process operating on the ECC code. However, an 8 bit per word overhead adds ,::

:.. .. ... .. .

- 53 ~ 132~ 4~

significant cost to the disk emulator. Accordingly, a new error detection process is implemented in the disk emulator which corrects hard memory errors using only a parity bit.
The error corr~ction is done during the read operation using a Read/InvertfWrite/Read~lnvert~Write sequence with the 8207 DRAM controller, latch circuit 803 and latch clock/error detection circuit 805 (Fig. 3). An example of the new error - -detection process is illustrated in Table I.
:
TABLE I

Ro~ WORD STORED PM ITY STORED PMITY GENERATED
1. 1111 1 "''' 2. 1011 1 "

3. 1011 1 ~ `
~. 0100 0 5. 0000 6. 0000 o 7. 1111 , For si~plicity of illustration and understanding, in Table I, a four bit word i8 u~ed a~ an example rather than the 66-bit word utili2ed in the di~k emulator. ~owever, the error detection and correction proces~ i~ independent of the word length and ~o a four bit example i~ ~ufficient to `~
de onstrate the process. In addition, the error detection and correction process of our invention i~ not limited to any particular ~ethod of generating the parity bit. For illustrative purpose~, since the disk emulator word length i8 " ~`
an even nunber of bits, an even parity wa~ chosen. The word, shown in Row 1 of Table I, has even parity becau~e the number of bits that are one i8 even and 80 the stored parity bit is ~ 1. ' '`"' To illustrate the operation of our error detection and . ; .
: : .
:. ' -: . .' :~

~ 54 ~ 1324~4~

correction process r we will assume the word in Row 1 isstored and that the second bit in t~e memory permanently fails. Therefore, the stored word is retrieved as 1011 and the stored parity is retrieved as 1, as shown in the second 5 row of I~able I. When the word loll is retrieved, a new parity bit is generated. I~he number of l's in the word is now odd so that the new parity bit is a 0. A comparison of the stored parity bit, a 1, and the new parity bit, a 0, indicates an error. When an error is detected the retrieved 10 word is inverted, as shown in Row 4 of Table I.
The inverted word and the new parity bit are written to memory and retrieved again. Since the second bit location has failed perm~,nently, when the number is read again, i.e., retrieved from memory, the word is `0000' and the parity bit 15 is 0 as shown in Row 6 of Table I. This word and the parity bit are inverted to restore the original word '1111'. ~ence, using only the parity information, the Read/Invert/Write/
Read/Invert~N'rite sequence corrects errors caused by failure of a single bit location in memory.
This error correction proces~ only works for a single bit failure and a ~emory that fails such that the failed bit, upon subsequent writes to the failed bit location, always re ~in8 in the state, either high or low~ to which the bit -`
originally failed. This is, in fact, simply the definition 25 Of a hard error and 80 the novel correction process will correct any single bit hard error.
The single bit failure per word is assured by the unique configuration of the DRAM array, as described previously.
The DRA~ array is designed such that each bit of a word iQ ~`
30 stored in a different DRAM integrated circuit and only a bit of every fourth word i9 stored in the same DRA~, integrated circuit. Thu~, to obtain two bit failures in tbe same word requires the simultaneous independent failure of a bit location in two of the DRAN integrated cir~uits. This 35 configuration of the DRAM array statistically improves the - 55 - 1 3 2 ~ 4~i~

probability of a misread by many thousand. In fact, without the error correction process a memory failure, a single bit hard error, is predicted to occur within 100 hours of operation, but with the error correction process, two 5 independent bit failures in the same word are not predicted until 50,000 hours of operation. Hence, the novel error correction process significantly impro~es the reliability of the disk emulator.

FORMATTING THE DISK EMULA~OR DRAM ARRAY
10To initially prepare the disk emulator for operation with ` `
a computer, a format write operation is utilized. In the format write operation, the address field for each sector is stored as the seroth word of each 64-word sector in DRAM
array 822 of the disk emulator ~ystem. The format write 15 operation configures DRAM array 822 of the disk emulator so that DRA~ array 822 is functionally equivalent to a formatted ` - -~ard disk.
~ owever, as previously explained, the data storage capability of a typical hard disk i~ reduced by up to 19~ by 20 d-ta that mu~t be ~tored on the hard disk to interface the dis~ ~ith the SMD disk controller. In the disk emulator, the 8 ~yte addres~ field i~ stored as one word for each sector, t~e 1 byte data sync pattern i~ stored and the parity bit is stored for each word in the sector, or a total of 138 bits 25 are used to store data required to interface the disk emulator with the SMD disk controller. Since each sector contains siYty-four 66-bit words and 6~ parity bits, only 138/~288 or about ~S of DRAM array 822 is not available for data storage. ~ence, the disk em~lator uses the stora~e 30 medium significantly more efficiently than the typical hard disk. Since the format write operation of the disk emulator is similar to the normal read and write operations of the disk ~mulator, only the normal read and write operation of the disk emulator in responQe to the SMD disk controller are - 56 - 132444~

considered in detail.

SEER COMMAND
During normal operation, in either a read or a write operation the ~MD disk controller first issues a ~eek command 5 to the disk emulator. ~ypically, in a hard disk drive whenever a seek command is issued, the cylinder must be chanqed and so the read/write heads must be mechanically moved to a new location on the disk and then iteratively centered. Since this mechanical operation is slow compared lo to the operatinq speed of the computer, the computer performs other activities during the time the hard disk drive is seeking the proper cylinder. For this reason, the hard disk drive typically sends a seek end signal to the hard disk controller when the proper track is found so that the disk 15 controller can notify th~ computer. aowever, in the disk emulator the time to change cylinders is virtually inst~ntaneous and the on-cylinder command and/or the seek end co~mand could be supplied to the disk controller virtually in~tantaneously. ~owevert the SMD convention requires a 20 ~ini~um ti~e between the time a seek command is issued and the ~eek is ended. Accordingly, this is one of the functions of on-cylinder circuit 8~0 (Fig. 20). The functions of on-cylinder circuit 8~0 are all related to moving the disk drive head off a given track.
During normal operation, the signal on a tag-l complement line 767 is the means for simulating the movement of the disk head off a given track within the disk emulator. The signal on tag-l complement line 767 is driven low by the SMD
controller when the lower order cylinder addresses are about 30 to change, i.e., the 5MD controller is issuing a seek com~and. The signal on a tag-2 complement line 768 is used by the SMD controller to change the head or higher order cylinder addresses, but a signal on tag-2 complement line 768 ig always followed by a signal on tag-l complement line 767 - S7 - 1 3 2 4 4l~

from the SMD controller. Therefore, the signal on tag-l complement line 767 ef~ectively indica~es that the SMD disk controller has issued a seek command under normal operation. The SMD controller asserts the tag-l signal by 5 providing a differential signal on lines J5-~1, J5-1 in the ~MD control cable to a differential current mode receiver 457 (Fig. 5) through a terminating resistor network.
Differential current mode receiver 467 in response to the differential signal on lines J5-31 and J5-1 generates a low 10 signal on tag-l complement line 767.
The low signal on tag-l complement line 767 is applied to a firQt input terminal of NAND gate 449 (Fig. 20) in on-cylinder circuit 840. The second input terminal of NAND
gate 499 is driven by the output signal from OR gate 448 15 which sumL the signal~ on tag-3 complement line 702 (Fig. 5) with the inverse of the signal on bit-6 line 763 (Fig. 5).
In all but special circumQtance~, which are described below, ~ `
the output i~ignal from OR gate 448 ii~ high and so NAND gate 4~9 has a high input signal and a low input signal when the 20 S~D disk controller drives the signal on tag-l complement line ~67 low. In response to these input signalQ, NAND gate 449 generates a pulse with a rising edge which is applied to an input terminal B of a one shot multivibrator 450 (Fig.
20). Since the signal on terminal CLR of multivibrator 450 25 is tied to the positive power supply voltage and multivibr~tor 450 has an input terminal A grounded, ~ultivibrator ~50 generates a high signal on an output `~
terminal ~ and a low output signal on a terminal Q for a time period determined by a re-Qi~tor and a capacitor connected to -~
30 multivibrator 450. The resistor and capacitor are selected 80 that the time required by the SMD convention between the time the seek cQmmsnd is issued, i.e., the time when the -`
slgnal on tag-l complement line 767 goes low, and the time the ~eek is ended, i.e., the signal on seek end line 772 goes 35 hiqh, are separated by the time required by the SMD
.,'',''.

- 58 - 1324~4~

convention.
When the high output signal from NAND gate 499 causes multivibrator 450 to fire and generate a low signal on on-cylinder complement line 771, the low signal on line 771 is 5 applied to a terminal P33 of a 8051 microprocessor 1063 (Fig.
21). Terminal P33 of 8051 microprocessor 1063 is the interrupt 1 input terminal so that the low signal on on-cylinder complement line 771 resets microprocessor 1063 and microprocessor 1063 enters t~e rapid section cycle mode, 10 described below~
The signals on seek end line 772 and on-cylinder complement line 771 are both generated by multivibrator 450 and so the ~eek end signal and the on-cylinder signal are deri~ed from the same souxce. While it iB possible for a 15 seek to end and a disk not to be on the proper cylinder, this would be a fault condition so that the derivation of the two ~ignal~ from the same source is appropriate.
The other -Qignal generated by on-cylinder circuit 840 (Fig. 20) i8 the return-to-sero ~RTZ) signal which i~ used by 20 the di~ controller to bring a disk drive back to the zero cylinder on t~e di~k. Thi~ signal i8 implemented by making the signal on a bie-6 line 763 high and qtrobing the signal on ~ tag-3 cooplement line 702. Thus, the input signals to OR g te -8 are both low and OR gate 448 generates a low 25 output signal on return-to-sero complement line 7?0 and to the second input terminal of NAND gate 449. The low input signal to NAND gate 44g generates a sequence of signals identical to t~ose di~cuased above when the signal on tag-l compleJent line 767 went low.
~ence, in response to the RTZ command, the microprocessor 1063 is initiali~ed. In addition, in ROM translation circuit 819, shown in Fiqs. 22a and 22b, the low signal on RTZ
co ple~ent line 770 clear~ flip-flops 479, 480, 483 and integrated circuits 1038, 1039, 1040, which each contain four 35 edge triggered D-type flip-flops with individual D input ~ 59 ~ 13244~

terminals and both Q and Q-complement output terminals.
Also, the low signal on RTZ complement line 770 drives the output signal from NAND gate 482 high, which in turn clears counters 1042, 1043, 1044, 1045 in Figs. 22a and 22b. The 5 return-to-2ero command, thus, operates similarly to the seek command in that microprocessor 1063 is initialized and in addition, ROM translation circuit 819 is cleared.

HIGH ORDER ADD~E~S GENERAT~ON
The SMD disk controller also provides the desired head 10 and track information over bit-O through bit-9 lines and tag-2 and tag-3 lines in the SMD control cable after the seek command. In a conventional hard disk, the head and track information ~pecified by tbe S~D disk controller i~ compared with the current track po~ition, which is typically read by a "
15 servo ~ead of the hard disk drive, and a new position for the bead i8 determined which is closer to the ~pecified track.
By repeating the proce~s of reading a track, comparing the apecified track witb the current po~ition and moving to a new position, tbe bard disk drive iteratively locates the track 20 8pecified by the SND controller. Obviously, if the data file i~ interleaved over several tracks on the hard disk, the hard disk drive ~ust repeat the search operation for each segment of tbe data. Tbus, in reading a data file comprised of ~ultiple sectors on several tracks, the seek time is 25 cumulative for a hard disk drive~ The disk emulator, as described belou, locates the track ~pecified by the SMD disk controller virtually instantaneously, and consequently eli~inates the seek time of the conventional hard disk drive. ~his feature alone substantially improve~ the perfor-30 mance of the disk emulator over the performance of hard diskdrives designed to operate under the SMD interface convention.
As previously described, the SMD disk controller provides differential signals which specify the desired location for .: .

- 60 - 132~

reading or writing to the disk emulator over the bit-0 through bit-9 lines in the SMD control cable and these signals are enabled with signals on tag-l line and tag-2 line in the SMD control cable ~in the Figures, the bit line and 5 tag lines shown are those of the disk emulator and the lines from the SM~ control cable or SMD data cable with the same name are indicated by the prefixes J4, J5).
AS shown in ~igs. 4, 5, and 6, each pair of lines from the SMD disk controller, which carries one of the bit or tag 10 signals, is coupled through a terminating resistor network to the input terminals of a differential current mode receiver which in responQe to the signals from the SMD disk controller drives the corresponding line in the disk emulator.
Accordingly, bit-0 through bit-9 lines 701, 703, 759-766 `
15 carry the geometric address Qignals from receivers g61-~70. ~ `
As pre~iously described, there are two methods for converting the geometric address information for the disk to contiguou~ binary addreaaes for the DRAM array of the disk e~ulator. The first method requires patching the computer 20 operatinq syste~ ao that the disk controller addreQse~ the di~k e~ulator with a binary format for the number of head~, ~ectors and cylinders. In this method, the information pres~nted acro~ the bit-0 through bit-9 linea which are enabled by signals on tag-l line and tag-2 line describe 25 contiguous binary addresses. Accordingly, the geometric address signal~ from receivers 461 to 470 in thia method are used directly to address the DRAM array as described in more detail below.
In the second method, a ROM baaed lookup table is used to 30 convert the geometrical addreaaes to contiguou~f binary addresses. This method allowa precise emulation of any eYls~lng hard disk drive. In the SMD convention, cylinders ~re 8pecified with 12 bita of information which allows addresslng a maxi~um of 4,096 cylindera. Similarly, the head 35 addres8es are specified with 5 bits for a maximum of 32 - 61 - 1~2~

heads. ~hus, to fully implement the SMD convention, 17 bits of address information ~ust be processed in the disk emulator. However, either the number of heads or the number of cylinders can vary. For example, the DEC model RMO3 disk 5 drive has 32 sectors, 823 cylinders, and S heads for a formatted capacity of 67.~2 megabytes. ~o emulate the DEC
RM03 requires nine DRAH cards, as previously described, in the disk emulator. Purther, only 10 bits are required to specify the 823 cylinders and three bits are required to 10 specify the five head~. Thus, for this particular hard disk drive, the input address signal to RQM translation circuit 819 consists of 13 bits rather than the full 17 bits available in the SND convention. The geometric address provided by t~e SND disk controller is nonbinary as 823 15 cylinder~ are addressed for each of the five heads. To emulate the DæC R~03, 4,115 l5 x 323) high order addresses are necessary. T~erefore, 13 bits of output are necessary from RO~ translation circuit 819.
ROM translation ~ircuit 819 IFigs. 22a and 22b) of the 20 disk e~ulator i~ implemented with a pair ROMs 575,576, for e~a~ple an ~itachi ~N62301P or equivalent, which have 131,072 eight bit addre~sable locations. Each RQM has 17 address input ter~inals ~o that the entire SMD cylinder/head bus is accom~odated, and 8 output terminals as shown in Fig. 22a. ;~
The S~D controller provides the lowest order bits of the 12 bits of cylinder address information on bit-0 through bit-9 lines 701, 703, 7S9-766 (Fig. 22a) and enables the lower order cylinder address bits with a low signal on tag-l ``
co~plement line 767. In the disk emulator, the cylinder 30 addre~s signals on bit-0 through bit-9 lines 701, 703, 759-766 are ~tored in regi~terQ oE integrated circuits 1200, 1201 ~-by the enabling low, signal on tag-l complement line 767.
The S~D controller provides the head addre~s information on bit-0 through bit-4 lines 701, 703, 759-761 and the two 35 hlghest order bits of the cylinder address information on - 62 - 132~4~

bit-7 and bit-8 lines 764, 765, all of which are enabled by a low signal on taq-2 complement line 768. These signals are stored in other registers of integrated circuit 1202. Thus, the registers in integrated circuits 1200, 1201, 1202 latch 5 the entire 17 bits of geometric address information provided by the SMD controller. The output terminals of integrated circuits 1200, 1201, 1202 are eonnected to the input terminals of RaMs 575, 576 so that each ROM simultaneously receives the entire 17 bits of cylinder and head address 10 information.
ROM 5~5 contains a lookup table which is used to convert the 17 bits of SND geometric address information to the seven least significant bits of the binary high order address for DRAM array 822 and ROM 576 contains a lookup table which is 15 used to convert the 17 bits SMD geometric address information to the eight most significant bits of the binary high order addreQ~ for DRAM array 822. The lookup tables, which are stored in ROWs 575, 576, can be generated manually, but in a preferred embodiment a computer proqram, written in the BASIC
20 cooputer language, (Figs~ 47a, 47b, 47c) wa-~ used to generate data that was programmed into ROMs 575, 576. The program (Figs. ~7a, ~7b, ~7c) wa~ executed u~ing an IBM PC with an NS-DOS version 3.2 operating system. More specifically, the interpretive BASIC package of ~S-DOS ver~ion 3.2 was used in 25 t~e IBM PC to execute the BASIC computer program. In Figs. 47a, 47b, ~7c, the numbers at ~he left hand side of each line are the line numbers for tbe program and the re~ainder of each line comprises a BASIC computer program instruction. To use the BASIC computer program, the number 30 of cylinders in the hard di~k drive being replaced with the d$sk emulator of this invention and the number of heads in that disk drive must be supplied. In Fig. 47b, the number of cyl$nders has been entered on line 1900 as 822 and the number of heads has been entered on line 1950 as 5. ~o change the 35 progra~, the user must enter the number of cylinders after - 63 - ~32~4 "C=" on line 1900 and the number of heads after "H=" on line 1950. To run the program, the command "RUN 1900" is given to the computer. The command "RUN 1900" begins program execution. The program then generates the necessary ROM
5 output signals for the various address input signals to ROMs 575, 576 from the SMD disk controller.
A portion of the output listing generated by the BASIC
computer program illustrated in Figs. 47a, 47b, 47c is gi~en in Fig. 48. The program generates pairs of output lines 1300 10 where the first line in each pair is labeled "A~DRESS" and the second line is labeled ~CONTBNTS.'` The ADDRESS line 1301 correspond~ to the geometric address signals on the input : `
terminals of RQNs 575, 576 from the SMD disk controller.
Since the address ~ignals are derived from SMD disk 15 controller, tbey are not binary in nature. Thus, every ~ddress for ROM~ 575, 576 i8 not used. ~he CONTENTS line ~`
represents the binary address for DRAM array 822 correspondi.~g to the gaometric address given in the ADDRESS
line. The first 8 bits 1~02 on the left hand Qide of the `~
20 CONT~WTS line are the output signals for ROM 576 and the second 8 bits 1303 on the right hand side are the output signals for RO~ 575. ~ote that the ROM output signals, as sbown in succe~sive ADDRESS line~, increment in perfect~`
binary. The data generated by using the BASIC computer 25 program must be programmed into ROM~ 575, 576. Means for progrumming the data from the ~ASIC computer program into ROMs 575, 576 are known to those skilled in the art.
The lookup tables programmed into ROMs 575, 576 translate the ~ignal~ from the 5MD disk controller on the input 30 ter~inals of ROMs 575, 576, which correspond to geometric addres~es for a hard disk, into signals on the output terminals of ROMs 575, 576 which correspond to contiguous higher order addresses in DRAM array 822 of the disk emulator. The output signals from ROM 576, which define the 35 higher order bits of the high order addresses, are provided - 64 - 132~4.~4 on the output terminals from ROM 576 to the DRAM bit-7 through DRAM bit-14 lines 857-864. The signals on DRAM bit-9 line 858 through DRAM bit-14 line 864 from translation ROM
576 are passed through a configuration block J9 ~Fig. 22b) to 5 input terminals D0, Dl, D2, D3 of integrated circuit 1038, the input terminal of D-type flip-flop 480, and the input terminal of the D-type flip-flop 479, respectively.
Similarly, configuration block J8 passes the signals on DRAM
bit-5 line througb DRAM bit-8 line 855-858 from ROMs 575, 576 10 to input terminals D0, Dl, D2, D3 of integrated circuit 1039 re~pectively and the signal on DRAM bit-4 line 854 to the input terminal of flip-flop ~83. The signals on DRAM bit-0 line 850 throuqh DRAM bit-3 line 853 from ROM 575 are applied to input terminals D0, Dlt D2, D3 of integrated circuit 1040, "
15 respectively IFigs~ 22a and 22b).
Configuration block~ J7, J8, J9 (~ig. 22b) permit eaQy modiEication of the coupling of the DRAM bit lines in the disk e~ulator to the addressing circuitry of the disk emulator, and consequently provide means for adapting the 20 disk e~ulator to an alternative implementation of the SMD
inter~ce convention~ One embodiment i~ ~hown in Figs. 22a ~nd 22b for t~e output signal~ from ROMs 575, 576 where the le~st ~ignific~nt bit is on DRAM bit-0 line 850 and the most significant bit is on DRAM bit-14 line 864. However, ROMs 25 575, 576 may be programmed ~o that the contiguous binary address appears in a different order on the output pins of RONs 575, 576. In such an embodiment, configuration block~
J7, J8, J9 are used to configure the binary address on the lnput terminals of flip-flops 483, 479 and 480 and integrated 30 circuits 103a, 1039.
The enabling signal, a low signal, on tag-l complement line 767 (Fig. 22b) from receiver 457 (Fig. 5) return_ to a high level and this low to high transition in the _ignal clocks flip_flops 479, 480 and flip-flop_ in integrated 35 circuits 1038, 1039 (Fig. 22b). Thus, the signal on tag-l :.
` : :

- 65 - 132~4~ ~

complement line 767 not only latches the lower order geometric cylinder addresses in integrated circuits 1200, 1201, but also latches the ten most significant bits of the contiquous binary address generated by ROMs 575, 576 in flip-flops 479, 480 and in flip-flops of integrated circuits 1038, 1039. Similarly, the siqnals on DRAM bit-0 line through DRAM
bit-4 line 850-854 are each latched in a flip-flop when the signal on tag-2 complement line 768 goes higb after latching the SMD bead address and the SMD higher order cylinder bits ``
10 in integrated circuit 1202. Hence, the signals on the tag-l complement line 767 and the tag-2 complement line 768 - `
effectively enable the translated signals by latching the signal~ in D-type flip-~lops (Fig. 22b).
The ~ignals stored in the D-type flip-flops from ROMs 15 575, 576 effectively replace the drive mechanism of the hard disk. The latched signals are equivalent to placing the read~write head of a hard disk over the desired track.
Consequently, the mechanical drive mechani~m, the means for deter~ining the position of the mechanical drive mechanism, 20 and the iterative procedure used to locate the desired track in a conventional hard diak are replaced with the ROM
translation circuit which instantaneously defines the contiguous higher order addresses which correspond to the geo etric address information for a typical hard disk 25 drive. The elimination of the drive mechaniQm i3hould enhance `-reliability, in addition to enhancing the response time, over ` `
a conventional hard disk.
In the e~bodiment which modifies the disk controller so that the controller generates binary addresses, ROMs 575, 576 30 and integrated circuits 1200, 1201, 1202 are eliminated from ROM translation circuit 819 (Figs. 22a and 22b), inverters are inserted in tag-l complement line 767 and tag-2 `~`~
complement line 768 (Fig. 22b), and the signals on the bit-0 through bit-9 lines are provided directly to the DRAM bit 35 lines according to the SMD convention. The other elements of ., .

- 66 - 132~

the ROM translation circuit 819 in the embodiment is identical to those shown in Figs. 22a and 22b.
Hence, when the 8051 microprocessor 1063, in Fig. 21, receives the signal on on-cylinder complement line 771 which 5 initiates the rapid sector cycle mode, the head and track information supplied by the SMD control cable have been converted to contiguous higher order binary addresses and latched for further use by the disk emulator.

LONER ORDER ADDRESS GENERATION -- SECTOR ADDRESS
Since the disk emulator has virtually no delay time for po~itioning the head over the track specified by the SMD disk controller, when t~e seek command is received from the SMD
di~k controller, the 8051 microprocessor 1063, in Fig. 21, enters the rapid cycle sector mode and immediately issues an 15 index pulse on an index line ~14, connected to terminal P06 of microproce~sor 1063. ~icroprocessor 1063 simultaneously provideQ on P00, P01, PQ2, P03, P04, lines 786-790, which are connected to terminals P00 to P04 respectively of micropro- ` "
ceissor 1063, t~e addre~ corre~ponding to the zero sector of 20 the track 8peeif~ed by the SMD disk controller. Since the normal convention i-~ that 32 ~ectors define any given ~rack, the 8ignals provided on oueput terminalQ ~00 through P04 of 8051 microprocessor 1063 uniguely de~ine eac~ sector in a track. `

25 INDEX PULS~
The index pul~e on the index line 714 from terminal P06 of microprocessor 1063 (Fig. 21) is pa~sed to sector/index circu~t 817 ~Fig. 23~ and SMD sector/index circuit 818 (Fig. 46). The fallin~ edge of the index signal, which is 30 applied to an input terminal A of monostable multivibrator 45~ (Fig. ~6), fires monostable multivibrator 454 because an ~nput terminal B of multivibrator 454 is connected to the po8~t~ve power supply voltage. Hence, multivibrator 454 - 67 ~ -13 2 4 ~ ~

generates a signal on a SMD index line 773 which is connected to an output terminal Q of multivibrator 454. The high signal on 5MD index line 773 is converted to a differential signal on SMD control cable lines J5-48, J5-18 by 5 differential current mode driver 471 (Fig. 7).
In sector/index circuit 817 tFi9- 23~, the high signal on index line 714 is inverted by NOR ~ate 451 and the low output signal from NQR gate 451 is inverted by inverter 452.
Inverter ~52 drives sector/index line 712 with a high output 10 signal and also drives inverter 453 which in turn generates a low signal on the sectorJindex complement line 711~ The high signal from inverter 452 is also applied to an input terminal A of monostable multivibrator 1070. The input terminal B of multivibrator 1070 is connected to the positive power supply 15 voltage. Hence, on the falling edge of the high signal from inverter ~52 monostable multivibrator 1070 generates a signal which is applied to an input terminal A of a monostable `"
multivibrator 1069 w~ich also has an input terminal B tied to the positive power supply voltage. On the falling edge of 20 the signal from multivibrator 1070, which occurs approYi~ately 1.5 microseconds after initiation of the pulse by ~ultivibrator 1070, monostable multivibrator 1069 generates a high signal with a pulse width of about 0.5-0.7 ~icrosecond~ on a read sero line 72~, which is connec~ed to 25 output terminal Q of monostable multivibrator 1069.
The high ~ignal on read sero line 724 initiates the initial read cycle of the disk emulator for each sector, as described below. Mowever, monostable multivibrators 1069, 1070, which both trip on a falling edge of the signal on 30 input terminal A, delay the initiation of the read cycle so that the signals on sector/index line 712 and sector/index comple~ent line 711 initialise the di~k emulator prior to initiation of the initial read cycle.
The high signal on ~ector/index line 712 is inverted by 35 NOR gate 405 (Fig. 15) and by NOR gate 407 in write control 132~4~1~

circuit 806 ~Fig. 15). The resulting low signal from NOR
gate 407 clears counters 1027, 1028, and the low signal from NOR qate 405 sets D-type flip-flop 428.
Similarly, in memory word counter circuit 807 in Pig. 19, 5 the high signal on line 712 is applied to a firs~ input terminal of NOR gate 497 and the resulting low output signal from NOR gate 497 clears J-X flip-flop Ag8 and so the signal on sector full line 757 from output terminal Q of flip-flop 498 iQ low and t~e signal on sector full complement line 758 10 Erom output terminal ~ of flip-flop 498 is high.
In read counter circuit 810 illustrated in Fig. 18, the high signal on ~ector/index line 712 drives the output signal from OR gate ~15 high which in turn drives the output signal from NOR gate ~17 low. The low output signal from NOR gate `
15 17 clears counters 1022 and 1023.
The low ~ignal on sector~index complement line ~11 is al80 used to clear components in the di~k emulator. In ~hiEt regi~ter circuit a02, shown in Fig. 10, the ~ignal on 8ector/inde~ co~plement line 711 clears each of the registers 20 in integr~ted circuit~ 1104-1111, 1121. Al~o, the low signal on sector/index complemen~ line 711 clears flip-flop 584 in writing flag cirCuit 811 ~Fig. 24) and as a result the signal on writing line 709 iQ low and the ~ignal on writing co~plement line 710 i~ high.
25 In Ro~ tranQlation circuit 81~ ~Fig~. 22a and 22b), after `-the h~gh ~ignal on sector/index line 712 return~ to a low level the output signal from OR ~ate 485 goeq low. ~his low ~ignal load~ counters 1042, 1043, 1044, 1045. Counters 1042, 10~3, 10~, 10~5 are used in the di~k emulator backup system 30 to generate the addre~seq necessary to acce~s the entire DRAM
array 822 w~en saving the content~ of DRAM array 822 on the SCSI disk. ~o~ever, in normal operation of the disk e~ul~tor, counters 1042, 1043, 1044, 1045 simply pass the signal on each input terminal of the counter to the line 35 attached to the associated output terminal. Thus, after the - 69 - 13244~

sector/index pulse on line 712 loads counters 1042, 1043, 1044, 1045, the signals on DRAM bit-0 line through DRAM
bit-14 lines 850-864 are passed to the output terminals of counters 1042-1045.
Specifically, counter 1042 ~Fig. 22b) passes the signal from bit-12 line 862 to input terminal D o~ four-line to sixteen-line decoder 1091 and counter 1043 passes the signals from DRAN bit-9 line 859 through bit-ll line 861 to input terminals A, ~, C respeceively of four-line to sixteen-line 10 decoder 1091. ~e signals on DRAN bit-9 line 859 through DRAM bit-12 line 862 go through configuration block J7 before reaching decoder 1091.
Counter 10~4 (Fig. 22b) passes ~he signals on D~AM bit-0 through DRA~ bit-3 lines 850-853 to lines J2-26, J2-90, J2-25 15 and J2-89 respectively, which in turn provide the signals to input terminalQ A~0, AHl, A~2, A~3 respectively of the 8207 DRA~ controllers in the disk emulator. Input terminals AH4 through ~H7 respectively of the 8207 DRAN controller are ``
driven by the sign~ls on DRA~ bit-4 line 854, DRAM bit-5 line 20 855, DRAM bit-6 line 856 and DRAM bit-8 line 858 re8pectively, which are passed through counter 1045.
Si~ilarly, the ~ignal on DRAM bit-8 line 858 is passed through counter 10~3 to terminal AH8 of the DRAM
controller~. `
Thus, the index pulse generated by microprocessor 1063 in response to the seek command from the SND disk controller efEectively passes the higher order addresses from the latches in ROM translation circuit 819 to the 8207 DRAM
controller on each of the sixteen DRAM cards comprising the 30 DRU~ array 822. The four-line to sixteen-line decoder 1091 (Fig. 22b) processes the signals from DRAM bit-9 through cylinder bit-12 line~ 859-862, and uniguely enables one of the sixteen DRAM cards by generating a low signal on card select line 792 for that card.

~~`'' ' ~ ` '`' `; ' '`' ''' "` ` ' ` ' ` "'`- ' '`''' '' -' ' - 70 - 132~4~

INI~IAL DRAM CARD SELECTION
Figures 26a and 26b illustrate a typical DRAM card used in the disk emulator. With the embodiment illustrated, there are a maximum of sixteen of these cards in the disk 5 emulator. It will, of course, be appreciated that the present invention is not limited to using any particular nu~ber of DRA~ cards. Each card has a 8207 DRAM controller, shown in detail in Fig. 25, a D0 buffer circuit 845, shown in detail in Figs. 27a throuqh 27d, a connector (not shown), 10 which interfaces the card with the remaining circuitry in the disk emulator, and four banks of DRAM integrated circuits wherein each bank iQ further subdivided into four blocks.
A typical block of a bank is illustrated in Figs. 28a throug~ 28c. Accordin~ly, each of the output lines from 15 decoder 1091 (Fig. 22b) interface~ with a card select line 792 to the DRAM controller circuit on one of the sixteen DRAM
cards and enable line 801 tFigs. 26a and 26b). For the fifteen DRAM card~ which receive a high signal on card select line 792 from one of the output lines of decoder 1091, 20 driver8 560, 561 in the DRAN controller circuit, Fig. 25, are inhibited. ~ence, on these fifteen DRA~ cards the signals fro~ each of the 8207 DRAM controllers to drivers 560, 561 are not pas~ed to the other circuits in the disk emulator.
Furtber, the high signal on enable line 801 (Figs. 27a 25 through 27d) to D0 buffer circuit 845 inhibits drivers 562- -573 in D0 buffer circuit 8~5 which effectively removes the DRA~ banka on the card from parallel bus 700.
Conversely, the low ~ignal on card select line 792 to the DRA~ controller circuit on the sixteenth DRAM card from 30 decoder 1091 (Pig~ 22b) enables drivers 560, 561 (Fig. 25) so ~ ;
th~t thi~ 8207 DRAM controller communicates with the other circuits in the disk emulator. Similarly, the low signal on enable line 801 (Figs. 27a through 27d) to D0 buffer circuit 8~5 interfaces the DRAM banks on the sixteenth DRAM card with 35 par~llel bus 700. It should be noted that the sixteenth .

- 71 - 1324~

card, as used here, does no~ mean the sixteenth DRAM card physically in the disk emulator, but rather the DRAM card which is selected by the higher order address to decoder 1091 and therefore is the DRA~ card referred to in the ~ollowin~
5 description.
The 8207 DRAM controller, as illustrated in Fig. 25, on the card enabled by decoder 1091 (Fig. 22b) addresses the region in the DRAMs corresponding to the siqnals on terminals -AHO through A~8 and also AL0 through AL8 of ~he controller.
10 T~e 8207 DRAM controller generates the appropriate signals on the multiplexed address output terminals A00 through A08 of the coneroller. EacA of the signals from ou~put terminals A00 through A08 pass through a driver in each block (Figs. 28a through 28c) of the DRAM bank and a resistor to 15 one of the address input terminals A0-A8 of each DRAM
integrated circuit in the block. The addresses are latched by the colu~n address strobe ~ignal~ and the row address strobe s1gnals from the 8207 D~AM controller.
.

SDCTOR AND NORD ADDR~SS INITIALIZATION
~hile the location oE the track requested by the SMD
controller i8 now compleeely identified in the DRAM array, the counter~ in the disk emulator that are used to identify the sector and the word~ within the sector must be initialired. In ~e~ory word counter circuit 807 (Fig. 19), 25 the low signal generated by NOR gate 495 in response to the high sign~l on sector/index line 712 loads counters 1054 and 1055 such th~t they count 64 clock pulses and then reset. In addition, the low signal~ loaded on output terminals QA, QB
oE counter 1055 drive bufEers 502, 501, respectively, which 30 in turn drive the b~nk select input terminals, BS0, BSl respectively, of the 8207 DRAM controller ~Fig. 25) 80 that the reroth ban~ of 256K DRAMs is ~ccessed on the DRAM card 8elected by decoder 1091 (Fig. 22b). - -,. ,, ~' ' `
' ' ` " ~' ~

- 72 - 132~4 ~

The low signal from output terminal QA of counter 1055 (Fig. 19) is also applied to a first input terminal of NOR
gate 509, to the input terminal of inverter 505 which in turn generates a high -~ignal on the first input terminal of NOR
5 gate 506. Thus, NOR gate 506, which also receives a low signal from terminal QB of counter 1055, generates a low signal which is applied to a first input terminal of NAND
gate 510. The low signal from terminal QB of counter 1055 is ~lso applied to the second input terminal of NOR gate 509 and 10 the high signal generated by NOR gate 509 is applied to the third input terminal of NAND gate 511.
Similarly, the low signals from output terminals QA, QB
of counter 1054 are supplied to the first and second input terminals of NOR gate 508, respectively. The resulting higb 15 signal gener~ted by NOR gate 508 is provided to the second input terminal of NAND gate 511 and to the third input terminal of NAND gate 510. T~e first input terminal of NAND
gate 511 and the second input terminal of NAND gate 510 each receive the high output signal from NOR gate 507 that is 20 generated in response to the low signals from terminals QC, QD of counter 1055, which are applied to tbe first and second ` `
input terminals of NOR gate 507 respectively.
Therefore, NAND gate 510, which receives the high output signals from NOR gate 507 and NOR gate 508, and the low 25 output signal from NOR gate 506, provides a high output signal to a first input terminal of OR gate 515 and to an input terminal of OR gate 513 which in turn passes the high ~ignal to the fir~t input terminal of NAND gate 512~ In response to the high input signal, OR gate 515 generates a 30 high output signal which is applied to address-l detection complement line 755. The high signal on address-l detection complement line 755 disables data sync comparator 1122 in comparator circuit 815, shown in Fig. 14.
The low output signal from NAND gate 511 ~Fig. 19), which -35 i8 qenerated by the hiqh input signal~ from NOR gate~ 507, ... . .

~ 73 ~ 13244~

508, 509, is passed to a first input terminal of OR gate 514 which in turn generates a low signal on address zero detection complement line 754, because the signal from write counter zero state complement line 718 to the second input 5 terminal of OR gate 514 and to the second input terminal of OR gate 515 is also low. The low signal on address zero `
detection complement line 754 enables the address sync comparator 1123 in comparator circuit 815 ~Fig. 14).
Consequently, the loading of counters 1054, 1055 of memory 10 word counter circuit 807 (~ig~ 19) by the index pulse from the microprocessor 1063 (Fig. 21) also initializes comparator circuit 815 (Fig. 14).
T~e low output signal from NAND gate 511 (Fig. 19) is alQo applied to the second input terminal of NAND gate 512 15 Which generates a high signal on word address 2-63 complement line 756 because both of the input signals are low.
The low signals, which are loaded onto output terminals QC and QD of counter 1055 IFig. 19) and output terminals QA
and QB of counter 1054 by the low Qignal from NOR gate 495 in 20 regponse to the index pulse on sector/index line 712, are also applied to the input terminal~ of buffers 500, 499, 504 and 503 respectively. Buffers 500, 499, 504, 503 generate low output signals that drive input terminals AL0, ALl, AL2 and AL3 respectively of the 8207 DRAM controller (Fig. 25).
25 ~ence, loading counters 105~, 1055 also initializes the lower order bits, whic~ correspond to the words in the sector, of the lower order address generated by the 8207 DRAM controller to the ~eroth word in the sector.
While the high signal on sector/index line 712 30initiali~ed word counters 1054, 1055 (Fig. 19) to the zero ~ord position, the signal on sector/index complement line 711 loads counters 1052, 1053 (Fig. 19) with the signals on their input terd nals. The signals from microprocessor 1063, (~ig. 21) corresponding to the sector address, are passed 35over P00 through P03 lines 786-789 to input terminal~ A, B, ~ 74 ~ 13244~4 C, D of counter 1053 respectively and the signal on P04 line 790 is applied ~o input terminal A of counter 1052. Since counters 1052, 1053 are part of the back-up system, they are not enabled as counters during normal operation~
5 Accordingly, the signal on sector/index complement line 711 loads the signals on P00-P04 lines 786-790 to the input terminals of buffers 491-494 and 490 respectively, and the resulting output signals from buffers 491, 492, 493, 494, and 490 drive the input terminals AL4-AL8 respectively of 8207 10 DRAM controller (Fig. 25~. The signals on the terminals AL~-AL8 define the higher order bits of the lower order addresses which correspond to the sectors in the track specified by the SMD controller~ Since all the signals on terminal~ AL~-AL8 are initialized to a low level, the zeroth 15 ~ector o~ the track is addre~sed.
Thus, the index signal from microprocessor 1063 (Fig. 21) with the sector addre~s generated by microprocessor 1063 and the initialisation of the counters in memory word counter circuit 807 (Fig. 19) has completed the definition of the ;
20 ~ddress of the first word in DRAM array 822 that will be supplied to the SND disk controller. This further deuonstrates the acces-~ time advantage of the disk emulator. The initial track was located virtually inst~ntaneously by the RQM translation clrcuit, and the 25 ~eroth word of the ~eroth sector, which is the address field of the ~eroth sector, is immediately identified as the first ~ord which will be provided to the SMD controller. As is -~`
sho~n below, even if this is not the sector requested by the `-SMD controller, the disk emulator provides the correct sector ~-30 to the SMD controller up to S00 times fa~ter than a conven-tional hard di~k.
The low signal on sector/index complement line 711 loads ~ -counters 1013, 1014 in first gap counter circuit 808 in Fig. 16 and counters 1011, 1012 in second gap counter circuit 35 809 (Fig. 16). As described previously, first gap counter ". .'-~' ,~
. . .
.. . ..

~ 7~ - 132~4~

808 is loaded with the number of bytes prior to the address field and second gap counter 809 is loaded with the number of bytes prior to the data field INITIALIZATION OF MEMORY RETRESH REQUEST
After the initialization of the circuits described above, the high signal on read sero line 724, which was initiated by the index pulse ~rom 8051 microprocessor 1063 ~Fig 21), is generated by monostable 10~9 (Fig ~3) and is passed through QR gate 426 in read counter circuit 810 ~ig 18) to early 10 read line 73~ Early read line 734 supplies the high si~nal to the second inpue terminal of NOR gate 440 in RFRQ circuit 741 (Fiq 29) Load write latch line 717 from the write control circuit 806 (Piq 15) supplies a low signal to a first input terminal of NOR gate 440 (Fig 29) and the line 15 connected to the output terminal Q of Elip-flop 442 also provides a lo~ ~ignal to the t~ird input terminal of NOR qate ~0 The lo~ output ~ignal from NOR gate 4~0 loads counters 1138, 1139 such that they count 128 clock pulse~ on DRAM
clock line 776 `
After t~e high 8ignal on early read line 734 loads counters 1138, 1139, counter 1138 counts each clock pulse on DaAM clock line 776 and after each fifteen clock pulses, counter 1138 rolls over and enables counter 1139 for one cloc~ pulse accordingly, after 128 clock pulses on DRAM
25 clock line 776, counter 1139 qenerates a low ~ignal on its output terminal E~, and ehis low signal is supplied to the input terminal D of D-type flip-flop 442~ The next clock pulse on DRA~ clock line 776 loads the low signal on input terminal D into flip-flop 442 and flip-flop 472 generates a 30 high signal on output terminal Q Thi~ high signal is passed through OR gate 4~3 to the RF~Q output line 778 and to RFRQ
input ter~in~l of the 8207 DRA~ controller~ over line J2-71 The high ~ignal from output terminal Q of flip-flop ~U i8 also passed back to the third input terminal of NOR

- 76 - 132~

gate 440 which generates a low signal and consequently reloads counters 1138, 11~9 and starts the cycle over again.
Accordingly, after the index pulse, R~RQ circuit 841 ~Fig. 29) generates after every 128 clock pulses a refresh 5 signal to the 8207 DRAM controllers which causes the controllers to refresh DRA~ array 822. This is necessitated by the volatile memory used as the storage media in the disk emulator. However, the RFRQ circuit assures that a refresh request does not conflict with a read or write sequence by 10 reloading the counters at the start of each read or write sequence.

RIST~I13VAL OF TEIE INIMAL ADDRESS FIELD
Prior to 128 clock pulseQ on DRAM clock line 776, read counter circuit 810 (Fig. 18~, and latch clock/error 15 detection circuit 805 ~ Fig. 31) generate a sequence of signals, shown in Figs. 30a through 30k, which load the reroth word of the ~eroth sector of the track specified by t~e S~D controller into latch circuit 803 (Fig. 11). Note ` `
that in Figs. 30a through 30k, the horizontal axi~ is not 20 drawn to 8c~1e, but the same scale is used in each of Figs. 30a through 30k.
Specifically, the high signal on read zero line ~24 (Fig. 30a) passes through OR gate 426 in read counter circuit 810 (Fig. 18) to terminal Bl of a first retriggerable 25 mono-table multivibrator in integrated circuit 1144. Since terminal Al of the first retriggerable monostable multivibrator is tied to ground, the first multivibrator in integrated circuit 1144 generates a positive going pulse having approximately a 1200 nanosecond pulse width to input 30 ter~inal a2 of a second retriggerable monostable multivibrator in integrated circuit 1144. Since terminal B2 oE the ~econd retriggerable monostable multivibrator in integrated circuit 1144 is tied to the positive supply voltage, the second multivibrator generates a positive going . ,.. :' - 77 - 1 32~

pulse having approximately a 190 nanosecond pulse width on the falling edge of the pulse from the first multivibrator in integrated circuit 1144. The pulse from the second multi~ibrator is applied to read line 733 (Fig. 30b) which is 5 connected to output terminal Q2 of the second multivibrator in integrated circuit 114~.
The positive pulse on read line 733 passes through OR
gate 516 in latch clock/error detection circuit 805 ~Fig. 31) and clocks flip-flop 517. Al~o, the positive signal on read 10 line 733 is changed to a low signal by inverter 577. ~he low --output signal from inverter 577, which is applied to terminal CLR of D type 1ip-flop 539, clears flip-flop 539. Hence, flip-flop 539 generates a low signal on output terminal Q which is applied to a second input terminal of AND
15 ~ate 5~1 and a first input terminal of NOR gate 542. Since flip-flop 539 is clocked by the signal on RFRQ line and the ;`
signal on this line is held low during the time interval of a read or write in the disk emulator, a~ described more co~pletely belo~, the signal from flip-flop 539 does not 20 change durinq the read cycle. Therefore, AND gate 541 qenerates a lo~ ~ignal to a first input terminal of OR gate 5~1 and the output ~ignal of NOR gate 542 to a second input ter~inal of OR gate 5~1 is determined by the signal on parity chec~ line 78~ during the read cycle. The signal on parity 25 ch~ck line 78~ i~ described in the description of the error correction process below.
Prior to the positive pulse on line 733 clocking flip-flop 517, the ~ignal on read B complement line 746, which is connected to output terminal Q of flip-flop 517, was 30 initiali~ed to a high level and the signal on read B line 7~5, which is coupled to output term~nal Q of flip-flop 517 through inverter 518, was initialized to a low level as shown in Fig. 30c and Fig. 30d, re~pectively. Since the signal on writing line 709, which is connected to input terminal D of 35 flip-flop 517 lFig. 31), is low, as previously described, the - 78 - 132~4~4 clocking of flip-flop 517 by the pulse on read line 733 drives the signal on read B line 745 high, as shown in Fig. 30d, and the signal on read B complement line 746 low, as shown in Fig. 30c.
The low signal on read B complement line 746 is applied to input terminal RDB of the 8207 DRAM controller in Fig. 25 and as a result the 8207 DRAN controller initiates a read memory request for the zeroth word of the zeroth sector of the track specified by the SND disk controller because, as 10 previously deqcribed, the disk emulator has addressed the zero word of the zeroth sector in response to signals supplied by the SND controller. As described previously, the ~eroth word of the sector is the address field for the sector. The 8207 DRAM controller provides the address field 15 for the seroth sector on 66-bit parallel bus 700 and the stored parity bit for that address field on line D(0) from DRAM array 822 which is the 67th bit in the parallel bus. `
Since the ~ignal on writinq line 709 is low, multiplexer 1125 (Fig. 13) connects read B complement line 746 to data ` `
20 enable line 751, positive power supply voltage to shift ` ~
register output control line 7~0, clock zero line 728 to ` `
shift regi~ter clock line 739, and read B line 745 to latch output enable line 742. The positive power supply voltage on shift register output control line 7~0 disables the parallel 25 output terminal in each reg~ster of shift register 802 during the read operation of the di~k emulator.
The high signal on latch output enable line 742 from read B line 7-5 tri-states the output terminal of each register in latch circuit 803 (Fig. 11), and the low signal on data 30 nable line 751 from read B complement line 746 tri-states the input ter~inals to the DRAM integrated circuits in DRAM
array 822. Accordingly, when the 8207 DRAM controller loads the addressed word onto the 66-bit parallel bus, the word i8 available to parity circuit 80i (Fig. 12) and to the input ~` `
35 terminals of latch circuit 803 (Fig. 11). `~ `

_ 79 _ 1~ 4 Since pRrity circuit 804 (Fig. 12) is connected to 66-bit parallel bus 700, i.e. lines D(66)-D(59) of parallel bus 700 are connected to the first eight input terminals A-H
respectively of integrated circuit 1094; lines D(58)-D(51) 5 are connected to the first eight input terminals A-H of the second integra~ed circuit 1095; the in~egrated circuits 1096-1101 are similarly connected to parallel bus 700; the integrated circuit 1102 has the lines D(l), D(2) connected to it~ input terminals A, B respectively; and the input terminal 10 or terminals on the integrated circuits 1094-1102 which are not utilized are connected to ground, when the address field is loaded onto bus 700 parity circuit 804 generates a new parity bit for the word as it is retrieved from DRAM array 822 since the odd output terminal from each of integrated 15 circuits 1094-1101 is connected to an input terminal of integrated circuit 1103, and the even output terminal of ```
integrated circuit 1103 is connected to the first ànput ter~inal of exclusive OR gate 302 (Fig. 11). Accordingly, integrated circuit 1103 provides the new parity bit 20 corre~ponding to the word on bus 700 to the fir~t input ter~inal of e~clusive OR gate 302. The atored parity bit is pro~ided over line D(0), the 67th line in the parallel bus, to the second input gate of exclusive OR gate 302.
For this example, assume that no error occurred in the 25 addre8s field and accordingly the parity bits on the input terminals of exclusive OR gate 302 ~Fig. 11) are the same.
Tbus, the output signal from exclusive OR gate 302 on parity check line 784 is a logical zero. Accordingly, the input signal to NOR gate 542 in latch clock/error detection circuit 30 805 ~Fig. 311 remain~ unchanged and the signal on error co~ple-ent line 783 to the 8207 DRAM controller does not cbange. Therefore, the 8207 DRAM controller performs a normal read/write cycle. The operation of the disk emulator wben a read error is detected is described later.
The low signal on read B complement line 746 also drives : `

- 80 - 1 32~

the output signal from NAND gate 441 in RFRQ circuit 741 (Fig. 29), high. The high signal from NAND gate 441 removes the load signal to counter 1136. Thus, counter 1136 starts to count and after four clock pulses on DRAM clock line 776, 5 counter 1136 rolls over and generates a high signal which passes through OR gate 443 to RFRQ output line 778. However, in a normal read, as described below, the signal on read B
complement line 746 goes high prior to four clock pulses on DRAM clock line 776 and the high signal on read B complement 10 line 746 holds counter 1136 in the load state. Thus, the roll-over of counter 1136 is utilized only to remove a stuck read command.
In the normal read cycle, the 8207 DRAM controller completes the read and sets the signal on XACKB complement 15 line 7?9 low l~ig. 30e). The low ~ignal on XACKB complement ` `
line 779 drives the ou~put signal of AND gate 533 (Fig. 31) low. The low output signal from AND gate 533 is a first input ~ignal to NOR gate 53Q. The second input signal to NOR
gate 530 i~ provided by DRAM clock complement line 777.
20 Thu~, NOR gate 530 generates a high output signal when the siqnal on D~A~ clock comple~ent line 777 goes low. The high output ~ignal from NOR gate 530 drives the output signal o$
NOR g~te 519 low. The low output ignal from NOR gate 519 preset~ flip-flop 517. Thus, the output signal from flip-25 flop 517, as previously described, causes the ~ignal on readB comple~ent line 7~6 to go high (Fig. 30c) and the signal on read B line 7-5 to go low ~Fig. 30d). The low ~ignal on read `
B line 7~5 to the latch output enable line 742 (Fig. 30j) through ~ultiplexer 1125 (Fig. 13) enables the parallel 30 output termin~ls in latch circuit 803 (Fig. 11).
The low output ~ignal from AND gate 533 (Fig. 31) in respon~e to the low signal on XACXB complement line 779 from 8207 DRAM controller also drives the low output signal of NAND qate 529 high. The high signal from NAND gate 529 `
35 pa~8es throuqh OR gate 527 to the latch clock line 743. The - 81 - 132~

high signal on latch clock line 743 (Fig. 30g) captures the address field on 66-bit parallel bus 700 in the latches of integrated circuits 1112-1120 (Fig. 11), because each of the lines D(59)-D(66) of parallel bus 700 is connected to an 5 input terminal D and an output terminal Q of one stage of the eight bit register comprising 1112, each of the lines D(51)-D(58) of parallel bus 700 is connected to an input terminal D and an output terminal Q of one of stage of the eight bit registers comprising IC 1113 and the lines 10 D(3)-D(50) of bùs 700 are connected to the integrated circuits 1114-1119 in a similar manner and the lines D(l)-D(2) are each connected to a stage of the eight bit regi_ter comprising integrated circuit 1120. The stored parity bit on line D~0) is captured in a latch of integrated 15 circuit 1120 (Fig. 11), Thus, the 8051 microproceQsor 1063 (Fig. 21) upon receipt of the seek signal from the SMD disk controller, has entered the rapid sector cycle mode and iQsued an index pulse. The index pulQe and the sactor addre~s data from 8051 20 microprocessor 1063 effectively address the seroth word in the ~eroth Qector for the track ~peciEied by the SMD
controller, and reset and load the counters and latcbe~ in ~ar~ous circuits of the disk emulator. Subsequently, a aeries of ~ignals are generated which result in loading the 25 address field and the stored parity bit for the zeroth sector of t~e track specified by the S~D disk controller into latch circuit 803~ Nhile the resetting, addressing and loading operations were de~cribed sequentially, in real time, they occur simultaneously and accordingly, unlike a conventional 30 hard disk drive, the disk emulator issues the index pulse imoediately after receiving the seek command from the SMD
controller and i8 waiting for the next command from the SMD
controller when a hard disk drive would still be searching for the track requeQted by the SMD controller.

, .
,;:'-' - 82 - L3~

READING THE ADDRESS FIELD
~ he SMD controller asserts the read gate after receiv~ng the index pulse. The SMD controller asserts the read gate by providing a differential signal on bit-l lines J5-5, J5-35 5 (~ig. 6) from the SMD control cable that is enabled by a differential signal on tag-3 lines J5-33, J5-3 (Fig. s) from the SMD control cable. Receiver 462 ~Fig. 6), converts the - `
differential signal on lines J5-5, J5-35 to a high signal on -bit-l line 703 and similarly receiver 459 in Fig. 5 generates -~
10 a low signal on the tag-3 cQmplement line 702 from the differential signal on lines J5-3, J5-33.
In read/write gate circuit 812 (Fig. 33), the high signal -on bit-l line 703 is inverted by inverter 43? and the low output ~ignal from inverter 437 i~ applied to a first input 15 terminal of NOR ~ate q38. The low signal on tag-3 complement ~`
line ?02 is applied to the second input terminal of NOR gate 438 and NOR gate ~38 ~enerate~ a high ~ignal on read gate line ?06. The high signal from NOR gaee 438 also drives read/write gate line 705 through OR gate 439.
The ~ignal on bit-0 line 701, in read/write gate circuit 812, i8 low when the read gate is as-~erted. Thus, ~he low 8ignal on bit-0 line ?01 is changed to a high signal by inve~ter 435 and applied to a first input terminal of NOR
gate ~36. The lo~ signal on tag-3 complement line 702 is 25 applied to the ~econd input terminal of NOR gate 436 and so .`
the output ~ignal from NOR gate 436 on write gate line 704 is low.
The low ~ignal on write gate line 704 is applied through OR qate 585 to input terminal J of the J-K flip-flop 584 in 30 ~riting flag circuit 8~1 (Fig. 24), because tbe signal on SCSI read/write enable line 70?, whicb is the second input signal to OR gate 585, is always low during normal operation of the di~k emulator. Hence, on the next clock pulse on cloc~ one line ?08 to J-R flip-flop 584, the output signal 35 from terminal Q of flip-flop 584 drives the signal-on writing ':;"".

13 2 ~ 4 Ll 4 output line ?09 from writing flag circuit 811 low, while the output signal from terminal Q of flip-flop 584 drives the signal on writing complement line ~10 high.
The high signal on writinq complement line 710 is 5 converted to a low signal by NOR gate 400 in write control circuit 806 (~ig. 15) and ~his low signal is applied to terminal 2~ of J-R flip-flop 432. Hence, a low signal level is generated on output terminal Q of J-K flip-flop 432. This low output signal from J-K flip-flop 432 is a first input 10 signal to NOR gate 402. The output signal from OR gate 403 is the ~econd input signal to NOR gate 403. OR gate 403 has a first input signal ~rom terminal QD of counters 1028 and a second input signal from terminal QA of counter 1027. The output ~ignals from couneers 1027, 1028 were set to a low 15 level by the index signal on sector/index line 712 which cleared bot~ counters. Thus, the output signal rom OR gate ~03 is low ~nd iSO both input signals ~o NOR gate 402 are ``
lo~. The resulting high output signal from NOR gate 402 drives the output signal from NOR qate 407 low which in turn 20 holds counters 1027, 1028 in the clear mode. Hence, the high signal on writing complement line 710 to write control circuit 806 effectively inhibits the operation of write control circuit 806 (Fig. 15).
The low signal on writing line 709 to the inverter of the 25 t~r~in~l ~7~ of multiplexer 1125 in Fig. 13 selects the `~
sign~l8 on input terminal Al-A4 of multiplexer 1125, which are re~d control signals for shift register 802 and latch circuit 803, a8 described previously. The generation and seguence of these signals are described below. ~ "
The low ~ignal on writing line 709 is applied to a first input ter~inal of OR gate 415 in read counter circuit 810 (~ig. 18). Since the second input terminal to OR gate 415 is connected to sector/index line 712, the output signal from OR
gate 415 is low. This output signal is applied to a first 35 input ter-inal of NOR gàte 417 and accordingly the signal on .

' 132~

the second input terminal of NOR gate 417 determines the level of the output signal from NOR gate 417.
~ ence, read counters 1022, 1023 (Fig. 18) are not held off by the low signal on writing line 709. However, counters 5 1022, 1023 are still inhibited. Initially, the signal on sector full complement line 758 from output terminal Q of the J-K flip-flop 498 in memory word counter 807 (Fig. 19) to a ~ -fir~t input terminal of NAND gate 409 (Fig. 18) is high because, as previou~ly described, the index pulse cleared ~:
10 flip-flop 498. The signal on read counter enable word 2-63 line 719 to a second input terminal of NAND gate 409 ~Fig.
18) is low because read counter enable word 2-63 line 719 is connected to output terminal QD of counter 1012 (Fig. 16) and tbe ~ignal on sector/index complement line 711, in response 15 to the index pul~e from microprocessor 1063, loaded a low ~ignal on output terminal QD of counter 1012. Accordingly, NAND gate 09 generates a high output signal which drives a first input terminal of NAND gate 410 (Fig. 18) high. The high signal from ripple carry output terminal RCO- of counter 20 1012 (Fig. 16~ drives the ~econd input terminal of NAND gate ~10 ~nd the high signal from ripple carry output terminal RCO
of counter 101~ ~Pig. 16) drive~ the third input terminal of NAND gate 10. Thu~, NAND gate 410 generates a low output 8ignal which in turn drive~ the output signal from NAND gate :`
25 ~11 high.
The high output signal from NAND gate 411 is applied to the input terminal D of D-type flip-flop 418. Con~eguently, a cloc~ signal on clock ~ero line 728 to clock terminal CLK
oE flip-Elop 418 generate~ a low signal on the output 30 terminal ~ of Elip-flop 418. This low ~ignal i5 inverted by NOR gate ~16 because the ~econd input signal, i.e. the output signal oE OR gate 421, de~cribed below, to NOR gate 416 is also low. The high output ~iqnal from NOR gate 416 i~ ~-applied to an input terminal of NOR gate 417, which in turn 35 generate~ a low ~ignal that hold~ counter 1022, 1023 in the , :-.. ..

clear mode. Hence, although the writin~ signal does notinhibit counters 1022, 1023, the high signal to the input terminal D of flip-flop 418 inhibits the counters and this signal does not change until one of the gap counters rolls over.
Since counters 1022, 1023 (Pig. 18) are in the clear mode, the signal on output terminal QA of counter 1022 and the signal on output terminal QD of counter 1023 are both low. The low signal from the output terminal QA of counter 10 1022 is a firQt output signal to OR gate ~21 and the low signal fro~ terminal QD of counter 1023 is a second input signal to OR gate ~21. Thus, OR gate 421 generates a low output signal which is passed to both input terminal J and input terminal K of J-K flip-flop 424 which is also clocked 15 by clock ~ero. The low output signal from OR gate 421 also holds the D-type flip-flop 425 in the clear mode. On the next clock pulse on clock zero line 728, J-K flip-flop 424 8upplies a low signal to a second input terminal of NOR gate ~19 which alao has a low signal on the first input terminal 20 froo output terminal Q of flip-flop 418. Thus, NOR gate ~19 generates a high signal on input terminal J of the J-K flip-flop ~22. The low signal on output terminal QA of the ``
counter 1022 i~ inverted by inverter 427 and the resulting high ~ignal i9 passed through OR gate 420 to input 25 terminal ~ of J-R flip-flop 422. Accordingly, J-K flip-flop ~22, on the rising edge oE the clock pulse on clock zero line 728, generates a high signal on output terminal Q to output ero line 729 and a low signal on output terminal Q to output ~ero comploment line 730.
Until one of the input signals to NAND gates 409 or 410 change and the resulting change in the output signal of NAND ~`
gate ~11 i8 clocked through flip-flop 418, the signal on ~
output ~ero complement line 730 from output terminal Q of J-K `
flip-flop ~22 ~Fig~ 18) provides a low signal to a first 35 lnput terminal of AND gate 593, shown in ~ig. 10.

- 86 - 132~4~

Accordingly, the output signal from AND gate 593, which drives read data line 755, is low independent of the signal on serial data output line 738 from shif~ register 802 to the second input terminal of AND gate 593.
The low signal on read data line 775 is converted by the differential current mode driver 476, shown in Fig. 7, to a differential signal on the lines J4-3, ~4-16 to the SMD disk controller. The low signal provided by driver 476 ~Fig. 7) to the SMD disk controller in response to the low output 10 signal from AND gate 593 represents the information in the sector prior to the addres~ field.
This demonstrates another advantage of the disk emulator. Since the disk emulator has neither a rotating -atorage media nor mechanical read/write head~, the nonsector-15 specific information is not required for operation of the disk emulator~ Accordingly, the non~ec~or-specific informReion is not stored in DRAM array 822, but rather recreated aQ a ~tring of zeroes when the SMD disk con~roller read~ from the disk emulator. This results in a more 20 efficient utili~ation of the ~torage media in the disk e~ulator than i8 achievable in a conventional hard disk drive. :`
~ hen the end of the first gap in the sector prior to the address field i8 reached, first gap counter 808 (Fig. 16) 25 co~prised of counters 1013, 1014 rolls over and the signal on first gap counter carry line 722 to NAND gate 410 in read counter circuit 810 (Fig. 18), and to a second input terminal of OR gate 535 in latch clock/error detection circuit 805 IFig. 31) goe~ low as shown in Fig. 30f. Since the signal on 30 writing line 709, which is connected to the first input ter~inal of OR gate 535, ia al80 low, OR gate 535 (Fig. 31) generates a low signal which i8 applied to the second input terminal of OR gate 532.
The earlier high signal, which was generated in response 35 to the index pulse, on read line ~33 (Fig. 30b) was inverted - 87 - 132~

by NOR gate 537 (Fig. 31), and the low output signal from NOR
gate 507 cleared flip-flop 538. Accordingly, ~he signal on output terminal Q, which is provided to the fir~t input terminal of OR gate 532, is low. ~ence, bot~ input signals 5 to OR gate ~2 are low, and OR gate 532 generates a low output signal that is applied to the second input terminal of NAND gate 529. (Note if an error had been detected in re~rieving the address field from the DRAM array, the error correction process, described later, clocks flip-flop 538 so 10 that the output ~ignal from flip-flop 538 to OR gate 532 is high, and ~or the read with error case the output signal from OR ~ate 532 remain_ high.) In respon~e to the low signal from OR gate 532 (Fig. 31) `
NAND gate 529 generates a high output signal. The high 15 output signal from NAND gate 529 pas~es through OR gate 527 onto latch clo~k line 743~ See Fig. 309. Since the latches originally inverted the addres~ field and since the input terainal of each latch is tied to the output terminal of the latcb, the signal on latch clock line 743 inverts tbe address 20 field to it~ correct form~ ThuQ, the address field in latch cir~uit 803 iQ ready for transferring to the SMD disk controller.
When the counter 1014 (Fiq. 16) carries, the low signal on first gap counter carry line 722 also drives the output 25 ~ignal from NAND gate ~10 (Fig. 18) high which in turn drives the output ~ignal from NAND gate 411 low as shown in Fig. 34a. The respon~e of read counter circuit 810 (Fig. 18) to the rollover, i.e. carry, of counter 1014 is illustrated in Fig. 34a through Fig. 34z. In Fig. 34a through Fig. 34z, 30 the nu~ber~ on the right hand ~ide of the figure represent the components in read counter circuit 810 in Fig. 18 with the same number, and ~INl~ is the first input terminal of the co~ponent, ~IN2~ iQ the Qecond input terminal of the co~ponent, ànd ~OUT~ is the output terminal of the 35 oo~ponent. The number in parèntheses repreQents another - 88 - ~32~

terminal having the same signal level as the given terminal.
The first clock pulse on clock zero line 72~ to ~-type flip-flop 418 af~er counter 1014 (Fig. 16) rolls over latches the low output signal from the NAND gate 411 ~Fig. 18) and 5 generates a high signal on output terminal Q of flip-flop 418 (Fig. 34b). This high signal is changed to a low signal by NOR gate 419, (Figs. 34r, 34s and 34t) and the low signal is applied to input terminal J of flip-flop 422 tFig. 34u). ``
However, the signal to terminal K of flip-flop 422 remains 10 high, ~Fig. 34~) and therefore the output signals from flip-flop 422 remain unchanged (Fig. 34w) on the next clock pulse to flip-flop ~22.
The high signal on terminal Q of flip-flop 418 is inverted by NOR gate 416 IFigs. 34c, 34d and 34e) and the 15 resulting low signal from NOR gate 416 is inverted by NOR
gate ~17 (Fig. 34f) because, as previously described, the other input signal to NOR gate 417 is also low. The high output signal from NOR gate 417 removes the clear signal to counters 1022, 1023 (Fig. 18). Thus, the first clock pulse 20 aft~r the cairry signal from the first gap counter 808 (Fig. 16~ enables read counters 1022, 1023 (Fig. 18).
The second clock pulse on clock sero line 728 after counter 101- (Fig~ 16) rolls over drive~ the signal on output ter~inal QA of counter 1022 high (Fig. 18). The high signal 25 Eroo termin~l QA passes through OR gate 421 (Fig. 34i), to input terminalis J, R of flip-flop 424 (Fig. 34p) and removes the clear signal to flip-flop 425 (Fig. 34y). The high slgnal from terminal QA of counter 1022 iis al~o applied to the input ter~inal of inverter 427 which in turn generates a 30 low signal which i8 applied to a second input terminal of OR
gate 20 ~Fig. 34k). The first input terminal of OR gate 420 ~Fig. 34~) receives a low signal from the output terminal QD
oE counter 1023. Accordingly, OR gate 420 generates a low ignal ~Fig. 34m) that is applied to terminal LD of counters 351022, 1023, to input terminal K of J-K flip-flop 422 - 89 - 132~

(Fig. 34v) and to the input terminal of inverter S82.
Inverter 582 generates a high signal on the first input terminal of AND gate 423. The high signal on SCSI halt complement line 727 is connected to the second input terminal 5 of AND gate 423 and so AND gate 423 generates a high output signal ~Fig. 34n), on Sl line 731. The high signal on Sl line 731 is applied to the terminal Sl of integrated circuits 1104-1111, 1121 in shiEt regi_ter 802 (Fig. 10). Since both the terminal S0 and the terminal Sl are high, on the third `
1~ clock pulse after the first gap counter roll~ over, the ~ignal on the parallel input terminal of each register comprising shift register 802 (Fig. 10) from the line of parallel 66-bit bus 700 i9 loaded into the register because line_ D(59)-D(66~ of bus 700 are connected to the parallel 15 input/output terminals A-H respectively of the integrated circuit 1104, the lines D(51)-D(50) of bus 700 are connected to the terminal~ A-~ respeceively of the integrated circuit 1105, and the remaining lines D(l)-D(50) of bus 700 are connected to t~e integrated circuit~ 1106-1111, 1121 in a 20 si~ilar fa~hion. ~ence, on the third clock pul~e after the fir8t gap counter rolls over each register in 66-bit ~hift register 802 i8 loaded simultaneously with one bit of the 66-bit word on parallel bus 700 from latch circuit 803, and th fourth clock pulse starts to shift the addres~ field 25 through the serial path of shift register 802 to AND gate 593.
Specifically, on the fourth clock pulse on shift register clock line 739, the bit in register B of IC 1121 (Fig. 10) i~
shifted onto ~erial da~a output line 738 and the bit in 30 r-gi~ter A of IC 1121 i-Q ahifted into register B of IC
1121. The bit in regi8ter H of IC 1111 i9 ~hifted into register A of IC 1121 over the line connecting terminal QH of IC 1111 to terminal SR of IC 1121 and eac~ additional bit in IC 1111 is shifted one bit internally within IC 1111. The 35 bit in register ~ of IC 1110 i- shifted in register A of IC

.. '.' ' _ 90 _ 132~

1111 over the line connec~inq terminal QH of IC 1110 to terminal SR of IC 1111 and each bit is shifted one bit internally in I~ 1110. IC 1109 through IC 1104 are similarly interconnected and so the bits in IC 1109 through IC 1104 ~`
5 also are shifted one register by the fourth clock pulse on line 739.
Recall that, as shown in ~ig. 34, the second clock pulse, which generated the high signal on Sl line 731, also generated a low signal on terminal X of J-K flip-flop 422 10 (Fig. 3~v) and a high signal on terminal J of J-R flip-flop 422 (Fig. 34u~. Thus, on the third clock pulse on clock zero line 728, J-K flip-flop 422 toggles (Fig. 34w) and generates a higb signal on output zero complement line 730. Thus, when the first bit of the address field is input to a first input 15 terminal of AND gate 593, the high signal on the output zero comple~ent line 730 is present on the second input terminal of AND gate 593, and the signal corresponding to the first bit of the addre~ field i~ the output signal of AND gate 593 on read data line 775 to the differential current mode driver `
20 ~76, in Fig. 7, ~hich drive~ the SMD data lines J4-3, J4-16.
Al~o, on the third clock pul~e after first gap counter 808 rolls over, the low 8ign~1 on each input terminal A, B, C, D of counter 1022 ~Fig. 18), the low signal on input ter~in~ls ~, B of counter 1023 (Plg. 18), and the low signal 25 on input ter~inals C, D of counter 1023 are loaded into counters 1022, 1023 because the signal on terminal LD of counters 1022, 1023 is low. The third clock pulse also shiEts the high signal on the input terminal D (Fig. 34x) of flip-flop 425 to its output terminal Q IFig. 34z). The high 30 ignal fra~ output terminal Q of flip-flop 425 is applied to -~
a fir~t input terminal of OR gate 426 which in turn generates a h$gh signal on early read line 734 and on input terminàl Bl of the first monostable multivibrator in integrated circuit 114~. The high signal from OR gate 426 generates a sequence 35 of signals froc aultivibrator integrated circuit 1144 ':' . `~
' ~. ' - 91 1321~

identical to those described pre~iously for the high signal on read zero line 724.
However prior to the generation of the read pulse on read line 738 by the second monostable multivibrator in 5 integrated circuit 1144 (~ig. 18) which starts the second read from DRA~ array 822 the address to the DRAM array is incremented because when ~he signal on the output terminal Q
of flip-flop 425 goes high (Fig. 348) the signal from outpu~
terminal Q of flip-flop 425 (Fig. 18) drives the signal on 10 read word counter line 732 low. The low signal on read word counter line 732 drives the signal on the counter clock line `
780 from NAND gate ~Fig. 3) ~06 high.
The fourth clock pulse on clock sero line 728 after the rollover of first gap counter 808 loads the high signal on 15 counter clock line 780 into in D-type flip-flop 488 (Pig. 19) ~nd the ~ignal on counter clock line 780 goeQ to a low level ```
because the signal on output terminal Q of flip-flop ~25 ` `
(Fig. 18) goes high. The resulting high signal on output ter~inal Q of flip-flop 488 IFig. 19) enerqizes counter 20 1055. The fifth cloek pul~e after rollover of first gap counter 808 increments counter 1055 and loads the low signal fro~ counter clock line ?80 into flip-flop 488 which in turn re~oves the high 8ign~1 on terminal ENP of counter 1055. The high signal on the output terminal QA of counter 1055 after 25 the fifth clock pulse drives the signal on line J2-32 to the terminal BS0 of the 820? DRAM controller high. This incrementQ ~he address for DRAM array 822 from the zeroth word in the sector to the first word in the sector.
Al~o the high ~ignal on output terminal QA of counter 30 1055 drives the output ~ignal from inverter 505 low which in turn drives the output signal from NOR gate 506 high because the signal from output terminal QB of counter 1055 ~Eig. 19) to the second input terminal of NOR gate 506 i~ still low.
Since the output signals from NOR gates 508 and 507 remain 35 unchanged fro~ the levels previously described the high . .
~'".' ': `

- 92 - 132~

output signal from NOR gate 506 causes the output signal from NAND gate 510 to switch from high to low. The low output ~ignal from NAND gate 510 changes the output signal from OR
gate 515 to a low level. The low signal from OR gate 515 on 5 address one detection complement line 755 enables data sync --comparator 1122 (Fig. 13~.
The high signal from terminal QA of counter 1055 (Fig. 191 also drives the output signal from NOR gate 509 low which in turn drives the output signal from NAND gate 511 10 high. The high output signal from NAND gate 511 changes the output signal from OR gate 51~ to a high signal and the input signal to the first input terminal of NAND gate 512 to a high signal. The high signal from OR gate 514 (Fig. 19) on address zero detection complement line 754 disables address 15 8ync comparator 1123 (Fig. 13). The high signal on word address 2-63 complement line 756 i~ not changed as a result of the high signal on terminal QA of counter 1055 because NAND gate 512 still ha~ a high input signal and a low input signal and hence generate~ a high output signal.
When the read signal is generated by the second multi-vibrator of integrated circuit 1144, memory word counter circuit 807 ha~ generated a signal which causes the 8207 DRAM
controller to address the first word in the sector and also has enabled the data sync comparator. As described 25 previously, the read pulse causes the word addressed by the 8207 DRAM controller to be loaded into latch circuit 803. As -`
shown in Fig. 35, the sequence of signal is identical to the seguence in Fig. 30 through the time of the first signal on latch clock line 743. Conseguently, the first word in the 30 sector i~ ~tored in latch circuit 803 ~Fig. 11) ready to be inverted and then loaded into shift register 802 (Fig. 10) before the ~eroth word is completely shiEted out of shift register ao2 ~Fig. 10).
Returning to the second clock pulse after the rollover of 35 fir~t gap counter 808, the signal from the output terminal Q

_ 93 - 1 3 2 ~ 4 ~ ~

of flip-flop 418 in Fig. 18 to NOR gates 416, 419 goes low, as shown in Fig. 34b. However, the high signal on output terminal QD of the counter 1023 passes through OR gate 421 (Figs. 34h, 34i) to NOR gate 416 (Fig. 34d) which in turn 5 generates a low output signal ~Fig. 34e). The low output signal from NOR gate 416 dri~es the output signal from NOR
gate 417 high (Fig. 34f). The high signal from NOR gate 417 to the terminal CLR of the counter 1022 holds off the clear function until counter 1023 rolls o~er. This permits the 8 10 byte address word to be ~hifted serially out of the shift register 802 because, as described below, two clock pulses aEter the counters 1022, 1023 roll over, the signal on the output zero complement line 730 goes low which drives the output signal from the disk emulator low, as described 15 previously.
Counter 1023 in read counter circuit 810 (Fig. 18) rolls over when two bits of the address field are ~till in shift register 802, because, as previou~ly described, after counters 1022, 1023 are loaded they count 64 clock pulses and 20 roll over, and counter 1022 started to count when the first bit ~a8 tran~ferred out of sh~ft register 802. As counter 1023 rolls o~er a high signal is generated on read counter TC
line 781 (~ig. 35;). The high signal on read counter TC line 781 i8 passed to a first input terminal of AND gate 534 in ;
25 laech clock/error detection circuit 805 (Fig. 31). Clock rero line 728 is coupled to the second input terminal of AND
~ate 534 through an inverter 536. Since the signal on read counter TC line 781 goes high when the clock zero pulse goes low, both input signals to AND gate 534 are high and the high ~`
30 output signal from AND gate 543 is applied to the first input terminal of AND gate 531. The second input terminal of AND
gate 531 is connected to terminal ~ of flip-flop 538. The high signal on read line 733, which initiated the reading of the first word in the sector, was also applied to NOR gate 35 537 ~nd NOR g te 537 generated a low rignal that cleared 132~4~

flip-flop 538. Thus, the signal on the second input terminal of AND gate ~31 is also high and AND gate 531 generates a -high output signal which passes through OR gates 528, 527 to latch clock line 743 (Fig. 35e). Recall, the latches in the 5 latch circuit 803 (Fig. 11) latch inver~ed data but the inpu~
terminal of each latch is connected to its output terminal.
Accordingly, this high signal on the latch clock line 743 to latch circuit 803 (Fig. 11) simply inverts the data in each latch and therefore pro~ides the first word of the sector in 10 latch circuit 803 so that it is ready to be loaded into shift register 802 (Fig. 10).
When counters 1022, 1023 in Fig. 18 roll over, the signal to the first input terminal of OR gate 421 from terminal QA
of counter 1022 i~ low and the signal to the second input 15 terminal of OR gate 421 from terminal QD of counter 1023 is also low. Thu~, OR gate 421 generates a low output signal t~at i8 inverted by ~OR gate 416. The high output signal from NOR gate ql6 is inverted by N0R gate 417 and the low `
signal from NOR gate ~17 clear~ counters 1022, 1023. Also, 20 t~e low output signal from OR gate 421 clears flip-flop 425 and is applied to the input terminal~ J, K of J-K flip-flop ~2~. The low output ~ignal from terminal QA of counter 1022 drives the output signal of inverter 427 high, and the high signal froo inverter 42~ passes through OR gate 420 to input 25 ter~inal ~ of J-~ flip-flop 422.
The first clock pulse on clock sero line 728 after counters 1022, 1023 (Fig. 18) roll over drives the signal on termln~l Q of J-X flip-flop 424 low and thus, both input 8ignal8 to NOR gate ~19 are low and con~equently NOR gate 419 `
30 generates a high signal to input terminal J of J-K flip-flop ~22. Since the signal on terminal X of flip-flop 422 i9 kigh, the second clock pulse on clock zero line 728 after counters 1022, 1023 roll over drives the output signal on output ~ero complement line 730 low which in turn drives the 35 output signal on the data output line from ~ND gate 593 low.

- ~5 ~ 132~4~4 Since the counters 1022, 1023 count sixty-four clock pulses and two additional clock pulses were required to disable the disk emulator output, the full 66 bit address field was shifted out of shift register 802 and now the disk 5 emulator system is ~enerating zeros to simulate the ~ap between the address field and the data field.
Thus, the SMD controller issued a seek command and the head and track information and in response the disk emulator virtually instantaneously translated the head and track 10 information into higher order addresses for the DRAM array and issued a seek end`signal to the SMD controller indicating the track specified was located. ~he index pulse initialized the di~k emulator and loaded the address field for the track specified into latcb circuit 803 Upon receiving the index signal, the SMD disk controller as~erted the read gate, and in response the disk emulator supplied the &~D controller with a string of zero bits for the gap in the ~ector prior to the address field~ When the precise nu~ber of bits in the gap was generated, the rollover 20 of the first gap counter 808 loaded the address field for the reroth sector of the specified track into shift register 802 ~nd the addre~s field was serially supplied to the SMD disk controller. ~ `~
Nhile the address field was being serially supplied to 25 the SMD di8~ controller, the disk emulator loaded the first word of the ~eroth sector of the track specified by the SMD
di~k controller into latch circuit 803. When the address field wa~ ~hifted out of shift register 802, the disk omulator again ~upplied a series of zero bits to the SMD disk 30 controller to represent the gap between the address field and the st~rt of the data field. Accordingly, to this time the disk emulator has performed the same function as a hard disk drive, except the seek time has been significantly enhanced. ~-~
, ', .

. .. ''.
; ' ' - g6 - 13244~4 DISK CONTROLLER RESPONSE TO ADDRESS FIELD
After the SMD disk controller recei~es the address field for the sero sector in the track specified by the controller, the SMD disk controller always deasserts the read gate at the 5 write splice field of the sector which is immediately after the address field. Next, the SMD disk controller initiates one of three actions;
1. If this is the sector to read, the SMD controller reasserts read qate.
2. If this is the sector to write, the SMD controller asserts write gate.
3. If this is not the sector of interest, neither gate "
i8 asQerted by the SMD disk controller.
Action~ 1 or 2 occur a predetermined time after the 15 sector/index _ignal is issued to the SMD controller by the dis~ emulator. T~e 8051 microprocessor 1063, in ~ig. 21, poll~ the terminal P37 to which read/write gate line 705 is attached and determine_ if either read gate or write gate has been asserted by the SMD disk controller and consequently 20 re~d/write gate circuit 812, ~hown in Fig. 33, has generated a high signal on read/write gate line 705, aQ described previously.
T~e predeter~ined time is defined by counters lOlS, 1016 (Fig. 17) and 8051 microproce~sor 1063 ~Fig. 21). Counter 25 1015 generates a high signal on line 850, which is connected to output ter~inal QC of counter lOlS, for every eight clock pulses counted, in a manner similar to that described previously for byte clock counter 1016, but counter 1015 is enabled to count only e~ery sixteenth clock pulse to counters 30 1015, 1016 because the enable terminal ~ of counter 1015 is connected to the ripple carry output terminal RCO of counter 1016. Thus, counter 1015 generates a clock pulse on line 850 every 16 bytes where one bit is a clock pulse on clock ~ero l~ne 728.
The high signal on line 850 i8 applied to the input pin -. , .. ... ,, ., .. . . - ... - . , .

~ 97 - 132~

P35 of microprocessor 1063 (Fig. 21). The predetermined time is defined by the pulse width of the signal on line 850.
Microprocessor 1063 monitors the signal on pin P35 and the end of the predetermined time is when the high signal on pin 5 P35 goes low. AS an example, a predetermined time of ten microseconds is used, but the actual time depends upon the clock frequency of the SMD disk controller to which the ~ignal on clock zero line 728 corresponds and the response characteristics of 8051 microprocessor 1063.

10 CONTINUA~ION OF RAPID SEC!I!OR CYCLE
If the signal on the terminal P37 of the 8051 microprocessor 1063 does not go high within the predetermined time, e.g. 10 micro~econds, microprocessor 1063 continues by incrementing the sector address by one bit on output 15 terminal~ P00-P04 and i~uing a sector pul~e on output termin~l P0~. The sector/index cireuit 817 in Fig. 23 receives the sector pulse from microprocessor 1063 on sector line ~13, and generates a high ~ignal on sector/index line ~12, re~d ~ero line 724, and a low signal on sector/index 20 co ple ent line 711. The ~ignals generated by sector/index circuit al7 in response to ~ sector pulse from microprocessor 106~ ~re identical to the signals generated by sector/index circuit 817 in respon~e to an index pulse from microprocessor 1063.
Accordingly, the ~equence of signals, described above for ~`
the re~ponse of the disk emulator to the index signal, is identically repe~ted by the disk emulator in response to the 8ector pulse. The signals on sector/index line 712 and ~-ctor/inde~ complement line 714 re~et the ~ame counters and 30 flip-flops a8 described above and load the same counters. --First gap counter 808 (Fiq. 16) rolls over and the address field for the fir~t sector in the track specified by the SMD
dis~ controller is loaded into shift register 802 and subsequently provided to the SMD disk controller while the ~ 98 - 132~

first word for the first sector is loaded into latch circuit 803.
If the SMD disk controller does not assert the read gate or write gate after receiving the address field for the fir~t 5 sector of the track specified by the SMD disk controller, the 8051 microprocessor 1063 issues another sector pulse and the address field for the second sector of the track is provided to the SMD disk controller. Thus, the address headers are read by the 5~D disk controller at predetermined intervals 10 until the de~ired sector is found. If the desired sector is the last one on the track, i.e. the thirty-second sector, three hundred twenty microseconds (10 microseconds x 32) are required to locate the ~ector when the predetermined interval i8 taken as 10 microseconds. A conventional hard disk 15 typically may require up to 16 milliseconds to locate the correct ~ector after the track i9 loc~ted. Hence, the disk e~ulator reduces the average rotational latency by a factor of 500 in this example~
This represents a significant increase in performance 20 over a conventional hard di~k and the rotational latency of the di8k emulator is no longer the limiting factor in the respon~e of the disk system. Now, the performance of the SMD
disk controller and the disk emulator i~ bounded by the re~pon~e ti~e of the SMD disk controller. Accordingly, to 25 further improve the latency reqùires a change in the SMD
convention. Thi~ increase in performance over prior art SMD
coopatible hard disks is achieved by using a volatile memory and circuitry to provide contiguous binary addresse~ based upon the information provided by the SMD disk controller 30 rather than by enhancing the speed of the hard disk, the density of the hard di~k or the method of ~torage of data on the hard disk, which are the methods suggested by the prior art.

1 3 2 ~

READING THE DATA FIELD
When the address field provided to the SMD controller corresponds to the sector sought by the controller, the controller a~serts the read gate if the central processing 5 unit driving the 5MD disk controller has requested the data stored in that sector. When the read gate is asserted read/write gate circuit 812 ~Fig. 33) provides a high signal on read~write gate line 705 to terminal ~37 of microprocessor 1063 (Fig. 21) and when the microprocessor polls terminal P37 lQ and detects the high signal it immediately leaves the rapid sector cycle mode of its operation. Since the read gate has been reasserted, the status of the disk emulator is identical to that described above when the disk emulator provided the address field for the seroth word after the index pulse.
15 Accordingly, first qap counter 808 has rolled over, the address field for the sector ~as been provided to the SMD
dis~ controller and the first word of the sector i9 in latch circuit 80~ (Fig. 11~ ready to be loaded into shift register 802 ~Pig. 10), and now a series of seros are being provided 20 by J-~ flip-flop 22 on output ~ero complement line 730 to `
AND gate 593 IFig~ 10). These zeros represent the second gap bet~een the address field and the first word in the data field.
During this period, since a sector/index pulse i8 not 25 i88ued, there i8 no initialization of the circuits in the disk emulator and memory word counter circuit 807 (Fig. 19) and latch clock~error detection circuit 805 tFig. 31) remain in the configuration created in supplying the address field -~
to the SMD disk controller, as previously described.
30 Accordingly, the state of the circuits in the disk emulator does not change until counter 1012 in second gap counter 809 (Fig. 16) roll~ over. `
When second gap counter 809 ~Fig. 16) has counted the number of bytes from the index pulse to the start of the data 35 field, counter 1012 generates a low signal on output - . - - - . .~ , ., .. . ~_ , . .... .

-loo- 132~

terminal RCO which drives the signal on second gap counter carry line 721 to the second input terminal of NAND gate 410 (Fig. 18) low. ~ence, when counter 1012 rolls over, the output signal from NAND gate 410 (Fig. 18) switches from a 5 high output signal to a low output signal. This is similar to the sequence of signals which occurred when first gap counter 808 rolled over. accordingly, the timing diagram Qhown in Fig. 36 is similar to that in Fig. 34 since read counter circuit 810 cannot differentiate between a signal 1~ generated by the rollover of first gap counter 808 and a signal generated by the rollover of second gap counter 809.
However, the rollover signal from the first gap counter was used to clock latch circuit 803 t~i9- 11), as shown in Figs. 30f, 30g, and as described previously. Now the input 15 signal to NAND gate 410 ~Fig. 18) from the rollover of second ~ap counter 809 IFig. 16) is not provided to latch circui~
803 ~Pig. 11~ because, as described previously, while the addresQ field was shifted out of shift regi8ter 802, the disk e~ulator latched and inverted the first word in the data 20 field in latch circuit 803 and 80 the first word is ready to be loaded into ~hift register 802 when second gap counter 809 - -rolloverQ. Accordingly, a clock pulse to latch circuit 803 is not required.
Thus, two clock pulseQ after the rollover of counter 1012 25 in s~cond gap counter 809, the first word in the sector is lo~ded from latch circuit 803 into shift regiQter 802 and then serially aupplied to the SMD disk controller on subsequent clock pulses, as described previously ~or the reroth word of the sector, and the second word in the sector 30 ia load d into latch circuit 803 and inverted by the means previously described, ~hile the first word of the sector i5 being serially ~hifted out of shift register 802.
Thus, at thi_ point in the read from the disk emulator, the disk e~ulator has provided the complete sector prior to 35 data field to the SMD disk controller even though the sector-.:

- lol 132~

specific address field was the only portion of the sector stored by the disk emulator. The string of zeros generated by the disk emulator to represent the first gap and the second gap are accepted as valid data by the SMD disk 5 controller and since the disk emulator has no nePd for the nonsector-specific data, the generation o~ the zeroes has no affect on the ability of the disk emulator to interface with the SMD disk controller. ~ence, the use of the volatile memory not only increases the speed of the disk emulator but -10 also makes it po~sible to eliminate both the mechanical mechanisms used in a conventional hard disk and the storage of the non~ector-Qpecific information.
A~ter the disk emulator has provided the first word in the data field to the SMD disk controller, the disk emulator 15 mu~t continue to sequentially provide word two through word "
sixty-three of the data field to the SMD disk controller.
Accordingly, the ~e~uence of ~ignals in the read counter circuit 810 continue~ as ~hown in Fig. 36. As the first word in the sector i~ ~hifted out of shift register 802 (Fiq. 10), ``
20 re~d counter circuit 810 (Fig. 18) is not inhibited by the "~
rollov~r of counter 1023 as it was when the zeroth word was ~hifted out of shift regi~ter 802 because the input signal (Fig. 36~ to flip-flop 418 does not go high on the first cloc~ pulse after second gap counter 809 lFig. 16) rolls over 25 a8 the sign~l to flip-flop 418 d~d when the first gap counter rollNd over (Fig. 84a).
Nhen the signal on the terminal RCO of counter 1012 in second gap counter 809 (Fig. 16) return~ to a high level, the ignal on ter~inal QD of counter 1012 goe~ high and this high 30 81gnal is applied to terminal ~ of counter 1011. The high signal on terminal G of counter 1011 inhibits ~econd gap counter 809. In addition, the high signal from output terminal QD of counter 1012 is applied to the first input terminal of the NAND gate 409 in read counter circuit 810 35 (Fig. 18). Since the second terminal of NAND gate 409 is ~
'~'. ':
':'.""'' "
. .

- 102 - 1324~

connected ~o sector full complement line 758 which carries a high signal, as previously described, the output signal from NAND gate 409 switches from a high signal to a low signal.
Accordingly, when the high signal on second read counter 5 carry line 721 to the second input terminal of NAND gate 410 switches to a low ~ignal, the output signals from NAND gates 410 and 411 are held constant by the low output signal from NAND gate 409 and a low signal is maintained at input terminal D of flip-flop 418. Accordingly, the signal at the 10 output terminal Q of flip-flop 418 remains high as shown in Fiq. 36a. ,-While this high input signal to flip-flop 418, (Fig. 36a) cre~tes a dif~erent timing diagram than that shown in Fig. 30 for the response of read counter circuit 810 after the 15 rollover of f;rst gap counter 808. The difference is ~ignificant only when counter 1023 rolls over. The difference does not affect the initial respon~e of read counter circuit 810.
When counter~ 1022, 1023 in read counter circuit 810 20 (Fig~ 18) roll over and the ~ignal on terminal QA of counter 1022 and the signai on terminal QD of counter 1023 ~o low, the counter~ are not inhibited a~ they were when the address Eield wa~ read. Rather, the ~equence of signals shown in t~e timing diagr~ of Fig. 36a through Fig. 36z occur after the 25 rollover of counters 1022, 1023. In fact, the seguence of ~ignals after the rollover of counters 1022, 1023 in Fig. 36a through 36~ i8 repeated for the second through the sixty-third word of the sector.
The first clock pul~e on clock zero line 728 after 30 counter 1023 rolls over does not change the high signal on output terminal Q of flip-flop 418 (Fig. 36b) because, a~
described above, the signal on input terminal D of flip-flop 418 (Fig. 36a) remain~ low. Accordingly, the low signal applied to input terminal J of flip-flop 422 ~Fig. 36u) 35 re~ains unchanged because, as described above, the high - 103 - 1 32~

signal from output terminal Q of flip-flop 418 is coupled to input terminal J of flip-flop 422 through NOR gate 419. -Also, the high signal on terminal Q of flip-flop 418 is inverted by NOR gate 416 and the resultinq low signal from 5 NOR gate 416 is inverted by NOR gate 417. Hence, the high output signal from NOR gate 417 continues to enable counters 1022, 1023, and the first clock pulse on clock zero line ?28 after counter 1023 rolls over drives the signal on output `-terminal QA of counter 1022 high (Fig. 369). The high signal 10 from terminal QA passes through OR gate 421 (Fig. 36i) to input terminals J~ R of flip-flop 424 (Fig. 36p) and removes the clear signal to flip-flop 425 (Fig. 36y). The high signal from terminal QA of counter 1022 is also applied to t~e input terminal of inverter 42~, which in turn generates a 15 low signal. Tbe low output signal from inverter 427 is ` ``
applied to a second input terminal of QR gate ~20 (Fig. 36k). The first input terminal of OR gate 420 receives a low signal from output terminal QD of counter 1023.
Accordingly, OR gate 420 generates a low output signal 20 (Fig. 36m) tbat i8 applied to terminal LD of counters 1022, 1023, to input terminal R of J-K flip-flop 422, and to the input ter~inal of inverter 582.
Inverter 582 generates a high signal on the first input terminal of AND gate 423. The high signal on SCSI halt 25 coaplement line 727 i8 connected to the second input terminal of AND gate 423 and 80 AND gate 423 generates a high signal, ~Fig. 36n) on Sl line 731. The high signal on Sl line 731 is applied to the Sl terminal of integrated circuits 1104-1111, 1121 (Fig. 10~ and since the signals on both terminal S0 and 30 terminal Sl are high~ on the second clock pulse after counter 1023 (Fig. 18) rolls over the second word, which is on parallel 66-bit bus ~00 from latch circuit 803, is loaded ~`
into shift register 802 as the last bit of the first word i~
shifted out of shift register 802. `;
35 Recall that, as shown in Fig. 36v, the first clock pulse, -.:
: ..

132~4~

which generated the high signal on Sl line 731, also generated a low signal on terminal K of the J-K flip-flop 422 and the low signal on terminal J of J-K flip-flop 422 remained unchanged, as shown in Fig. 36u. Thus, on the 5 second clock pulse on clock zero line 728 the output signals of J-K flip-flop 422 remain unchanged, as shown in Fig. 36w, for output terminal Q.
Also, on the second clock pulse after counter 1023 rolls over, the low signal on each input terminal A, B, C, D of the 10 counter 1022, the low signal on input terminals A, B of counter 1023, and the high i3ignal on input terminals C, D of counter 1023 are loaded into the counters 1022, 1023 becau-qe the _ignal on terminal LD of counters 1022, 1023 is low. ~he second clock pulse also i3~ifts the high signal on input lS terminal D of the flip-flop 425 to its output terminal Q
(Fig. 36z). The high 8ignal from output terminal Q of ~lip-flop ~25 iQ applied to a fir~t input terminal of OR gate 426 which in turn generates a high signal on early read line 734 and on input terminal Bl of a first monostable multivibrator 20 in integr~t-d circuit 11~. The high signal from OR gate 426 generates an identical sequence of actions to those described previouisly.
~ owever, prior to the generation of the read pulse on the read line 733 by a isecona mono~table multivibrator in ~5 integrated circuit 11~ which starts the third read from the DRAM array, the address to the DRAM array is incremented, as `
previously described, by the signal on read word counter line 732.
~ence, each word i5 read after the high signal from flip-30 flop ~25 in read counter circuit 810 (Fig. 18) incrementsword counter circuit 807 by one word. When the last word in the sector i~ loaded into latch circuit 803 (Fig. 11), counter 105~ in memory word counter circuit 807 ~Fig. 19) generate~ a high signal on output terminal RCO in response to 35 the high signal on counter clock line 780. Hence, both input - 105 - 132~

signals, the signal from terminal RCO of counter 1054 and tbe signal from terminal Q of flip-flop 488, to AND gate 496 are high and J-X flip-flop 496 generates a high signal on sector full line 757 and a low signal on sector full complement line 5 ~58.
NAND qate 40g in read counter circuit 810 in Fig. 18 has both input signals low so that the output signal of NAND gate 409 goes high, which results in a hi~h signal on input terminal D of flip-flop 418, as previously described.
10 Consequently, when counters 1022, 1023 in read counter circuit 810 roll over after the last word in the sector, counters 1022, 1023 are inhibited just as they were at the end of the addre~s field pre~iously described.
After the aixty-third word of the sector is shifted out 15 Of the disk emulator, the read operation is completed. If the 5MD di~k controller wants to read another sector from the disk emulator, the controller issues another seek or read gate ~ignal and the prior process is repeated. Hence, the `
novel disk emulator of thi~ invention appears to the SMD disk 20 contxoller as ~ hard diQk drive with substantially improved performance. The seek time and the rotational latency are significantly enhanced and the utilisation of the ~RAM array is ~ore efficient than the utilisation of the disk space in a ``
hard disk drive.

25 WRITING TO TH~ DATA FIELD
When the central processor wants to store data in the disk emulator, the 5MD disk controller initially proceeds as previously described. That is, the 5MD disk controller i~8Ue8 a seek co~mand and supplies the head and track -~
30 infor~aeion to the di~k emulator. The disk emulator issues an inde~ pulse and the SMD disk controller asserts the read gate. The disk emulator proceed~ in the rapid sector cycle mode, previously de~cribed, to supply address fields for each sector in the ~pecified track until the correct location in ? . ~ . ~r ~ .

132~4 the track is found. Then, after the correct location is found, the SMD controller asserts the write gate. Again, the disk emulator eliminates the seek time and substantially reduces the rotational latency so that the disk emulator is 5 ready to receive data from the SND controller much faster than a conventional hard disk drive.
When the SMD disk controller asserts the write gate, the disk emulator is in a configuration identical to that described previously in the read cycle a~ter the desired 10 sector was identified and the read gate reasserted. The memory word counter circuit 807 ~Fig. 19) is incremented to addre~ the fir~t word in the ~ector. The signal on the addreQs ~ero detection complement line 754 from memory word counter circult 807 disables address sync comparator 1122 15 (Fig. 14) and the signal on addre~ one detection complement line 755 from memory word counter circuit 807 enables data sync comparator 1123 ~Fig. 1~). The second gap counter 809 (Fig. 16) i~ counting the byte~ prior to the data field in the ~ector and read counter circuit 810 is generating seros 20 on output ~ero cQmplement line 730.
IA the SND interface, the write gate is as~erted by a differential ~ignal on bit-0 line that i~ enabled by a differential signal on taq-3 line o~ the SMD control cable.
The differential current mode receiver 461, in Fig. 5, i~
25 coupled to the differential bit-0 line J5-4, J5-34 from the SND controller through a re~i~tor network. Receiver 461 drives bit-0 line 701. Similarly, tag-3 complement line 702 is coupled to S~D controller lines J5-3, J5-33 through receiver 459 and resi~tor network shown in Figure 5.
In read/write gate circuit 812 (Fig. 33), the high signal on bit-0 line 701 is inverted by inverter 435 and the low output signal from inverter 435 is applied to a first input terminal of NOR gate 436. The low signal on tag-3 complement line 702 is applied to the second input terminal of NOR gate 35 436, 8c that NOR gate 436 generates a high signal on write - 107 _ 132~

gate line 704 and the high signal from NOR gate 436 drives the signal on read/write gate line 705 high.
The signal on bit-l line 703, in read/write gate circuit 812 (Fig. 33), is low when the write gate is asserted. Thus, 5 the low signal on bit-l line ~03 is changed to a hi~h signal by inverter 437 and applied to a first input terminal of NOR
gate 438. The low signal on tag-3 cQmplement line 702 is applied to the second input terminal of NOR gate 438 and so the output signal from NOR gate 438 on read gate line 706 is 10 low.
The high signal on write gate line 704 is applied ~hrough OR gate 585 to input terminal J of J-K flip-flop 584 in -writing flag circuit 811 ~Fig. 24). ~ence~ on the next clock `
pul~e on clock one line 708 to J-~ flip-flop 584, the signal 15 on writing output line 709 from writing flag circuit 811 goes `
high, while the signal on the writing complement line 710 90eQ low, becau~e the signal on the SCSI read/write enable line 707 iQ always low during normal operation of the disk e~ulator. ` `
The low ~ignal on writing complement line 710 is `
converted to a high signal by NOR gate ~00 in write control ``
circuit 806 (Fig. 15) and this high signal i8 applied ~o ter~inal CLR of J-R flip-flop 427. The high signal removes the clear fro~ J-~ flip-flop 427, and J-K flip-flop 427 is ~ `
25 ready to respond to the ~ignals on its input terminals.
The high signal on writing line 709 from writing flag circuit 811 (Fig. 24) i8 applied to select terminal ~7~ of multiple~er 1125 in Fig. 13. Hence, as previously described, the signal on write clock line 750 i8 applied over shift 30 register clock line 73g to the clock terminal CLK of the int-grated circuits 1104-1111, 1121 comprising the shift register 802 (~ig. 10); the signal on write B complement line 7~8 i8 applied over latch output enable line 742 to output enable ter~inal ~ of each of the integrated circuits 35 1112-1120 in latch circuit 803 ~Fig. 11); the positive p~wer - 108 - 132.~

supply ~oltage is applied to data enable line 751; and the signal on write B line 747 is applied to shift register output control line 740.
As previously described, writing line 709 also supplies 5 the signal to one of the input terminals of OR gate 415 in `
read counter circuit 810 in Fig. 18. Thus, the high signal -on writing line 709 passes through OR gate 415 to the second input terminal`of N~R gate 417. NOR gate 417 generates a low signal that holds counters 1022, 1023 in read counter circuit 10 810 in the clear mode. Conseguently, when second gap counter 809 rolls over as described previously in the read from the disk emulator, read counter 810 remains disabled.
In latch clock/error detection circuit 805 (Fig. 31), the high Qignal on writing line 709 i9 applied to a first input 15 terminal of OR gate 535, a -Qecond input terminal of NOR gate 537, a firQt input terminal of OR gate 544 ànd to input ter~inal D of D-type flip-flop 517. The high signal generated by OR gate 535 in response to the high signal on writing line 709 is pas~ed through OR gate 532 to a first 20 input terminal of NAND gate 529. Accordingly, the output signal froa NA~ gate 529 i8 determined by the output signal fro~ ~ND qate 533 which is applied to a second input terminal of N~ gate 529. The output signal from AND gate 533 is deter~ined by the signal on the XACKB complement line 779 25 froa the 820? DRA~ controller and read/write complement line ~82 from the 820~ DRA~ controller.
The I~OR gate 537 (Fig. 31) inverts the high $ignal on . :.
writing line t09 and the low output signal from NOR gate 537 holds flip-flop 538 in the clear mode. Hence, a low signal 30 i8 ~pplied to the second input terminal of OR gate 532, which ~8 connected to output terminal Q of flip-flop 538 and a high ~ignal i8 applied to the second input terminal of AND gate 531 which is connected to output terminal Q of flip-flop 533. ~he high signal generated on error complement line 783 35 by OR gate 544 in responQe to the high signal on writing line - log - 132~4 709 disables the error detection function of the 8207 DRAM
controller.
After asserting the write gate, the SMD disk controller supplies the data to be written to the disk emulator on the 5 SMD data cable. Lines J4-8, J4-20 from the SMD data cable supply a differential signal to receiver 547, as shown in Pig. 4, and receiver 547 generates the complement of the data signal on write data complement line 735.
In input control circuit 801 (Fig. 9 and Fig. 10~, the 10 8ignal on the SND/SCSI complement line 725 to the first input terminal of NAND gate 446 i~ high and the signal on write -gate line 70~ to the second input terminal of NAND gate 446 i~ high also, because the SND controller asserted the write gate. The low output signal generated by NAND gate 446 in 15 re8pon8e to the high input signals is applied to a first input ter~inal of NOR gate 445 and the signal on write data co ple~ent line 735 is applied to the second input terminal -of NOR gate ~5. Accordingly, the complement of the data signal on line 735 i~ in~erted by NOR gate 4~5 and paQsed 20 t~rough OR gate 44~ to input terminal SR of the integrated circuit 110~ ~Fig. 10). With each clock pulse on write clock line ~50 one bit of the data i8 ~hifted through the serial data path of C6-bit shift register 802 comprised of - int~grated circuits 1104-~111, 1121 in Fig. 10, as described 25 previou~ly when data was ~hifted out of the shift register 802 durin~ the read operation.
Digital comparator 1122 in comparator circuit 815 ~Fig. 13~ cocpares the signals on input terminals P0-P7 with tbe 8ignal8 that have been preset on eight position DIP
30 ~itc~ 291. Coaparator 1122 is located on 66-bit bus 700 ~uch that uhen the data sync pattern is detected, the ~irst 66-bit word of the data field is in shift register 802 after t~o additional clock pulges on write clock line 750. When coqparator 1122 detects the data sync pattern, the si~nal on 35 data sync detection comple~ent line ~53, which is connected '. ~:`~;.` ' '`" `.

- llo - 132~

to the inverter on the terminal P=Q of comparator 1122, goe~ -low. This low signal is applied to the second input terminal of NAND gate 401 in write control circuit 806 (Fig. 15) over data sync detection complement line 753. The signal on 5 address sync detection complement line 752 to the first input terminal of NAND gate 401 is high, as is the signal on word addreQs 2-63 complement line 756 to the third input terminal of NAND gate 401. Accordingly, NAND gate 401 generates a high signal that is applied to input terminal J of J-K $1ip-10 Elop ~32. Fig. 37a through Fig. 37v illu~trate the responseof write control circuit 806 ~Fig. 15) to the low signal on data sync detection complement line 753.
~ ince the initialization of the write control circuit produced a hiqh ~ignal on input terminal K of J-K flip-flop 15 432 IFig~ 37f) the first clock pulse on write clock line 750 aEter the detection of the data sync pattern moves one more bit of data into shiEt register 802 and loads the high signal ``
on input terminal J into J-K flip-flop ~32 (Fig. 37e) which drive_ the signal level on the output terminal Q of flip-flop 20 32 high (Fig. 379). The high ~ignal ~rom the output terminal Q of J-~ flip-flop ~32 drives the output ~ignal of NOR g te 402 low (Fig. 37~) which in turn drives the output ignal of NOR gate 407 high ~Fig. 37m) because the second input signal to NOR gate 407 from sector/index line 712 is 25 lo~. The high signal Erom NOR gate 407 removes the clear signal fro~ counters 1027, 1028. Also, after the ~irst clock pulse, the data sync pattern is no longer on the input ter~inals oE comparator 1122 and thus the signal on data sync detection co~plement line 753 goes high (Fig. 37b) which in 30 turn drives the output signal of NAND gate 401 low (Fig. 37d).
The second clock pul~e on write clock line 750 after detection oE the data sync pattern Eills the 66-bit shift ~`
regiQter 802 and generates a high signal on output terminal 35 QA oE counter 1027. This high signal is inverted by inverter - 111 - 1 32~4 ~

431 to a low signal that is applied to a second input terminal of OR gate 408 (Fig. 37s). The signal on the first input terminal of OR gate 408 from the output terminal QD of counter 1028 is low (Fig. 37r) and thus the output signal 5 from OR gate 408 goes low (Fig. 37t). ~he low signal from OR
gate 408 is applied to input terminal LD of counters 1027, 1028 so that on the third clock pulse on write clock line 750 after detection of the data sync pattern the counters 1027, 1028 are loaded with the signal on their respective input -10 terminals. The low output Qignal from OR gate 408 is also applied to input terminal K of J-X flip-flop 432 (Fig. 3?f) and through the integrator comprised of resistor R100 and capacitor C330 to the input terminal of Schmitt trigger `
inverter ~29. The high output signal from inverter 429 is 15 applied to input terminal Bl of retriggerable monostable ~ultivibrator 11~3. Since input terminal Al of multivibrator 11~3 is grounded, monostable multivibrator 1143 generates a positi~e pu18e on load write latch line 717 (Fig. 37u).
Inverter ~30 invert~ the pulse Erom multivibrator 1143 and 20 the output ~ignal from inverter 430 is applied to write line 716 ~Fig. 3~v)~
The high ~ignal on load write latch line 717 passes through OR gates 461, 46~ in latch clock/error detection circuit 805 (Fig~ 31) to latch clock line 7~3. ConQequently, 25 the second cloc~ pulse on write clock line 750 after detection of the data sync pattern by comparator 1122 clocks the latche~ in latch circuit 803 (Fig. 11) and captures the word of data which is on 66-bit parallel buQ 700 from shift register 802 lFi9~ 10) in latch circuit 803. Hence, the disk 30~ulator, which operates at 25 Megahertz or higher, has stored the first word in the data field so that it can be written to ~emory while the next word is being loaded into shift register 802. This permits operation at the high _peed a8 well as writing to DRAM array 822 in a reaQonable time 3sfra~e. Al~o, this demonstrates how the sector-~pecific data .
' " ' field is detected and proc~ssed Since the SMD disk emulator now passes the remainder of the data field to the disk emulator, the disk emulator must continue to generate a clock signal to latch circuit 803 on every 66th write clock pulse 5 and write each word to DRA~ array 822 before the next word is captured in latch circuit 803 The high signal on load write latch line 717 is also applied to the first input terminal of NOR gate 440 in RFRQ
circuit 841, shown in Fi9. 29 The high signal on load write 10 latch line 717 drives the output signal from the NOR gate 440 low and, as previously described, the low signal from NOR
gate 4~0 loads counter~ 1138 and 1139 The response of counters 1138, 1139 in RFRQ circuit 841 is now identical to that described when the high ~ignal on early read line 724 15 drove the output signal from NOR gate 440 low ~he third clock pulse on write clock line 750 after detection of the data sync pattern loads counters 1027, 1028 ``
lFig 15) ~o that the signal on output terminal QA of counter 1027 goes lo~ ~hich in turn drives the output signal from 20 inverter ~31 to the Qecond input terminal of OR gate 408 high (Fig 378) The signal from output ~erminal QD of counter 1028 al80 goes high and t~i~ high ~ignal is supplied to the first input terminal of OR gate ~08 (Fig 37r) Accordingly, th- output ~ignal fro~ OR gate ~08 (Fig 37t) remains high ~ ;
25 until one clock pulse after counter 1028 rolls over T~e high signal generated on output terminal QD of counter 1028 by the third clock pUlQe iQ also applied to OR
gate 03 ~Fig 37n) and the high output signal from OR gate ~03 (Fig 37g) i~ applied to the fir~t input terminal of NOR
30 gate 02 (Fig 37h) The third clock pulse to J-K flip-flop ~32 drives the signal on output terminal Q low (Fig 37g) b~cause the signal on the input terminal-~ J, K are both low ~ `;
~Pig 37e and Fig 37f) Accordingly, since NOR gate 402 has a high input ~ignal ~Fiq 37h) and a low input signal 35 ~Flg 37i~ the output signnl ~rom Noa gate 402 remains low - 113 - 1 32~4 (Fig. 37j). This low output signal maintains the output -signal from NOR gate 407 at a high level ~Fig. 37m) which inhibits the clear function for counters 1027, 1028.
The high output signal from OR gate 403 is also applied 5 to the input terminal of OR gate 514 and OR gate 515 in memory word counter circuit IFig. 19) 807 by write counter zero state complement line 718. The high signal on write counter zero state complement line 718 causes OR gate 514 to maintain a high signal on addre~s zero detection complement 10 line 754 and causes OR gate 515 to maintain a high signal on address one detection complement line 755. Hence, comparator circuit 815 (Fig. 14) i~ inhibited.
As counters 102~, 1028 (Fig. 15) count the clock pulses on write clock line 750, counter 1028 generates a high signal 15 on output terminal QB. However, prior to this time, the disk e~ulator mu~t write the word stored in latch circui~ 803 to DRA~ array 822, because, as deQcribed below, tbe high signal on output terminal QB of counter 1028 cauQes memory word counter circuit 807 ~Fig. 19) to increment the word address 20 for ~RAM ~rray 822 by one~ The write to DRAM array 822 is initiated when the lo~d write latch signal on line 717 goes lo~ because at thi~ time the signal on write line 716 goes higb a~d the hig~ signal on write line 716 initiates the write sequence.
The dur~tion of the high 8ignal on load write latch line 717, approxi~ately 500 nanosecond~, is determined by the resistor R101 and the capacitor C331, which are connected to `-input ter~inals of multivibrator 1143 aQ ~hown in Fig. 15.
~hen the signal on the load write latch line 717 goes to 30 ~ero, the signal on write line 716 goes high. Figs. 38a through Figs. 38~ illu~trate the sequence of signals that write the ~ord from latch circuit 803 to DRAM array 822. In Fig. 38, the names and associated numbers on the right hand Jlde of the figure each represent the lines in the disk 35 e~ula~or with the s~me number. The horizontal axis is not to ','.,'" ' - 114 - 132~4~14 scale, but each figure has the same scale.
The transition from a low signal to a high signal on write line 716 clocks D-type flip-flop 553 in write B circuit 814 (Fig. 39). Accordingly, the low signal on input terminal 5 D of flip-flop 553 is provided to output terminal Q of flip-flop 5~3. The low ~ignal on output terminal Q drives the signal on write B complement line 748 low (Fig. 38c). The low signal on output terminal Q of flip-flop D is also applied to the input terminal of inverter 553 and the 10 resulting high output signal from inverter 553 drives the ~ignal on write B line 747 high (Fig~ 38d).
The high signal on write B line 747 tristates the output terminals of the register~ in the shift register 802 ~Fig. 38h) and the low signal on the write B complement line 15 7~8 is passed through multiplexer 1125 (Fig. 13) to the latch output enable line 7~2 and the latch output terminals are enabled 80 that the 66-bit word in latch circuit 803 is on the parallel bus ~00 IFig. 38i). `
The low signal on write B complemient line 748 is applied 20 to input ter~inal WRB of the 8207 DRAM controller. In response to the low signal on the input terminal ~RB, the 8207 DRA~ controller gener~tes a low signal on read/write oonple~ent line 782 (Pig. 38f). The low signal on read/write co pl-oent line 782 drives the output signal from AND gate 25 533 in latch clock/error detection circuit 805 ~Fig. 31) low. The low output signal from AND gate 533 drives the output signal ~rom NAND gate 529 high and the high output ~ign~l from NAND gate 529 passes through OR gate 527 to latch clock line 743 (Fig. 38~). Since the output terminals in ~ `
30 l~tch circuit 803 are enabled, the high signal on latch clock line 743 captures the ~nverted signals on the output ;~
terminals from the latches in circuit 803 on the input terminals in the latche~ in circuit 803. Consequently, the : -66-bit word storea in latch circuit 803 is inverted so that 35 the word i8 now ready to be written to DRAM array 822. The ..: " . .
. :

~ ~, : ` ` .

- 11S - 132~14 8207 DRAM controller subseguently stores the word in the location specified by the address signals from ROM
translation circuit 819 and memory word counter circuit 807, as previously described.
After the word is written to the specified location in DRAM array 822, the 8207 DRAM controller drives the signal on XACKB complement line 779 low. The low signal on XACKB
complement line ~79 is a first input signal ~o NOR gate 550 in write B circuit 814 (Fig. 39). The second input signal to 10 NOR gate 550 i~ on DRAM clock complement line 777.
Accordingly, NOR gate 550 generates a high output signal when the signal on DRAM clock complement line 777 goes low. The ~igh output signal from NOR gate 550 drives the output signal from NOR gate 551 low which presets the flip-flop 552 and 15 therefore drives t~e signal on write B complement line 748 high ~Fig. 38c) because write B complement line 748 is :
connected to output terminal Q of flip-flop 552. The high output signal from terminal Q of flip-flop 552 is also an ``
input ~ignal to inverter 55~, which in turn generates a low 20 output sign~l on write B line ?~7 (Fig. 38d).
Hhen the 8207 DRAM controller dri~es the signal on the XACRB cooplement line 779 low (Fig. 38e), the signal on read/write co~plement line 782 to AND gate 533 ~Fig. 31) was "`.
already low (Fig~ 38f) and 90 the output signal from AND gate 25 533 in latch clock error detection circuit 805 ~Fig. 31) remains unchanged by the low signal on XACKB complement line 779. Consequently, a clock pulse is not generated on latch ``
clock line 7-3 by the low signal on XACKB complement line 779. After the low signal on XACK~ complement line 77g 30 returns to a high level ~Fig. 38eJ the signal on`read/write co pl~ent line 782 also returns to a high level ~Fig. 38f) and tbis completes the write to DRAM array 822.
Recall this response of the disk emulator to the load write latch signal and the write signal was generated by the 35 8econd clock pulse on write clock line 750 after detection of - 116 - 132~4~

the data sync pattern. As counter 1027, 1028 (~ig. 15) count the ~lock pulses on write clock line 750 and generate a high signal on output terminal QB of counter 1028, referred to previously, the high signal on output terminal QB of counter 5 1028 drives the output signal from NAND gate 404 to input terminal D of flip-flop 428 low, because the signals on the two other input terminals of NAND gate 404 were set high when counter 1028 was loaded. On the next clock pulse on write clock line ?50, the low signal on input terminal D of flip-10 flop 428 is loaded into flip-flop 428 and applied to output terminal Q which drive~ write counter line 715. ~he low signal on write counter line 715 is inverted by NAND gate 406 -~Fig. 3). The hig~ Qignal generated on counter clock line 780 by NAND gate ~06 increment~ counters 1054, 1055 in memory 15 word counter circuit 807, as previously described.
Since this i8 the second word counted, the output signal on terminal QA of counter 1055 in memory word counter circuit 80~ ~ig. 19) is low, the output signal on terminal QB of ~ `
counter 1055 is high, and the output ~ignals on ~he terminals 20 QC and QD of counter 1055 and the terminals QA and QB of counter 105~ are all low. Accordingly, the next word in the 8ector of the track ~pecified by the SMD controller is addre~sed on lines J2-30, J2-9~, J2-32, J2-96, J2-31, and -`
J2-95 to the 820~ DRAM controller which are coupled to 25 terminal8 QA through QD of counter 1055 and terminals QA, QB
of counter 105~, respectively. :`
Also, the low signal from output terminal QA of counter 1055 ia also applied to a first input terminal of NOR gate `-509 and to an input terminal of inverter 505 which in turn 30 generates a high signal on the first input terminal of NOR
gate 506. Thus, NOR g~te 506, which also receives the high signal from terminal QB of counter 1055, generates a low signal which is applied to a first input terminal of NAND
gate 510. The high signal from terminal QB of counter 1055 35 is also applied to the second input terminal of NOR gate 509 ~.```'`.

- 117 - i32~

and the low signal generated by NOR gate 509 is applied to the third input terminal of NAND gate 511. Similarly, the low signals from output terminals QA, QB of counter 1054 are supplied to the first and second input terminals of NOR gate 5 508 respectively. The resulting high ~ignal generated by NOR
gate 508 is provided to the second inpu~ terminal of NAND
gate 511 and to the third input terminal of NAND gate 510.
The first input terminal of NAND gate 511 and the second ~` -input terminal of NAND gate 510 each receive the high output 10 signal from NOR gate 507 thàt is generated in response to the low signals from terminals QC, QD of counter 1055 which are applied to the first and second input terminals of NOR gate 507 respectively.
Therefore, NAND gate 510, which receives the high output 15 8ignals from NOR gate 507 and NOR gate 508 and the low output signal from NOR gate 506, provides a high output signal to a fir~t input terminal of OR gate 515, which in turn generates ~ hig~ Qignal on address one detection complement line 755.
The hig~ output signal from NAND gate 510 is also passed 20 through OR ~ate 513 to the first input terminal of NAND gate 512. The hig~ output signal from NAND gate 511, which is generated by the high input signals from NOR gates 507, 508 ~nd the low input signal from NOR gate 509 is passed to a first input terminal of OR gate 514~ The high output signal 25 from NAND gate 511 is also applied to ~he ~econd input ter~inal of NUND gat~ 512~ Since the signals on both input terminals of NAND gate 512 are high, NAND gate 512 generates a lo~ signal on word address 2-63 complement line 756~
T~e lo~ signal on word address 2-63 complement line 756 30 drive~ the output 8ignal from NAND gate 401 in write control circuit 806 (Fig~ 15) bigh. Accordingly, the signal~ on both input terminals J, R of flip-flop 432, in write control circuit 806 (Pig. 15) are high and on the next clock pulse on ~rite clock line 750 the signal on output terminal Q of flip-35 flop 432 goes high. As previously described, this high 118 - 1 3 2 ~ ~ 1 4 signal inhibits the clear function on counters 1027, ~028.
Thus, when counters 1027, 1028 roll over after counting 64 bits of the second word, the counters do not clear when the signal on output terminal QD of counter 1028 goes low.
5 Rather, the first clock pulse on write clock line after counter 1028 rolls over drives the output signal on terminal QA of counter 102~ high and the output signal on terminal QD ` .`
of counter 1028 remains low. Also, one additional bit of data is shifted into shift register 802. The high signal 10 from terminal QA of counter 1027 and the low signal from counter 1028 produces a second high signal on load wri~e latch line 717, as previously described, and the second high signal on load write latch line 717 generates a clock pulse -`
on latch clock line 743 which captures the sixty-six bit word lS in shift register 802 in latch circuit 803. Since one bit of the word was shifted into shift register 802 by the clock pulse which loaded counters 1027, 1028 after the previous load write latch signal, an additional 64 bits of the word ~ .`
were shifted into shift register 802 by the clock pulses 20 which cau~ed counter 1028 to roll over, and one additional bit was shifted into shift register 802 as the second load write latch signal was generated, the clock pulse on latch clock line 743 is generated at precisely the instant another full sixty-si~ bit word is in shift register 802~ The 25 counters 1027 and 1028 are again loaded after the generation of the second load write latch signal and the memory word counter circuit 807 is incremented as described above.
Hence, as each 66-bit word fills shift register 802 and counter 1028 rolls over, one clock pulse later the load write 30 latch 8ignal on line 717 is generated and the process repeats its~lf.
Thi~ process continues until counter 1054 in memory word counter circuit 807 (Fig. 19) generates a carry pulse signal ~ -to AND gate 496 which in turn generates a high signal on 35 input terminal J of the flip-flop 499, as previously - llg - 132~4 described. On the next clock pulse on clock zero line 728 the signal on sector full line 757, which is connected to output terminal Q of flip-flop 498, goes high. The high signal on sector full line 757 drives the output signal from 5 NQR gate 400 ~n write control circuit 806 (Fig. 15) low. The low output signal from N~ gate 400 clears flip-flop 432.
The resulting low signal on output terminal Q of flip-flop ~32 is Qupplied to the first input terminal of NOR gate 402 a8 previously described. Thus, when counter 1028 rolls over, 10 the output signal of NOR gate 402 goe~ low and counters 1027, 1028 are in the clear mode, as previously described. Thus, the disk emulator read~ t~e data field of the sector provided by the SND di~k controller and then inhibits write control circuit 806. Hence, the disk emulator functions in the write 15 operation as a hard disk drive with substantially improved performance.
Following this mode of operation, the SMD disk controller may write any number of sectors to the disk emulator. The co par~tor circuit 815 detects the sector specific data and 20 only aector specific data i9 written to the DRAM array. This ~ini~ires the amount of DRAM required and gives a better utili~ation oÇ the storage medium than the prior art hard di8k drives. Also, as described, the disk emulator significantly i~proves the seek time and the rotational 25 latency and operates at 25 M~2 or higher ~o that the speed ~ith ~hich data is written to the disk emulator is governed ~`
by the ~peed of the SMD disk controller, rather than the diQk ~ulator. This dependence of performance on the SMD disk controller completely reverses the dependence found in the 30 prior art, ~here the performance of the hard disk drive was `~
the li~iting factor.

R~AD ~IT~ ERROR
In the ia~ediately preceding description of the read operation from the di~k emulator, the error correction `,'' ,, - 120 ~ 1 3 2 ~

capability of the disk emulator was not discussed. It was assumed that no hard errors, as defined previously, occurred while the data was stored in the DRAM array. In the normal read, the cycle was: 1) read the word from DRAM array 822 5 and store it in latch circuit 803; 2) invert the word in latch circuit 803; and 3) write the word from latch circuit 803 to shift register 802. This was a READ/INVER~WRITE
cycle.
The extra invert cycle may seem extraneous from the lo normal read cycle with no errors, but examination of the read cycle with an error demon~trates the benefits of the inverting latche~ in latch circuit 803.
The read from memory with an error requires the Read/Invert/Write~Read/In~ert/Write cycle previously 15 illu~trated in Table I. This cycle must be accompli~hed within the time required for the pre~ious 66 bit word to be ~`
shifted through Qhift register 802. ~he error correction sequence requires the moQt time to accomplish, and, as ~uch, i8 the li~iting factor for serial data tran~fer to the SMD
20 di8k controller. Since the data is read and immediately inverted in con~unction with the latching operation, ;`~
significant time is saved. This allows the six step error correction operation to fit within the 66-bit time at a clock rate of up to 50 MH~. ``
A read with error cycle begins, as previously described, ~ith the read request to 8207 DRAM controller, i.e., applying a low signal on terminal RDB of the 8207 controller.
Figs. ~Oa through 40; illustrate the sequence of signal~ for a read ~ith error. In Fig. 40a through 40i the names and -30 ~ssociated nu~bers on the left hand side of the figure each represent the lines in the disk emulator with the ~ame nu-ber. Fig. 40~ i6 the response of terminal Ql in multivibrator 1131 ~Fig. 31). In Fig. 40, the horizontal ~Xi8 is not to scale, but each figure has the same Qcale.
~pon receipt of the low slgnal on terminal RDB, the 8207 .
.

1 3 2 ~

DRAM controller performs the memory fetch, and loads a 66-bit word on 66-bit parallel bus 700 and a stored parity bit for the 66-bit word appears on line D(0) as previously described. Parity circuit 804 (Fig. 12) generates a new parity bit on parity bit line 744 for the retrieved word on 66-bit parallel bus 700. Recall that during this operation the parallel output terminals in shift register 802 (Fig. 10) are tri-~tate.
The new parity bit on parity bit line 744 i9 applied to 10 the first input terminal of Exclusive OR gate 302 ~Fi~ . The Qtored parity bit on line D(0) is applied to the second input terminal of Exclusive OR gate 302. If the -output ~ignal from OR gate 302 i~ zero, then no error occurred and the read cycle progresses as previously 15 described. However, since for illustrative purposes an error i8 a~Qu~ed, the new parity bit i8 different from the stored parity bit and the output ~ignal from Exclusive OR gate 302 on parity check line 784 is high.
The hig~ ~ignal on parity check line 784 is applied to a 20 first input terminal of NOR gate 542 in the latch clock/error detection circuie 805 (Fi~ 31). The signal on the second input terminal of NOR gat~ 542 and the signal on the first input terminal of AND gate 541 are both low because the signal on read line ~33, which initiated the read cycle, 25 dro~e the output ~ignal of lnverter 577 low and the low output ~ignal from in~erter 577 cleared flip-flop 539.
Similarly, the low ~ignal on read B complement line 746 (Fig. 40b) cleared flip-flop 540 and the resulting low signal on the output terminal Q of flip-flop 540 i~ applied to the 30 8econd input terminal of AND gate 541. Accordingly, NOR gate 542 generate~ a low -~lgnal which is applied to the first input terminal of OR gate 543 and AND gate 541 also generates "
a lo~ signal ~hich i~ applied to the ~econd input terminal of OR gate 543. The low output signal generated by OR gate 543 35 i~ passed through OR gate 544 to error complement line 783 ` ` ::

- 122 - 1324'~4 because the signal on writing line 709 to the other input terminal of OR gate 544 i-~ also low. ~he low signal on error complement line 783 is applied to the error pin of the 8207 DRAM controller.
When the signal on the error pin of the 8207 DRAM
controller is low, the controller modifies the read cycle from that previously described. Instead of generating the low signal on XACRB complement line 779 as in the error free read, the 8207 controller generates a low signal on the 10 read/write complement line 782 ~Fig. 40f) which is connected to terminal Rf~ of the controller. This indicates that the réad cycle has been altered to become a Read-Modify-Write "
cycle.
The low signal on read/write complement line 782 drives 15 the output ~ignal from AND gate 533 in latch clock/error detection circuit 805 ~Fig. 31) low and the re~ponse of NAND ~`
gate 529 to the low output signal from AND gate 533 is identical to that in the error free read. Consequently, the ch~nge ln the signal on the read/write complement line 782 20 cau8e8 latch clock/error detection circuit 803 (Fig. 40e) to latch the word on parallel bus 700. Since latch circuit 803 inverts the word when it latches, latch circuit 803 provides an inverted word on the parallel bus 700 to DRAM array 822.
The a207 DRA~ controller then writeQ the inverted word back 25 to the same location in DRAM array 822 from which the word was retrieved.
The low output signal from AND gate 533 is also applied to a first input terminal of NOR gate 530. The input signal on the ~econd input terminal of NOR gate 530 is the comple-30 Jent of the DRAM clock signal on DRAM clock complement line777. The ~ignal on read/write complement line 782, which drives the output ~ignal of AND gate 533, and the signal on DRAM clock complement 777 are timed ~uch that both are low on ~`
the input terminals of NQR gate 530 so that NOR gate 530 35 g-nerate~ a high output signal. The high output signal from - 123 - ~32~

NOR gate 530 drives the output signal of NOR gate Sl9 low.
As previously described, the low output signal from NOR gate 519 sets flip-flop 517 and consequently a high signal is generated on read B complement line 746 (Fig. 40b) and a low 5 signal on read B line 745 (Pig~ 40c).
The signal generated by 8207 DRAM controller on read/write complement line 782 (Fig. 40f) also clock~ the error flag register, flip-flop 538. Accordingly, since the ~ignal on input terminal D of the flip-flop 538 was high, the 10 ~ignal on output terminal Q of flip-flop 538 goes high and the ~ignal on output terminal ~ of flip-flop 538 goes low.
The high signal from output terminal Q of flip-flop 538 is applied to one of the input terminals of OR gate 532. This ` -i8 nece~sary becau~e the error correction scheme leaves the 15 corrected word ready to be loaded into shift register 802, but in a read without error for the zeroth word of a sector the signal on line 722 iQ u~ed to drive the output signal of OR gate 532 high which subsequently generates a clock pulse on latch clock line 7~3. ~owever, since the clock pul~e on 20 line 7~3 i~ not needed in a read with error, the high signal provided by flip-flop 538 to OR gate 532 cau~es the OR gate 532 to generate a high output signal at all times until another read ~ignal on read line 733 to NOR gate 537 causes NOR gate 537 to clear flip-flop 538. ~he low signal on the 25 output terminal ~ of flip-flop 538 similarly drives the output signal of AND gate 53i low 80 that when the read counters roll over and generate a high signal on read counter ~C line 781, the high signal on line 781 does not generate a cloc~ pulse on latch clock line 743.
Finally, the signal generated by the 8207 DRAM controller on read/write complement line 782 after the detection of the parity error sets flip-flop 539 80 that the signal on output ter~inal Q of flip-flop 539 is high. The high signal from output terminal Q of flip-flop 539 drives the output signal 35 o~ NOR gate 542 low. The high signal from output terminal Q -`
. , . -- 124 _ ~ 32~

of flip-flop 539 is also applied to the second input terminal of AND gate 541. The signal on the first input terminal of AND gate 541 from the output terminal Q of flip-flop 540 i5 ~.
low because just prior to the low signal on read/write 5 complement lines 782 (Fig. 40f) the signal on read B
complement line 746 (Fig~ 40b) was low and this low signal held the flip-flop 540 in the clear mode.
Accordingly, with a high input signal and a low input signal, AND gate 541 generates a low output signal. Hence, 10 OR gate 543 has two low inpu~ signals and accordingly generates a low output Qignal which passes through OR gate 54~ to error complement line 783. The low signal on error complement line 783 forces the error pin of the 8207 DRAM
controller active QO that a guaranteed error will occur when 15 the 8207 DRAM controller performs the second read cycle.
The high siqnal from output terminal Q of flip-flop 538 which was generated by the clocking of flip-flop 538 by the signal on read/write complement line 782 which wa~ generated by ~he 8207 DRA~ controller after the detection of the parity - -20 error tr~ggers monostable multivibrator 1134 because input ter inal Al of multivibrator 1134 is qrounded. The high output signal from multivibrator 1134, (Fig. 40;) is passed through OR gate 516 to the terminal CLK of the flip-flop 517. ;
Accordingly, when multivibrator 1134 triggers ~lip-flop 517 is clocked and, as described previously, the signal on read B complement line 746 ~Fig. 40b) goes low and the signal on read ~ line 745 (Fig. 40c) goes high. The low signal on -read B complement line 746 is applied to input 30 t~r~inal RDB of the 8207 DRAM controller and accordingly the 8207 DRAH controller initiates a second read cycle with an error because of the low signal on error complement line 783, a8 previously de~cribed.
This cycle is identical to the first cycle except now the 35 low ~ignal on the read/write complement line 782 (Fig. 40f) `
, ; ' , . 'A . ~ , ~r~

- 125 - 132~

does not change the output signal ~rom flip-flop 538 and conseguently multivibrator 1131 is not retriggered.
Accordingly, this second cycle simply reads and inverts the data from the DRAM array which was written there by the first s cycle of the error correction process. As explained previously with respect to Table I, the second Read/Invert~Write cycle leaves the error corrected word in latch circuit 803. This word is subsequently loaded into the shift registers and the SMD controller sees correct data and 10 is unaware that any memory failure has occurred.
This error correction process is completed while the previous word is being shifted out of shift register 802 and the use of the inverting latches in latch circui~ 803 and the unique Read/Invert/write/Read/Invert~write process eliminates `-15 any potential problem with single bit failures in the DRAM
array.
The disk emulator of thi~ invention significantly improves both the seek time and the rotational latency.
Also, the data storage medium in the disk emulator is used 20 more efficiently than the data ~torage medium in a conven-tional hard disk. Finally, ~ince the di~k emulator has no mechanical or movinq parts and since the novel error correc-tion process corrects hard memory failures, the reliability of the disk e ulator should be significantly better than the 25 reliability of prior art hard disks. While one embodiment of this invention have been disclosed, it should be understood that the present disclosure merely exemplifies the principles of the invention and is not intended to limit the invention to embodiment~ illustrated. From the present disclosure, 3~ other embodiments and advantages of the invention will be apparent to one skilled in the art.

;. ' .:"
.`'':

.

Claims

1. A data storage subsystem for storing and retrieving data used by a central processor, said subsystem comprising:
a disk emulator including a volatile storage medium having data storage locations therein; and disk controller means, operatively connected to said central processor and to said disk emulator, for controlling data storage and retrieval from said disk emulator, wherein;
said disk controller means (i) specifies the location within said volatile storage medium where data is to be stored and from which stored data is to be retrieved, by means of geometric address information, (ii) provides to said disk emulator a serial data stream comprised of bits of data to be stored in said volatile storage medium, (iii) accepts stored data from said disk emulator as a serial data stream comprised of bits of data, and (iv) provides control signals to said disk emulator; and said disk emulator further comprises:
serialiser/deserialiser means, operatively coupled to said disk controller means, for (i) receiving said serial data from said disk controller means and providing parallel data on data lines, and (ii) receiving parallel data on said data lines and providing serial data to said disk controller means;
temporary data storage means, operatively coupled to said serializer/deserialiser data lines and to said volatile storage medium, for receiving data input signals and subsequently generating data output signals, said temporary data storage means having a control input line;
wherein in a first mode of operation of said disk emulator, said parallel data signals from said serializer/deserializer means, are provided to said temporary data storage means and said data output signals from said temporary data storage means are provided to said volatile storage medium; and in a second mode of operation of said disk emulator, data signals from said volatile storage medium are provided to said temporary data storage means and said data output signals from said temporary data storage means are provided to the data lines of said serializer/deserializer means;
addressing means, operatively coupled to said disk controller means, for generating an address signal for a specified location in said volatile storage medium in response to a first control signal and said geometric address information from said disk controller means;
data storage control means, operatively coupled to said disk controller means, to said serializer /deserializer means, to said control input line of said temporary data storage means, to said volatile storage medium, and to said addressing means, for (i) selectively connecting said parallel data signals of said serializer/deserializer means to said temporary data storage means, and (ii) selectively connecting said data output signals of said temporary data storage means to said specified location in said volatile storage medium in response to said address signal and a second control signal from said disk controller means; and data retrieval control means, operatively coupled to said control input line of said temporary data storage means, to said serializer/deserializer means, to said volatile storage medium, to said addressing means, and to said disk controller means, for (i) selectively connecting said temporary data storage means to said specified location in said volatile storage medium in response to the address signal from said addressing means, and (ii) selectively connecting said temporary data storage means to said data lines of said serializer/deserializer means in response to a third control signal from said disk controller means.

2. A system as in Claim 1 wherein said addressing means further comprises:
data receiving means, operatively coupled to said disk controller means, for receiving said geometric addresses.

3. A system as in Claim 2 wherein said addressing means further comprises means, operatively coupled to said data receiving means, for translating said geometric addresses to a high order address for a first contiguous region of said volatile storage medium wherein said first contiguous region comprises r contiguous storage locations in said volatile storage medium where r is a first selected integer.

4. A system as in Claim 3 wherein said parallel data of said serializer/deserializer means comprise n-bit words, where n is a second selected integer.

5. A system as in Claim 4 wherein said addressing means further comprises means, operatively coupled to said translation means, for generating lower order addresses for said first contiguous region of said volatile storage medium, said lower address generating means comprising:
means for generating addresses for second contiguous regions of said volatile storage medium within said first contiguous region wherein each of said second contiguous regions comprises m contiguous (n+1)-bit words, where m is a third selected integer;
and means for generating addresses for m contiguous word locations of said volatile storage medium within said second contiguous region wherein said specified location is defined by said high order address and said lower order addresses.

6. A system as in Claim 5 wherein said operative coupling between said data lines of said serializer/
deserializer means, said temporary data storage means, and said volatile storage medium comprises a parallel bus.

7. A system as in Claim 6 wherein said disk emulator further comprises;
means, operatively coupled to said parallel bus, for generating a parity signal wherein in said first mode of operation of said disk emulator, said parallel bus simultaneously provides said data output signals from said means for temporary data storage to said means for generating a parity signal and to said volatile storage medium, and in response to said data output signals, said means for generating a parity signal generates a parity output signal and said parity output signal is provided to said volatile storage medium by said parallel bus.

8. A system as in Claim 7 wherein said parity output signal is stored in said volatile storage medium as a bit of said (n+1)-bit word.

9. A system as in Claim 1 wherein said first mode of operation of said disk emulator has a substantially zero seek delay time.

10. A system as in Claim 1 wherein said second mode of operation of said disk emulator has a substantially zero seek delay time.

11. A data storage subsystem for storing and retrieving data used by a central processor, said subsystem comprising:
a disk emulator including a volatile storage medium having data storage locations therein; and a disk controller, operatively coupled to said central processor and to said disk emulator, to control data storage and retrieval from said disk emulator, wherein;
said disk controller (i) specifies the location within said volatile storage medium where data is to be stored and from which stored data is to be retrieved by means of geometric address information, (ii) provides to said disk emulator a serial data stream comprised of bits of data to be stored in said volatile storage medium, (iii) accepts stored data from said disk emulator as a serial data stream comprised of bits of data, and (iv) provides control signals to said disk emulator wherein said serial data stream comprises sectors, each of said sectors being comprised of sector-specific data and nonsector-specific data; and said disk emulator further comprising:
serializer/deserializer means, operatively coupled to said disk controller, for (i) receiving said serial data from said disk controller and providing parallel data on data lines and (ii) receiving parallel data on said data lines and providing serial data to said disk controller wherein said parallel data comprises an n-bit word, where n is a first selected integer;
temporary data storage means, operatively coupled to said serializer/deserializer means data lines, and to said volatile storage medium, for receiving data input signals and subsequently generating data output signals, said temporary data storage means having a control input line;
wherein in a first mode of operation of said disk emulator, said n-bit word is provided to said temporary data storage means and said data output signals from said temporary data storage means are transferred to said volatile storage medium; and in a second mode of operation of said disk emulator, data signals from said volatile storage medium are provided to said temporary data storage means and said data output signals from said temporary data storage means are provided to the data lines of said serializer/deserializer means;
parallel bus means comprising said operative coupling between said data lines of said serializer/deserializer means, said temporary data storage means and said volatile storage medium;
addressing means, operatively coupled to said disk controller, for generating an address signal for a specified location in said volatile storage medium in response to a first control signal and said geometric address information from said disk controller wherein said addressing means further comprises:
data receiving means, operatively coupled to said disk controller, for receiving said geometric address information;
means, operatively coupled to said data receiving means, for translating said geometric address information to a high order address for a first contiguous region of said volatile storage medium wherein said first contiguous region comprises r contiguous storage locations in said volatile storage medium where r is a second selected integer; and means for generating lower order addresses for said first contiguous region of said volatile storage medium comprising;
means for generating addresses for second contiguous regions of said volatile storage medium within said first contiguous region wherein each of said second contiguous regions comprises m contiguous (n+1)-bit words, where m is a third selected integer; and means for generating addresses for m contiguous word locations of said volatile storage medium within said second contiguous region wherein said specified location is defined by said high order address and said lower order addresses;
means, operatively coupled to said parallel bus means, for generating a parity signal, wherein in said first mode of operation of said disk emulator, said parallel bus means simultaneously provides said data output signals from said temporary data storage means to said means for generating a parity signal and to said volatile storage medium, and in response to said data output signals, said means for generating a parity signal generates a parity output signal and said parity output signal is provided to said volatile storage medium by said parallel bus means wherein said parity output signal is stored in said volatile storage medium as a bit of said (n+1)-bit word;
data storage control means, operatively coupled to said disk controller, to said serializer/deserializer means, to said control input line of said temporary data storage means, to said volatile storage medium, and to said addressing means, for (i) selectively connecting said parallel data signals of said serializer/deserializer means to said temporary data storage means, and (ii) selectively connecting said data output signals of said temporary data storage means to said specified location in said volatile storage medium in response to the address signal and a second control signal from said disk controller;
data retrieval control means, operatively coupled to said control input line of said temporary data storage means, to said serializer/deserializer means, to said volatile storage medium, to said addressing means and to said disk controller, for (i) selectively connecting said temporary data storage means to said specified location in said volatile storage medium in response to the address signal from said addressing means, and (ii) selectively connecting said temporary data storage means to said serializer/deserializer means data lines in response to a third control signal from said disk controller; and means, operatively coupled to said data storage control means and to said parallel bus means, for selecting sector specific data for storage in said temporary data storage means wherein said parallel data signals from said serializer/deserializer means are provided to said means for selecting sector specific data, and said means for selecting sector specific data, in response to a pattern of parallel data signals from said serializer/deserializer means indicating the initiation of sector specific data, generates an output signal to said data storage control means.

12. A system as in Claim 11 wherein said data storage control means, further comprises means, responsive to said output signal of said means for selecting sector specific data, for generating a sequence of control signals to said addressing means, to said serializer/deserializer means, and to said means for temporary data storage so that said sector specific data from said disk controller are stored in said volatile storage medium.

13. A system as in Claim 12, said second mode of operation further comprising said parallel bus means simultaneously providing said data signals retrieved from said volatile storage medium to said temporary data storage means and to said means for generating a parity signal and in turn said means for generating a parity signal generates a parity output signal for said retrieved data signals.

14. A system as in Claim 13 wherein said parity generating means generates a parity signal for n-bits of a retrieved (n+1)-bit word wherein n-bits of said retrieved (n+1)-bit word comprise said stored data from said disk controller.

15. A system as in Claim 14 said parallel bus means further comprising a parity line wherein said stored parity signal is retrieved from said volatile storage medium on said parity line of said parallel bus means.

16. A system as in Claim 15 wherein said disk emulator further comprises means, operatively coupled to said parity line and to said parity generating means, for co paring parity signals wherein said parity signal generated for said n-bits of said retrieved word is compared with said retrieved parity signal and an output signal is generated upon said parity signals being different.

17. A system as in Claim 16 wherein said disk emulator further comprises means, operatively coupled to said temporary data storage means, to said data retrieval control means and to said means for comparing parity signals, for error correcting an n-bit word wherein said means for error correcting is activated only upon receipt of said output signal of said means for comparing, and upon activation, said error correcting means corrects said retrieved n-bit word.

18. A system as in Claim 17 wherein said disk emulator further comprises:
means, operatively coupled to said serializer/
deserializer means and to said data retrieval control means, for generating a nonsector specific serial data stream wherein said data retrieval control means generates a sequence of signals to said addressing means, to said serializer/deserializer means, to said temporary data storage means, and to said means for generating a nonsector specific serial data stream and in turn said serial data stream provided to said disk controller comprises a sector having nonsector specific data provided by said means for generating nonsector specific data and sector specific data retrieved from said volatile storage medium.

19. A system as in Claim 18 wherein said disk controller comprises a SMD disk controller.

20. A system as in Claim 18 wherein said volatile storage medium comprises a DRAM array.

21. A system as in Claim 11 wherein said first mode of operation of said disk emulator has a substantially zero seek delay time.

22. A system as in Claim 11 wherein said second mode of operation of said disk emulator has a substantially zero seek delay time.

23. A disk emulator for (i) receiving control signals and data from a disk controller and in response thereto storing said data in said disk emulator and (ii) upon request via control signals from such a disk controller providing said stored data to said disk controller, wherein such a disk controller specifies a storage location for the data within said disk emulator by means of geometric address information, and further wherein such a disk controller provides data to and receives data from said disk emulator as a serial data stream, said disk emulator comprising:
a volatile storage medium having storage locations;
means, operatively couplable to such a disk controller, for receiving serial data from such a disk controller and for providing serial data to such a disk controller; and means, operatively coupled to said volatile storage medium and to said receiving/providing serial data means, for storing and retrieving data;
wherein in a first mode of operation, in response to first control signals from such a disk controller, said means for storing and retrieving data stores said received serial data at a location in said volatile storage medium corresponding to said geometric address information; and in a second mode of operation, in response to second control signals from such a disk controller said means for storing and retrieving data retrieves data at a location in said volatile storage medium corresponding to said geometric address information and provides said retrieved data to said receiving/providing serial data means wherein in turn said receiving/providing serial data means provides said retrieved data as a serial data stream to such a disk controller.

24. A disk emulator as in Claim 23 wherein said means for receiving serial data and providing serial data further comprises:
serializer/deserializer means for (i) receiving serial data from such a disk controller and providing parallel data on parallel data lines of said serializer/deserializer means and for (ii) receiving parallel data on said parallel data lines and providing a serial data stream to such a disk controller.

25. A disk emulator as in Claim 24 wherein said means for storing and retrieving data further comprises:
temporary data storage means, operatively coupled to said serializer/deserializer parallel data lines and to said volatile storage medium, for receiving data input signals and subsequently generating data output signals, said temporary data storage means having a control input line;
wherein in said first mode of operation of said disk emulator, said parallel data from said serializer/deserializer means, are provided to said temporary data storage means and said data output signals from said temporary data storage means are provided to said volatile storage medium; and in said second mode of operation of said disk emulator, data signals from said volatile storage medium are provided to said temporary data storage means and said data output signals from said temporary data storage means are provided to the parallel data lines of said serializer/deserializer means;
addressing means, operatively couplable to such a disk controller, for generating an address signal for a specified location in said volatile storage medium in response to said geometric address information and a first control signal from such a disk controller;
data storage control means, operatively couplable to such a disk controller, and operatively coupled to said serializer/deserializer means, to said control input line of said temporary data storage means, to said volatile storage medium and to said addressing means, for (i) selectively connecting said parallel data signals of said serializer/deserializer means to said temporary data storage means and (ii) selectively connecting said data output signals of said temporary data storage means to said specified location in said volatile storage medium; and data retrieval control means, operatively coupled to said control input line of said temporary data storage means, to said serializer/deserializer means, to said volatile storage medium, to said addressing means, and operatively couplable to such a disk controller, for (i) selectively connecting said temporary data storage means to said specified location in said volatile storage medium and (ii) selectively connecting said temporary data storage means to said parallel data lines of said serializer/
deserializer means.

26. A disk emulator as in Claim 25 wherein said addressing means further comprises data receiving means, operatively couplable to such a disk controller, for receiving said geometric address information from such a disk controller.

27. A disk emulator as in Claim 26 wherein said addressing means further comprises means, operatively coupled to said data receiving means, for translating said geometric address information to a high order address for a first contiguous region of said volatile storage medium wherein said first contiguous region comprises r contiguous storage locations in said volatile storage medium where r is a first selected integer.

28. A disk emulator as in Claim 27 wherein said parallel data of said serializer/deserializer means comprise n-bit words, where n is a second selected integer.

29. A disk emulator as in Claim 28 wherein said addressing means further comprises means, operatively coupled to said translation means, for generating lower order addresses for said first contiguous region of said volatile storage medium, said lower address generating means comprising:
means for generating addresses for second contiguous regions of said volatile storage medium within said first contiguous region wherein each of said second contiguous regions comprises m contiguous (n+1)-bit words, where m is a third selected integer;
and means for generating addresses for m contiguous word locations of said volatile storage medium within said second contiguous region wherein said specified location is defined by said high order address and said lower order addresses.

30. A disk emulator as in Claim 29 wherein said operative coupling between said parallel data lines of said serializer/deserializer means, said temporary data storage means, and said volatile storage medium comprises a parallel bus.

31. A disk emulator as in Claim 30 further comprising;
means, operatively coupled to said parallel bus, for generating a parity signal wherein said first mode of operation of said disk emulator, said parallel bus simultaneously provides said data output signals from said means for temporary data storage to said means for generating a parity signal and to said volatile storage medium, and in response to said data output signals, said means for generating a parity signal generates a parity output signal and said parity output signal is provided to said volatile storage medium by said parallel bus.

32. A disk emulator as in Claim 31 wherein said parity output signal is stored in said volatile storage medium as a bit of said (n+1)-bit word.

33. A disk emulator as in Claim 23 wherein said first mode of operation of said disk emulator has a substantially zero seek delay time.

34. A disk emulator as in Claim 23 wherein said second mode of operation of said disk emulator has a substantially zero seek delay time.

35. A disk emulator for (i) receiving control signals and data from a disk controller and in response thereto storing said data in said disk emulator and (ii) upon request via control signals from such a disk controller, providing said stored data to said disk controller, wherein such a disk controller specifies a storage location for the data within said disk emulator by means of geometric address information, and further wherein such a disk controller provides data to and receives data from said disk emulator as a serial data stream, and serial data stream comprises sectors wherein each of said sectors is comprised of sector-specific data and nonsector-specific data, said disk emulator comprising:
a volatile storage medium having data storage locations wherein;
serializer/deserializer means, operatively couplable to such a disk controller, for (i) receiving said serial data from such a disk controller and providing parallel data on parallel data lines of said serializer/deserializer means and (ii) receiving parallel data on said parallel data lines and providing a serial data stream to such a disk controller, wherein said parallel data comprises an n-bit word, where n is a first selected integer;
temporary data storage means, operatively coupled to said serializer/deserializer parallel means data lines, and to said volatile storage medium, for receiving data input signals and subsequently generating data output signals, said temporary data storage means having a control input line;
wherein in a first mode of operation of said disk emulator, said n-bit word is provided to said temporary data storage means and said data output signals from said temporary data storage means are transferred to said volatile storage medium; and in a second mode of operation of said disk emulator, data signals from said volatile storage medium are provided to said temporary data storage means and said data output signals from said temporary data storage means are provided to the parallel data lines of said serializer/deserializer means and in turn said serializer/deserializer provides serial data to such a disk controller;
parallel bus means comprising said operative coupling between said parallel data lines of said serializer/deserializer means, said temporary data storage means and said volatile storage medium;
addressing means, operatively couplable to such a disk controller, for generating an address signal for a specified location in said volatile storage medium in response to a first control signal and said geometric address information from such a disk controller wherein said addressing means further comprises:
data receiving means, operatively couplable to such a disk controller, for receiving said geometric address information;
means, operatively coupled to said data receiving means, for translating said geometric address information to a high order address for a first contiguous region of said volatile storage medium wherein said first contiguous region comprises r contiguous storage locations in said volatile storage medium where r is a second selected integer; and means for generating lower order addresses for said first contiguous region of said volatile storage medium, said lower order addresses generating means comprising;

means for generating addresses for second contiguous regions of said volatile storage medium within said first contiguous region wherein each of said second contiguous regions comprises m contiguous (n+1)-bit words, where m is a third selected integer; and means for generating addresses for m contiguous word locations of said volatile storage medium within said second contiguous region wherein said specified location is defined by said high order address and said lower order addresses;
means, operatively coupled to said parallel bus means, for generating a parity signal, wherein in said first mode of operation of said disk emulator, said parallel bus means simultaneously provides said data output signals from said temporary data storage means to said means for generating a parity signal and to said volatile storage medium, and in response to said data output signals, said means for generating a parity signal generates a parity output signal and said parity output signal is provided to said volatile storage medium by said parallel bus means wherein said parity output signal is stored in said volatile storage medium as a bit of said (n+1)-bit word;
data storage control means, operatively couplable to said disk controller, to said serializer/deserializer means, to said control input line of said temporary data storage means, to said volatile storage medium, and to said addressing means, for (i) selectively connecting said parallel data signals of said serializer/deserializer means to said temporary data storage means, and (ii) selectively connecting said data output signals of said temporary data storage means to said specified location in said volatile storage medium;
data retrieval control means, operatively coupled to said control input line of said temporary data storage means, to said serializer/deserializer means, to said volatile storage medium, to said addressing means and operatively couplable to such a disk controller, for (i) selectively connecting said temporary data storage means to said specified location in said volatile storage medium, and (ii) selectively connecting said temporary data storage means to said serializer/deserializer means parallel data lines; and means, operatively coupled to said data storage control means and to said parallel bus means, for selecting sector specific data for storage in said temporary data storage means wherein said parallel data signals from said serializer/deserializer means are provided to said means for selecting sector specific data, and said means for selecting sector specific data, in response to a pattern of parallel data signals from said serializer/deserializer means indicating the initiation of sector specific data, generates an output signal to said data storage control means.

36. A disk emulator as in Claim 35 wherein said data storage control means further comprises means, responsive to said output signal of said means for selecting sector specific data, for generating a sequence of control signals to said addressing means, to said serializer/deserializer means, and to said means for temporary data storage so that said sector specific data from such a disk controller are stored in said volatile storage medium.

37. A disk emulator as in Claim 36, said second mode of operation further comprising said parallel bus means simultaneously providing said data signals retrieved from said volatile storage medium to said temporary data storage means and to said means for generating a parity signal and in turn said means for generating a parity signal generates a parity output signal for said retrieved data signals.

38. A disk emulator as in Claim 37 wherein said parity generating means generates a parity signal for n-bits of a retrieved (n+1)-bit word wherein n-bits of said retrieved (n+1)-bit word comprise said stored data from said disk controller.

39. A disk emulator as in Claim 38 said parallel bus means further comprising a parity line wherein said stored parity signal is retrieved from said volatile storage medium on said parity line of said parallel bus means.

40. A disk emulator as in Claim 39 further comprising means, operatively coupled to said parity line and to said parity generating means, for comparing parity signals wherein said parity signal generated for said n-bits of said retrieved word is compared with said retrieved parity signal and an output signal is generated upon said parity signals being different.

41. A disk emulator as in Claim 40 further comprising means, operatively coupled to said temporary data storage means, to said data retrieval control means and to said means for comparing parity signals, for error correcting an n-bit word wherein said means for error correcting is activated only upon receipt of said output signal of said means for comparing, and upon activation, said error correcting means corrects said retrieved n-bit word.

42. A disk emulator as in Claim 41 further comprising:
means, operatively coupled to said serializer/
deserializer means and to said data retrieval control means, for generating a nonsector specific serial data stream wherein said data retrieval control means generates a sequence of signals to said addressing means, to said serializer/deserializer means, to said temporary data storage means, and to said means for generating a nonsector specific serial data stream and in turn said serial data stream provided to such a disk controller comprises a sector having nonsector specific data provided by said means for generating nonsector specific data and sector specific data retrieved from said volatile storage medium.

43. A disk emulator as in Claim 42 wherein such a disk controller comprises a SMD disk controller.

44. A disk emulator as in Claim 42 wherein said volatile storage medium comprises a DRAM array.

45. A disk emulator as in Claim 23 wherein said means for receiving serial data and providing serial data comprises:
data input/output means having a serial data input line for receiving serial data from such a disk controller, a serial data output line for providing serial data to such a disk controller, a serial data path through said data input/output means connecting said serial data input line and said serial data output line, data input/output lines, and a control input line;
wherein in said first mode of operation of said disk emulator, said data input/output means being responsive to control signals on said control input line to receive data on serial data input line and to provide output signals on said input/output lines; and in said second mode of operation of said disk emulator, said data input/output means being responsive to control signals on said control input line to receive data on said data input/output lines and to provide serial data on said serial output line.

46. A disk emulator as in Claim 45 wherein said means for storing and retrieving data comprises:
temporary data storage means, operatively coupled to said data input/output lines of said data input/output means and to said volatile storage medium, for receiving data input signals and subsequently generating data output signals, said temporary data storage means having a control input line;
wherein in said first mode of operation of said disk emulator, said data output signals from said data input/output means are provided to said temporary data storage means and in turn, said data output signals from said temporary data storage means are transferred to said volatile storage medium; and in said second mode of operation of said disk emulator, data signals from said volatile storage medium are provided to said temporary data storage means and in turn, said output signals from said temporary data storage means are provided to said data input/output lines of said data input/output means;
addressing means, operatively couplable to such a disk controller, for generating an address signal for a specified location in said volatile storage medium in response to said geometric address information and a first control signal from such a disk controller;
data storage control means, operatively coupled to said control input line of said data input/output means, to said control input line of said temporary storage means, to said volatile storage medium and to said addressing means, for (i) selectively connecting said data output signals of said data input/output means to said temporary data storage means; and (ii) selectively connecting said data output signals of said temporary data storage means to said specified location in said volatile storage medium; and data retrieval control means, operatively coupled to said input control line of said means for temporary data storage, to said control input line of said data input/output means, to said volatile storage medium, and to said addressing means, for (i) selectively connecting said temporary data storage means to said specified location in said volatile storage medium and (ii) selectively connecting said temporary data storage means to said data input/output means.

47. A disk emulator as in Claim 46 wherein said addressing means further comprises:
data receiving means, operatively couplable to such a disk controller, for receiving said geometric address information.

48. A disk emulator as in Claim 47 wherein said addressing means further comprises means, operatively coupled to said data receiving means, for translating said geometric address information to a high order address for a first contiguous region of said volatile storage medium wherein said first contiguous region comprises r contiguous storage locations in said volatile storage medium where r is a first selected integer.

49. A disk emulator as in Claim 48 wherein said data output signals of said data input/output means comprise n-bit words, where n is a second selected integer.

50. A disk emulator as in Claim 49 wherein said addressing means further comprises means, operatively coupled to said translation means, for generating lower order addresses for said first contiguous region of said volatile storage medium, said lower address generating means comprising:
means for generating addresses for second contiguous regions of said volatile storage medium within said first contiguous region wherein each of said second contiguous regions comprises m contiguous (n+1)-bit words, where m is a third selected integer;
and means for generating addresses for m contiguous word locations of said volatile storage medium within said second contiguous region wherein said specified location is defined by said high order address and said lower order addresses.

51. A disk emulator as in Claim 50 wherein said operative connection between data input/output lines of said data input/output means, said temporary data storage i means and said volatile storage medium comprises a parallel bus.

52. A disk emulator as in Claim 51 further comprising;
means, operatively coupled to said parallel bus, for generating a parity signal wherein in said first mode of operation of said disk emulator, said parallel bus simultaneously provides said data output signals from said means for temporary data storage to said means for generating a parity signal and to said volatile storage medium, and in response to said data output signals, said means for generating a parity signal generates a parity output signal and said parity output signal is provided to said volatile storage medium by said parallel bus.

53. A disk emulator as in Claim 52 wherein said parity output signal is stored in said volatile storage medium as a bit of said (n+1)-bit word.

54. A disk emulator as in Claim 35 wherein said first mode of operation of said disk emulator has a substantially zero seek delay time.

55. A disk emulator as in Claim 35 wherein said second mode of operation of said disk emulator has a substantially zero seek delay time.

56. A disk emulator for (i) receiving control signals and data from a disk controller and in response thereto storing said data in said disk emulator and (ii) upon request via control signals from such a disk controller, providing said stored data to said disk controller, wherein such a disk controller specifies a storage location for the data within said disk emulator by means of geometric address information, and further wherein such a disk controller provides data to and receives data from said disk emulator as a serial data stream, and serial data stream comprises sectors wherein each of said sectors is comprised of sector-specific data and nonsector-specific data, said disk emulator comprising:
a volatile storage medium having data storage locations therein;
data input/output means having a serial data input line for receiving serial data from such a disk controller, a serial data output line for providing serial data to such a disk controller, a serial data path through said data input/output means connecting said serial data input line and said serial data output line, data input/output lines, and a control input line;
wherein in a first mode of operation of said disk emulator, said data input/output means being responsive to control signals on said control input line to receive data on said serial data input line and to provide output signals on said input/output lines, said output signals comprising n-bit words, where n is a first selected integer; and in a second mode of operation of said disk emulator, said data input/output means being responsive to control signals on said control input line to receive data on said data input/output lines and to provide serial data on said serial output line;
temporary data storage means, operatively coupled to said data input/output lines of said data input/output means, and to said volatile storage medium, for receiving data input signals and subsequently generating data output signals, said temporary data storage means having a control input line;
wherein in said first mode of operation of said disk emulator, said n-bit word is provided to said temporary data storage means and in turn, said data output signals from said temporary data storage means are transferred to said volatile storage medium; and in said second mode of operation of said disk emulator, data signals from said volatile storage medium are provided to said temporary data storage means and in turn, said data output signals from said temporary data storage means are provided to the data input/output lines of said data input/output means;
parallel bus means comprising said operative coupling between said data input/output lines of said data input/output means, said temporary data storage means and said volatile storage medium;
addressing means, operatively couplable to such a disk controller, for generating an address signal for a specified location in said volatile storage medium in response to a first control signal and said geometric address information from such a disk controller wherein said addressing means further comprises:
data receiving means, operatively couplable to such a disk controller, for receiving said geometric address information;
means, operatively coupled to said data receiving means, for translating said geometric address information to a high order address for a first contiguous region of said volatile storage medium wherein said first contiguous region comprises r contiguous storage locations in said volatile storage medium where r is a second selected integer; and means for generating lower order addresses for said first contiguous region of said volatile storage medium, said lower order addresses generating means comprising;
means for generating addresses for second contiguous regions of said volatile storage medium within said first contiguous region wherein each of said second contiguous regions comprises m contiguous (n+1)-bit words, where m is a third selected integer; and means for generating addresses for m contiguous word locations of said volatile storage medium within said second contiguous region wherein said specified location is defined by said high order address and said lower order addresses;
means, operatively coupled to said parallel bus means, for generating a parity signal, wherein in said first mode of operation of said disk emulator, said parallel bus means simultaneously provides said data output signals from said temporary data storage means to said means for generating a parity signal and to said volatile storage medium, and in response to said data output signals, said means for generating a parity signal generates a parity output signal and said parity output signal is provided to said volatile storage medium by said parallel bus means wherein said parity output signal is stored in said volatile storage medium as a bit of said (n+1)-bit word;
data storage control means, operatively couplable to said disk controller, to said control input line of said input/output means, to said control input line of said temporary data storage means, to said volatile storage medium, and to said addressing means, for (i) selectively connecting said data output signals of said data input/output means to said temporary data storage means, and (ii) selectively connecting said data output signals of said temporary data storage means to said specified location in said volatile storage medium;
data retrieval control means, operatively coupled to said control input line of said temporary data storage means, to said control input line of said data input/output means, to said volatile storage medium, to said addressing means, for (i) selectively connecting said temporary data storage means to said specified location in said volatile storage medium, and (ii) selectively connecting said temporary data storage means to said data input/output lines of said data input/output means; and means, operatively coupled to said data storage control means and to said parallel bus means, for selecting sector specific data for storage in said temporary data storage means wherein said data output signals from said data input/output means are provided to said means for selecting sector specific data, and said means for selecting sector specific data, in response to a pattern of parallel data output signals from said data input/output means indicating the initiation of sector specific data, generates an output signal to said data storage control means.

57. A disk emulator as in Claim 56 wherein said data storage control means further comprises means, responsive to said output signal of said means for selecting sector specific data, for generating a sequence of control signals to said addressing means, to said data input/output means, and to said means for temporary data storage so that said sector specific data from such a disk controller are stored in said volatile storage medium.

58. A disk emulator as in Claim 57, said second mode of operation further comprising said parallel bus means simultaneously providing said data signals retrieved from said volatile storage medium to said temporary data storage means and to said means for generating a parity signal and in turn said means for generating a parity signal generates a parity output signal for said retrieved data signals.

59. A disk emulator as in Claim 58 wherein said parity generating means generates a parity signal for n-bits of a retrieved (n+1)-bit word wherein n-bits of said retrieved (n+1)-bit word comprise said stored data from said disk controller.

60. A disk emulator as in Claim 59 said parallel bus means further comprising a parity line wherein said stored parity signal is retrieved from said volatile storage medium on said parity line of said parallel bus means.

61. A disk emulator as in Claim 60 further comprising means, operatively coupled to said parity line and to said parity generating means, for comparing parity signals wherein said parity signal generated for said n-bits of said retrieved word is compared with said retrieved parity signal and an output signal is generated upon said parity signals being different.

62. A disk emulator as in Claim 61 further comprising means, operatively coupled to said temporary data storage means, to said data retrieval control means and to said means for comparing parity signals, for error correcting an n-bit word wherein said means for error correcting is activated only upon receipt of said output signal of said means for comparing, and upon activation, said error correcting means corrects said retrieved n-bit word.

63. A disk emulator as in Claim 62 further comprising:
means, operatively coupled to said data input/output means and to said data retrieval control means, for generating a nonsector specific serial data stream wherein said data retrieval control means generates a sequence of signals to said addressing means, to said data input/output means, to said temporary data storage means, and to said means for generating a nonsector specific serial data stream and in turn said serial data stream provided to such a disk controller comprises a sector having nonsector specific data provided by said means for generating nonsector specific data and sector specific data retrieved from said volatile storage medium.

64. A disk emulator as in Claim 63 wherein such a disk controller comprises a SMD disk controller.

65. A disk emulator as in Claim 63 wherein said volatile storage medium comprises a DRAM array.

66. A disk emulator as in Claim 56 wherein said first mode of operation of said disk emulator has a substantially zero seek delay time.

67. A disk emulator as in Claim 56 wherein said second mode of operation of said disk emulator has a substantially zero seek delay time.

68. A method for correcting single bit hard errors in a stored digital data word of "n" bits, where n is a selected integer, comprising the steps of:
a) generating a parity bit for said n-bit word according to a predetermined algorithm prior to storing said word;
b) storing said digital data word in a selected storage location;
c) storing said parity bit;
d) retrieving said stored n-bit word from said selected storage location;
e) retrieving the stored parity bit for said n-bit word;
f) generating a new parity bit for said retrieved word according to said predetermined algorithm;
g) comparing said new parity bit with said retrieved parity bit; and h) error correcting said n-bit retrieved word only when said parity bits are different.

69. A method as in Claim 68 wherein said error correcting step comprises:
a) inverting said retrieved word;
b) writing said inverted word to said selected storage location;
c) retrieving said word from said selected storage location; and d) inverting said word retrieved from said selected location.

70. A solid state data storage system, adapted to be connected to a disk controller, for storing and retrieving data comprising:
n-bit shift register means, where n is a selected integer, having a serial input terminal for receiving data from such a disk controller, a serial output terminal for providing data to such a disk controller, a serial data path through said n-bit shift register means connecting said serial input terminal and said serial output terminal, parallel data input/output terminals for each bit of said n-bit shift register means, and a control input line;
n-bit latch means having parallel data input/output terminals for each bit of said n-bit latch means and a control input line;
solid state memory means adapted to store n-bit words and having parallel data input/output terminals for each bit of said n-bit words;
parallel bus means, operatively interconnecting said parallel data input/output terminals of said n-bit shift register means with said parallel data input/output terminals of said n-bit latch means and with said parallel data input/output terminals of said solid state memory means;
memory address selector means, operatively connected to said solid state memory means, for receiving (i) a first input signal comprising a high order address for said solid state memory means, and (ii) a second input signal comprising a low order address for said solid state memory means wherein said memory address selector means selectively connects said parallel bus means to the region of said solid state memory means corresponding to said input signals;
address translation means, operatively connected to such a disk controller and to said memory address selector means, for generating an output signal in response to geometric address information from such a disk controller wherein said output signal comprises said first input signal to said memory address selector means;
control means, operatively connected to such a disk controller, to said memory address selector means, to said solid state memory means, to said control input line of said n-bit latch means, for (i) generating signals to said n-bit shift register means, said n-bit latch means, said memory address selector means, and said solid state memory means to store data as n-bit words in said solid state memory means and to retrieve data from said solid state memory means; and (ii) in response to signals from such a disk controller, generating said second input signal for said memory selector address means.

71. A system as in Claim 70 wherein a serial data stream from such a disk controller comprises sectors and each of said sectors includes sector specific data and nonsector specific data.

72. A system as in Claim 71 further comprising:
means, operatively connected to said control means, said parallel bus means, and said n-bit shift register means, for selecting sector specific data for storage in said n-bit latch means wherein said means for selecting sector specific data, in response to a pattern of data output signals from said n-bit shift register means indicating the initiation of sector specific data, generates an output signal to said control means.

73. A system as in Claim 72 wherein said control means further comprises means, responsive to said output signal of said means for selecting sector specific data, for generating a sequence of control signals to said memory address selector means, to said n-bit shift register means and to said n-bit latch means so that said sector specific data from such a disk controller is stored as said n-bit words in said solid state memory means.

74. A system as in Claim 73 wherein said solid state memory means further comprises means for storing an (n+1)-bit for each n-bit word and a parallel data input/output terminal for said (n+1)-bit.

75. A system as in Claim 74 further comprising means, operatively connected to said parallel bus means, for generating a parity bit wherein in a first mode of operation, said parity bit generating means generates a first parity bit for said n-bit word in said n-bit latch means and said first parity bit is stored in said (n+1)-bit storage means of said solid state memory means; and in a second mode of operation, said parity bit generating means generates a second parity bit for an n-bit word retrieved from said solid state memory means.

76. A system as in Claim 75 said parallel bus means further comprising a parity line wherein said stored first parity bit is retrieved from said solid state memory means on said parity line of said parallel bus means.

77. A system as in Claim 76 further comprising means, operatively connected to said parity line and to said parity generating means, for comparing parity bits wherein said second parity bit generated for said n-bit word retrieved from said solid state memory means is compared with said first parity bit and an output signal is generated upon said parity bits being different.

78. A system as in Claim 77 further comprising means, operatively coupled to said n-bit latch means, to said control means, and to said parity bit comparing means, for error correcting an n-bit word, wherein said error correcting means is activated only upon receipt of said output signal of said parity bit comparing means, and upon activation, said error correcting means corrects said retrieved n-bit word.

79. A system as in Claim 78 further comprising:
means, operatively connected to said serial output terminal of said n-bit shift register means and to said control means, for generating a nonsector specific serial data stream wherein said control means generates a sequence of signals to said memory address selector means, to said n-bit shift register means, to said means for generating a nonsector specific serial data stream, and to said n-bit latch means, and in turn said serial data stream provided to such a disk controller comprises a sector having nonsector specific data generated by said means for generating a nonsector specific serial data stream and sector specific data retrieved from said solid state memory means.

80. A system as in Claim 70 wherein such a disk controller comprises a SMD disk controller.

81. A system as in Claim 70 wherein said solid state memory means comprises a DRAM array.

82. A method for improving the access time for retrieving data for a disk controller and storing data from the disk controller wherein the disk controller specifies the location of said data by a geometric address, said method comprising the steps of:
providing a volatile storage medium having data storage locations therein;
providing serializer/deserializer means for (i) receiving serial data from said disk controller and providing parallel data on data lines and (ii) receiving parallel data on said data lines and providing serial data to said disk controller;
providing temporary data storage means for receiving parallel data input signals and subsequently generating parallel data output signals, said temporary data storage means having a control input line;
generating an address signal for a specified location in said volatile storage medium in response to a first control signal and said geometric address from said disk controller;
selectively connecting said data output signals of said temporary data storage means to said specified location in said volatile storage medium wherein said data output signals are stored in said volatile storage medium;

selectively connecting said temporary data storage means to said specified location in said volatile storage medium wherein said stored data in said specified location are stored in said temporary data storage means; and selectively connecting said temporary data storage means to said serializer/deserializer means wherein said stored data in said temporary storage means are stored in said serializer/deserializer and in turn provided to said disk controller as serial data;
wherein in storing data, said parallel data signals from said serializer/deserializer means are provided to said temporary data storage means and said data output signals from said temporary data storage means are provided to said volatile storage medium, said storage of data being performed with substantially zero seek time delay thereby improving the access time for storing data; and in retrieving data, data signals from said volatile storage medium are provided to said temporary data storage means and said data output signals from said temporary data storage means are provided to the data lines of said serializer/deserializer means and in turn said serializer/deserializer means provides said retrieved data as a serial data stream to said disk controller, said retrieving of data being performed with substantially zero seek time delay thereby improving the access time for retrieving data.

83. A method as in Claim 82 wherein said the step of generating said address signal further comprises translating said geometric address to a high order address for a first contiguous region of said volatile storage medium wherein said first contiguous region comprises r contiguous storage locations in said volatile storage medium where r is a first selected integer.

84. A method as in Claim 83 wherein said parallel data comprise n-bit words, where n is a second selected integer.

85. A method as in Claim 84 wherein said addressing step further comprises:
generating addresses for second contiguous regions of said volatile storage medium within said first contiguous region wherein each of said second contiguous regions comprises m contiguous (n+1)-bit words, where m is a third selected integer; and generating addresses for m contiguous word locations of said volatile storage medium within said second contiguous region wherein said specified location is defined by said high order address and said lower order addresses.

86. A method as in Claim 85 further comprising the step of providing a parallel bus for coupling together of said serializer/deserializer means, said temporary data storage means and said volatile storage medium.

87. A method as in Claim 86 further comprising the step of;
generating a parity signal wherein in said storing of data, said parallel bus simultaneously provides said parallel data output signals from said means for temporary data storage to said means for generating a parity signal and to said volatile storage medium, and in response to said data output signals, said means for generating a parity signal generates a parity output signal and said parity output signal is stored in said volatile storage medium.

88. A method as in Claim 87 wherein said data from said disk controller and said data provided to said disk controller comprise sectors of data and each sector of data includes sector-specific data and nonsector-specific data.

89. A method as in Claim 88 further comprising the step of:
selecting only sector specific data for storage in said temporary data storage means.

90. A method as in Claim 89 further comprising the step of:
generating a sequence of control signals to said addressing means, to said serializer/deserializer means and to said means for temporary data storage so that said sector specific data in said temporary data storage means are stored in said volatile storage medium.

91. a method as in Claim 90 further comprising the step of:
simultaneously providing n-bit word data signals retrieved from said volatile storage medium to said temporary data storage means and to said means for generating a parity signal wherein said means for generating a parity signal generates a parity output signal for said retrieved data signals.

92. A method as in Claim 91 further comprising the steps of retrieving said stored parity signal from said volatile storage medium.

93. A method as in Claim 92 further comprising the step of comparing said parity signal generated for said n-bits of said retrieved word with said retrieved parity signal and generating an output signal upon said parity signals being different.

94. A method as in Claim 93 further comprising the step of error correcting said n-bit retrieved word upon receipt of said output signal of said parity signal comparing step.

95. a method for improving the access time for reading data and writing data by a disk controller wherein the disk controller specifies the location of said data by a head and track geometric address, said method comprising the steps of:
issuing, with substantially zero seek time delay, a command to said disk controller indicating that a position, indicated by said head and track geometric addresses from said disk controller, has been located upon receipt of a command from said disk controller indicating the controller is ready to read or write data;
converting serial data from said disk controller to n-bit words after receiving a command from said disk controller to write data where n is a selected integer;
storing said n-bit words in a volatile storage medium;
retrieving stored n-bit words from said volatile storage medium after receiving from said disk controller a command to read data; and converting said retrieved n-bit words to a serial data stream that is provided to said disk controller.

96. A method as in Claim 95 further comprising, immediately after the command issuing step, the step of:
sequentially providing sector by sector to the disk controller a zeroth word of the sector until the disk controller issues one of the write command and the read command wherein the zeroth word for a sector specifies the address of the sector.