CA1335674C - Electronic filters, signal conversion apparatus, hearing aids and methods - Google Patents

Abstract

An electronic filter for filtering an electrical signal. Signal processing circuitry therein includes a logarithmic filter having a series of filter stages with inputs and outputs in cascade and respective circuits asso-ciated with the filter stages for storing electrical repre-sentations of filter parameters. The filter stages include circuits for respectively adding the electrical representa-tions of the filter parameters to the electrical signal to be filtered thereby producing a set of filter sum signals.
At least one of the filter stages includes circuitry for producing a filter signal in substantially logarithmic form at its output by combining a filter sum signal for that filter stage with a signal from an output of another filter stage. The signal processing circuitry produces an inter-mediate output signal, and a multiplexer connected to the signal processing circuit multiplexes the intermediate output signal with the electrical signal to be filtered so that the logarithmic filter operates as both a logarithmic prefilter and a logarithmic postfilter. Other electronic filters, signal conversion apparatus, electroacoustic sys-tems, hearing aids and methods are also disclosed.

Description

~ 64725-469 Cross-reference to Related Application The subject matter of the present application is related to Canadian Patent No. 1,326,285 for "Electronic Filters, Hearing Aids and Methods" issued January 18, 1994 to A. M.
Engebretson, one of the inventors herein, M. P. O'Connell and B~ Zheng.
Field of the Invention The present invention relates to electronic filters, signal conversion apparatus and methods of operation for electronic systems generally. Applications in electroacoustic systems such as hearing aids and public address systems are also discussed.
Background of the Invention Without limiting the scope of the present invention in general, the background of the invention is described by way of example in its application to hearing aids.
A person's ability to hear speech and other sounds well enough to understand them is clearly important in employment and many other daily life activities. Improvements in hearing aids which are intended to compensate or ameliorate hearing deficiencies of hearing impaired persons are conse~uently important not only to these persons but also to the community at large.
Electronic hearing aids and methods ~rediscussed in co-assigned U. S. Patent 4,548,082 by Engebretson (an inventor herein), Morley (an inventor herein) and Popelka. The hearing aid described in that patent is an example of an electronic system in which the present invention can be used.

. 64725-469 An article on electronic hearing aid problems by one of the present inventors (Morley) is "Breaking the frequency barrier" IEEE Potentials, February 1987, pp. 32-35.
"Digital Filtering Using Logarithmic Arithmetic" by No G. Kingsbury et al., Electronics Letters 7:56-58 (1971) discusses multiplication by adding logarithms, and using a read-only-memory to do addition and subtraction.

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Logarithmic analog-to-digltal and digital-analog conversion are mentioned.
"RC Logarithmic Analog-to-D;gital (LAD) Conver-sion" by E.J. Duke, IEEE ~ransactlons on Instrumentation and Measurement, February, 1971, utilizes an RC circuit approach to conversion.
"All-MOS Charge Redistribution Analog-to-Digital Conversion lechniques--Part II" by ~.E. Suarez et al., IEEE
J. Solid-State Circuits, vol. SC-10, pp. 379-385, Dec.
1975, describes a two-capacitor successive approximation technique for linear conversion of each bit in a digital word.
Moser U.S. Patent 4,187,413 describes a hearing a;d with a finite impulse response (FIR) filter and states that it can be implemented using only one multiplier in a time multiplexed configuration.
Steager U.S. Patent 4,508,940 suggests a hearing aid based on sampled-data analog circuits which has a plur-ality of parallel signal channels each including a ~andpass ilter, controlled gain amplifier with volume control, cir-cuits for non-linear signal processing and bandpass fil-ter.
Conventionally, a microphone in the hearing aid generates an electrical output from external sounds. An amplifying circuit in the aid provides a filtered version of the electrical output corresponding to the sounds picked up by the microphone. ~he filtering can be due to an inherent characteristic of the amplifying circuit or may be deliberately introduced. Ihe amplified and filtered output of the hearing aid is fed to an electrically driven "receiver" for emitting sound into the ear of the user of the hearing aid. (In the hearing aid field, a receiver is the name of an electronic element analogous to a loud-speaker or other electroacoustic transducer.) Some of the 8pd J CID 5513 PAIENI

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sound emitted by the receiver returns to the microphone to add a feedback contribution to the electrical output of the microphone. Ihe feedback ;.s amplifi.ed by the hearing aid, and ringing or squeal;.ng often arise in an endlessly cir-cular feedback process.
Ihe commercial viabili.ty of a hearing a;.d havingsophisticated performance features as described in coas-signed U.S. Patent 4,548,082 ;.s strongly ti.ed to the premise that electronic circuits can be reali.zed in which the total power consumption does not exceed a few milli-watts. Given the computationally i.ntensive nature of the signal processing required to implement filtering used .i.n shaping the desired frequency selective response as well as the power needed by numerous circuits needed for signal conversion and amplificat.lon, this is an extremely diffi-cult task. Only a few hundred microwatts are available for the filtering in a viable hearing aid.
Sophisticated performance requirements imply a massive computational burden. It is believed that millions of arithmetic calculations per second are probably needed in a sophisticated hearing aid. Generally speaking, elec-tronic circuitry dissipates more power as performance increases, unless basic improvements can be found.

Summary of the Invention Among the objects of the present invent;.on are to provide improved electronic filters, electronic signal conversion apparatus, hearing aids, and methods which can provide sophisticated features compatible with VLSI and low power constraints to provide new circuit subcombinations which can be used to i.mprove electronic systems generally to provide further improved electronic filters, electronic signal. conversion apparatus, hearing aids, and methods which substantially prevent undesirable feedback ringing and squealing; and to provide improved electronic filters, electronic signal conversion apparatus, hearing aids and other systems which are reliable, compact and economical.
Generally, one form of the invention is an electronic filter for filtering an electrical signal, comprising: a filter having an input for receiving a signal to be filtered, having an output producing a filtered signal and having signal processing means including logarithmic filter means producing an intermediate output signal; said filter having a plurality of filter stages having inputs and outputs coupled in cascade, each said filter stage filtering signals at its input according to electrical representations of filter parameters; electronic control means coupled to said filter for altering the electrical representations to vary a value of each of said filter parameters in substantially constant percentage amounts of the value of that one of said fil-ter parameters; each said filter stage having means connected to it for storing its electrical representations of filter para-meters; each said filter stage including means for adding its electrical representations of the filter parameters to the signal at its input thereby producing a filter sum signal; at least one of said filter stages including means for producing a filter sig-nal in logarithmic form at its output by combining its filter sum signal with a signal from the output of one of the other filter stages; and wherein said electronic filter further comprises means connected to said signal processing means for multiplexing its ~`

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intermediate output signal with the electrical signal to be fil-tered and for providing the multiplexed signal to the input of said filter whereby said logarithmic filter means operates as both a. logarithmic prefilter and a logarithmic postfilter.
Generally, another form of the invention is an electron-ic filter for filtering an electrical signal, comprising: a fil-ter having an input for receiving a signal to be filtered, having an output producing a filtered signal and having signal processing means including logarithmic filter means producing an intermediate output signal; said filter having a series of filter stage means having inputs and outputs coupled in cascade, each said filter stage means filtering signals at its input according to electrical representations of filter parameters; electronic control means coupled to said filter for altering the electrical representations to vary a value of each of said filter parameters in substantially constant percentage amount of the value of that one of said filter parameters; means for storing electrical representations of filter parameters for said filter stage means; and said series of filter stage means including means for filtering signals through the series of filter stage means from a first to a last of said filter stage means and then filtering signals back through said series of filter stage means from the last to the first of said filter stage means to produce the filtered signal.
Generally, a further form of the invention is an ~;
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1 3 3 S 6 7 ~ 6472 5-469 electronic filter for filtering an electrical signal having a polarity, comprising: a filter having an input for receiving a signal to be filtered, having an output producing a filtered sig-nal and having signal processing means including logarithmic fil-ter means producing an intermediate output signal; said filter having a plurality of filter stages having inputs and outputs coupled in cascade, each said filter stage respectively filtering input according to electrical representations of filter para-meters; said filter including means for filtering signals through the series of filter stages from a first to a last of said filter stages and then filtering signals back through said series of filter stages from the last to the first of said filter stages;
and electronic control means coupled to said filter for altering the electrical representations to vary a value of each of said filter parameters in substantially constant percentage amounts of the value of that one of said filter parameters.
In general, an additional form of the invention is an electronic filter for an electroacoustic system having microphone means for generating an electrical output from external sounds and electrically driven transducer means for emitting sound, some of the sound emitted by the transducer means returning to the micro-phone means to add a feedback contribution to its electrical out-put, the electronic filter comprising: means for converting the electrical output of the microphone means to a logarithmic elec-trical representation; first means for combining the microphone output so converted with an adaptive output in logarithmic 0~
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133~674 64725-469 electrical form to produce a combined signal input in logarithmic electrical form; means for electronically filtering the combined signal input in logarithmic form to produce a fiLtered signal in logarithmic form; means for generating a distinct signal; second means for combining the filtered signal with the distinct signal for the transducer means; and said means for electronically fil-tering also including logarithmic adaptive filter means having electrically stored parameters representing coefficients in logar-ithmic forms, said means for electronically filtering further including linear control means for continually altering the co-efficients to vary them in magnitude in substantially constant percentage amounts, said logarithmic adaptive filter means further including means for electronic processing of the filtered signal and the distinct signal relative to the electrically stored para-meters to produce an adaptive output in logarithmic form to said irst means for combining to substantially offset the feedback contribution in the electrical output of the microphone means in the electroacoustic system.
Generally, still another form of the invention is an electronic filter for an electroacoustic system having microphone means for generating an electrical output from external sounds and electrically driven transducer means for emitting sound corres-ponding to the external sound, some of the sound emitted by the transducer means returning to the microphone means to add a feed-back contribution to its electrical output, the electronic filter comprising: means for converting the electrical output of the ~J
-microphone means to an electrical representation; first means for combining the microphone output so converted with an adaptive output to produce a combined signal input; electronic filter means for electronically filtering the combined signal input to produce a filtered signal; adaptive filter means having electrically stor-ed parameters representing coefficients, said adaptive filter means including linear control means for altering the coefficients in substantially constant percentage amounts, said linear control means interconnected with said electronically filtering means, said adaptive filter means further including means for electronic processing of the filtered signal relative to the electrically stored coefficients to produce said adaptive output to said first means for combining to substantially offset the feedback contribu-tion in the electrical output of the microphone means in the elec-troacoustic system, means for generating a distinct signal; and second means for combining the filtered signal with the distinct signal for the transducer means.
Other forms of the invention are also disclosed, includ-ing systems and circuits and methods for operating them.
Other objects and features will be in part apparent and in part pointed out hereinafter.
Brief Description of the Drawings Fig. 1 is a pictorial of a user with a hearing aid of the invention including an electronic filter according to the invention, part of the hearing aid shown in cross-section;
Fig. 2 is a pictorial side view of the hearing aid of Fig. l;

- 8a -~f' Fig. 3 is a partially block, partially pictoriaL diagram of an invention two-chip digital hearing aid;
Fig. 4 is an electrical block diagram showing inventive circuitry for the hearing aid of Fig. 3;
Fig. 5 is a bLock diagram of a conventional FIR filter structure;
Fig. 6 is a partially block, partialLy schematic diagram of a logic circuit for controlling an inventive adaptive filter in Fig. 4;
LO Fig. 7 is a partiaLly block, partiaLly schematic diagram of another form of logic circuit for controlLing an inventive adaptive fiLter for simulating a feedback path;
Fig. 8 is a graph of coefficient C value versus coefficient number showing adaptation in constant percentage units in inventive circuitry;

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13356~4 Fig. 9 is a graph o coefficient C value versus coefficient number showing adaption ln constant increments in a linear adaption approach Fig. 10 is a block diagram of a logarithmic filter-limit-filter of the invention Fig. 11 is a block diagram of a multiplexed log-arlthmlc multlply accumulate cell (MLMAC) of the inventlon and used in several blocks in Fig. 10 Flg. 12 is a block diagram of a hard l;miter circuitry of the invention used in Fig. 10 Fig. 13 ls a schematlc diagram of a switched capacitor arrangement operated by methods of the invention:
Fig. 14 ls a partially block, partially schematlc diagram of a logarithmic analog-to-digital, digital-to-analog slgnal conversion apparatus of the invention and Fig. 15 i8 a process flow dlagram illustratingsome inventive methods for operating a logarithmic ADC/DAC
converslon apparatus of the invention.
Corresponding reference characters indicate cor-respo~ding parts throughout the several views of the draw-lngs.

Detailed Description of Preferred Embodiments In Fig. 1 a hearlng aid 11 receives external sounds at an input microphone 13 in an earpiece 14. Micro-phone 13 generates an electrical output from sounds exter-nal to the user of the hearing aid for an over-the-ear-unit 15 which produces an electrical output for a receiver or transducer 17 that emits filtered and amplified sound from earpiece 14 into the ear of the user of the hearing aid.
(In another hearing aid, not shown, the microphone 13 and receiver 17 are in a behlnd-the-ear (BIE) unit and not in " ~ 133567464725_469 an earpiece, and the improvements described herein are equally applicable to this and other units.) For purposes of the present disclosure it is important to note that some of the sound emitted by receiver 17 returns to the microphone 13 as feedback indicated by arrows such as 19 and 21 from the opening of a channel 23 by which receiver 17 communi-cates with the ear canal of the user. Other feedback passes through the side of earpiece 14 and takes a shorter path to the input microphone as illustrated by arrow 25. Some sound 29 feeds 10 back directly from receiver 17 through interior absorber material 27 of earpiece 14 to the microphone 13.
Feedback is disadvantageously associated with squealing, ringing, erratic operation and instability in the operation of hearing aid 11. Accordingly it is desirable to find some way to permit hearing aid 11 to operate more satisfactorily even though feedback according to the numerous paths indicated by arrows 19, 21, 25 and 29 unavoidably occurs.
Fig. 2 shows a side view of hearing aid 11 with its over-the-ear unit 15 which includes filtering and amplifying cir-20 cuitry. In a clinical fitting procedure, unit 15 is loaded withdigital information through a connector 35 connected by a cord 37 from a host computer system such as that described in U.S. patent 4,548,082. After the hearing aid 11 has been loaded at the clinic with information which suits it to ameliorate the particular hear-ing deficiency of the user, connector 35 is detached from the rest of the hearing aid and replaced with a battery pack 39 for 1 33 S 6 7g convenient daily use. One type of preferred embodiment is improved with inventive feedback ofsetting circuitry that requires no additional information rom the host system to govern the offsetting operations.

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Hear;,ng aid features, requested by audiologists on the basis of past experiences in clinical pract;ce and research, are in excess of those provided by any aid com-mercially available to date. Not only is th;s gap is S believed to be unbridgable by using existing unsophisti-cated analog amplifier components, but also digital signal processing (DSP) strains the power budget of a mult;,-channel, ear-level, battery-operated hear;ng a;,d. Ihe power drain o current general purpose digital signal processors demands frequent replacement of batteries which impedes acceptance by the very publ,ic who need extensive processing capability most.
~ ig. 3 shows an inventive two ch,ip VLSI based battery-operated hearing aid 41. VLSI, or very large scale intes}ation, involves the fabrication of thousands of microscopic electronic components on a chip, die or sub-strate. qhe hearing aid is suitably implemented in either analog VLSI or dig;,tal VLSI form, and digital embodiments are described herein for purposes of example only. '~ne chip or VLSI die 43 is responsible for data acquisition and reconstruction while a second chip or VLSI die 45 is dedi-cated to the DSP circuitry. A custom digi,tal signal proc-essor~ potentially capable o performing over 3 million multiply accumulate operations per second while consuming less than a fraction of a milliwatt, is fabricated on chip 4S to implement a four-channel hearing aid. Power consump-tion is minimized while maintaining a wide dynamic range through the use of sign/logarithm arithmetic. Ihis capabil-ity wi,ll allow the processing of several hundred filter taps with a 12.5 kHz sampling rate.
Advantageously, the system architecture is tailored to provide the essential functions and to allow reconfiguration of the signal processing elements to imple-ment a variety of hearing aid designs. qhe VLSI digital 8~d ! CID 5513 ; ~ ~ ~ ~~ P~IENI

133~674 hearing aid 41 has a power consumption that compares favor-ably with conventional analog units.
In Fig. 3 input microphone, or field microphone, 13 senses external sounds and produces an electrical output for an antialiasing filter AAF 51 for low pass filtering and cutoff at a Nyquist frequency of about 6 kl~z. Loga-rithmic analog-to-digital and digital-to-analog signal conversion circuitry 53 is fabricated on die 43 and has a pair of capacitors having respective electrical charges and a circuit for redistributing the charges repeatedly a vari-able number of times, which variable number relates digital to analog. An all-hardware logarithmic filter-limit-filter circuit 55 fabricated on die 45 has a dig.ital input 57 and a digital output 59 connected to the logarithmic signal conversion circuitry 53. Circuit 55 acts as a digital signal processor employing sign/logarithm ar;.thmetic and offering extremely low power consumption. ~he analog microphone output (filtered by AAF 51) is connected to the logarithmic signal conversion circuitry 53 for convërs.ton to digital form for the input 57 of the logarithmic filter-limit-filter circuit 55. Receiver 17 is an.output transducer connected via its output amplifier 61 elsewhere to the logarithmic signal conversion circuitry 53 which converts the digital signal at output 59 of the logarithmic filter-limit-filter circuit 55 to analog form for receiver 17. Iiming for the circuits is provided by a piezoelectric crystal 62, associated timer circuit 63 and control lines 64.
Iwo separate power sources such as a main battery 65 and a parameter retention battery 67 are employed to separate relatively high-power-consumption circu.itry in chips 43 and 45 from a parameter memory in chip 45. Ihe parameters, downloaded from a host computer 69 through a serial interface as described in coassigned U.S. Patent 4,548,082 and as further described herein, are all that need to be altered to fit the response of the digital hearing aid 41 to many hearing-impaired patients. Hence, although the main battery 65 may discharge over a period of days, the parameters that are spe-cific to the patient are retained by separate battery 67 for an extended period (a year or more).
As thus described, one chip 43 is an Analog Interface Chip (AIC) responsible for data acquisition and reconstruction while the second chip 45 is dedicated to the specific DSP circuit-ry. AIC chip 43 contains an input preamplifier with anti-aliasing filter 51. Conversion circuitry 53 is also regarded as acting as a compressor and expander to convert the analog input to a logar-ithmically encoded digital word and the digital output samples back to a linear analog voltage. Use of logarithmic circuitry permits substantially reduced power consumption by the DSP chip 45. The DSP chip 45 accepts logarithmically encoded data from the ADC output of the AIC chip 43, processes it in accordance with the desired hearing-aid response, and then passes the result to the DAC function o conversion circuitry 53 for conversion back to analog, filtering and driving the output transducer.
In Fig. 4, the system of Fig. 3 is shown in bLock dia-gram form without regard to arrangement on the chips. Further description of circuit 55 now refers to Fig. 4. Circuit 55 acts like a bank of four bandpass filter channels A, B, C and D in a logarithmic domain in which the gain and maximum power output of each channel can be controlled independently to shape the desired 133567~ 64725-469 response. In concept, each channel has a bandpass logarithmic ilter 81 called a prefilter followed by a hard limiter 83 and a bandpass logarithmic postfilter 85 that removes distortion - 13a -~J

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introduced by the hard limiter 83. Ihis nonlinear combina-tion is called a filter-limit-filter logarithmic digital filter or logarithmic sandwich filter 87.
Ihe logarithmic operations for filtering purposes herein are now contrasted with the linear operations of a conventional finite impulse response (FIR) filter.
One of the principal factors governing the power consumption of a digital fllter is the wordlength used. In a filter employing linear arithmetic in which the numbers stored in the registers are directly proportional to the signal amplitudes, the accuracy of a number depends on its magnitude. But for adequate signal-to-noise ratio and a reasonable wordlength, the dynamic range o the filter is severely limited.
Moreover, the distribution of speech amplitudes, often modeled as a Laplacian, has several implications with regard to choosing an appropriate number system. It is important that any proposed number system concentrate the available resolution near zero while retalning cognizance of distant states. In the context of information theory it can be shown that for a given number of code words the maximum information rate through a channel is achieved when all code words are equally likely to be transmitted. If the digital code words used to represent instantaneous speech pressures are uniformly distributed over a given range, those code words representing small changes in pres-sure will have a much higher probability of being used than those words which code larger changes in pressure.
In the embodiment of Fig. 4 computational proc-esses use numbers proportional to the logarithm of thesignal amplitude. Sign/logarithm arithmetic is especially well-suited to a digital hearing aid application, fulfil-ling the requirements for wide dynamic range (75 dB), small wordsize, and sufficient signal-to-noise ratio (SNR). RMS

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signal-to-quantizing noise ratios in excess of 30 dB are easily attainable with an 8-bit sign/logar;thm representa-tion. Because of the logarithmic nature oE the number system, the RMS si.gnal-to-noise ratio is a constant, inde-pendent of signal magn.itude, distribution, or frequencyspectrum. ~he logarithmic data representation permits data compression without compromising the fidelity of the sig-nals while reducing the power consumption and s;.ze of the integrated circuits dramatically.
While fi.ltering in the logarithmic mode shows great promise, it results in an extremely inefficient implementation on presently available commercial digital signal processors such as the lexas Instruments qMS320.
Over twenty times as many clock cycles are required to process a single FIR tap. A special purpose processor as described herein changes this situation dramatically by processing the samples in a much more efficient manner.
Also, low-power, precision signal conversion circuitry described herein for the acquisition and reconstruction of the sampled data is key to the successful attainment of a practical ear-level digital hearing aid.
As stated earlier, the implementation of digital filters is the primary task of the processor. An FIR fil-ter, as illustrated in Fig. 5, can be viewed as a tapped delay line in which at each stage the incoming signal is held in a register, multiplied by a constant (filter coef-ficient), and the product added to the partial sum output of the previous.stage. E~owever, the multiplication requires repeated additions which consume time and scarce power~ A logarithmic filter, such as 81 or 85 in Fig. 4, provides an advantageous alternative to the E?IR filter in these respects. When the logarithmic filter is preceded by logarithmic signal conversion and followed by antiloga-rithmic signal conversion, the logarithmi.c filter causes 8pd , . CID 5513 . ~ ~' PAIENI

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the receiver 17 to produce substantially the same acoustic output that lt would be caused to emit if a linear ADC/DAC
with a filter-limit-filter using FIR prefilter and post-filter were used.
By processing logarithmically encoded data directly, filtering performance is improved, circuit area is reduced, and power consumption is minimized as a result of the shorter wordlength required. Furthermore, power is not improvidently wasted in converting the logarithmically encoded samples to a linear format before tlley can be proc-essed by more conventional processors and re-compressing the output samples before they are expanded by a CODEC
~coder-decoder).
Because the theory of the FIR filter is useful ln studying the more advanced subject of the logarithm~c fil-ter, it is convenient to think in FIR terms when describing the logarithmic ilter. Eiowever, it is emphasized that the actual circuitry and operations used in the two filters are very different.
In sign/logarithm arithmetic, multiplication becomes simple addition. Ihis means that an add circuit executing an add operation is used in a logarithmic ilter instead of a multiply circuit executing repeated add opera-tions as in an FIR filter. Multiplication in a logarithmic filter is exact and introduces no roundoff error.
A logarithmic operation on two numbers A and B in the logarithmic filter which is analogous to adding two numbers X and Y, where A is log X by definition and B is log Y by definition, is understood by recognizing that X + Y = X(l+Y/X) (1) Accordingly, the logarithmic operation should compute a number C where .i r~
r~_~ 64725-469 133~674 C = log (X + Y) (2) Substituting Equation (1), C = log (X(l+Y/X)) (3) By recognizing that the log of a product is a sum of logarithms of factors, and the log of a ratio is a difference D of logarithms of dividend and divisor, E~uation (3) reduces to C = log X + log (1 + antilog (log Y - log X)) (4) Since by definition A = log X, B = log Y, and D = B - A, the logarithmic operation analogous to adding X and Y is given as C = A + log (1 + antilog (D)) (5) where D is defined to be D = B - A (6) Consequently, the logarithmic add involves a first operation of a subtraction corresponding to Equation (6), which is electronically implemented by circuitry essentially similar to an add circuit.
Second, an operation log (1 + antilog (D)) is performed electronically by a table lookup for instance. Third, the value A is electronically added by an add circuit to the result of the table lookup.
The term "Logarithmic Multiply Accumulate (LMA) cell"
is used herein to refer to the electronic circuitry in a logarithmic filter which is very different from, but analogous to, a stage of multiplication and addition in an FIR filter. In an 8 bit VLSI realization of a single LMA cell of the present work, less than 25% of the table entries for purposes of the table lookup are non-zero. The table can be efficiently implemented as a programmable logic array (PLA). Roundoff error propagation associated with the accumulate operation is a factor which should ,'~

~ 64725-469 be considered in using the lookup approach. With an 8-bit encoding and a sparse lookup table a dynamic range in excess of 100 dB and an RMS signal to RMS noise ratio of 31 dB is obtainable.
For convenience of description, the logarithmic operation analogous to adding in an FIR filter may be called "adding in the logarithmic domain" or "accumulating". Similarly, addition of logarithms may be called a "multiply" even though there is no repeated addition of them. The shorthand terminology also appears in the expression Logarithmic Multiply Accumulate (LMA) used above. However, it is emphasized that in the present context, the logarithmic multiply operation is not an electronic multiplication in the conventional sense of repeated addition.
Furthermore, the logarithmic accumulate operation is not adding in the conventional sense of the term because a logarithmic value A = 2 when "added" to a logarithmic value of B = 2 is not a logarithmic value of 4. Instead it is 2.3010.... Thus, in this example, 2 + 2 equals 2.3010....because A - B = 2 - 2 = 0; log (1 + antilog (0)) = log (2) = 0.3010.... and C = A + log (2) - 2 + 0.3010.... = 2.3010.... A logarithmic value A = 3 when "added"
to a logarithmic value of B = 2 is neither a logarithmic value of 5 nor a logarithmic value of 3.
For the present purposes a logarithmic filter suitably has a series of filter stages with inputs and outputs in cascade and respective registers associated with the filter stages for storing electrical representations of filter parameters. The filter stages include electronic 8pd J CID 5513 . PAIEN~
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addition circuits for respectively adding the electrical representations of the filter parameters to the electrical signal to be filtered thereby producing a set of filter sum signals. At least one of the filter stages includes a logarlthmic accumulate circuit for producing a filter sig-nal in substantially logarithmic form at its output by nonllnearly combining a filter sum signal for that filter stage with a signal from an output of another filter stage.
For the reasons discussed above, the electronic hardware (or software when used) in a logarithmic filter is thus very different from that of the FIR filter.
A filter-limit-filter digital filter by its interven.ing limit operation also lntroduces a nonllnearity which makes the filter-limit-filter different from any mere linear filter such as the FIR (finite impulse response) filter, even when the prefilter and postfilter are linear and not logarithmic. If the combination of filter, limiter and filter were equivalent to any single FIR filter, econ-omy and power dissipation considerations would dictate areduction in the circuitry to such a single FIR filter, if it existed. E~owever, no FIR filter exists which is equiva-lent to the filter-limit-filter, or sandwich filter.
Since the limit operation is set to prevent excessive signal levels that will routinely occur in hear-ing aid operation, the nonlinearity is pervasive, not to mention that the logarithmic analogy to addition imple-mented in the PLA is nonlinear. As a result, the digital to analog converter does not produce an analog output in accordance with the filtered signal from the prefilter, nor is the output of the prefilter itself adapted to the fre-quency response of the microphone, receiver and ear. Due to the nonlinearity of the hard limiter, the postfilter does not process a signal in accordance with the signal 8pd J ~ CID 5513 PAIENI

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from the analog-to-digital converted signal either. Ihe logarithmic sandwich filter acts as a whole to more fully ameliorate hearing deficiencies and prevent painfully loud sounds from being emitted by the receiver than a linear system can.
An 8-bit LMA cell in CMOS (complementary metal oxide semiconductor) technology with a power supply of 5 volts and a minimum feature size of 3 micrometers illus-tratively has a power consumption of 20 microwatts. Il-e cell includes the PLA lookup table, parameter registers that hold filter parameter values K or the logarithmic digital filter corresponding to the logarithms of ltnear FIR filter coefficients, and combinatorial logic circui-try. By avoiding the use of dynamic CMOS design styles, the cell consumes only a few microwatts when input vectors are changing at a very slow rate. In this manner, the processor conserves power when the hearing aid is in a quiet environment.
Ihe LMA cell requlres just over 1500 translstors in a preferred embodiment. Ihe area occupied by the cell is 2 square millimeters. Iherefore, 32 of these multiply accumulate cells arranged in a linear systolic array easily f;t on a 10 millimeter square chip. With a sampling rate of the system of 12.5 k~z, and the LMA circuit producing outputs at a 10 M~z ratet multlplexing the 32 LMA cells by a factor of 8 provides suitable processing (256 FIR filter taps) for a four-channel, instantaneous-compression hearing aid with a power consumption of 5 milliwatts. Ihis arrangement is called a Multiplexed Logarithmic Multiplier Accumulator Cell (MLMAC) wherein additional coefficient and data registers permit multiple LMA operations during a sampling period.
With a power supply voltage of 1.5 volts and state~of-the-art, 1 micrometert VLSI fabrication, a power 8~d ~ ~. CID 5513 PAIENI

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consumption of 200 microwatts is contemplated for the DSP
chip ~S. Using similar VLSI fabrication of the AIC ch.ip 43, the overall power consumption of chips 43 and 45 together is on the order of a milliwatt.
Referring again to Fig. 4, the post;1ter outputs of the four channels A, B, C and D of logarithmic sandwich filter 87 are combined by logarithmic accumulation in a logarithmic combiner circuit 91, the output of which is supplied to the antilogarithmic DAC conversion operation in circu.;t 53. If adaptive feedback offsetting is omitted, the input from logarithmic ADC i8 directly supplied to each prefi~ter of channels A, B, C and D. Fig. 4, however, shows a more sophisticated arrangement for offsetting feed-back by an all-hardware logarithmic filter 93 having its input connected to the output of logarithmic combiner 91.
Ihe log filter 93 has its output connected to a log com-biner 95 to which the output of the logarithmic ADC is also connected. In this way, the log filter produces a signal in logarithmic form which offsets in log combiner 9~ the feedback contribution in the microphone 13 output. Ihe output of log combiner 95 is a combined signal input sup-plied to each of the four prefilters for channels A, B, C
and D.
~he filter parameters of the log filter 93 are continually varied by a logic circuit, or electronic con-trol, 97 as necessary to simulate feedback path ~If and cancel the feedback even under changing physical conditions in daily use of the hearing aid by the hearing impaired person. A signal generating circuit 99 produces a signal Se distinct from in waveshape from, and uncorrelated with, the external sound received by microphone 13. Signal Se is weighted by adding the logarithm of a weight Wl to it before logarithmic accumulation in log combiner 91. Also, signal Se and the combined signal input from log combiner 1 3 3 5 ~ ~ ~ 6472 5-469 95 are provided on separate lines to logic circuit 97. Logic circuit 97 compares the signal Se with combined signaL input, which is an error signal in logarithmic form for adaptive filter-ing purposes, and updates parameters for log filter 93 according-ly -It should be recognized that the logarithmic adaptivefilter embodiment of Fig. 4 is a logarithmic analog of correspond-ing linear filter circuitry disclosed in above-mentioned Canadian patent application S.N. 594,441. Several embodiments with differ-ent connections and operatio~s using the signal Se are shown inabove-mentioned Canadian patent application S.N. 594,441 and are interpreted in their linear form. Also, it is additionally noted herein that each of the drawings of said application represents a system that is additionally interpreted and implemented in logar-ithmic form according to the principles stated herein. Figures 12 and 24 of the above-mentioned Canadian Patent application are reproduced herein as Figs. 6 and 7.
Figs. 6 and 7 illustrate two of many different possible alternative circuits for implementing logic circuit 97 of Fig. 4.
~e add/subtract circuits in Figs. 6 and 7 are in one example provided as electronic adder/subtracters. In the logarithmic context, however, they operate as if they were multiplier/dividers in the linear domain because they add and subtract logarithmic signals. Advantageously, these circuits modify the filter para-~ 1335674 64725-469 meters of logarithmic adaptive filter 93 in increments of log representation.
As shown in Fig. 8, the coefficients in the linear domain are adjusted in equal percentage increments, - 22a -8pd ) ~ CID 5513 PAIENI

as a result of using the circuits from said parent applica-tion for controlling a logarithmic filter. Ilhe percentage increments are equal, for example, because adding a con-stant logarithmic amount to any number is equivalent to multiplying the linear number by a constant. Multiplying a number by a constant increases that number by a constant percentage, regardless of the number value. Ihis results in a smaller error and statistical fluctuation for smaller coefficients as shown in Fig. 8 than would be the case in Fig. 9 representing the circuits of Fig. 6 and 7 for adap-tively controlling an FIR filter that was described in said parent application CID 5512.
Filter 93 of Fig. 4 is thus an example of a log-arithmic adaptive filter having electrically stored parame-ters representing coefficients in logarithmic form. Logiccircuit 97 is an example of a linear control means for continually altering the coefficients to vary them in mag-nitude in substantially constant percentage amounts. Ihe linear control means is interconnected with means for elec-tronically filtering (e.g. logarithmic sandwich filter87). Ihe logarithmic adaptive filter further include means for electronic processing of a filtered signal and a dis-tinct signal relative to the electrically stored coeffi-cients to produce an adaptive output in logarithmic form to a first means for combining to substantially offset the feedback contribution in the electrical output of the microphone means in the electroacoustic system.
Log filter 93 suitably has a series of filter stages with inputs and outputs in cascade and respective registers associated with its filter stages for storing electrical representations of variable filter parameters corresponding to logarithms of values of adaptive filter coefficients. qhe filter stages respectively add the elec-trical representations of the filter parameters to the 8pd , CID 5513 -~ ~ ~ PAIE~I

133567~
electrical signal from log combiner 91 to be filtered thereby producing a set of filter sum s.lgnals. Logarithmi.c accumulation in a filter stage produces a filter signal in substantially logarithmic form at its output by combining a filter sum signal for that filter stage with a signal from an output of its predecessor filter stage.
Ihe electronic control circu.ltry of logic circui.t 97 continually alters the electrical representations to vary each filter coefficient in magnitude in substantially constant percentage amounts of the value of that coeffi-cient at any given time. For example, in Fi.g. 6 the elec-tronic control circuitry responds to first and second externally derived control signals such as noise signal Se (or output Y from log combiner 91) and the polar.ity signal from log combiner 95 which both have respective changing polarities. Registers 181.0-.M temporarily store a series of values representing changing polariti.es of the first externally derived control signal. Each filter parameter is increased and decreased in magnitude by a constant amount in add/subtract circuits 185.0-.M. qhe increasing and decreasing respectively depend on whether a correspond-ing value in the series of values has the same or opposite polarity compared to the polarity of the second externally derived control signal (e.g. log combiner 95 output) cur-rently. In this way, each coefficient, the logarithm ofwhich is represented by each filter parameter, is increased and decreased in increments of a substantially constant percentage of each coeffic.tent at any given time.
In Fig. 7, the electronic control circuitry has a first set of registers 301.0-.M for holding running totals that are incremented and decremented by add/subtract cir-cuits 305.0-.M as a function of polarity of the log com-biner 95 output and polarity of at least one signal (Se, U, or Y) from logarithmic sandwich filter 87. A second set of 8pd ~ ~ CID 5513 PAIENI

133~674 registers 303.0-.M hold digital values in logarithmic form representing each parameter. Add circuits 307.0-.M respec-tively add the running totals in the first set of registers to corresponding digital values in the second set of regis-ters less frequently than the incrementing and decrementingof the first set of registers occurs.
In Fig. 10 a preferred electronic filter struc-ture 400 implements logarithmic sandwich filter 87 of Fig.
4 for filtering an 8-bit electrical signal LOG SIGNAL such as the output of log combiner 95. In Fig. 10 a series of eight MLMAC filter stages 401, 402,...407, 408 are respon-sive to the electrical signal and have 8 bit bus inputs Dl and 8 bit bus outputs Ql in cascade. Each filter stage has a second bus input D2 and bus output Q2 (both 8 bits).
Filter stage 408 has its output Ql connected to its own second input D2, and the ilter stages have their inputs D2 and outputs Q2 connected in cascade ln reverse to the cas-cading of inputs Dl and outputs Ql.
Each filter stage 401-408 stores electrical rep-resentations of filter parameters K consecutively suppliedin parallel form on a bus KI~ 411.1 from host computer 69 of Fig. 4 and loads from stage to stage on buses 41i.2-.8 in the manner of loading a long shift register. Ihe series of filter stages 401-408 include other shift-register based circuits for filtering signals from the Q outputs through the series of filter stages from the first (401) to the last (408) of the filter stages and then filtering signals back through the series of filter stages from the last to the first of them to produce a filtered slgnal output in parallel form on an 8 bit bus 413.
As described, the series of filter stages 401-408 processes in two directions, forward and reverse. In fact, each particular filter stage processes filter signals in both directions with respect to each filter parameter in 8pd J CID 5513 PAIENI
133~7 ~

that particular filter stage. Advantageously, it is recog-nized herein as being desirable to make the logarithmic prefilter and postfilters analogous to a linear phase fil-ter. In FIR f;lter theory, a linear phase filter has taps with filter coefficients which are symmetric with respect to the center of the series of taps. Ihe logarithmic transformation does not disturb this symmetry, and the logarithmic filter parameters are advantageously also sym-metric. For example, in a 32 tap logarithmic filter, par-ameter K0=K31, Kl=K30, K2=K29, K3=K28,...K15=K16. IheMLMAC stages are conceptually folded around the center of symmetry, so that the first stage 401 holds parameter K0 which is also used as K31. Further coefficient multiplex-ing in the first stage provides parameter Kl which is also used as K30. Second stage 402 holds parameters K2 and K3, which are also used as K29 and K28. In this way only 8 MLMAC stages act as a 32 tap logarithmic filter.
Ihe 8 bit Q2 output bus 413 of first MLMAC stage 401 is connected to an 8 bit input bus 415 for a hard limit (E~.L.) circuit 417, as well as to an 8 bit filter output bus 419. E3ard limit circuit 417 responds to the bus 415 prefilter output part of the Q2 output of stage 401 to produce an intermediate output signal generally limited to a predetermined range of electrical values. Ihis inter-mediate output signal is supplied on a bus E3.L.OU~ 429 to a2-to-1 multiplexer 431. Multiplexer 431 has an 8 bit out-put bus 433 carrying each sample X in parallel digital form simultaneously to all of the filter stages 401-408 at once. Multiplexer 431 multiplexes the intermediate output signal on El.L.OUI bus 429 with LOG SIGNAL supplied on an input bus 435 so that the logarithmic filter stages 401-408 operate as both a logarithmic prefilter and a logarithmic postilter.

8pd ~ PAIENI

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Control or the logarithmic sandwich filter 400 of Fig. 10 is provided by a circuit 441 for generating clock pulses on the order of 10 MHz, a digital counter 443 for counting the clock pulses to produce a count output on a bus 445, and a decoder 447 for decoding the count output into control signals on six control lines 449 for coordi-nating the operations of each MLMAC stage, two control lines 451 for the hard limit circuit 417 and a line 453 for multiplexer 431.
Demultiplexing the output bus 413 onto buses 415 and 419 is accomplished by control signals on the control lines from decoder 447. For example, decoder 447 is con-nected by a line 455 to a latch 457. Decoder 447 only clocks latch 457 when a multiplexed digital signal repre-senting postfilter output is present on bus 419, and not when the information on bus 419 is prefilter output intended for hard limit circuit 417. In t~lis way way latch 457 is rendered insensitive to prefilter output which is not intended for it anyway. On the other hand, when pre-filter output is present on buses 413 and 415, decoder 447 selects the hard limit output bus 429 input by activating control line 453 to the 2-to-1 multiplexer 431. At other times, multiplexer 431 is made to connect LOG SIGNAL to the MLMAC stages 401-408.
Advantageously, multiplexer 431 in Fig. 10 doubles the processing capabilities of MLMAC stages 401-408 by making them act as both prefilter and postfilter to the hard limit circuit 417 and thereby even more efficlentl~
implement logarithmic sandwich filter 87 oE Fig. 4. It is emphasized that this multiplexing provided by multiplexer 431 is additional to multiplexing within each MLMAC stage, further described next, and thus provides another important contribution to the practical implementation of the loga-rithmic sandwich filter 87.

_ 8pd J CID 5513 .
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In Fig. 11 a representative circuit 402 of each MLMAC filter stage has eight registers 501.1-.8 for storing digital representations of a number of filter parameters in association that individual filter stage. Each of the eight registers holds an eight bit representation of a respective filter parameter. Ihe filter parameters are indexed according to their channel A, B, C or D. Iwo fil-ter parameters for each channel are stored in association with each ilter stage for the total of eight registers 501.1-.8. Advantageously, therefore, the channels are multiplexed as well as a pair of parameters for each chan-nel in each filter stage.
An 8-to-1 multiplexer 503 receives 64 lines from the registers 501.1-.8 and is operated by three control lines 505 from decoder 447. Multiplexer 503 and decoder 447 multiplex the operations of each individual filter stage with respect to the digital representations of the parameters so that the filter 401-408 of Fig. 10 operates as a plurality of bandpass filters equal in number to the number of filter parameters for different channels associ-ated with each filter stage, e.g., the number of channels themselves. Decoder 447 coordinates the operations of each filter stage and causes the multiplexer 503 in each filter stage to select corresponding filter parameters by channel in all of the filter stage means at once in accordance with values of an index represented in parallel digital form on the three select lines 505. In this way, operations are multiplexed so that the filter as a whole operates as a plurality of bandpass filters, and each bandpass filter has a filter characteristic defined by the set of filter par-ameters in the filter stages selected according to the same value of the index.
In Fig. 10 the filter stages are in predecessor-successor relationship electrically speaking (without 8pd , ~ CID 5513 PAIENI
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regard to actual placement on the VLSI die). For example, MLMAC stage 401 is a predecessor, or previous cell, to MLMAC stage 402 and MLMAC stage 403 is a successor, or next cell, relative to MLMAC stage 402.
In ~ig. 11 signals are filtered through the ser-ies of stages 401-408 by first and second 16-cell shift registers 511 and 513. Each shift register 511 and 513 holds 8 bits of parallel digital informatlon in each cell and acts as a 16 stage FIFO (first-in-first-out) structure for whole bytes. In other words, each shift register holds 8 bits times 16 cells or 128 bits in all. ~he 16 cells in shift register 511 are cascaded for transfering i1ter signals for both prefilter and postfilter purposes in all four filter channels A, B, C and D to a successor filter stage in the series 401-408. Second shift register 513 also has 16 cascaded cells for transfering further filter signals for both prefilter and postfilter purposes in all four filter channels A, B, C and D to a predecessor filter stage in the series. Ihe 16 cells thus accommodate 2 fil-ters x 4 channels x 2 taps = 16 bytes.
Processinq in ~ig. 11 is performed by an adder521 and log PLA combiner 523. Adder 521 is fed by an 8 bit bus from 8-to-1 multiplexer 503 to which 8 bit sample X on bus 433 is added. An 8-bit output sum from adder 521 is fed to log PLA combiner 523 which supplies an 8 bit result on a data bus 525 to both shift registers 511 and 513.
Decoder 447 clocks all of the cells in shlft register 511 by a control signal on a line 527 when shift register 511 is to receive the result from combiner 523. Decoder 447 clocks all of the cells in shift register 513 by a control signal on a line 529 when shift register 513 is to receive the result from combiner 523. Clocking moves the contents in the 16 cells ahead by one cell and delivers a latest sample at 8 bit output Ql of shift register 511 or 8 bit 8pd J ~ CID 5513 PAIENI

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output Q2 of shift register 513 to the successor or prede-cessor filter stage. Ihe entire filter assembly with its repeated synchronized data moves in all fllter stages com-prise a systolic array implementation.
A 2-to-1 multiplexer 531 has first and second 8 bit input buses Dl and D2 respectively connected to the predecessor and successor filter stages as shown in Fig.
10. Ihus input bus Dl is connected to a first shift regis-ter in the predecessor filter stage analogous to 511 and to a second shift register in the successor filter stage ana-logous to 513. Multiplexer 531 selects bus Dl or D2 under control of decoder 447 on a line 533, to feed log PLA com-biner 523 on an 8 bit bus 535.
Adder 521 and log PLA combiner 523 thus act as an electronic processer that adds each electrical representa-tion of a filter parameter to the electrical signal X to be filtered thereby producing a filter sum signal for combiner 523. Combiner 523 produces a filter signal in substantial-ly logarithmic form for the first or second shift r'egister (511 or 513 respectively) by nonlinearly combining the filter sum signal with a signal from the multiplexer 531 derived from the first shift register in the predecessor filter stage or from the second shift register in the suc-cessor filter stage respectively.
~he entries Pr (prefilter) and Po (postEllter) followed by channel designations (~, B, C, D) and coeffi-cient numerals in the boxes of the shift registers 511 and 513 specify the order (working from Q output back through the cells) in which the decoder 447 is set to call out parameters from the 8-to-1 multiplexer 503 and to operate the 2-to-1 multiplexer 431 of Fig. 10. In the prefilter mode, multiplexer 431 of Fig. 10 is caused to select input line 435 LOG SIGNAL, and decoder 447 selects the channels in order on lines 505 for a given parameter number. On 8pd ~! ~ CID 5513 PAI~NI
133~674 each channel select operation, decoder 447 operates line 527 to cause multiplexer 531 to select output from previous cell on input Dl (tap i) and then select output from next cell on input D2 (tap 31-i). Concurrently in the same channel select operation, decoder 447 activates line 529 to clock the tap i result into the shift register 511 and then to activate line 527 to clock the tap 31-i result into the shift eegister 513.
In the postfilter mode, multiplexer 431 of Fig.
10 is caused to select input line 429 H.L.OUI, and decoder 447 selects the channels in order on lines 505 for the given parameter number, with multiplexer 531 and shift registers 511 and 513 operating within each channel select operation as described. Ihen the decoder 447 proceeds to the second coefficient and executes the prefilter channel selects and then the postfilter channel selects all over again. Ihis completes a full cycle, which is repeated endlessly. It should be understood that the legends in the shift register cells indicate the order and position of the data when prefilter-channel-A-coefficient 2 is in the cell nearest output Ql. During the rest of the cycle the data is shifted through the cells continually in the manner of a cyclic ~uffer store.
Fig. 12 shows more details of hard limiter 417 of Fig. 10. ~ard limiter 417 acts as limiting means, respon-sive to a signal from an output of a filter stage in said series, for producing a filtered signal output generally limited to a predetermined range of electrical values.
Multiplexer 431 is connected to the first of the filter 30 stages in Fig. 10 and multiplexes the filtered signal out-put of the hard limiter 417 with the electrical signal to be filtered so that the electrical signal is prefiltered through the series of filter stages and back again, then 8~.d I ~ CI D 5513 ~ -- PAI ENI

133S67~
limited by hard limiter 417, and then postfiltered through the series of filter stages and back again.
E~ard limiter 417 in E?ig. 12 has four storage registers 551 for holding electrical representation of a boost value for each filter channel A, B, C and D. Ihe appropriate boost value is selected from registers 551 by a 4~to-1 multiplexer 555 which is controlled by decoder 447 by two select lines 451 which are suitably connected to two channel select lines in lines 505 or otherwise as appropri-ate. A digital adding circuit 553 is connected to theoutput of multiplexer 555 for electrically adding to, or increasing, the 8 bit digital signal on bus 415 with the digital representation of the boost value for the selected channel. Adding circuit 553 produces a first output signal on a line 557 having a variable level depending on the magnitude of the boost value and the magnitude of the digi-tal signal on bus 415. Adding circuit 553 has a maximum value, such as 11111111 of which it is capable, so its output does not exceeding that maximum output level. A
digital subtractor 559 has its subtracting (-) input con-nected to the 8 bit line from the multiplexer 555, and its plus (+) input connected to the output of adding circuit 553. Subtractor 559 decreases the first output signal from the adding circuit 553 by the digital representation of the boost value for the channel to produce a limiter output.
Ihe limiter output represents the same magnitude as the electrical signal on bus 415 unless the electrical signal exceeded a predetermined magnitude inversely related to the boost value. Specifically, if the maximum level of which addin~ circuit 553 ls capable is designated M~X, then the hard limit value HL imposed on the magnitude of the signal to be limited is MAX less the boost value, or HL = MAX -BOOSI. If the magnitude of the signal exceeds E~L, then the limiter output is EiL. If the magnitude of the signal does 8~,pd .~ CID 5513 PAI ENI

not exceed RL, then the limiter output is the magnitude of the signal unchanged. In overall operations, the circuitry of Figs. 12 and 10 is suitably arranged to multiplex the operations of each individual filter stage for filtering with respect to each of the plurality of filter parameters for that individual filter stage and for concurrently mul-tiplexing, for the means for increasing (e.g. adding cir-cuit 553) and said means for decreasing (e.g. subtracting circuit 559 ), the electrical representations of the boost values from storage means so that the boost values for limiting purposes respectively correspond to particular filter parameters.
Iurning to Fig. 13, an ADC-DAC logarithmic con-version circuit based on a charge-redistribution technique is believed to be the most suitable for low-power applica-tions. Ihe circuit is uncomplicated, has extremely low power consumption, and feasible to implement in VLSI. Ihe ADC and DAC are implemented with a logarithm base d=0.941.
Ihis corresponds to an RMS Signal-to-Noise Ratio (SNR) of 35.1 dB, a dynamic range 67.1 dB with an accuracy of 3~
with regard to the filter coefficients. ~nother logarithm base d=0.908 with the wordlength of 8 bits was also studied. Ihis corresponds to an RMS Signal-to-Noise Ratio of 31.1 dB, and a dynamic range of 106 dB with an accuracy of 4.9~ with regard to the filter coefficients. Ihese performance parameters are based on the input quantization only and do not include degradation due to the signal proc-essing. Ihe logarithm base is selected by the skilled worker with a tradeoff between dynamic range and SNR in mind. An embodiment with base d = 0.941 appears to be preferable for the hearing aid purposes, and the same base d should be used in both the DSP and ADC/DAC circuits.
Ihe logarithmic D/A conversion is based on a charge-redistribution technique, which uses two unequally weighted capacitors Cl and C2 in Fig. 12.

8pd J CID 5513 PAIENI
- 133S67~

Prlor to a D/A cycle, capacitor Cl is pre-charged to a reference voltage (Vref) by closure of swltch Sl, and capacitor C2 is discharged completely by closure of switch S2. During a phase 1 of an input clock, with switches Sl and S2 open, a switch S3 is closed and the charge on capacitor Cl is redistributed to capacitor C2. After redistribution the voltage on the capacitors is:

VREFXCl/(Cl+C2) d = Cl/(Cl t C2) During phase 2 of the clock, switch S3 is opened and switch S2 is closed thereby discharging capacitor C2 completely. Ihe residual voltage on capaci-tor Cl is now Vl (as given above). On the next phase 1, switch S3 is closed once again to redistribute the charge. Ihe resulting voltage across the capacitors is:

V2=(Cl/(Cl + C2))2 X VREF=d2 X V~EF

Ihe process is continued in this fashion for n clock cycles, after which the final voltage on capacl-tor Cl is given by:

Vn=(Cl/(Cl ~ C2)) X VREF=dn X VREF

Ihe ratio 'd' corresponds to the base of loga-rithms for the system. For a base d=0.941, the capacitor values chosen are Cl=32 pF and C2=2 pF.

An 8-bit counter monitors the number of clock cycles used. Ihe 7-bit digital word that is to be con-verted is compared with the lower 7 bits of the counter.

8pd ! 1 CID 5513 ;" PAI ENI
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When equal, the clock to the switches is disabled. Ihe residual voltage on capacitor Cl corresponds to the ana-log equivalent of the input digital word.
For analog-to-digital conversion, the analog signal is sampled and the sample is compared with the ana-log output of the DAC. When equal, the clock to the switches in the D/A converter is stopped and at the same time the counter value is latched. Ihis 7-bit word is the digital equivalent of the input analog sample. Ihe clock to the switches is disabled if the digital comparator fires, or the input digital word is equivalent to zero, or if the analog comparator fires.
Ihis basic logarithmic converter of Fig. 12 can be made more efficient in terms of speed of operation by the addition of another capacitor C3(2pF), which like C2 is also used for discharging capacitor Cl. (See Fig. 14) Ihe two capacitors C2 and C3 are used alter-nately to discharge capacitor Cl i.e., when the charge on capacitor Cl is being shared with capacitor C2, capacitor C3 is discharged and vice versa. ~his results in twice the original conversion speed. ~
A block-schematic diagram of a preferred version of a logarithmic ADC-DAC 601 is shown in Fig. 14. Here an 8-bit counter 611 is used with a decoder 613 to generate the required control and timing signals. Counter 611 is asynchronous and is operated from an oscillator 615 with a clock frequency of 4 MHz. A least significant bit (QO) of counter 611 provides a 2 ME~z input to a two phase clock generator. Ihe two phases are then used to control num-erous switches of the logarithmic signal conversion cir-cuitry 601. All 8 bits (QO to Q7) of the counter 611 are connected to a digital comparator 621 and to an output latch 623.

~d J CID 5513 13:~5674 Each conversion cycle illustratively takes 40 microseconds with 4 MHz time base. On supplying power to the circuit, the counter 611 is reset, the capacitor Cl is charged, and a D/A cycle is initiated. In analog-to-digital conversion a Sample.H high signal is asserted andused to sample an anti-aliased analog input s;gnal from microphone 13. An analog comparator 651 compares the volt-age on capacitor Cl with the analog input voltage via oper-ational amplifier and switchlng circuitry 653. When the analog comparator 651 fires, the counter 611 value at that instant is latched into latch 623. Since the analog com-parator output is asynchronous, it is latched by a D flip-flop in latch block 623. Ihe output of the D flip-flop enables or disables the latch 623.
During a D/A cycle an input latch 631 holds a digital word from the DSP chip for conversion to analog form. Ihe outputs of the counter 611 and the latch 631 are compared by the digital comparator 621, whose output goes high when the count value is same as the input word Ihis comparator output signal disables the clock to the switches, and capacitor Cl thereupon holds the analog voltage to which the digital value in latch 631 is con-verted. A sample-and-hold (S/~) circuit 641 is enabled and sample the analog voltage on capacitor Cl and hold it as the analog output of the logarithmic D~C.
Some design and layout considerations are next discussed. It is possible to implement accurate capacitor ratios in MOS technology. qhe electrodes of MOS capacitors can be realized in the following ways:

1. Metal or Polysilicon-over-diffusion structure In this structure a thin layer of SiO2 is grown over a heavily doped region in the substrate. Ihis doped d , CID 5513 ~' PAIENI
-region forms the bottom plate of the capacitor and the top plate is formed by covering the SiO2 with metal or polysilicon. Ihe variation in oxide thickness is usually within ~15~ causing a 0.1~ error in the capa-citance value.

2. Polysilicon-over-Polysilicon structure In a silicon-gate "double poly" process, a second layer of low resistivity polysilicon is used as an intercon-nect or or the formation of a floating gate for memory application. Ihese two poly layers can be used as the plates of a capacitor. A major disadvantage oE this type of capacitor is the random variation in oxide thickness caused by the granularity of the polysilicon surface causing a 0.12% error in the capacitance val-ue. Ihe ratio of capacitance to area for this type of structure is smaller than that of a Metal or Polysilicon-over-diffusion structure.

3. Metal-over-Polysilicon structure . .
Ihe two plates of the capacitor are metal and polysili-con. Ihe properties of this type of capacitor are similar to the polysilicon-over-polysilicon structure.

In all the above structures, there is a large parasitic capacitance from the bottom plate of the capaci-tor to the substrate, and thus to the substrate bias. In the case of the metal or polysilicon over diffusion capaci-tor, where the bottom plate is embedded in the substrate, this stray capacitance is that of a reverse biased p-n junction and can be 15-30~ of the total capacitance (C), depending on the oxide thickness and the construction of 8pd ~ , CID 5513 PAIEN~
~ .
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the device. For the "double poly" and metal-over-polysilicon structures the stray capacitance associated with the bottom plate is typically 5-20% of C.
Ihe accuracy of the logarithmic D/A converter depends on the accuracy of the ratio (Cl/(Cl~C2).
Ihe capacitance ratio is affected by the inaccuracies of the capacitances themselves. Errors in the ratio are due to change in area (random edge variations), the oxide thlckness of the capacitors, and the "undercut". Ihis undercut is due to the lateral etching o~ the plates of the capacitor along its perimeter during fabrication. It decreases C, which is proportional to the perimeter of the device. A common approach to avoid this undercut is to connect identically sized small "unit" capacitors in paral-lel to construct a larger one. Using this technique thearea/perimeter ratio is nearly the same for any two capaci-tors. However, these capacitors occupy large areas since they utilize only 60% of the available space. A typical layout of a capacitor is cross-shaped. Ihe capacitors Cl, c2, and C3 are implemented with slmilar layouts.
In its digital to analog conversion aspect, elec-tronic signal conversion apparatus is provided in Fig. 14 which has a circuit 631 for temporarily holding a digital value which is to be converted to analog form. First and second capacitors Cl and C2 are provided. Switches are generally operable for executing selective operations including selectively charging at least one of the first and second capacitors, selectively discharging at least one of tlle first and second capacitors, and selectively con-necting the first and second capacitors so that a redistri-bution of charge between them occurs. In Fig. 14 switch POS SGN and PRE A2D act as a first switch generally opera-ble for charging first capacitor Cl to a first voltage from ~pd ~' '~ PAIENI

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the source of voltage. Sw,itch PI~S2 discharges second capacitor C2 to a voltage level different from the voltage to which first capacitor Cl is charged. A third switch A2D
connects first capacitor Cl so charged to second capacitor C2 so that a redistribution of charge occurs and the volt-age across first capacitor Cl is reduced to a predetermined fraction of the first voltage.
Decoder 613 responds to counter 611 for repeated-ly operating the second and third switches PE~S2 and A2D
alternately so that the voltage across first capacitor Cl is repeatedly reduced by the predetermined fraction a num-ber of times, the number being represented by the digital value held in the latch 631, so that the voltage remaining across first capacitor Cl after being reduced for that number of times is an analog voltage to which the digital value ls converted. Ihe analog voltage to which the digi-tal value is converted is substantially proportional to a first constant d to a power number N where N is substan-tially proportional to the number of times that the"first and second capacitors are connected, or the number of redistribution operations performed by the switches in a particular conversion. Ihe number N is a direct function of and proportional to the digital value which is to be converted to analog form, so that the voltage across at least one of the capacitors Cl and C2 after the operations are executed is an analog voltage to which the digital value is converted. It is believed that the value d is preferably established between 0.85 and 0.99. In most cases, the capacitance Cl is preferably at least ten times the capacitance C2.
In the analog to digital conversion aspect decoder 613 operates the switches to make them perform a sequence of the selective operat,lons among which operations 8~d J PAIENI

133~674 the redistribution of charge repeatedly occurs a number of times until a predetermined electrical condition, involving the sample of the analog signal, occurs. Circuitry pro-duces a digital value as a function of the number of times the redistribution of charge occurs, so that the digital value so produced when the operations are executed ls the digital value to which the sample of the analog signal is converted. For example, counter 611 continually increments a count of a number proportional to the number of times the selective operation of redistributing charge occurs. Elec-tronic comparing circuitry 653 and 651 responds to the voltage across the first capacitor Cl reaching a particular level and supplying a control signal on a line 661 to data latch 623 to latch the count from counter 611 when the level is reached.
A process diagram of Fig. 15 shows illustrative operations of logarithmic A/D signal conversion. Opera-tions commence with a SIARI 701 and proceed to a step 703 to reset a counter value N to zero. Ihe analog signal is sampled in a step 705. Step 707 disconnects C2 ~rom Cl and discharges the second capacitor to a voltage level differ-ent from the voltage to which the first capacitor is charged. Ihen a step 709 charges the first capacitor to a first voltage from the source of voltage.
A test step 711 determines whether the voltage across first capacitor Cl is less than the level sampled in step 705. If not operations proceed to a step 713 to con-nect the first capacitor so charged to the second capacitor so that a redistribution of charge occurs and the voltage across the first capacitor is reduced to a predetermined fraction of its previous voltage. Ihen a step 715 incre-ments the counter index N. Step 717 disconnects C2 from Cl and again discharges the second capacitor to a voltage ~ pd ~J PAIEN~
..

133~67~
level different from the voltage to which the first capaci-tor is charged. Operations return to test step 711 and until the test is satisfi.ed, repeatedly perEorm the dis-charging and connecting steps alternately (713-717) so that the voltage across said first capacitor is repeatedly reduced by the predetermined fraction a number of t.imes, the number being represented by the digital value N. When the test of step 711 is satisfied, the voltage remaining across the first capacitor after being reduced for that number of t.imes is an analog voltage to which the digital value corresponds. Operations branch from step 711 to a step 719 to latch index N as the log digital representation and provide it as output. D/A conversion operates con-versely. Operations loop back to step 703 through a test 721 if the process is to continue. If not, operations branch from test 721 to an END 723.
Ihe invention comprehends numerous embodiments using digital or analog technology and incorporating soft-ware, hardware, or firmware as appl.ications dictate;
Applicat.ions, combinations and processes for hearing aids, public address systems and other electronic systems.gener-ally for use in air, underwater, space or in other environ-ments are within the scope of the invention.
In view of the above, it will be seen that the several objects of the invention are achieved and other advantageous results attained.
As various changes could be made in the above constructions without departing from the scope of the invention, it is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a scope-limitLng sense.

Claims (46)

1. An electronic filter for filtering an electrical signal, comprising:
a filter having an input for receiving a signal to be filtered, having an output producing a filtered signal and having signal processing means including logarithmic filter means producing an intermediate output signal;
said filter having a plurality of filter stages having inputs and outputs coupled in cascade, each said filter stage filtering signals at its input according to electrical representations of filter parameters;
electronic control means coupled to said filter for altering the electrical representations to vary a value of each of said filter parameters in substantially constant percentage amounts of the value of that one of said filter parameters;
each said filter stage having means connected to it for storing its electrical representations of filter parameters;
each said filter stage including means for adding its electrical representations of the filter parameters to the signal at its input thereby producing a filter sum signal;
at least one of said filter stages including means for producing a filter signal in logarithmic form at its out-put by combining its filter sum signal with a signal from the output of one of the other filter stages; and wherein said electronic filter further comprises means connected to said signal processing means for multi-plexing its intermediate output signal with the electrical signal to be filtered and for providing the multiplexed signal to the input of said filter whereby said logarithmic filter means operates as both a logarithmic prefilter and a logarithmic postfilter.

2. An electronic filter as set forth in claim 1 wherein said signal processing means further includes limiting means, responsive to said logarithmic filter means, for producing the intermediate output signal generally limited to a predetermined range of electrical values.

3. An electronic filter as set forth in claim 1 wherein said means for producing a filter signal in loga-rithmic form includes means for nonlinearly combining the filter sum signal for that filter stage with a signal from an output of another filter stage.

4. An electronic filter as set forth in claim 1 wherein said logarithmic filter means includes means for filtering signals through the series of filter stages from a first to a last of said filter stages and then filtering signals back through said series of filter stages from the last to the first of said filter stages.

5. An electronic filter as set forth in claim 1 wherein said logarithmic filter means includes means for filtering signals through the series of filter stages from a first to a last of said filter stages and then filtering signals back through said series of filter stages from the last to the first of said filter stages, whereby said means for filtering processes in two directions, each particular filter stage being responsive to the means for storing an electrical representation of a filter parameter connected thereto for processing the filter signals in both directions with respect to each same filter parameter in that particular filter stage.

6. An electronic filter as set forth in claim 1 wherein said means for storing includes means for holding digital representations of a plurality of filter parameters for each individual filter stage, and second means for multi-plexing the plurality of filter parameters controlling the filtering of each individual filter stage.

7. An electronic filter as set forth in claim 1 wherein said means for storing includes means for holding a number of digital representations of filter parameters for each individual filter stage, and second means for multi-plexing the number of digital representations controlling the filtering of each individual filter stage so that said loga-rithmic filter means operates as a plurality of bandpass filters equal in number to the number of digital representa-tions of filter parameters held for each individual filter stage.

8. An electronic filter as set forth in claim 1 wherein said means for storing includes means for holding a number of digital representations of filter parameters for each individual filter stage, means for selecting correspond-ing filter parameters in all of the filter stages at once in accordance with values of an index, and means for multiplex-ing the number of digital representations controlling the filtering of each individual filter stage so that said loga-rithmic filter means operates as a plurality of bandpass filters wherein each bandpass filter has a filter character-istic defined by the set of filter parameters in the filter stages selected according to the same value of the index.

9. An electronic filter as set forth in claim 8 wherein said logarithmic filter means also includes means for filtering signals through the series of filter stages from a first to a last of said filter stages and then filtering signals back through said series of filter stages from the last to the first of said filter stages, whereby said means for filtering processes in two directions, each particular filter stage being responsive to the means for storing an electrical representation of a filter parameter connected thereto for processing the filter signals in both directions with respect to each same filter parameter in that particular filter stage.

10. An electronic filter as set forth in claim 8 further comprising means for supplying clock pulses, means for counting the clock pulses to produce a count output, and means for decoding the count output into control signals for coordinating the operations of said means for selecting and said means for multiplexing.

11. An electronic filter as set forth in claim 1 further comprising means for supplying clock pulses, means for counting the clock pulses to produce a count output, and means for decoding the count output into control signals for coordinating the operations of said logarithmic filtering means and said means for multiplexing.

12. An electronic filter as set forth in claim 1 wherein said logarithmic filter means is a digital filter.

13. An electronic filter as set forth in claim 12 wherein the electrical signal to be filtered is an analog signal and the electronic filter further comprises analog-to-digital converter means for converting the electrical signal to be filtered to logarithmic digital form for said logarith-mic filter means, and digital-to-analog converter means for converting the filter signal in logarithmic form at the out-put of said one of said filter stages of said logarithmic filter means to analog linear form.

14. An electronic filter as set forth in claim 13 wherein said logarithmic filter means and means for multi-plexing are integrated together on a first very large scale integration (VLSI) die and said analog-to-digital converter means and said digital-to-analog converter means are integrated together on a second VLSI die.

15. An electronic filter as set forth in claim 1 wherein each of said filter stages includes a shift register having cascaded cells for temporarily holding a filter signal in logarithmic form for prefilter purposes and a filter signal in logarithmic form for postfilter purposes and shifting each filter signal to an adjacent one of said filter stages.

16. An electronic filter for filtering an electrical signal, comprising:
a filter having an input for receiving a signal to be filtered, having an output producing a filtered signal and having signal processing means including logarithmic filter means producing an intermediate output signal;
said filter having a series of filter stage means having inputs and outputs coupled in cascade, each said filter stage means filtering signals at its input according to electrical representations of filter parameters;
electronic control means coupled to said filter for altering the electrical representations to vary a value of each of said filter parameters in substantially constant percentage amounts of the value of that one of said filter parameters;
means for storing electrical representations of filter parameters for said filter stage means; and said series of filter stage means including means for filtering signals through the series of filter stage means from a first to a last of said filter stage means and then filtering signals back through said series of filter stage means from the last to the first of said filter stage means to produce the filtered signal.

17. An electronic filter as set forth in claim 16 wherein at least one of said filter stage means includes means for adding an electrical representation of a filter parameter to the electrical signal to be filtered thereby producing a filter sum signal and means for producing a filter signal in logarithmic form for output to another filter stage means by nonlinearly combining the filter sum signal with a signal from a selected filter stage means in the series of filter stage means.

18. An electronic filter as set forth in claim 16 wherein at least two of said filter stage means are in predecessor-successor relationship and said means for filter-ing signals through the series of filter stage means includes respective means in each of said at least two filter stage means for electronic processing of signals supplied by its predecessor stage means and corresponding means for multiplexing signals from its adjacent predecessor stage means and its successor filter stage means.

19. An electronic filter as set forth in claim 16 wherein at least two of said filter stage means are in predecessor-successor relationship and said means for filter-ing signals through the series of filter stage means includes means for electronic processing of the signals, first means in each of said filter stage means connected to said means for electronic processing including a first shift register having cascaded cells for transferring signals supplied by its predecessor stage for its successor filter stage means in said series of filter stage means and second means in each of said filter stages connected to said means for electronic processing including a second shift register having cascaded cells for transferring further filter signals supplied by its successor stage to its predecessor filter stage means in said series of filter stage means.

20. An electronic filter as set forth in claim 19 wherein said means for filtering signals through the series of filter stage means further includes respective means in each of said at least two filter stage means for multiplexing signals for said means for electronic processing from the first shift register means in its predecessor filter stage means and from the second shift register means in its successor filter stage means.

21. An electronic filter as set forth in claim 20 wherein said means for electronic processing includes means for adding each electrical representation of a filter param-eter to the electrical signal to be filtered thereby produc-ing a filter sum signal and means for producing a filter signal in substantially logarithmic form for the first or second shift register means in the filter stage means to which each filter parameter corresponds by nonlinearly com-bining a filter sum signal for that filter stage means with a signal from the means for multiplexing for that filter stage means derived from the first shift register means in the predecessor filter stage means or from the second shift register means in the successor filter stage means respectively.

22. An electronic filter as set forth in claim 16 wherein said filter means further comprises:
limiting means, responsive to a signal from an output of a filter stage means in said series of filter stage means, for producing the filtered signal output generally limited to a predetermined range of electrical values; and means, connected to the first of said filter stage means, for multiplexing the filtered signal output of said limiting means with the electrical signal to be filtered so that the electrical signal is prefiltered through said series of filter stage means and back again, then limited by said limiting means, and then postfiltered through said series of filter stage means and back again.

23. An electronic filter as set forth in claim 22 wherein each of said filter stage means includes a shift register having cascaded cells for temporarily holding a filter signal for prefilter purposes and another filter signal for postfilter purposes and shifting each filter signal to an adjacent one of said filter stage means.

24. An electronic filter as set forth in claim 22 wherein at least some of the filter stage means are in predecessor-successor relationship and each of these filter stage means includes first shift register means having cascaded cells for temporarily holding a first filter signal for prefilter purposes and a second filter signal for post-filter purposes and for transferring the first and second filter signals to a successor filter stage means in each series of filter stage means, and second shift register means having cascaded cells for temporarily holding a third filter signal for prefilter purposes and a fourth filter signal for postfilter purposes and for transferring the third and fourth filter signals to a predecessor filter stage means in said series of filter stage means.

25. An electronic filter as set forth in claim 16 further comprising means connected to said filter stage means for multiplexing the filtered signal output with the electrical signal to be filtered so that said filter stage means operates as both a prefilter and a postfilter.

26. An electronic filter as set forth in claim 25 wherein said filter means includes means for storing digital representations of a number of filter parameters for each individual filter stage means, and second means for multiplex-ing the operations of each individual filter stage means to use the plurality of filter parameters for that individual filter stage means.

27. An electronic filter as set forth in claim 16 wherein said filter means includes means for storing digital representations of a number of filter parameters in associa-tion with each individual filter stage means, and means for multiplexing the operations of each individual filter stage means with respect to the digital representations so that said filter means operates as a plurality of bandpass filters equal in number to the number of filter parameters associated with each filter stage means.

28. An electronic filter as set forth in claim 16 wherein said filter means includes means for storing digital representations of a number of filter parameters for each filter stage means, means for selecting corresponding filter parameters in all of the filter stage means at once in accor-dance with values of an index, and means for multiplexing the operations of each individual filter stage means with respect to the digital representations so that said filter means operates as a plurality of bandpass filters wherein each bandpass filter has a filter characteristic defined by the set of filter parameters in the filter stages selected according to the same value of the index.

29. An electronic filter as set forth in claim 16 wherein said filter means is a digital filter further compris-ing means for supplying clock pulses, means for counting the clock pulses to produce a parallel digital count output, and means for decoding the count output into control signals for coordinating the operations of said filter stage means.

30. An electronic filter as set forth in claim 16 wherein at least one of said filter stage means includes digital means for adding an electrical representation of a filter parameter to the electrical signal to be filtered thereby producing a filter sum signal and programmed logic array means for producing a filter signal in substantially logarithmic form for output to another filter stage means by nonlinearly combining the filter sum signal with a signal from a selected filter stage means in the series of filter stage means, said filter means further including means for supplying clock pulses, means for counting the clock pulses to produce a parallel digital count output, and means for decoding the count output into control signals for coordi-nating the operations of said filter stage means.

31. An electronic filter for filtering an electri-cal signal having a polarity, comprising:
a filter having an input for receiving a signal to be filtered, having an output producing a filtered signal and having signal processing means including logarithmic filter means producing an intermediate output signal;
said filter having a plurality of filter stages having inputs and outputs coupled in cascade, each said filter stage respectively filtering signals at its input according to electrical representations of filter parameters;
said filter including means for filtering signals through the series of filter stages from a first to a last of said filter stages and then filtering signals back through said series of filter stages from the last to the first of said filter stages; and electronic control means coupled to said filter for altering the electrical representations to vary a value of each of said filter parameters in substantially constant percentage amounts of the value of that one of said filter parameters.

32. An electronic filter as set forth in claim 31 wherein said electronic control means operates by keeping running totals that are incremented and decremented as a function of the polarity of the electrical signal to be filtered and as a function of the polarity of at least one of said plurality of filter signals, by keeping digital values in logarithmic form representing each of said filter parame-ters, and by respectively adding the running totals to corresponding ones of said digital values.

33. An electronic filter as set forth in claim 32 wherein said electronic control means respectively adds the running totals to the corresponding ones of said digital values less frequently than the incrementing and decrementing occurs.

34. An electronic filter as set forth in claim 31 wherein said electronic control means is responsive to first and second externally derived control signals having respec-tive changing polarities, wherein said electronic control means temporarily stores a series of values representing changing polarities of the first externally derived control signal, and wherein the electronic control means increases and decreases each of said filter parameters in magnitude by a constant amount, the increasing and decreasing respectively depending on whether a corresponding value in said series of values has the same or opposite polarity compared to the polarity of the second externally derived control signal currently.

35. An electronic filter as set forth in claim 31 wherein at least two of said filter stages are in predecessor-successor relationship and said means for filtering signals through the series of filter stage means includes means con-nected to an individual filter stage for multiplexing signals from outputs of its predecessor and successor filter stages for that individual filter stage.

36. An electronic filter as set forth in claim 31 wherein at least two of said filter stages are in predecessor-successor relationship and said means for filtering signals through the series of filter stage means includes means con-nected to each of these filter stages including a first shift register having cascaded cells for transferring the filter signals to a successor filter stage to the connected filter stage and a second shift register having cascaded cells for transferring a further filter signal to a predecessor filter stage to the connected filter stage in said series of filter stage means.

37. An electronic filter for an electroacoustic system having microphone means for generating an electrical output from external sounds and electrically driven trans-ducer means for emitting sound, some of the sound emitted by the transducer means returning to the microphone means to add (Continuing claim 37) a feedback contribution to its electrical output, the electronic filter comprising:
means for converting the electrical output of the microphone means to a logarithmic electrical representation;
first means for combining the microphone output so converted with an adaptive output in logarithmic electrical form to produce a combined signal input in logarithmic electrical form;
means for electronically filtering the combined signal input in logarithmic form to produce a filtered signal in logarithmic form;
means for generating a distinct signal;
second means for combining the filtered signal with the distinct signal for the transducer means; and said means for electronically filtering also including logarithmic adaptive filter means having electri-cally stored parameters representing coefficients in loga-rithmic forms, said means for electronically filtering further including linear control means for continually altering the coefficients to vary them in magnitude in substantially constant percentage amounts, said logarithmic adaptive filter means further including means for electronic processing of the filtered signal and the distinct signal relative to the electrically stored parameters to produce an adaptive output in logarithmic form to said first means for combining to substantially offset the feedback contribution in the electrical output of the microphone means in the electroacoustic system.

38. An electronic filter for an electroacoustic system having microphone means for generating an electrical output from external sounds and electrically driven trans-ducer means for emitting sound corresponding to the external sound, some of the sound emitted by the transducer means returning to the microphone means to add a feedback contri-bution to its electrical output, the electronic filter comprising:
means for converting the electrical output of the microphone means to an electrical representation;
first means for combining the microphone output so converted with an adaptive output to produce a combined signal input;
electronic filter means for electronically filter-ing the combined signal input to produce a filtered signal;
adaptive filter means having electrically stored parameters representing coefficients, said adaptive filter means including linear control means for altering the coef-ficients in substantially constant percentage amounts, said linear control means interconnected with said electronically filtering means, said adaptive filter means further including means for electronic processing of the filtered signal rela-tive to the electrically stored coefficients to produce said adaptive output to said first means for combining to substan-tially offset the feedback contribution in the electrical output of the microphone means in the electroacoustic system;
means for generating a distinct signal; and second means for combining the filtered signal with the distinct signal for the transducer means.

39. An electronic filter as set forth in claim 38 wherein said electronically filtering means includes loga-rithmic filter means having a series of filter stages with inputs and outputs in cascade and respective means connected to said filter stages for storing electrical representations of filter parameters, said filter stages including means for respectively adding the electrical representations of the filter parameters to the combined signal input thereby pro-ducing a set of filter sum signals, at least one of said filter stages including means for producing the filtered signal in logarithmic form at its output by combining a filter sum signal for that filter stage with a signal from an output of another filter stage.

40. An electronic filter as set forth in claim 39 wherein said means for electronically filtering means further includes limiting means, responsive to a signal from an output of a filter stage in said logarithmic filter means, for producing an intermediate output signal generally limited to a predetermined range of electrical values.

41. An electronic filter as set forth in claim 40 wherein said electronically filtering means further includes means for multiplexing the intermediate output signal with the combined signal input applied to the electronic filtering means so that said logarithmic filter means operates as both a logarithmic prefilter and a logarithmic postfilter to said limiting means.

42. An electronic filter as set forth in claim 39 wherein said logarithmic filter means includes means for filtering signals through the series of filter stages from a first to a last of said filter stages and then filtering signals back through said series of filter stages from the last to the first of said filter stages.

43. An electronic filter as set forth in claim 39 wherein said logarithmic filter means includes means for hold-ing a number of digital representations of filter parameters for each individual filter stage, and second means for multi-plexing the number of digital representations controlling the filtering of each individual filter stage so that said loga-rithmic filter means operates as a plurality of bandpass filters equal in number to the number of digital representa-tions of filter parameters held for each individual filter stage.

44. An electronic filter as set forth in claim 31 wherein said filter includes respective means coupled to said filter stages for storing electrical representations of filter parameters corresponding to logarithms of values of filter coefficients, and wherein said filter stages include means for respectively adding the electrical representations of the filter parameters to the electrical signal to be filtered thereby producing a set of filter sum signals, at least one of said filter stages including means for producing a filter signal in logarithmic form at its output by combin-ing a filter sum signal for that filter stage with a signal from an output of another filter stage.

45. An electronic filter as in claim 31 wherein said filter operates in logarithmic form.

46. An electronic filter as in claim 38 wherein said electrical representation is substantially in logarith-mic form, wherein said combined signal is substantially in logarithmic form, wherein said adaptive output is in loga-rithmic form, wherein said combined signal is substantially (Continuing claim 46) in logarithmic form, wherein said filtered signal is substan-tially in logarithmic form, wherein said coefficients are substantially in logarithmic form, and wherein said adaptive filter means operates in logarithmic form.