CA2000151A1 - Parallel Data Processor - Google Patents

Parallel Data Processor

Info

Publication number
CA2000151A1
CA2000151A1 CA2000151A CA2000151A CA2000151A1 CA 2000151 A1 CA2000151 A1 CA 2000151A1 CA 2000151 A CA2000151 A CA 2000151A CA 2000151 A CA2000151 A CA 2000151A CA 2000151 A1 CA2000151 A1 CA 2000151A1
Authority
CA
Canada
Prior art keywords
cell
data processor
parallel data
cells
circuitry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2000151A
Other languages
French (fr)
Other versions
CA2000151C (en
Inventor
Wlodzimierz Holsztynski
Richard W. Benton
W. Keith Johnson
Robert A. Mcnamara
Roger S. Naeyaert
Douglas A. Noden
Ronald W. Schoomaker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Martin Marietta Corp
Original Assignee
Martin Marietta Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Martin Marietta Corp filed Critical Martin Marietta Corp
Publication of CA2000151A1 publication Critical patent/CA2000151A1/en
Application granted granted Critical
Publication of CA2000151C publication Critical patent/CA2000151C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus

Abstract

A parallel data processor comprised of an array of identical cells concurrently performing identical operations under the direction of a central controller, and incorporating one or more of a special cell architecture including a segmented memory, conditional logic for preliminary processing, and circuitry for indicating when the cell is active, and programmable cell interconnection including cell bypass and alternate connection of edge cells.
CA002000151A 1988-10-07 1989-10-04 Parallel data processor Expired - Lifetime CA2000151C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US25471888A 1988-10-07 1988-10-07
US07/254,718 1988-10-07

Publications (2)

Publication Number Publication Date
CA2000151A1 true CA2000151A1 (en) 1990-04-07
CA2000151C CA2000151C (en) 1997-12-09

Family

ID=22965319

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002000151A Expired - Lifetime CA2000151C (en) 1988-10-07 1989-10-04 Parallel data processor

Country Status (6)

Country Link
US (1) US5421019A (en)
EP (1) EP0390907B1 (en)
JP (1) JP2930341B2 (en)
CA (1) CA2000151C (en)
DE (1) DE68926783T2 (en)
WO (1) WO1990004235A1 (en)

Families Citing this family (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IE920032A1 (en) * 1991-01-11 1992-07-15 Marconi Gec Ltd Parallel processing apparatus
WO1992018935A1 (en) * 1991-04-09 1992-10-29 Fujitsu Limited Data processor and data processing method
US5689719A (en) * 1991-06-28 1997-11-18 Sanyo Electric O., Ltd. Parallel computer system including processing elements
US5717947A (en) * 1993-03-31 1998-02-10 Motorola, Inc. Data processing system and method thereof
JPH076146A (en) * 1993-06-18 1995-01-10 Fujitsu Ltd Parallel data processing system
US6073185A (en) * 1993-08-27 2000-06-06 Teranex, Inc. Parallel data processor
US5603046A (en) * 1993-11-02 1997-02-11 Motorola Inc. Method for complex data movement in a multi-processor data processing system
US5742848A (en) * 1993-11-16 1998-04-21 Microsoft Corp. System for passing messages between source object and target object utilizing generic code in source object to invoke any member function of target object by executing the same instructions
WO1996008778A1 (en) * 1994-09-13 1996-03-21 Lockheed Martin Corporation Parallel data processor
GB2293468B (en) * 1994-09-21 1999-09-29 Sony Uk Ltd Data processing systems
US5943242A (en) 1995-11-17 1999-08-24 Pact Gmbh Dynamically reconfigurable data processing system
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19651075A1 (en) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like
US6338106B1 (en) 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
DE19654593A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Reconfiguration procedure for programmable blocks at runtime
DE19654595A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0 and memory bus system for DFPs as well as building blocks with two- or multi-dimensional programmable cell structures
DE19654846A1 (en) 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Process for the independent dynamic reloading of data flow processors (DFPs) as well as modules with two- or multi-dimensional programmable cell structures (FPGAs, DPGAs, etc.)
ATE243390T1 (en) 1996-12-27 2003-07-15 Pact Inf Tech Gmbh METHOD FOR INDEPENDENT DYNAMIC LOADING OF DATA FLOW PROCESSORS (DFPS) AND COMPONENTS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL STRUCTURES (FPGAS, DPGAS, O.L.)
DE19704044A1 (en) * 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Address generation with systems having programmable modules
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704728A1 (en) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Method for self-synchronization of configurable elements of a programmable module
DE19704742A1 (en) 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internal bus system for DFPs, as well as modules with two- or multi-dimensional programmable cell structures, for coping with large amounts of data with high networking effort
US9092595B2 (en) 1997-10-08 2015-07-28 Pact Xpp Technologies Ag Multiprocessor having associated RAM units
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (en) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Repairing integrated circuits by replacing subassemblies with substitutes
DE19807872A1 (en) 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Method of managing configuration data in data flow processors
US6067609A (en) * 1998-04-09 2000-05-23 Teranex, Inc. Pattern generation and shift plane operations for a mesh connected computer
US6185667B1 (en) 1998-04-09 2001-02-06 Teranex, Inc. Input/output support for processing in a mesh connected computer
US6173388B1 (en) 1998-04-09 2001-01-09 Teranex Inc. Directly accessing local memories of array processors for improved real-time corner turning processing
US6212628B1 (en) 1998-04-09 2001-04-03 Teranex, Inc. Mesh connected computer
FR2778764B1 (en) * 1998-05-15 2001-01-05 France Etat METHOD FOR CONTROLLING A PROCESSOR NETWORK
US7003660B2 (en) 2000-06-13 2006-02-21 Pact Xpp Technologies Ag Pipeline configuration unit protocols and communication
AU5805300A (en) 1999-06-10 2001-01-02 Pact Informationstechnologie Gmbh Sequence partitioning in cell structures
US6532317B2 (en) 2000-04-17 2003-03-11 Polyoptic Technologies, Inc. Optical circuit board
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US7595659B2 (en) 2000-10-09 2009-09-29 Pact Xpp Technologies Ag Logic cell array and bus system
US6854117B1 (en) 2000-10-31 2005-02-08 Caspian Networks, Inc. Parallel network processor array
GB2370381B (en) 2000-12-19 2003-12-24 Picochip Designs Ltd Processor architecture
GB2370380B (en) 2000-12-19 2003-12-31 Picochip Designs Ltd Processor architecture
US6990555B2 (en) * 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US9436631B2 (en) 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
US9552047B2 (en) 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US9141390B2 (en) 2001-03-05 2015-09-22 Pact Xpp Technologies Ag Method of processing data with an array of data processors according to application ID
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US9250908B2 (en) 2001-03-05 2016-02-02 Pact Xpp Technologies Ag Multi-processor bus and cache interconnection system
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
RU2202123C2 (en) * 2001-06-06 2003-04-10 Бачериков Геннадий Иванович Programmable-architecture parallel computer system
WO2002103532A2 (en) 2001-06-20 2002-12-27 Pact Xpp Technologies Ag Data processing method
US10031733B2 (en) 2001-06-20 2018-07-24 Scientia Sol Mentis Ag Method for processing data
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
EP1483682A2 (en) 2002-01-19 2004-12-08 PACT XPP Technologies AG Reconfigurable processor
JP3902741B2 (en) * 2002-01-25 2007-04-11 株式会社半導体理工学研究センター Semiconductor integrated circuit device
US8127061B2 (en) 2002-02-18 2012-02-28 Martin Vorbach Bus systems and reconfiguration methods
US9170812B2 (en) 2002-03-21 2015-10-27 Pact Xpp Technologies Ag Data processing system having integrated pipelined array data processor
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
AU2003289844A1 (en) 2002-09-06 2004-05-13 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US7237041B2 (en) * 2002-12-02 2007-06-26 Adc Telecommunications, Inc. Systems and methods for automatic assignment of identification codes to devices
US20040252547A1 (en) * 2003-06-06 2004-12-16 Chengpu Wang Concurrent Processing Memory
EP1676208A2 (en) 2003-08-28 2006-07-05 PACT XPP Technologies AG Data processing device and method
US7707387B2 (en) 2005-06-01 2010-04-27 Microsoft Corporation Conditional execution via content addressable memory and parallel computing execution model
US7451297B2 (en) * 2005-06-01 2008-11-11 Microsoft Corporation Computing system and method that determines current configuration dependent on operand input from another configuration
US7793040B2 (en) * 2005-06-01 2010-09-07 Microsoft Corporation Content addressable memory architecture
US8250503B2 (en) 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software
EP2477109B1 (en) * 2006-04-12 2016-07-13 Soft Machines, Inc. Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
US8856197B2 (en) 2008-10-16 2014-10-07 Nxp, B.V. System and method for processing data using a matrix of processing units
GB2470037B (en) 2009-05-07 2013-07-10 Picochip Designs Ltd Methods and devices for reducing interference in an uplink
GB2470891B (en) 2009-06-05 2013-11-27 Picochip Designs Ltd A method and device in a communication network
GB2470771B (en) 2009-06-05 2012-07-18 Picochip Designs Ltd A method and device in a communication network
GB2482869B (en) 2010-08-16 2013-11-06 Picochip Designs Ltd Femtocell access control
EP2689326B1 (en) 2011-03-25 2022-11-16 Intel Corporation Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
GB2489919B (en) 2011-04-05 2018-02-14 Intel Corp Filter
GB2489716B (en) 2011-04-05 2015-06-24 Intel Corp Multimode base system
KR20150130510A (en) 2013-03-15 2015-11-23 소프트 머신즈, 인크. A method for emulating a guest centralized flag architecture by using a native distributed flag architecture

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3287703A (en) * 1962-12-04 1966-11-22 Westinghouse Electric Corp Computer
US3643236A (en) * 1969-12-19 1972-02-15 Ibm Storage having a plurality of simultaneously accessible locations
US3815095A (en) * 1972-08-29 1974-06-04 Texas Instruments Inc General-purpose array processor
US4187551A (en) * 1975-11-21 1980-02-05 Ferranti Limited Apparatus for writing data in unique order into and retrieving same from memory
JPS5352029A (en) * 1976-10-22 1978-05-12 Fujitsu Ltd Arithmetic circuit unit
US4215401A (en) * 1978-09-28 1980-07-29 Environmental Research Institute Of Michigan Cellular digital array processor
US4309755A (en) * 1979-08-22 1982-01-05 Bell Telephone Laboratories, Incorporated Computer input/output arrangement for enabling a simultaneous read/write data transfer
US4314349A (en) * 1979-12-31 1982-02-02 Goodyear Aerospace Corporation Processing element for parallel array processors
US4384273A (en) * 1981-03-20 1983-05-17 Bell Telephone Laboratories, Incorporated Time warp signal recognition processor for matching signal patterns
US4524455A (en) * 1981-06-01 1985-06-18 Environmental Research Inst. Of Michigan Pipeline processor
US4574394A (en) * 1981-06-01 1986-03-04 Environmental Research Institute Of Mi Pipeline processor
US4533993A (en) * 1981-08-18 1985-08-06 National Research Development Corp. Multiple processing cell digital data processor
GB2111267B (en) * 1981-12-08 1985-10-16 Burroughs Corp Constant-distance structure polycellular very large scale integrated circuit
US4507726A (en) * 1982-01-26 1985-03-26 Hughes Aircraft Company Array processor architecture utilizing modular elemental processors
US4667308A (en) * 1982-07-21 1987-05-19 Marconi Avionics Limited Multi-dimensional-access memory system with combined data rotation and multiplexing
US4489381A (en) * 1982-08-06 1984-12-18 International Business Machines Corporation Hierarchical memories having two ports at each subordinate memory level
US4511967A (en) * 1983-02-15 1985-04-16 Sperry Corporation Simultaneous load and verify of a device control store from a support processor via a scan loop
US4739474A (en) * 1983-03-10 1988-04-19 Martin Marietta Corporation Geometric-arithmetic parallel processor
US4630230A (en) * 1983-04-25 1986-12-16 Cray Research, Inc. Solid state storage device
US4635292A (en) * 1983-12-19 1987-01-06 Matsushita Electric Industrial Co., Ltd. Image processor
US4573116A (en) * 1983-12-20 1986-02-25 Honeywell Information Systems Inc. Multiword data register array having simultaneous read-write capability
GB8401805D0 (en) * 1984-01-24 1984-02-29 Int Computers Ltd Data processing apparatus
US4660155A (en) * 1984-07-23 1987-04-21 Texas Instruments Incorported Single chip video system with separate clocks for memory controller, CRT controller
US4663742A (en) * 1984-10-30 1987-05-05 International Business Machines Corporation Directory memory system having simultaneous write, compare and bypass capabilites
US4623990A (en) * 1984-10-31 1986-11-18 Advanced Micro Devices, Inc. Dual-port read/write RAM with single array
JPH0799515B2 (en) * 1984-11-05 1995-10-25 ヒユ−ズ・エアクラフト・カンパニ− Instruction flow computer
CA1233260A (en) * 1985-03-13 1988-02-23 Chuck H. Ngai High performance parallel vector processor having a modified vector register/element processor configuration
US4739476A (en) * 1985-08-01 1988-04-19 General Electric Company Local interconnection scheme for parallel processing architectures
US4720780A (en) * 1985-09-17 1988-01-19 The Johns Hopkins University Memory-linked wavefront array processor
CN1012297B (en) * 1985-11-13 1991-04-03 奥尔凯托N·V公司 Array recognization with internal cellular control and processing
US4769779A (en) * 1985-12-16 1988-09-06 Texas Instruments Incorporated Systolic complex multiplier
US4773038A (en) * 1986-02-24 1988-09-20 Thinking Machines Corporation Method of simulating additional processors in a SIMD parallel processor array
US4933846A (en) * 1987-04-24 1990-06-12 Network Systems Corporation Network communications adapter with dual interleaved memory banks servicing multiple processors

Also Published As

Publication number Publication date
JPH03501787A (en) 1991-04-18
DE68926783D1 (en) 1996-08-08
DE68926783T2 (en) 1996-11-28
EP0390907A1 (en) 1990-10-10
US5421019A (en) 1995-05-30
EP0390907B1 (en) 1996-07-03
WO1990004235A1 (en) 1990-04-19
CA2000151C (en) 1997-12-09
JP2930341B2 (en) 1999-08-03

Similar Documents

Publication Publication Date Title
CA2000151A1 (en) Parallel Data Processor
CA2022056A1 (en) Distributed memory architecture for a configurable logic array and method for using distributed memory
EP0774758A3 (en) Memory architecture using content addressable memory, and systems and methods using the same
DE3483541D1 (en) DATA PROCESSING CELL AND DATA PROCESSING DEVICES WITH SUCH CELLS.
EP0554901A3 (en) A semiconductor memory device
EP0318952A3 (en) Semiconductor memory device having a function of simultaneously clearing part of memory date
EP1158532A3 (en) Semiconductor memory device
EP0323648A3 (en) Semiconductor memory device
HK1001481A1 (en) Eeprom system with bit error detecting function
EP0165612A3 (en) Memory circuit having a plurality of cell arrays
EP0149049A3 (en) Data memory with simultaneous write and read
EP0375105A3 (en) Memory apparatus for multiple processor systems
EP0961289A3 (en) Flash memory with improved erasability and its circuitry
EP0371243A3 (en) Fail-safe modular memory
CA2018065A1 (en) Data processing system with means to convert burst operations into pipelined operations
EP0194415A3 (en) Bus to bus converter
CA2145106A1 (en) Intelligent Memory-Based Input/Output System
US4884270A (en) Easily cascadable and testable cache memory
EP0341905A3 (en) Computer with intelligent memory system
EP0166309A3 (en) Memory chip for a hierarchical memory system
EP0376245A3 (en) Semiconductors memory device provided with an improved redundant decoder
JPS54139343A (en) Clock-system memory
EP0338757A3 (en) A cell stack for variable digit width serial architecture
CA2195836A1 (en) Semiconductor memory having main word line and subword lines provided correspondingly to the main word line
EP0337457A3 (en) Memory device having a plurality of memory cell arrays with different organization

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed
MKEC Expiry (correction)

Effective date: 20121202