CA2001886A1 - Data processing apparatus - Google Patents

Data processing apparatus

Info

Publication number
CA2001886A1
CA2001886A1 CA2001886A CA2001886A CA2001886A1 CA 2001886 A1 CA2001886 A1 CA 2001886A1 CA 2001886 A CA2001886 A CA 2001886A CA 2001886 A CA2001886 A CA 2001886A CA 2001886 A1 CA2001886 A1 CA 2001886A1
Authority
CA
Canada
Prior art keywords
time counter
access
register
processing apparatus
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2001886A
Other languages
French (fr)
Other versions
CA2001886C (en
Inventor
Kouji Kinoshita
Shigeyuki Ozawa
Shigenori Takekawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CA2001886A1 publication Critical patent/CA2001886A1/en
Application granted granted Critical
Publication of CA2001886C publication Critical patent/CA2001886C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8076—Details on data register access
    • G06F15/8084—Special arrangements thereof, e.g. mask or switch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/88—Monitoring involving counting

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • Complex Calculations (AREA)
  • Memory System (AREA)
  • Debugging And Monitoring (AREA)

Abstract

A data processing apparatus includes a register, an access time counter, a comparator, and a bank waiting time counter. The register calculates a minimum period of time required to access all elements which constitute vector data when the vector data is accessed. The access time counter counts a time lapse after access for the vector data is started. The comparator compares a value calculated by the register with a value obtained by the access time counter. The bank waiting time counter is incremented in accordance with a comparison result obtained by the comparator.
CA002001886A 1988-11-07 1989-10-31 Data processing apparatus Expired - Fee Related CA2001886C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP279410/88 1988-11-07
JP63279410A JP2674809B2 (en) 1988-11-07 1988-11-07 Information processing device

Publications (2)

Publication Number Publication Date
CA2001886A1 true CA2001886A1 (en) 1990-05-07
CA2001886C CA2001886C (en) 1995-12-12

Family

ID=17610708

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002001886A Expired - Fee Related CA2001886C (en) 1988-11-07 1989-10-31 Data processing apparatus

Country Status (5)

Country Link
US (1) US5251309A (en)
EP (1) EP0372231B1 (en)
JP (1) JP2674809B2 (en)
CA (1) CA2001886C (en)
DE (1) DE68925572T2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6324120B2 (en) 1990-04-18 2001-11-27 Rambus Inc. Memory device having a variable data output length
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Integrated circuit i/o using a high performance bus interface
US6539440B1 (en) 1998-11-16 2003-03-25 Infineon Ag Methods and apparatus for prediction of the time between two consecutive memory accesses
US6453370B1 (en) 1998-11-16 2002-09-17 Infineion Technologies Ag Using of bank tag registers to avoid a background operation collision in memory systems
US6216178B1 (en) 1998-11-16 2001-04-10 Infineon Technologies Ag Methods and apparatus for detecting the collision of data on a data bus in case of out-of-order memory accesses of different times of memory access execution

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588837A (en) * 1968-12-30 1971-06-28 Comcet Inc Systems activity monitor
US3577185A (en) * 1969-10-02 1971-05-04 Ibm On-line system for measuring the efficiency of replacement algorithms
US3723975A (en) * 1971-06-28 1973-03-27 Ibm Overdue event detector
US4217636A (en) * 1976-02-27 1980-08-12 Black Bocs, Ltd. Computer performance measurement device and process
KR860001434B1 (en) * 1980-11-21 1986-09-24 후지쑤 가부시끼가이샤 Bank interleaved vector processor having a fixed relationship between start timing signals
JPS6052468B2 (en) * 1982-03-04 1985-11-19 株式会社東芝 DMA bus load variable device
JPS6057447A (en) * 1983-09-09 1985-04-03 Nec Corp Memory access control system
EP0205193B1 (en) * 1985-06-17 1996-10-23 Nec Corporation Information processing system comprising a register renewal waiting control circuit with renewal register number registering means
US4745545A (en) * 1985-06-28 1988-05-17 Cray Research, Inc. Memory reference control in a multiprocessor
JPS62180470A (en) * 1986-02-04 1987-08-07 Hitachi Ltd Vector processor
JP2806524B2 (en) * 1988-03-04 1998-09-30 日本電気株式会社 Vector operation instruction issue control method

Also Published As

Publication number Publication date
EP0372231A3 (en) 1993-01-13
EP0372231A2 (en) 1990-06-13
DE68925572D1 (en) 1996-03-14
CA2001886C (en) 1995-12-12
JP2674809B2 (en) 1997-11-12
DE68925572T2 (en) 1996-06-05
US5251309A (en) 1993-10-05
JPH02126365A (en) 1990-05-15
EP0372231B1 (en) 1996-01-31

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Legal Events

Date Code Title Description
EEER Examination request
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