CA2001886C - Data processing apparatus - Google Patents
Data processing apparatusInfo
- Publication number
- CA2001886C CA2001886C CA002001886A CA2001886A CA2001886C CA 2001886 C CA2001886 C CA 2001886C CA 002001886 A CA002001886 A CA 002001886A CA 2001886 A CA2001886 A CA 2001886A CA 2001886 C CA2001886 C CA 2001886C
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- access
- time
- vector data
- memory
- path
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
- G06F15/8076—Details on data register access
- G06F15/8084—Special arrangements thereof, e.g. mask or switch
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
- G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/88—Monitoring involving counting
Abstract
A data processing apparatus includes a register, an access time counter, a comparator, and a bank waiting time counter. The register calculates a minimum period of time required to access all elements which constitute vector data when the vector data is accessed. The access time counter counts a time lapse after access for the vector data is started. The comparator compares a value calculated by the register with a value obtained by the access time counter. The bank waiting time counter is incremented in accordance with a comparison result obtained by the comparator.
Description
2Ql886 Specification - Title of the Invention Data Processing Apparatus Background of the Invention The present invention relates to a data processing apparatus and, more particularly, to a data processing apparatus which deals with vector data.
In a conventional data processing apparatus which deals with vector data, in order to perform a high-speed arithmetic operation, a large amount of data must be accessed at high speed to supply the accessed data to an arithmetic unit. Therefore, various techniques to realize a high throughput, e.g., a multibank technique have been freely used. However, for example, when elements of a two-dimensional data array are accessed in a column direction, all the elements often access a single bank depending on an array size, and the throughput may often be decreased noticeably.
20In the above-mentioned conventional data processing apparatus, if the throughput of an entire system is decreased because of a throughput of memory access, in order to determine that a loss during the memory access causes performance degradation, a program must be analyzed to seek a location where the cause exists, i.e., whether the cause exists in the memory access, or in other operations. Program analysis must employ different -1- ~
viewpoints depending on the cases wherein causes exist in , the memory access and in other operations. Therefore, if a cause is not apparent, a large number of operation steps must be undesirably required.
Summary of the Invention It is a principal object to provide a data processing apparatus which can count a delay time caused by a bank conflict between elements of vector data when the vector data is accessed.
According to one aspect of the present invention, there is provided a data processing apparatus for accessing vector data from a memory having a plurality of banks to perform a vector arithmetic operation, comprising:
calculating means for calculating a minimum period of time required to access all elements which constitute the vector data when the vector data is accessed;
first counting means for counting a time lapse after access for the vector data is started;
comparing means for comparing a value calculated by the calculating means with a value obtained by the first counting means; and second counting means incremented in accordance with a comparison result obtained by the comparing means.
According to another aspect of the present invention, there is provided a data processing apparatus for accessing vector data from a memory having a plurality of banks to perform a vector arithmetic operation, - comprising:
calculating means for calculating a minimum period of time required to access all elements which constitute the vector data when the vector data is accessed;
counting means for counting a time lapse after access for the vector data is started;
subtracting means for calculating a difference between a value obtained by the counting means and a value calculated by the calculating means; and accumulating means for accumulating the difference obtained by the subtracting means in synchronism with an end of the access for the vector data.
Brief Description of the Drawings Fig. 1 is a block diagram showing an arrangement of a data processing apparatus according to a first embodiment of the present invention;
Fig. 2 is a block diagram showing a detailed arrangement of a memory access control unit shown in Fig. 1;
Figs. 3 and 4 are timing charts for explaining an operation in the first embodiment;
Fig. 5 is a block diagram showing an arrangement of a data processing apparatus according to a second embodiment of the present invention;
Fig. 6 is a block diaqram showing a detailed - arrangement of a memory access control unit shown in Fig. 5; and Figs. 7 and 8 are timing charts for explaining an operation in the second embodiment.
Detailed Description of the Preferred Embodiments The present invention will be described hereinafter in detail with reference to the accompanying drawings.
Fig. 1 shows an arrangement of a data processing apparatus according to a first embodiment of the present invention. The data processing apparatus includes an instruction control unit 1, a memory access control unit 2, a memory 3, an arithmetic unit count register 11, a memory port count register 12, a shift circuit 13, a register 14, an access time counter 15, a comparator 16, and a bank waiting time counter 17.
The instruction control unit 1 controls and executes instructions. This unit includes one or a plurality of sets of arithmetic operation pipelines defined by the arithmetic unit count register 11 (to be described later). In the plurality of arithmetic operation pipelines, the identical arithmetic operations are parallelly performed. When the instruction control unit 1 executes a memory reference instruction, a memory access request is output, and access data such as a request signal, a request address, an interelement distance of 200~886 vector data on the memory, and the number of elements of - the vector data are supplied to the memory access control unit 2 through a path 101.
The memory access control unit 2 controls access of the memory 3 in accordance with the access data supplied from the instruction control unit 1 through the path 101.
The number of elements of the vector data is supplied to the shift circuit 13 through a path 113, an access start signal for the memory 3 is supplied to the register 14 and the access time counter 15 through a path 115, and an in-access signal for the memory 3 is supplied to the comparator 16 through a path 118.
The memory 3 consists of a plurality of banks and is connected to the memory access control unit 2 through a path 102 via a plurality of ports.
The arithmetic unit count register 11 holds the number of sets of the arithmetic operation pipelines in the instruction control unit 1. A value is set in the register 11 upon initialization of the system through a line (not shown). The held value is supplied to the shift circuit 13 through a path 111.
The memory port count register 12 holds the number of memory ports between the memory access control unit 2 and the memory 3. A value is set in the register 12 upon initialization of the system through a line (not shown). The held value is supplied to the shift circuit 13 through the path 112.
The shift circuit 13 receives the number of - elements of the vector data from the memory access control unit 2 through the path 113. The supplied data is shifted to the right as a shift number on the basis of the number of simultaneously accessible elements determined in accordance with the number of sets of the arithmetic operation pipelines supplied through the path 111 and the number of memory ports supplied through the path 112. When the shifted bits include a "1" bit, the shift result is incremented by "1" to obtain a period of time required when there is no bank conflict between access operations of the elements in access for the vector data. The obtained period of time is supplied to the register 14 through a path 114.
The register 14 holds the period of time required when there is no bank conflict among the elements constituting the vector data during the access for the vector data which is supplied through the path 114. The register 14 is set at a timing when an access start signal supplied through a path 115 is set at "1". The contents of the register 14 are supplied to the comparator 16 through a path 116.
The access time counter 15 is reset to be "0" in response to the access start signal supplied through the path 115. Thereafter, the counter 15 is incremented by one for every cycle. The contents of the counter 15 are supplied to the comparator 16 through a path 117.
The comparator 16 compares the period of time - required when there is no bank conflict, which time data is supplied through the path 116, with a period of time elapsed after the access is started, which time data is supplied through the path 117. During a period when the time period elapsed after the access is started is equal to or longer than the time period required when there is no bank conflict, and the in-access signal supplied through a path 118 is set at "1", a path 119 is set at "l", and the comparison result is output to the bank waiting time counter 17.
The bank waiting time counter 17 is incremented by one for every cycle in response to a signal representing that the period of time elapsed after the access is started, which time data is supplied through the path 119, exceeds the period of time required when there is no bank conflict. The band waiting time counter 17 represents a waiting time due to the bank conflict.
Fig. 2 shows a detailed arrangement of the memory access control unit 2 shown in Fig. 1.
A request signal, a request address, an interelement distance of the vector data, and the number of elements of the vector data are supplied from paths 101-1 to 101-4, and are set in registers 51, 53, 54, and 55, respectively. The register 51 holds the request signal during only one cycle, and instructs the start to access the vector data through the path 115. An in-access flag 52 is also set by the register 51. The in-access flag 52 - holds "1" until it is reset in response to an access end signal supplied through a path 205. The contents of the flag 52 are supplied to a decoder 56 through the path 118, and are also supplied to the comparator 16 shown in Fig. 1.
A control operation is performed through a line (not shown) so that a request signal is not supplied through the path 101-1 during a period when the in-access flag 52 is set at "1" .
The request address represents an address of the first element of the vector data, and is supplied from the register 53 to an address adder 59 through a path 201. The address adder 59 adds interelement distances supplied through a path 202 to the request address to calculate an address of each element. The contents of the adder 59 are supplied to the memory 3 through the path 102-2. The address adder 59 is connected to the memory 3 through a plurality of ports. An address is generated in units of ports. The address of the first element accessed at the succeeding timing is generated by adding a value obtained by multiplying the interelement distance with the number of simultaneously accessible elements to the address of the first element at the preceding timing in accordance with the number of simultaneously accessible elements which is supplied through the path 203. Similarly, the addresses of the elements which constitute the vector data are generated until the address of the last element is generated, and the contents are supplied to the memory 3. The number of , simultaneously accessible elements can be obtained by decoding the interelement distance by the decoder 56.
The decoder 56 decodes the interelement distance supplied through the path 202. In each cycle, the same number of elements are accessed in accordance with a relationship between the interelement distance and the number of banks in the memory. In this case, this relationship is derived from whether the interelement distance is relatively prime with the number of banks in the memory. The number of simultaneously accessible elements which do not cause an interelement bank conflict is calculated. At the same time, a time interval that the memory 3 can be accessed is calculated. The number of simultaneously accessible elements is supplied to a remaining element counter 57 and the address adder 59 through the path 203.
The decoder 56 generates a request timing with respect to the memory 3 using a time interval that the memory can be accessed, in the same manner as disclosed in, e.g., Japanese Patent Laid-Open No. 60-57447. The request timing is supplied to the memory 3, a bank busy counter 58, and the remaining element counter 57 through a path 102-1.
The request timing is set at "1" during only a period when the in-access flag 52 is set at "1", and access for the memory 3 in practice can be started only when a value in the bank busy counter 58 is set to be "0".
The remaining element counter 57 monitors the - number of remaining elements to be processed. The counter 57 receives the number of elements through the path 113.
The number of access operations for the memory 3 is obtained in accordance with the number of simultaneously accessible elements supplied through the path 203, and the obtained number is set in the counter 57 as an initial value. The value is decremented by 1 at each request timing supplied to the memory 3 through the path 102-1 every request. When the counter 57 detects that the value is set to be "0", i.e., that the counter is set at "1" and the path 102-1 is set at "1", the access end signal on a path 205 is set at "1", and the in-access flag 52 is reset.
A bank cycle time is set in the bank busy counter 58 as an initial value every request supplied to the memory 3. The value is decremented by one for every cycle. When the value is set to be "0", all the banks are not busy, and a l-bit output from the counter 58 is supplied to the decoder 56.
With the above arrangement, an operation in the first embodiment will be described below with reference to timing charts. In addition, assume that, in this embodiment, the number of memory ports is 2, the number of sets of the arithmetic operation pipelines is 2, the number of banks in the memory is 16 (8 for each port), and a bank cycle time is given as 8 cycles. Assume that each bank has an 8-byte width. In other words, a maximum of two elements can be simultaneously accessed.
Fig. 3 shows an operation when vector data having an 8-byte interelement distance is accessed. The number of 5 elements is 8. When a request signal is supplied from the instruction control unit 1 to the memory access control unit 2 through the path 101-1 during a time interval T
the register 51 is set at "1", and a start address, an interelement distance, and the number of elements are set in the resisters 53, 54, and 55, respectively.
Since the register 51 is set at "1" during a time interval T1, the in-access flag 52 is set by the path 115.
In addition, a period of time required when there is no bank conflict is set in the register 14. Since the maximum 15 number of simultaneously accessible elements is 2, at this time, a value "4" obtained by dividing the number of elements "8" by 2 is set in the register 14. In addition, the access time counter 15 is cleared.
Thereafter, the access time counter 15 is 20 incremented by 1 during time intervals T2, T3, T4, ..., and the value set in the counter 15 is the same as the value "4" held in the register 14 during the time interval T6.
However, since the access for the memory is completed during four cycles, i.e., the time intervals T2, T3, T4, 25 and T5, the in-access flag 52 is reset to be "0" during the time interval T6, and an output from the comparator 16 is invalid. Therefore, when the vector data having the 8-byte 2Q01~386 interelement distance is accessed, the bank waiting time - counter 17 is never incremented.
Fig. 4 shows an operation when vector data having a 32-byte interelement distance and four elements is 5 accessed. In the same manner as in Fig. 3, a request signal is supplied from the instruction control unit 1 through the path 101-1 during a time interval To~ and a start address, an interelement distance, and the number of elements are set in the registers 53, 54, and 55, 10 respectively.
The in-access flag 52 is set during a time interval Tl, and a value "2" obtained by dividing the number of elements "4" by the maximum number of simultaneously accessible elements is set in the register 15 14. In addition, the access time counter 15 is reset to be "0" during the time interval Tl.
The access time counter 15 is incremented by one for every cycle from a time interval T2, and is incremented from "1" to "2" during a time interval T3. Thereafter, a 20 value larger than "2" is set in the counter 15 until access for the next vector data is started. If the interelement distance is given as 32 bytes, only one element can be accessed during two cycles under the given conditions of the number of banks and the bank cycle time. In practice, 25 the access is performed every four banks, so that the access is returned to the first bank after four elements are accessed. Therefore, when each element is accessed every two cycles, any bank conflict does not occur between - the elements because the bank cycle time is given as 8 cycles.
For this reason, the remaining element counter 57 5 is decremented by one in response to the first request on the path 102-1 to the memory during the time interval T2.
Thereafter, the counter 57 is decremented by one every two cycles. When the last request to the memory is supplied during a time interval T8, the counter 57 is set to be "0".
lO Therefore, the in-access flag 52 is set at "l" during a cycle from the time interval T2 to the time interval T8.
In addition, a period in which a value set in the access time counter 17 is equal to or larger than a value "2" held in the register 14 during the cycle from the time interval 15 T2 to the time interval T8, i.e., a 5-cycle period from the time interval T4 to the time interval T8, the bank waiting time counter 17 is incremented. From a time interval Tg, the value at the counter 17 is incremented by "5".
In practice, 7 cycles are required for access due 20 to a bank conflict although only 2 cycles are required if there is no bank conflict. A time period required for, e.g., the banks is given as 5 cycles, and this value is accumulated in the bank waiting time counter 17.
Fig. 5 shows an arrangement of a data processing 25 apparatus according to a second embodiment of the present invention. This apparatus includes an instruction control unit 1, a memory access control unit 2a, a memory 3, an arithmetic unit count register 11, a memory port count - register 12, a shift circuit 13, a register 14, an access time counter 15, a subtracter 16a, and a bank waiting time register 17a. Only differences between the first and second embodiments will be described hereinafter.
The memory access control unit 2a supplies an access end signal for the memory 3 to the bank waiting time register 17a through a path 118a.
The contents of the register 14 are supplied to the subtracter 16a through a path 116. The contents of the access time counter 15 are supplied to the subtracter 16a through a path 117. The subtracter 16a subtracts a time period required when there is no bank conflict, which time data is supplied through the path 116, from a time lapse after access is started, which time data is supplied through the path 117, and this difference is supplied to the bank waiting time register 17a through a path 119. The bank waiting time register 17a adds the difference between the time lapse after the access is started, which time data is supplied through the path 119, and a time period required when there is no bank conflict to a value held by the register 17a. In addition, the register 17a is set at an access end timing supplied through the path 118a to accumulate a time period delayed due to a bank conflict.
Fig. 6 shows a detailed arrangement of the memory access control unit 2a shown in Fig. 5. Only differences in memory access control unit between the first and second embodiments will be described hereinafter.
An in-access flag 52 holds "1" until it is reset in response to an access end signal supplied through a path 205. The contents of the flag 52 are supplied to a decoder 56 through a path 206.
When the remaining element counter 57 detects that its value is set to be "0", an access end flag 60 is set. The access end flag 60 is a flip-flop for holding the access end signal from the path 205 during one cycle. The contents of the flag 60 are supplied to the bank waiting time register 17a through the path 118a.
With the above arrangement, an operation in the second embodiment will be described hereinafter with reference to the timing charts. Assume that, in this embodiment, the number of memory ports is 2, the number of sets of arithmetic operation pipelines is 2, the number of banks in the memory is 16 (8 for each port), and a bank cycle time is given as 8 cycles, as in the first embodiment. In addition, assume that each bank has an 8-byte width. In other words, a maximum of two elements can be simultaneously accessed.
Fig. 7 shows an operation when vector data having an 8-byte interelement distance is accessed. The number of elements is 8. When a request signal is supplied from the instruction control unit 1 to the memory access control unit 2a through a path 101-1 during a time interval To~ a register 51 is set at "1", and a start address, an - interelement distance, and the number of elements are set in the registers 53, 54, and 55, respectively.
Since the register 51 is set at "1" during a time interval T1, the in-access flag 52 is set by a path 115.
In addition, a time period required when there is no bank conflict is set in the register 14. Since the maximum number of simultaneously accessible elements is 2, at this time, a value "4" obtained by dividing the number of elements "8" by 2 is set in the register 14. In addition, the access time counter 15 is cleared.
When the interelement distance is given as 8 bytes, a request signal is supplied to the memory 3 through a path 102-1 every cycle. Therefore, the last request is supplied during a time interval T5. Since the remaining element counter 57 is set to be "1" at this timing, the access end signal on the path 205 is set at "1", and the access end flag 60 is set at "1". Therefore, a difference between the value set in the access time counter 15 and that in the register 14 during a time interval T6 which is the succeeding cycle is supplied to the bank waiting time register 17a. The value set in the access time counter 15 is only "4" although it is incremented by "1" for every cycle from a time interval T2.
A difference in value between the counter 15 and the register 14 is "0", and the value set in the bank waiting time register 17a is not changed.
~001886 Fig. 8 shows an operation when vector data having - a 32-byte interelement distance and four elements is accessed. In the same manner as in Fig. 7, a request signal is supplied from the instruction control unit 1 through the path 101-1 during a time interval To~ and a start address, an interelement distance, and the number of elements are set in the registers 53, 54, and 55, respectively.
The in-access flag 52 is set during a time interval Tl, and a value "2" obtained by dividing the number of elements "4" by the maximum number of simultaneously accessible elements, i.e., "2", is set in the register 14. In addition, the access time counter 15 is reset to be "0" during the time interval Tl.
If the interelement distance is given as 32 bytes, only one element can be accessed during two cycles under the given conditions of the number of banks and the bank cycle time. In practice, the access is performed every four banks, so that the access is returned to the first bank after four elements are accessed.
Therefore, when each element is accessed every two cycles, any bank conflict does not occur between the elements because the bank cycle time is given as 8 cycles.
For this reason, after a value "4" which is the number of elements is set in the remaining element counter 57 during the time interval T1, the counter 57 is decremented by one for every output of a request signal Z0~1886 supplied to the memory 3 through the path 102-1. The value in the counter 57 is set to be "1" during a time interval T8. The last request signal is supplied to the memory 3, and the access end flag 60 is set. On the other hand, the access time counter 15 is incremented by one for every cycle from time T2, and the value in the counter lS is set to be "7" during a time interval Tg. Therefore, a difference "5" between a value "7" in the access time counter 15 and a value "2" held by the register 14 is supplied to the bank waiting time register 17a during the time interval Tg.
In practice, 7 cycles are required for access due to a bank conflict although only 2 cycles are required if there is no bank conflict, and a time period required to wait for the bank access, i.e., 5 cycles, is accumulated in the bank waiting time register 17a.
As has been described above, according to the present invention, when vector data is accessed, the time period required when there is no bank conflict between the elements is compared with a time lapse after the access is started in practice. When the time lapse is equal to the time period, or a counter incremented by a difference between the two periods is arranged, or a means is arranged for subtracting the time period required when there is no bank conflict between the elements in the vector data from the time lapse required from the access start to the access end in practice, a time delay due to the bank conflict between elements in the vector data upon access for the vector data can be counted.
In a conventional data processing apparatus which deals with vector data, in order to perform a high-speed arithmetic operation, a large amount of data must be accessed at high speed to supply the accessed data to an arithmetic unit. Therefore, various techniques to realize a high throughput, e.g., a multibank technique have been freely used. However, for example, when elements of a two-dimensional data array are accessed in a column direction, all the elements often access a single bank depending on an array size, and the throughput may often be decreased noticeably.
20In the above-mentioned conventional data processing apparatus, if the throughput of an entire system is decreased because of a throughput of memory access, in order to determine that a loss during the memory access causes performance degradation, a program must be analyzed to seek a location where the cause exists, i.e., whether the cause exists in the memory access, or in other operations. Program analysis must employ different -1- ~
viewpoints depending on the cases wherein causes exist in , the memory access and in other operations. Therefore, if a cause is not apparent, a large number of operation steps must be undesirably required.
Summary of the Invention It is a principal object to provide a data processing apparatus which can count a delay time caused by a bank conflict between elements of vector data when the vector data is accessed.
According to one aspect of the present invention, there is provided a data processing apparatus for accessing vector data from a memory having a plurality of banks to perform a vector arithmetic operation, comprising:
calculating means for calculating a minimum period of time required to access all elements which constitute the vector data when the vector data is accessed;
first counting means for counting a time lapse after access for the vector data is started;
comparing means for comparing a value calculated by the calculating means with a value obtained by the first counting means; and second counting means incremented in accordance with a comparison result obtained by the comparing means.
According to another aspect of the present invention, there is provided a data processing apparatus for accessing vector data from a memory having a plurality of banks to perform a vector arithmetic operation, - comprising:
calculating means for calculating a minimum period of time required to access all elements which constitute the vector data when the vector data is accessed;
counting means for counting a time lapse after access for the vector data is started;
subtracting means for calculating a difference between a value obtained by the counting means and a value calculated by the calculating means; and accumulating means for accumulating the difference obtained by the subtracting means in synchronism with an end of the access for the vector data.
Brief Description of the Drawings Fig. 1 is a block diagram showing an arrangement of a data processing apparatus according to a first embodiment of the present invention;
Fig. 2 is a block diagram showing a detailed arrangement of a memory access control unit shown in Fig. 1;
Figs. 3 and 4 are timing charts for explaining an operation in the first embodiment;
Fig. 5 is a block diagram showing an arrangement of a data processing apparatus according to a second embodiment of the present invention;
Fig. 6 is a block diaqram showing a detailed - arrangement of a memory access control unit shown in Fig. 5; and Figs. 7 and 8 are timing charts for explaining an operation in the second embodiment.
Detailed Description of the Preferred Embodiments The present invention will be described hereinafter in detail with reference to the accompanying drawings.
Fig. 1 shows an arrangement of a data processing apparatus according to a first embodiment of the present invention. The data processing apparatus includes an instruction control unit 1, a memory access control unit 2, a memory 3, an arithmetic unit count register 11, a memory port count register 12, a shift circuit 13, a register 14, an access time counter 15, a comparator 16, and a bank waiting time counter 17.
The instruction control unit 1 controls and executes instructions. This unit includes one or a plurality of sets of arithmetic operation pipelines defined by the arithmetic unit count register 11 (to be described later). In the plurality of arithmetic operation pipelines, the identical arithmetic operations are parallelly performed. When the instruction control unit 1 executes a memory reference instruction, a memory access request is output, and access data such as a request signal, a request address, an interelement distance of 200~886 vector data on the memory, and the number of elements of - the vector data are supplied to the memory access control unit 2 through a path 101.
The memory access control unit 2 controls access of the memory 3 in accordance with the access data supplied from the instruction control unit 1 through the path 101.
The number of elements of the vector data is supplied to the shift circuit 13 through a path 113, an access start signal for the memory 3 is supplied to the register 14 and the access time counter 15 through a path 115, and an in-access signal for the memory 3 is supplied to the comparator 16 through a path 118.
The memory 3 consists of a plurality of banks and is connected to the memory access control unit 2 through a path 102 via a plurality of ports.
The arithmetic unit count register 11 holds the number of sets of the arithmetic operation pipelines in the instruction control unit 1. A value is set in the register 11 upon initialization of the system through a line (not shown). The held value is supplied to the shift circuit 13 through a path 111.
The memory port count register 12 holds the number of memory ports between the memory access control unit 2 and the memory 3. A value is set in the register 12 upon initialization of the system through a line (not shown). The held value is supplied to the shift circuit 13 through the path 112.
The shift circuit 13 receives the number of - elements of the vector data from the memory access control unit 2 through the path 113. The supplied data is shifted to the right as a shift number on the basis of the number of simultaneously accessible elements determined in accordance with the number of sets of the arithmetic operation pipelines supplied through the path 111 and the number of memory ports supplied through the path 112. When the shifted bits include a "1" bit, the shift result is incremented by "1" to obtain a period of time required when there is no bank conflict between access operations of the elements in access for the vector data. The obtained period of time is supplied to the register 14 through a path 114.
The register 14 holds the period of time required when there is no bank conflict among the elements constituting the vector data during the access for the vector data which is supplied through the path 114. The register 14 is set at a timing when an access start signal supplied through a path 115 is set at "1". The contents of the register 14 are supplied to the comparator 16 through a path 116.
The access time counter 15 is reset to be "0" in response to the access start signal supplied through the path 115. Thereafter, the counter 15 is incremented by one for every cycle. The contents of the counter 15 are supplied to the comparator 16 through a path 117.
The comparator 16 compares the period of time - required when there is no bank conflict, which time data is supplied through the path 116, with a period of time elapsed after the access is started, which time data is supplied through the path 117. During a period when the time period elapsed after the access is started is equal to or longer than the time period required when there is no bank conflict, and the in-access signal supplied through a path 118 is set at "1", a path 119 is set at "l", and the comparison result is output to the bank waiting time counter 17.
The bank waiting time counter 17 is incremented by one for every cycle in response to a signal representing that the period of time elapsed after the access is started, which time data is supplied through the path 119, exceeds the period of time required when there is no bank conflict. The band waiting time counter 17 represents a waiting time due to the bank conflict.
Fig. 2 shows a detailed arrangement of the memory access control unit 2 shown in Fig. 1.
A request signal, a request address, an interelement distance of the vector data, and the number of elements of the vector data are supplied from paths 101-1 to 101-4, and are set in registers 51, 53, 54, and 55, respectively. The register 51 holds the request signal during only one cycle, and instructs the start to access the vector data through the path 115. An in-access flag 52 is also set by the register 51. The in-access flag 52 - holds "1" until it is reset in response to an access end signal supplied through a path 205. The contents of the flag 52 are supplied to a decoder 56 through the path 118, and are also supplied to the comparator 16 shown in Fig. 1.
A control operation is performed through a line (not shown) so that a request signal is not supplied through the path 101-1 during a period when the in-access flag 52 is set at "1" .
The request address represents an address of the first element of the vector data, and is supplied from the register 53 to an address adder 59 through a path 201. The address adder 59 adds interelement distances supplied through a path 202 to the request address to calculate an address of each element. The contents of the adder 59 are supplied to the memory 3 through the path 102-2. The address adder 59 is connected to the memory 3 through a plurality of ports. An address is generated in units of ports. The address of the first element accessed at the succeeding timing is generated by adding a value obtained by multiplying the interelement distance with the number of simultaneously accessible elements to the address of the first element at the preceding timing in accordance with the number of simultaneously accessible elements which is supplied through the path 203. Similarly, the addresses of the elements which constitute the vector data are generated until the address of the last element is generated, and the contents are supplied to the memory 3. The number of , simultaneously accessible elements can be obtained by decoding the interelement distance by the decoder 56.
The decoder 56 decodes the interelement distance supplied through the path 202. In each cycle, the same number of elements are accessed in accordance with a relationship between the interelement distance and the number of banks in the memory. In this case, this relationship is derived from whether the interelement distance is relatively prime with the number of banks in the memory. The number of simultaneously accessible elements which do not cause an interelement bank conflict is calculated. At the same time, a time interval that the memory 3 can be accessed is calculated. The number of simultaneously accessible elements is supplied to a remaining element counter 57 and the address adder 59 through the path 203.
The decoder 56 generates a request timing with respect to the memory 3 using a time interval that the memory can be accessed, in the same manner as disclosed in, e.g., Japanese Patent Laid-Open No. 60-57447. The request timing is supplied to the memory 3, a bank busy counter 58, and the remaining element counter 57 through a path 102-1.
The request timing is set at "1" during only a period when the in-access flag 52 is set at "1", and access for the memory 3 in practice can be started only when a value in the bank busy counter 58 is set to be "0".
The remaining element counter 57 monitors the - number of remaining elements to be processed. The counter 57 receives the number of elements through the path 113.
The number of access operations for the memory 3 is obtained in accordance with the number of simultaneously accessible elements supplied through the path 203, and the obtained number is set in the counter 57 as an initial value. The value is decremented by 1 at each request timing supplied to the memory 3 through the path 102-1 every request. When the counter 57 detects that the value is set to be "0", i.e., that the counter is set at "1" and the path 102-1 is set at "1", the access end signal on a path 205 is set at "1", and the in-access flag 52 is reset.
A bank cycle time is set in the bank busy counter 58 as an initial value every request supplied to the memory 3. The value is decremented by one for every cycle. When the value is set to be "0", all the banks are not busy, and a l-bit output from the counter 58 is supplied to the decoder 56.
With the above arrangement, an operation in the first embodiment will be described below with reference to timing charts. In addition, assume that, in this embodiment, the number of memory ports is 2, the number of sets of the arithmetic operation pipelines is 2, the number of banks in the memory is 16 (8 for each port), and a bank cycle time is given as 8 cycles. Assume that each bank has an 8-byte width. In other words, a maximum of two elements can be simultaneously accessed.
Fig. 3 shows an operation when vector data having an 8-byte interelement distance is accessed. The number of 5 elements is 8. When a request signal is supplied from the instruction control unit 1 to the memory access control unit 2 through the path 101-1 during a time interval T
the register 51 is set at "1", and a start address, an interelement distance, and the number of elements are set in the resisters 53, 54, and 55, respectively.
Since the register 51 is set at "1" during a time interval T1, the in-access flag 52 is set by the path 115.
In addition, a period of time required when there is no bank conflict is set in the register 14. Since the maximum 15 number of simultaneously accessible elements is 2, at this time, a value "4" obtained by dividing the number of elements "8" by 2 is set in the register 14. In addition, the access time counter 15 is cleared.
Thereafter, the access time counter 15 is 20 incremented by 1 during time intervals T2, T3, T4, ..., and the value set in the counter 15 is the same as the value "4" held in the register 14 during the time interval T6.
However, since the access for the memory is completed during four cycles, i.e., the time intervals T2, T3, T4, 25 and T5, the in-access flag 52 is reset to be "0" during the time interval T6, and an output from the comparator 16 is invalid. Therefore, when the vector data having the 8-byte 2Q01~386 interelement distance is accessed, the bank waiting time - counter 17 is never incremented.
Fig. 4 shows an operation when vector data having a 32-byte interelement distance and four elements is 5 accessed. In the same manner as in Fig. 3, a request signal is supplied from the instruction control unit 1 through the path 101-1 during a time interval To~ and a start address, an interelement distance, and the number of elements are set in the registers 53, 54, and 55, 10 respectively.
The in-access flag 52 is set during a time interval Tl, and a value "2" obtained by dividing the number of elements "4" by the maximum number of simultaneously accessible elements is set in the register 15 14. In addition, the access time counter 15 is reset to be "0" during the time interval Tl.
The access time counter 15 is incremented by one for every cycle from a time interval T2, and is incremented from "1" to "2" during a time interval T3. Thereafter, a 20 value larger than "2" is set in the counter 15 until access for the next vector data is started. If the interelement distance is given as 32 bytes, only one element can be accessed during two cycles under the given conditions of the number of banks and the bank cycle time. In practice, 25 the access is performed every four banks, so that the access is returned to the first bank after four elements are accessed. Therefore, when each element is accessed every two cycles, any bank conflict does not occur between - the elements because the bank cycle time is given as 8 cycles.
For this reason, the remaining element counter 57 5 is decremented by one in response to the first request on the path 102-1 to the memory during the time interval T2.
Thereafter, the counter 57 is decremented by one every two cycles. When the last request to the memory is supplied during a time interval T8, the counter 57 is set to be "0".
lO Therefore, the in-access flag 52 is set at "l" during a cycle from the time interval T2 to the time interval T8.
In addition, a period in which a value set in the access time counter 17 is equal to or larger than a value "2" held in the register 14 during the cycle from the time interval 15 T2 to the time interval T8, i.e., a 5-cycle period from the time interval T4 to the time interval T8, the bank waiting time counter 17 is incremented. From a time interval Tg, the value at the counter 17 is incremented by "5".
In practice, 7 cycles are required for access due 20 to a bank conflict although only 2 cycles are required if there is no bank conflict. A time period required for, e.g., the banks is given as 5 cycles, and this value is accumulated in the bank waiting time counter 17.
Fig. 5 shows an arrangement of a data processing 25 apparatus according to a second embodiment of the present invention. This apparatus includes an instruction control unit 1, a memory access control unit 2a, a memory 3, an arithmetic unit count register 11, a memory port count - register 12, a shift circuit 13, a register 14, an access time counter 15, a subtracter 16a, and a bank waiting time register 17a. Only differences between the first and second embodiments will be described hereinafter.
The memory access control unit 2a supplies an access end signal for the memory 3 to the bank waiting time register 17a through a path 118a.
The contents of the register 14 are supplied to the subtracter 16a through a path 116. The contents of the access time counter 15 are supplied to the subtracter 16a through a path 117. The subtracter 16a subtracts a time period required when there is no bank conflict, which time data is supplied through the path 116, from a time lapse after access is started, which time data is supplied through the path 117, and this difference is supplied to the bank waiting time register 17a through a path 119. The bank waiting time register 17a adds the difference between the time lapse after the access is started, which time data is supplied through the path 119, and a time period required when there is no bank conflict to a value held by the register 17a. In addition, the register 17a is set at an access end timing supplied through the path 118a to accumulate a time period delayed due to a bank conflict.
Fig. 6 shows a detailed arrangement of the memory access control unit 2a shown in Fig. 5. Only differences in memory access control unit between the first and second embodiments will be described hereinafter.
An in-access flag 52 holds "1" until it is reset in response to an access end signal supplied through a path 205. The contents of the flag 52 are supplied to a decoder 56 through a path 206.
When the remaining element counter 57 detects that its value is set to be "0", an access end flag 60 is set. The access end flag 60 is a flip-flop for holding the access end signal from the path 205 during one cycle. The contents of the flag 60 are supplied to the bank waiting time register 17a through the path 118a.
With the above arrangement, an operation in the second embodiment will be described hereinafter with reference to the timing charts. Assume that, in this embodiment, the number of memory ports is 2, the number of sets of arithmetic operation pipelines is 2, the number of banks in the memory is 16 (8 for each port), and a bank cycle time is given as 8 cycles, as in the first embodiment. In addition, assume that each bank has an 8-byte width. In other words, a maximum of two elements can be simultaneously accessed.
Fig. 7 shows an operation when vector data having an 8-byte interelement distance is accessed. The number of elements is 8. When a request signal is supplied from the instruction control unit 1 to the memory access control unit 2a through a path 101-1 during a time interval To~ a register 51 is set at "1", and a start address, an - interelement distance, and the number of elements are set in the registers 53, 54, and 55, respectively.
Since the register 51 is set at "1" during a time interval T1, the in-access flag 52 is set by a path 115.
In addition, a time period required when there is no bank conflict is set in the register 14. Since the maximum number of simultaneously accessible elements is 2, at this time, a value "4" obtained by dividing the number of elements "8" by 2 is set in the register 14. In addition, the access time counter 15 is cleared.
When the interelement distance is given as 8 bytes, a request signal is supplied to the memory 3 through a path 102-1 every cycle. Therefore, the last request is supplied during a time interval T5. Since the remaining element counter 57 is set to be "1" at this timing, the access end signal on the path 205 is set at "1", and the access end flag 60 is set at "1". Therefore, a difference between the value set in the access time counter 15 and that in the register 14 during a time interval T6 which is the succeeding cycle is supplied to the bank waiting time register 17a. The value set in the access time counter 15 is only "4" although it is incremented by "1" for every cycle from a time interval T2.
A difference in value between the counter 15 and the register 14 is "0", and the value set in the bank waiting time register 17a is not changed.
~001886 Fig. 8 shows an operation when vector data having - a 32-byte interelement distance and four elements is accessed. In the same manner as in Fig. 7, a request signal is supplied from the instruction control unit 1 through the path 101-1 during a time interval To~ and a start address, an interelement distance, and the number of elements are set in the registers 53, 54, and 55, respectively.
The in-access flag 52 is set during a time interval Tl, and a value "2" obtained by dividing the number of elements "4" by the maximum number of simultaneously accessible elements, i.e., "2", is set in the register 14. In addition, the access time counter 15 is reset to be "0" during the time interval Tl.
If the interelement distance is given as 32 bytes, only one element can be accessed during two cycles under the given conditions of the number of banks and the bank cycle time. In practice, the access is performed every four banks, so that the access is returned to the first bank after four elements are accessed.
Therefore, when each element is accessed every two cycles, any bank conflict does not occur between the elements because the bank cycle time is given as 8 cycles.
For this reason, after a value "4" which is the number of elements is set in the remaining element counter 57 during the time interval T1, the counter 57 is decremented by one for every output of a request signal Z0~1886 supplied to the memory 3 through the path 102-1. The value in the counter 57 is set to be "1" during a time interval T8. The last request signal is supplied to the memory 3, and the access end flag 60 is set. On the other hand, the access time counter 15 is incremented by one for every cycle from time T2, and the value in the counter lS is set to be "7" during a time interval Tg. Therefore, a difference "5" between a value "7" in the access time counter 15 and a value "2" held by the register 14 is supplied to the bank waiting time register 17a during the time interval Tg.
In practice, 7 cycles are required for access due to a bank conflict although only 2 cycles are required if there is no bank conflict, and a time period required to wait for the bank access, i.e., 5 cycles, is accumulated in the bank waiting time register 17a.
As has been described above, according to the present invention, when vector data is accessed, the time period required when there is no bank conflict between the elements is compared with a time lapse after the access is started in practice. When the time lapse is equal to the time period, or a counter incremented by a difference between the two periods is arranged, or a means is arranged for subtracting the time period required when there is no bank conflict between the elements in the vector data from the time lapse required from the access start to the access end in practice, a time delay due to the bank conflict between elements in the vector data upon access for the vector data can be counted.
Claims (2)
1. A data processing apparatus for accessing vector data from a memory having a plurality of banks to perform a vector arithmetic operation, comprising:
calculating means for calculating a minimum period of time required to access all elements which constitute the vector data when the vector data is accessed;
first counting means for counting a time elapse after access for the vector data is started;
comparing means for comparing a value calculated by said calculating means with a value obtained by said first counting means; and second counting means incremented in accordance with a comparison result obtained by said comparing means.
calculating means for calculating a minimum period of time required to access all elements which constitute the vector data when the vector data is accessed;
first counting means for counting a time elapse after access for the vector data is started;
comparing means for comparing a value calculated by said calculating means with a value obtained by said first counting means; and second counting means incremented in accordance with a comparison result obtained by said comparing means.
2. A data processing apparatus for accessing vector data from a memory having a plurality of banks to perform a vector arithmetic operation, comprising:
calculating means for calculating a minimum period of time required to access all elements which constitute the vector data when the vector data is accessed;
counting means for counting a time lapse after access for the vector data is started;
subtracting means for calculating a difference between a value obtained by said counting means and a value calculated by said calculating means; and accumulating means for accumulating the difference obtained by said subtracting means in synchronism with an end of the access for the vector data.
calculating means for calculating a minimum period of time required to access all elements which constitute the vector data when the vector data is accessed;
counting means for counting a time lapse after access for the vector data is started;
subtracting means for calculating a difference between a value obtained by said counting means and a value calculated by said calculating means; and accumulating means for accumulating the difference obtained by said subtracting means in synchronism with an end of the access for the vector data.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP279410/88 | 1988-11-07 | ||
| JP63279410A JP2674809B2 (en) | 1988-11-07 | 1988-11-07 | Information processing device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2001886A1 CA2001886A1 (en) | 1990-05-07 |
| CA2001886C true CA2001886C (en) | 1995-12-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002001886A Expired - Fee Related CA2001886C (en) | 1988-11-07 | 1989-10-31 | Data processing apparatus |
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| US (1) | US5251309A (en) |
| EP (1) | EP0372231B1 (en) |
| JP (1) | JP2674809B2 (en) |
| CA (1) | CA2001886C (en) |
| DE (1) | DE68925572T2 (en) |
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|---|---|---|---|---|
| US6324120B2 (en) | 1990-04-18 | 2001-11-27 | Rambus Inc. | Memory device having a variable data output length |
| US6751696B2 (en) | 1990-04-18 | 2004-06-15 | Rambus Inc. | Memory device having a programmable register |
| IL96808A (en) * | 1990-04-18 | 1996-03-31 | Rambus Inc | Integrated circuit i/o using a high performance bus interface |
| US6216178B1 (en) | 1998-11-16 | 2001-04-10 | Infineon Technologies Ag | Methods and apparatus for detecting the collision of data on a data bus in case of out-of-order memory accesses of different times of memory access execution |
| US6453370B1 (en) | 1998-11-16 | 2002-09-17 | Infineion Technologies Ag | Using of bank tag registers to avoid a background operation collision in memory systems |
| US6539440B1 (en) | 1998-11-16 | 2003-03-25 | Infineon Ag | Methods and apparatus for prediction of the time between two consecutive memory accesses |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3588837A (en) * | 1968-12-30 | 1971-06-28 | Comcet Inc | Systems activity monitor |
| US3577185A (en) * | 1969-10-02 | 1971-05-04 | Ibm | On-line system for measuring the efficiency of replacement algorithms |
| US3723975A (en) * | 1971-06-28 | 1973-03-27 | Ibm | Overdue event detector |
| US4217636A (en) * | 1976-02-27 | 1980-08-12 | Black Bocs, Ltd. | Computer performance measurement device and process |
| KR860001434B1 (en) * | 1980-11-21 | 1986-09-24 | 후지쑤 가부시끼가이샤 | Bank interleaved vector processor having a fixed relationship between start timing signals |
| JPS6052468B2 (en) * | 1982-03-04 | 1985-11-19 | 株式会社東芝 | DMA bus load variable device |
| JPS6057447A (en) * | 1983-09-09 | 1985-04-03 | Nec Corp | Memory access control system |
| DE3650578T2 (en) * | 1985-06-17 | 1997-03-06 | Nec Corp | Information processing system with a control circuit for waiting for a register renewal and a receiving means of the register to be renewed |
| US4745545A (en) * | 1985-06-28 | 1988-05-17 | Cray Research, Inc. | Memory reference control in a multiprocessor |
| JPS62180470A (en) * | 1986-02-04 | 1987-08-07 | Hitachi Ltd | Vector processor |
| JP2806524B2 (en) * | 1988-03-04 | 1998-09-30 | 日本電気株式会社 | Vector operation instruction issue control method |
-
1988
- 1988-11-07 JP JP63279410A patent/JP2674809B2/en not_active Expired - Lifetime
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1989
- 1989-10-31 CA CA002001886A patent/CA2001886C/en not_active Expired - Fee Related
- 1989-11-03 US US07/431,188 patent/US5251309A/en not_active Expired - Fee Related
- 1989-11-06 DE DE68925572T patent/DE68925572T2/en not_active Expired - Fee Related
- 1989-11-06 EP EP89120475A patent/EP0372231B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02126365A (en) | 1990-05-15 |
| DE68925572D1 (en) | 1996-03-14 |
| EP0372231A3 (en) | 1993-01-13 |
| DE68925572T2 (en) | 1996-06-05 |
| US5251309A (en) | 1993-10-05 |
| EP0372231B1 (en) | 1996-01-31 |
| EP0372231A2 (en) | 1990-06-13 |
| CA2001886A1 (en) | 1990-05-07 |
| JP2674809B2 (en) | 1997-11-12 |
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