CA2003821C - Process controller single memory chip shadowing technique - Google Patents

Process controller single memory chip shadowing technique

Info

Publication number
CA2003821C
CA2003821C CA002003821A CA2003821A CA2003821C CA 2003821 C CA2003821 C CA 2003821C CA 002003821 A CA002003821 A CA 002003821A CA 2003821 A CA2003821 A CA 2003821A CA 2003821 C CA2003821 C CA 2003821C
Authority
CA
Canada
Prior art keywords
memory
address
program
main
memory chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002003821A
Other languages
French (fr)
Other versions
CA2003821A1 (en
Inventor
Richard J. Molnar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elsag International BV
Original Assignee
Elsag International BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elsag International BV filed Critical Elsag International BV
Publication of CA2003821A1 publication Critical patent/CA2003821A1/en
Application granted granted Critical
Publication of CA2003821C publication Critical patent/CA2003821C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615Address space extension
    • G06F12/0623Address space extension for memory modules

Abstract

A process and apparatus for shadowing memory uses a single memory chip which is addressable into an address field which is smaller than the memory chip. A program having a main control portion is programmed into a main memory area of the memory chip and is directly connected to a main address space of the address field. The program also includes a plurality of secondary program portions which can be used one at a time with the main control portion of the program. Each of the secondary program portions is stored in a separate secondary and shadowed memory area of the memory chip. A secondary address space of the address field which is large enough to accommodate only one secondary memory area at a time, is controlled so as to be latched to only one secondary memory area at a time. Latching is achieved through higher bits of address locations in a selected portion of the address field. Interrupt and power-up routines are provided in the main portion of the program to avoid entering and leaving the program through different secondary program portions.

Description

,SE 4978 ~ 2003~Z~

PROCESS CONTROLLER SINGLE MEMORY CHIP S~IADOWING TEC~INIQUE
FIELD AND BACKGROUND O~ THE INVENTION
The present invention relates in general to computer technology, and in particular to a new and useful method and apparatus for utilizing a slngle memory chip with shadowed memory portions.
Shadowing is a method by which memory expansion can be accomplished without extending the address field.
Often, the directly addressable memory in a memory chip is sufficient to store the controller code for a program that is used to achieve a selected result. An example is the control program for PID control of steam temperature for a boiler. Sometimes, however, the controller requires extra memory for grappics, large look-up tables, additional functionality, or the like. If no more memory is directly addressable, then the rest must be shadowed.
Shadowing is typically done by setting some bits on a port or latch to control the upper address lines of a memory chip. The lower set of address lines remain tied to the *

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address bus. The memory enable is designed to be selected only when the micro-processor address falls within a certain field.
This field may be located any where in the available memory address map; however, break points using higher bit states typically dictate the field location in the map. The field width is defined by the number of actual lower memory chip address lines tied directly to the micro-processor address bus. The number of shadowed 1evels is determined by the number of high address bits that are set by a latch or port. To access different areas of the memory chip, the latched bits must be set to indicate which area is to be accessed.
If all of the memory is shadowed, then special software routines must be written to keep track of which shadow level the program is in and where to go next.
Another way to keep track is to use two or more separate memory chips and sort them into control memory chips and shadowed memory chips. In this way, basic shadowing methods can easily be applied.
The use of one chip, however, does not lend itself well to basic shadowing techniques. The reason for this is that upon power-up or during an interrupt in an industrial process controller, the program can go off track unless special care is taken to keep track of w~lich level it is operating out of when all of the memory is shadowed.
S~MMARY OF THE INVENTION
The present invention is based on the concept that it is better to have a control memory that is not shadowed, in order to control the parts of the memory that are shadowed.
The invention allows this even when both memorles are on the same chip. The control memory includes all of the ~ zoo~
.

interrupt vectors, interrupt routines, and power-up algorithms that always dominate and manipulate the shadowed memory .
Accordingly, an object of one aspect of the present invention is to provide a process for shadowing memory using a single memory chip which is addressable into an address field which is smaller than the memory chip, with a program having a main program portion and a plurality of secondary program portions usable with the main program portion, the process comprising: storing the main program portion in a main memory area of the memory chip; storing each of the secondary program portions in a separate shadowed memory area of the memory chip; assigning a main address space of the address field, which is large enough to receive the main memory area, to the main memory area; assigning a single secondary space of the address f ield which is large enough to receive only one of the shadowed memory areas at a time, to each of the shadowed memory areas; latching one of the secondary memory areas at a time to the secondary address space; and providing interrupt means for interrupting the program in the main program portion so that, regardless of the point in the program which is active during an interruption, interruption will always return to the program from the main memory interrupt portion.
Another object of the present invention is to provide a process and apparatus for establishing and using shadowed memory, which is simple in design and economical to manufacture.
~ hus, according to a further aspect of the present invention there is provided an apparatus for shadowing memory containing a program having a main program portion and plurality of secondary program portions each usable one at a time with the main program, the apparatus comprising a single memory chip having a main memory area for containing the main program portion, and a plurality of secondary memory areas each for containing one of the Z~)~38Z~
secondary program portions; interrupt means in the program stored in the main memory area for permitting power-up and interrupt only through the main program portion; address means providing an address field having a main address space which is large enough to receive the main memory area, and a secondary address spaces large enough for receiving only one secondary memory area at a time; and latching means operatively connected between said address means and said memory chip for latching one secondary memory area at a time to said secondary address space.
The various features of novelty which characterize the invention are pointed out with particularity in the claims annexed to and forming a part of this disclosure. For a better understanding of the invention, its operating advantages and specific o~jects attained by its uses, reference is made to the accompanying drawings and descriptive matter in which a preferred embodiment of the invention is illustrated.

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BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings:
FIG. 1 is a block diagram showing the single memory chip and its address map, used in accordance with the present invention; and FIG. 2 is a block diag~am showing a micro-processor apparatus using the present invention.
DESCRIPTIO~ OF TI~E PREFERRED EMsODIMENT
Fig. 2 illustrates a micro-processor apparatus which can be used, for example, for a stand alone PID controller for controlling steam temperature from a boiler. Th~ apparatus uses a main program control stored in main memory area A' of a memory chip 10 and a plurality of secondary program portions each stored in a separate secondary shadowed memory area B and B'', of the memory chip 10. The secondary program portions may for example be thermo-couple look-up tables or subprograms that are needed for the controller.
Micro-processor 20, is connected to memory chip 10 through lower address lines 12 and higher address lilles 14, 15 with an intermediate logic means or element 16. Each address location may, for example, be a 16 bit word with 14 low address lines and two higher address lines. As an exalllple, memory chip 10 may be an EPROM (erasable programmable read only memory).
Even if the single memory chip 10 is substantially larger than the available address field 22 provided by the micro-processor 20, in accordance with the present invention, a shadowing technique can be utilized to access each of the secondary program parts in either memory B or memory B , as long as these memory areas are accessed one at a time.

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Latching means, in the form of a latch 18, is provide~
in the present invention to operate logic means 16 for operating the high address lines.
The program stored in the memory chip 10 yields instructions that are carried over the data bus 32 back to the micro-processor 20.
Fig. 1 illu6trates the situation where the available address space 22 is not large enough to cover the memory size.
From Fig. 1, it can be seen that the memory in A can fit into address space A; however, only one (either B or B ) memory can use the address space B at any one time. Therefore, B' and B memory must be shadowed into address space B. A with A' is control memory, and B with B, and B is shadowed memory.
When the controller is powered up or gets an interrupt, the code will be executed from A' memory. Since the interrupt is serviced out of A', it does not matter if the current program was running in A', B, or B . For instance, if the program were running in A' memory and one wants to call a subroutine from B memory, one would first write the bit code corresponding to setting up B memory to latch 18 (see Fig.
2 ) . This will set up the logic to channel the latched bit code to the memory chip address lines, when the micro-processor address lines to the logic reflect a shadow memory access address .
Now, one can immediately jump to the subroutine in B' .
If while running in this subroutine, one gets an interrupt, the interrupt vector will point to somewhere in A and is serviced.
Recall that A memory is not shadowed. It can return immediately to where it had left off in the B subroutine without any shadowing concerns to worry about. When the subroutine in B finishes, it will return to the A memory where it was initiated from.

Fig. 2 shows that the logic has inputs from the latch and micro-processor higher address lines 14. The output of the logic 16 feeds the memory chip higher address lines 15. The invention determines what signal the memory chip address lines will receive based on the state of the micro-processor address lines. The micro-processor address lines will dictate whet~ler t~ere is an access to control memory (address space A in Fig.
1) or shadowed memory (address space s in Fig. 1). From here one can set up combinational 'logic to perform the following f un c t i on :
When micro-processor address lines reflect a control memory access, simulate the micro-processor address lines straight through to the memory chip. When the micro-processor address lines reflect a shadowed memory access, direct the latched bits to the memory chip higher address lines. The logic 16 for each separate address line 15 to do this function should be of the following form: [ (control memory access address ) AND ( the micro-processor address line 14 ) ] OR [ ( not control memory access address) AND (latched shadow location bit 18 ) ] . ~ach memory chip address line 15 that must be manipulated should have the preceding logic going to it.
Areas 24 and 26 in address map 22 are reserved areas that are not available.
Upon a power-up or any other interrupt, the corresponding interrupt vector will point to an address located in the A memory area and will be completely serviced out of A' memory. At no time will the interrupt routine need to enter shadowed memory s' or s'' areas hence, this does not change the latched bits which are set for either a s' or B'' area.
Therefore, if the program was running out of s it will return to s ; if it was running out of B it will return to B; if it was running out of A it will return to A . There are only two modes that this example can be in. The first is A' memory 200382~.

in A address space and B memory in B address space. The second way is A memory in A address space and B'' memory in B
address space. There is no problem when jumping back and forth between A and B, A and B ', or A' and A . The only time that there is a concern is when the jumping is done between B' and B'', because the latch must be set differently every time there is access to a different s'ection of the shadowed memory.
This is the reason we always return to A' memory before entering a new shadowed section, so that the latch can be set up to enter the newly desired shadowed section before actually entering it. An interrupt that is serviced out of A will never require B to B jumping, it will always be between (A ) and (B, B or A ) which is fine.
The present invention has many advantages. First, there is no need for special subroutines or bookkeeping to maintain control over the shadowing. Second, a larger single memory chip can be used to replace many memory chips and still maintain shadowing capability. This will save costs and, in addition, save board space. Also, it offers flexibility to the software by having control over subroutines running out of shadowed memory. For instance, subroutines may be called back and forth between control memory and the selected shadowed memory as if they were both hooked up direct to the address bus. Control will be maintained as long as the control memory initiates the call ,and is returned to at the end; ~lence, there is less chance of sof tware bugs due to the shadowing .
This invention can be used in many memory applications.
Practically any memory chip size may be used. The number of shadowed levels may be increased or decreased depending on the available addressing, allowable complexity of logic to be used, and memory size. The invention call apply to many types of memory such as RAM or EPROM, Bipolar or CMOS, and so on.
While a specific embodiment of the invention has been shown and described in detail to illustrate the application of the principles of the invention, it will be understood that the invention may be embodied otherwise witho~lt d~rart in~ from suc~

,~38~1 1(~)

Claims (5)

1. A process for shadowing memory using a single memory chip which is addressable into an address field which is smaller than the memory chip, with a program having a main program portion and a plurality of secondary program portions usable with the main program portion, the process comprising:
storing the main program portion in a main memory area of the memory chip;
storing each of the secondary program portions in a separate shadowed memory area of the memory chip;
assigning a main address space of the address field, which is large enough to receive the main memory area, to the main memory area;
assigning a single secondary space of the address field which is large enough to receive only one of the shadowed memory areas at a time, to each of the shadowed memory areas latching one of the secondary memory areas at a time to the secondary address space; and providing interrupt means for interrupting from the current program to the main program portion so that, regardless of the point in the program which is active upon an interruption, interruption will always return to the program from the main program portion.
2. A process according to claim 1 wherein each address location in the address field has a plurality of bits, the process including dividing the bits of each address location into higher and lower bits, and latching the secondary address space to one of the secondary memory areas using the higher address bits.
3. A process according to claim 1 including providing a micro-processor for containing the address field, each address location in the address field having higher and lower bits, the lower bits being connected directly from the micro-processor to the memory chip, and providing logic means connected between the micro-processor and the memory chip for controlling higher bits of at least some of the address locations between the micro-processor or latched bits and the memory chip.
4, An apparatus for shadowing memory containing a program having a main program portion and plurality of secondary program portions each usable one at a time with the main program, the apparatus comprising:
a single memory chip having a main memory area for containing the main program portion, and a plurality of secondary memory areas each for containing one of the secondary program portions;
interrupt means in the program stored in the main memory area for permitting power-up and interrupt only through the main program portion;
address means providing an address field having a main address space which is large enough to receive the main memory area, and a secondary address spaces large enough for receiving only one secondary memory area at a time; and latching means operatively connected between said address means and said memory chip for latching one secondary memory area at a time to said secondary address space.
5. An apparatus according to claim 4 wherein said address means comprises a micro-processor, each address location of said address field having lower bits connected directly between said micro-processor and said memory chip, higher bits of said address location being connected between said micro-processor and said memory chip through said logic means.
CA002003821A 1989-04-20 1989-11-24 Process controller single memory chip shadowing technique Expired - Fee Related CA2003821C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US34098589A 1989-04-20 1989-04-20
US340,985 1989-04-20

Publications (2)

Publication Number Publication Date
CA2003821A1 CA2003821A1 (en) 1990-10-20
CA2003821C true CA2003821C (en) 1996-12-03

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US (1) US5410665A (en)
EP (1) EP0393281A3 (en)
JP (1) JPH0752409B2 (en)
AU (1) AU628519B2 (en)
CA (1) CA2003821C (en)

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US5537627A (en) * 1993-09-08 1996-07-16 Hilevel Technology, Inc. Microprogrammable processor capable of accessing unused portions of control store as fast data memory
DE19720990A1 (en) * 1997-05-20 1998-11-26 Alsthom Cge Alcatel Program-controlled setup with the possibility of reloading and switching to the second operating system without program interruption
DE19829615A1 (en) * 1997-07-10 1999-02-25 Schenck Vibro Gmbh Program memory expansion for microprocessor
US5986962A (en) * 1998-07-23 1999-11-16 International Business Machines Corporation Internal shadow latch
US6968469B1 (en) 2000-06-16 2005-11-22 Transmeta Corporation System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored

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Publication number Publication date
EP0393281A2 (en) 1990-10-24
CA2003821A1 (en) 1990-10-20
JPH033049A (en) 1991-01-09
AU628519B2 (en) 1992-09-17
AU5373690A (en) 1990-10-25
EP0393281A3 (en) 1991-07-10
US5410665A (en) 1995-04-25
JPH0752409B2 (en) 1995-06-05

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