CA2011807A1 - Data base processing system using multiprocessor system - Google Patents

Data base processing system using multiprocessor system

Info

Publication number
CA2011807A1
CA2011807A1 CA2011807A CA2011807A CA2011807A1 CA 2011807 A1 CA2011807 A1 CA 2011807A1 CA 2011807 A CA2011807 A CA 2011807A CA 2011807 A CA2011807 A CA 2011807A CA 2011807 A1 CA2011807 A1 CA 2011807A1
Authority
CA
Canada
Prior art keywords
data base
processing operation
processor module
resource
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2011807A
Other languages
French (fr)
Other versions
CA2011807C (en
Inventor
Katsumi Hayashi
Masaaki Mitani
Yutaka Sekine
Tomohiro Hayashi
Kazuhiko Saito
Yoshinori Shimogai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP1068814A external-priority patent/JP2825839B2/en
Priority claimed from JP1068815A external-priority patent/JPH07120305B2/en
Application filed by Individual filed Critical Individual
Publication of CA2011807A1 publication Critical patent/CA2011807A1/en
Application granted granted Critical
Publication of CA2011807C publication Critical patent/CA2011807C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/524—Deadlock detection or avoidance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/912—Applications of a database
    • Y10S707/922—Communications
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99931—Database or file accessing
    • Y10S707/99938—Concurrency, e.g. lock management in shared database

Abstract

In a data base processing system using a multi-processor system, the data base processing system includes: a storage unit provided in the shared memory for storing data base management information representing either and object of a shared processing operation or an object of a local processing operation for every resource; and access management unit provided in each of the processor modules for performing an access control for an access request to the data base under either the shared processing operation or the local processing operation in accordance with the data base management information, the shared processing operation being symmetrically performed, and the local processing operation being asymmetrically performed in each processor module; and a control unit provided in the processor module for controlling the shared/local conversion in such a way that: an access state of the resource is managed for every resource; when a frequency of the access is unevenly distributed to a particular processor module, the resource of that processor module is determined as the object of the local processing operation at that particular processor module; and when the frequency of the access is not unevenly distributed to a particular processor module, the resource of a particular processor module is determined as the object of the shared processing operation. The data base processing system further includes a deadlock detection system.
CA002011807A 1989-03-20 1990-03-15 Data base processing system using multiprocessor system Expired - Fee Related CA2011807C (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP1-068814 1989-03-20
JP1068814A JP2825839B2 (en) 1989-03-20 1989-03-20 Deadlock detection processing method
JP1068815A JPH07120305B2 (en) 1989-03-20 1989-03-20 Database processing method by multiprocessor
JP1-068815 1989-03-20

Publications (2)

Publication Number Publication Date
CA2011807A1 true CA2011807A1 (en) 1990-09-20
CA2011807C CA2011807C (en) 1999-02-23

Family

ID=26410003

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002011807A Expired - Fee Related CA2011807C (en) 1989-03-20 1990-03-15 Data base processing system using multiprocessor system

Country Status (7)

Country Link
US (1) US5649184A (en)
EP (1) EP0389242B1 (en)
KR (1) KR930000853B1 (en)
AU (1) AU614225B2 (en)
CA (1) CA2011807C (en)
DE (1) DE69032337T2 (en)
ES (1) ES2116267T3 (en)

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US7523157B2 (en) * 2003-09-25 2009-04-21 International Business Machines Corporation Managing a plurality of processors as devices
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US20050071828A1 (en) * 2003-09-25 2005-03-31 International Business Machines Corporation System and method for compiling source code for multi-processor environments
US7389508B2 (en) * 2003-09-25 2008-06-17 International Business Machines Corporation System and method for grouping processors and assigning shared memory space to a group in heterogeneous computer environment
US7475257B2 (en) * 2003-09-25 2009-01-06 International Business Machines Corporation System and method for selecting and using a signal processor in a multiprocessor system to operate as a security for encryption/decryption of data
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US20050289143A1 (en) * 2004-06-23 2005-12-29 Exanet Ltd. Method for managing lock resources in a distributed storage system
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US7616218B1 (en) * 2005-12-05 2009-11-10 Nvidia Corporation Apparatus, system, and method for clipping graphics primitives
JP2007328461A (en) * 2006-06-06 2007-12-20 Matsushita Electric Ind Co Ltd Asymmetric multiprocessor
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US8347064B1 (en) 2006-09-19 2013-01-01 Nvidia Corporation Memory access techniques in an aperture mapped memory space
US8352709B1 (en) 2006-09-19 2013-01-08 Nvidia Corporation Direct memory access techniques that include caching segmentation data
US8543792B1 (en) 2006-09-19 2013-09-24 Nvidia Corporation Memory access techniques including coalesing page table entries
US8707011B1 (en) 2006-10-24 2014-04-22 Nvidia Corporation Memory access techniques utilizing a set-associative translation lookaside buffer
US8700883B1 (en) 2006-10-24 2014-04-15 Nvidia Corporation Memory access techniques providing for override of a page table
US8347065B1 (en) * 2006-11-01 2013-01-01 Glasco David B System and method for concurrently managing memory access requests
US8533425B1 (en) 2006-11-01 2013-09-10 Nvidia Corporation Age based miss replay system and method
US8706975B1 (en) 2006-11-01 2014-04-22 Nvidia Corporation Memory access management block bind system and method
US8607008B1 (en) 2006-11-01 2013-12-10 Nvidia Corporation System and method for independent invalidation on a per engine basis
US8504794B1 (en) 2006-11-01 2013-08-06 Nvidia Corporation Override system and method for memory access management
US8700865B1 (en) 2006-11-02 2014-04-15 Nvidia Corporation Compressed data access system and method
US8543773B2 (en) 2008-08-25 2013-09-24 International Business Machines Corporation Distributed shared memory
US9411661B2 (en) * 2009-04-08 2016-08-09 International Business Machines Corporation Deadlock avoidance
US10146545B2 (en) 2012-03-13 2018-12-04 Nvidia Corporation Translation address cache for a microprocessor
US9880846B2 (en) 2012-04-11 2018-01-30 Nvidia Corporation Improving hit rate of code translation redirection table with replacement strategy based on usage history table of evicted entries
US10241810B2 (en) 2012-05-18 2019-03-26 Nvidia Corporation Instruction-optimizing processor with branch-count table in hardware
US9104502B2 (en) 2012-12-15 2015-08-11 International Business Machines Corporation Managing resource pools for deadlock avoidance
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Also Published As

Publication number Publication date
EP0389242A3 (en) 1993-06-30
ES2116267T3 (en) 1998-07-16
EP0389242A2 (en) 1990-09-26
AU614225B2 (en) 1991-08-22
US5649184A (en) 1997-07-15
KR900015010A (en) 1990-10-25
CA2011807C (en) 1999-02-23
DE69032337T2 (en) 1998-09-24
EP0389242B1 (en) 1998-05-27
AU5200190A (en) 1990-09-27
KR930000853B1 (en) 1993-02-06
DE69032337D1 (en) 1998-07-02

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Effective date: 20070315